Test and / or measurement systems and methods

Abstract

This enables more time-efficient measurement of noise generated by the device under test. [Solution] In the test and / or measurement system 10, a noise circuit 14 generates a noise signal having a frequency spectrum that extends over a predetermined frequency band and connects to a first port 22 that is connectable to a first DUT port of the device under test 12. A second port 24 is connectable to a second DUT port of the device under test 12 to receive a test signal from the device under test, and a receiving circuit 18 is connectable to the second port to receive the test signal. The receiving circuit 18 digitizes the test signal and acquires the digitized test signal. A processing circuit 50 converts the digitized test signal into the frequency domain and acquires a converted test signal having multiple frequency bins, and simultaneously determines the signal power of the converted test signal for at least two of the multiple frequency bins.

Description

Technical Field

[0001] The present invention generally relates to a test and / or measurement system. The present invention further relates to a test and / or measurement method for testing a device under test.

Summary of the Invention

[0002] Noise measurement of a device under test is typically performed by sweeping a receiver over the entire frequency band of interest, and the noise generated by the device under test is sequentially measured at all frequency locations.

[0003] Due to the low power levels of typical noise generated by the device under test, these measurements usually take a fairly long time, especially when the frequency range to be tested is wide.

[0004] Therefore, an object of the present invention is to provide a test and / or measurement system and a test and / or measurement method that enable more time-efficient measurement of the noise generated by a device under test.

[0005] According to the present invention, the problem is solved by a test and / or measurement system. The test and / or measurement system comprises a noise circuit, a first port, a second port, at least one receiving circuit, and at least one processing circuit. The noise circuit is configured to generate a noise signal, the noise signal having a frequency spectrum extending over a predetermined frequency band of interest. The noise circuit is connected to a first port, which is connectable to a first DUT port of the device under test so that the noise signal can be supplied to the device under test. The second port is connectable to a second DUT port of the device under test so as to receive a test signal from the device under test, and at least one receiving circuit is connectable to the second port so as to receive the test signal. At least one receiving circuit is configured to digitize the test signal, thereby obtaining the digitized test signal. At least one processing circuit is configured to convert the digitized test signal into the frequency domain, thereby obtaining a converted test signal having multiple frequency bins. At least one processing circuit is configured to simultaneously determine the signal power of the converted test signal for at least two of the multiple frequency bins.

[0006] The term “circuit” as used herein and thereafter is understood to describe appropriate hardware, appropriate software, or a combination of hardware and software configured to have a specific function.

[0007] In practice, the term "circuit" is understood to refer to a module that has the appropriate hardware, appropriate software, or a combination of hardware and software configured to have a specific function.

[0008] The hardware may include, in particular, a CPU, GPU, FPGA, ASIC, or other form of electronic circuitry.

[0009] Furthermore, the term "connected" is understood to refer to direct or mediated connections between the components. For example, the components may be connected via conductors and / or electromagnetic coupling.

[0010] The test and / or measurement system according to the present invention is based on the idea of ​​simultaneously determining the noise generated by the device under test for at least two frequency bins.

[0011] This is achieved by a receiving circuit configured to process and digitize a test signal that has sufficient bandwidth to simultaneously determine the signal power of the converted test signal for at least two frequency bins.

[0012] Therefore, the receiving circuit may be implemented as a broadband receiving circuit, that is, a receiving circuit configured to process and digitize the test signal across the entire bandwidth corresponding to the frequency band of interest, at least partially, and especially entirely.

[0013] The test signal corresponds to the noise signal processed by the device under test. Therefore, the test signal includes the noise signal modified by the transfer function of the device under test, as well as noise generated by the device under test itself.

[0014] In this context, the power level of the noise signal is known. In fact, the power level of the noise signal may be known in advance and / or determined by other measurements.

[0015] Based on known noise signals and the converted test signals, the noise power level of the noise generated by the device under test can be determined. The determined noise level may then be used to determine the noise characteristics of the device under test, such as the noise figure of the device under test.

[0016] If the signal power of the converted test signal is determined simultaneously for at least two frequency bins instead of sequentially for each frequency bin, the measurement time required to determine the noise generated by the device under test is significantly reduced compared to the prior art.

[0017] If the device under test has more than one output port, i.e., at least two second DUT ports, the measurements described above and below can be performed simultaneously on at least two second DUT ports.

[0018] In fact, the test and / or measurement system may include at least two receiving circuits, each receiving circuit connected to at least one of two second ports.

[0019] According to aspects of the present invention, the digitized test signal is a data stream. In particular, the test signal is continuously received and digitized by at least one receiving circuit, thereby generating a digitized test signal which is a continuous data stream.

[0020] The test and / or measurement system according to the present invention may be implemented as a vector network analyzer, a spectral analyzer, and / or any other suitable form of test and / or measurement instrument, or may comprise them.

[0021] According to one aspect of the present invention, at least one processing circuit is configured to subtract the signal power of a noise signal from the determined signal power of a converted test signal for each of at least two frequency bins. By subtracting the signal power of a noise signal from the determined signal power of a converted test signal, the noise power level of the noise generated by the device under test can be determined for each of at least two frequency bins.

[0022] In embodiments of the present invention, at least one receiving circuit is configured to digitize a noise signal and thereby acquire the digitized noise signal; at least one processing circuit is configured to convert the digitized noise signal into the frequency domain and thereby acquire the converted noise signal having a plurality of frequency bins; and at least one processing circuit is configured to simultaneously determine the signal power of the converted noise signal for at least two of the plurality of frequency bins. Thus, the signal power of the noise signal can be determined in another measurement, for example, in another calibration measurement performed to calibrate the test and / or measurement system according to the present invention.

[0023] According to a modified version of the present invention, at least one receiving circuit may comprise a first receiving circuit and a second receiving circuit. The first receiving circuit may be configured to digitize a noise signal, while the second receiving circuit may be configured to digitize a test signal. In this configuration, both measurements can be performed simultaneously.

[0024] However, it is also conceivable that at least one receiving circuit may be configured to digitize both the noise signal and the test signal. In this case, the calibration measurement, i.e., determining the signal power of the converted noise signal, and the measurement on the test signal may be performed in sequence.

[0025] The test and / or measurement system may further include a coupling circuit, which is connected between a noise circuit and a first port, and which is further connected to at least one receiving circuit, and which is configured to transmit a noise signal to both the first port and at least one receiving circuit.

[0026] In this configuration, the coupling circuit may include an electrical connection connecting the noise circuit and the first port. The coupling circuit may further be configured to couple the noise signal from the electrical connection toward at least one receiving circuit, particularly using electromagnetic coupling.

[0027] Instead, the coupling circuit may comprise an electrical connection connecting the noise circuit and at least one receiving circuit. In this case, the coupling circuit may be further configured to couple the noise signal from the electrical connection towards the first port, in particular using electromagnetic coupling.

[0028] For example, the coupling circuit may be implemented as a directional coupler.

[0029] The test and / or measurement system according to the claim may further comprise a memory, and the signal power of the noise signal for a plurality of frequency bins is stored in the memory. In fact, the signal power of the noise signal may be stored permanently in the memory, or may be updated at regular time intervals, in particular periodically. For example, the signal power of the noise signal stored in the memory may be updated during calibration measurements that may be carried out at regular time intervals, in particular periodically.

[0030] <0​​​​​​​​​​​​In fact, the frequency spectrum of the digitized test signal may extend across the entire frequency band in question, so that the noise generated by the device under test can be determined simultaneously across the entire frequency band in question, thereby significantly reducing the measurement time required to determine the noise power level of the noise generated by the device under test.

[0034] In a further embodiment of the present invention, at least one processing circuit is configured to simultaneously determine the signal power of the converted test signal for at least a portion of a plurality of frequency bins, the portion of which spans at least partially across the frequency band of interest. Therein, the term “at least partially” is understood to mean that the portion of which spans at least two frequency bins, in particular over a certain proportion of the frequency band of interest. Thus, the measurement time required to determine the noise generated by the device under test is significantly reduced, and the noise power level of the noise generated by the device under test can be simultaneously determined for a significant portion of the frequency band of interest.

[0035] For example, the percentage may be 5%, 10%, 25%, 75%, or any other value in between or greater than these.

[0036] In fact, some of the multiple frequency bins may extend across the entire frequency band in question, so that the noise generated by the device under test can be determined simultaneously across the entire frequency band, thereby significantly reducing the required measurement time.

[0037] One aspect of the present invention provides that the receiving circuit is adjustable to different portions of the frequency band under consideration. Thus, the signal power of the converted test signal, the signal power of the noise signal, and / or the noise generated by the device under test can be determined sequentially for different portions of the frequency band under consideration. This reduces the measurement time required to determine the noise generated by the device under test, while also enabling the use of a receiving circuit with a lower bandwidth, thereby reducing the manufacturing cost of the test and / or measurement system.

[0038] In a further embodiment of the present invention, at least one receiving circuit comprises a mixer circuit configured to mix a test signal with a local oscillator signal, thereby converting the test signal to an intermediate frequency IF. More precisely, the mixer circuit may be configured to mix the test signal with a local oscillator signal such that the test signal is converted to a specific IF band. This ensures reduced signal loss downstream of the mixer circuit and efficient processing of the test signal downstream of the mixer circuit.

[0039] At least one receiving circuit may further include a mixer, the further mixer configured to mix the noise signal with a local oscillator signal, thereby converting the noise signal to an intermediate frequency IF. More precisely, the mixer may be configured to mix the noise signal with a local oscillator signal such that the noise signal is converted to a specific IF band. This ensures reduced signal loss downstream of the further mixer and efficient processing of the noise signal downstream of the further mixer.

[0040] At least one receiving circuit may include at least one filter circuit connected to the mixer downstream of the mixer. Using at least one filter circuit, undesirable frequency ranges of the test signal and / or noise signal mixed with the local oscillator signal can be reliably blocked.

[0041] A further aspect of the present invention provides that at least one receiving circuit comprises at least one analog-to-digital converter, i.e., at least one ADC, which is configured to digitize a test signal, the at least one ADC is connected to a second port, and the signal path between the second port and the at least one ADC comprises a mixer or does not comprise a mixer.

[0042] If the signal path between the second port and at least one ADC does not include a mixer circuit, at least one ADC may be a broadband ADC such that the test signal is broadband digitized.

[0043] If the bandwidth of the test signal is wider than the bandwidth of the test signal, a mixing circuit may be provided to convert the test signal to the operating bandwidth of at least one ADC.

[0044] The test and / or measurement system may further include a data storage circuit, which is connected to at least one ADC and configured to store the digitized test signal. As a result, post-processing of the digitized test signal may be performed, eliminating the need to perform the aforementioned measurements in real time.

[0045] According to another aspect of the present invention, the processing circuit is configured to read a digitized test signal from a data storage circuit.

[0046] In embodiments of the present invention, the processing circuit is configured to weight the digitized test signal with a window function. In fact, the window function is a time-domain window function such that a specific time slice of the digitized test signal is selected by the window function.

[0047] The processing circuit may be configured to convert the digitized test signal, weighted by a window function, into the frequency domain, thereby obtaining the converted test signal.

[0048] In fact, the window function may correspond to the impulse response of the resolution filter, and the bandwidth of the resolution filter determines the length of the transformation to the frequency domain, in particular the length of the corresponding Fast Fourier Transform.

[0049] The processing circuit may be configured to determine the square of the magnitude for each of at least two frequency bins of the converted test signal, thereby obtaining the signal power. In fact, the square of the magnitude of the converted test signal may be determined separately for each frequency bin.

[0050] A further aspect of the present invention provides that a plurality of frequency bins include interpolated frequency bins. In other words, the processing circuit may be configured to interpolate the converted test signal such that the converted test signal includes frequency bins resulting from interpolation and frequency bins resulting from conversion to the frequency domain. In this method, the resolution for determining the signal power of the converted test signal and / or the noise power level of the noise generated by the device under test can be adapted.

[0051] In fact, the frequency bins resulting from the conversion to the frequency domain and the frequency bins resulting from the interpolation may occur alternately.

[0052] According to one aspect of the present invention, at least one receiving circuit is configured to repeatedly digitize a test signal, and a processing circuit is configured to repeatedly determine the signal power, and the processing circuit is configured to determine an average signal power corresponding to the signal power of the test signal averaged over time. Thus, the average noise power level of the noise generated by the device under test may be determined by the processing circuit based on the determined average signal power.

[0053] According to another aspect of the present invention, the digitized test signal includes IQ data relating to the test signal. Therefore, the digitized test signal includes both amplitude and phase information relating to the test signal.

[0054] The signal path between the noise circuit and the first port does not need to include an amplifier. Therefore, the noise signal supplied to the device under test is not amplified and / or distorted by any further amplifier. Furthermore, when determining the noise generated by the device under test, it is not necessary to consider the gain applied to the noise signal by an amplifier.

[0055] In embodiments of the present invention, the noise circuit is either an active noise circuit or a passive noise circuit. In other words, the noise circuit may actively generate a noise signal, for example, via a suitable signal generator. Alternatively, or in addition, the noise circuit may passively generate a noise signal, that is, without active signal generation.

[0056] For example, a noise circuit comprises a signal generator, an attenuator, and / or a resistor having a predetermined resistance value.

[0057] Therefore, the signal generator of the noise circuit may actively generate noise signals.

[0058] The attenuator may attenuate RF signals generated or received by another circuit having a large attenuation coefficient of, for example, 50 dB or more.

[0059] A resistor passively generates a predetermined thermal noise signal that depends on the resistor's temperature.

[0060] According to the present invention, the problem is further solved by a test and / or measurement method for testing the device under test. The test and / or measurement method is A step of generating a noise signal using a noise circuit, wherein the noise signal has a frequency spectrum that extends over a predetermined frequency band of interest, The steps include supplying a noise signal to the device under test via the first port, The second port receives a test signal corresponding to the noise signal from the device under test, The steps include: digitizing the test signal using at least one receiving circuit and thereby obtaining the digitized test signal; The process involves converting a digitized test signal into a frequency domain using at least one processing circuit, thereby obtaining a converted test signal having multiple frequency bins. The process involves simultaneously determining the signal power of the converted test signal for at least two of the multiple frequency bins using at least one processing circuit, and Includes.

[0061] In fact, a test and / or measurement system relating to any one of the above-described modifications may be configured to perform a test and / or measurement method.

[0062] For further advantages and properties of the test and / or measurement methods, refer to the description given above for the test and / or measurement systems, which also apply to the test and / or measurement methods and vice versa. [Brief explanation of the drawing]

[0063] The aforementioned aspects and the many associated benefits of the claimed protected subject matter will be better appreciated and understood by referring to the detailed description below in conjunction with the accompanying drawings. [Figure 1] Figure 1 schematically shows the test and / or measurement system according to the present invention. [Figure 2] Figure 2 schematically shows the processing circuit of the test and / or measurement system shown in Figure 1. [Figure 3] Figure 3 shows a flowchart of the test and / or measurement method according to the present invention. [Figure 4] Figure 4 schematically shows a second modification of the test and / or measurement system of Figure 1. [Figure 5] Figure 5 schematically shows a third modification of the test and / or measurement system of Figure 1. [Figure 6]Figure 6 schematically shows a fourth modification of the test and / or measurement system of Figure 1. [Modes for carrying out the invention]

[0064] In conjunction with the accompanying drawings, the detailed description below uses the same figures to refer to the same elements and is intended to describe various embodiments of the protected subject matter disclosed, and not to represent only those embodiments. Each embodiment described in this disclosure is given merely as an example and should not be construed as being preferable or advantageous to other embodiments. The examples provided herein are not intended to be exhaustive or to limit the protected subject matter claimed to be in the exact form disclosed.

[0065] For the purposes of this disclosure, the phrase “at least one of A, B, and C” means, for example, (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C), and also includes all further possible permutations when there are three or more elements. In other words, the term “at least one of A, B” generally means “A and / or B,” i.e., “A” only, “B” only, or “A and B.”

[0066] Figure 1 schematically shows a test and / or measurement system 10 configured to perform tests and / or measurements on the device under test 12.

[0067] Generally, the device under test 12 is an electronic device configured to receive and process an input signal, thereby obtaining an output signal.

[0068] For example, the device under test 12 may be an amplifier, a mixer, a filter, or other electronic component or device.

[0069] The test and / or measurement system 10 may be implemented as a vector network analyzer (VNA) or a spectrum analyzer, or may include both.

[0070] The test and / or measurement system 10 may be implemented or comprised of any other suitable form of a test and / or measurement device configured to perform the functions described later.

[0071] For example, the test and / or measurement system 10 may be, or may include, additional transmitters and / or receivers compared to the embodiments described exemplified below.

[0072] In a particular example, the test and / or measurement system 10 may be an N-gate vector network analyzer configured to measure all S-parameters of the device under test 12, or may include such an analyzer.

[0073] The test and / or measurement system 10 includes a noise circuit 14, a first receiving circuit 16, and a second receiving circuit 18.

[0074] Generally, the noise circuit 14 is configured to generate a noise signal, the noise signal having a frequency bandwidth that corresponds at least partially, and in certain cases completely, to the target frequency band of the device under test 12.

[0075] For example, the noise signal may include white noise, thermal noise, or any other form of noise suitable for testing the device under test 12.

[0076] Within that context, the target frequency band is the frequency band of the test device 12 being tested.

[0077] For example, the noise circuit 14 may be implemented as a signal generator, and in particular as an optional waveform generator. In other words, the noise circuit 14 may be an active noise source.

[0078] As another example, the noise circuit 14 may be a passive noise source, such as a resistor having a predetermined resistance value and a constant temperature, or an attenuator connected to a signal source and applying strong attenuation to the signal received from the signal source.

[0079] The noise circuit 14, the first receiving circuit 16, and / or the second receiving circuit 18 may be integrated into the same test and / or measuring device, such as a vector network analyzer or a spectrum analyzer.

[0080] Therefore, the noise circuit 14, the first receiving circuit 16, and / or the second receiving circuit 18 may be housed in a common housing.

[0081] Alternatively, the noise circuit 14, the first receiving circuit 16, and / or the second receiving circuit 18 may be provided in different test and / or measuring devices and / or different housings.

[0082] Downstream of the noise circuit 14, the coupling circuit 20 may be provided to connect the noise circuit 14 to the first port 22 of the test and / or measurement system so that the noise signal generated by the noise circuit 14 is transferred to the first port 22.

[0083] Furthermore, the coupling circuit 20 may be configured to transfer the noise signal to the first receiving circuit 16.

[0084] For example, the coupling circuit 20 may be implemented as a directional coupler.

[0085] The first port 22 is connected to the first DUT port of the device under test 12, in particular to the input of the device under test 12.

[0086] The test and / or measurement system 10 further includes a second DUT port of the device under test 12, in particular a second port 24 connected to the output of the device under test 12.

[0087] The second port 24 is connected to the second receiving circuit 18 such that the output signal of the device under test 12 is transferred to the second receiving circuit 18 via the second port 24.

[0088] The first receiving circuit 16 includes a first mixing circuit 26 connected to the coupling circuit 20 and the local oscillator (LO) signal generation circuit 28.

[0089] Downstream of the first mixing circuit 26, the first filter circuit 30 is provided.

[0090] The first receiving circuit 16 further includes at least one first ADC 32 which is first connected downstream of the first filter circuit 30.

[0091] Optionally, memory 34 may be provided downstream of at least one first ADC 32.

[0092] The first receiving circuit 16 further includes a first processing circuit 35 connected to at least one first ADC 32, and in particular to a memory 34 downstream of at least one first ADC 32.

[0093] The second receiving circuit 18 may optionally include a coupling circuit 38 connected to the second port 24.

[0094] Furthermore, the second receiving circuit 18 may include a second mixing circuit 40 connected to the second port 24, particularly via a coupling circuit 38.

[0095] The second mixing circuit 40 is further connected to an additional LO signal generation circuit 42.

[0096] It should also be noted that both the first mixing circuit 26 and the second mixing circuit 40 may be connected to a common LO signal generator.

[0097] A second filter circuit 44 is provided downstream of the second mixing circuit 40.

[0098] The second receiving circuit 18 further includes at least one second ADC 46 connected to the second filter circuit 44 downstream of the second filter circuit 44.

[0099] Optionally, the data storage circuit 48 may be provided downstream of at least one second ADC 46.

[0100] The second receiving circuit 18 further includes a second processing circuit 50 downstream of at least one second ADC 46, and connected to at least one second ADC 46, in particular to a data storage circuit 48.

[0101] It should also be noted that the first processing circuit 36 ​​and the second processing circuit 50 may be integrated into a common processing circuit.

[0102] In the exemplary embodiment shown in Figure 1, the test and / or measurement system 10 further includes a processing circuit 52 connected to both the first processing circuit 36 ​​and the second processing circuit 50.

[0103] It should be understood that the first processing circuit 36, the second processing circuit 50, and / or the processing circuit 52 may be integrated into a common processing circuit.

[0104] Figure 2 shows a schematic representation of the first processing circuit 36 ​​in more detail.

[0105] It is understood that the second processing circuit 50 may be implemented in the same manner as the first processing circuit 36.

[0106] The first processing circuit 36 ​​includes a weighting sub-circuit 54 connected to at least one first ADC 32 or rather to the memory 34.

[0107] Downstream of the weighting subcircuit 54, the FFT subcircuit 56 is provided.

[0108] The first processing circuit 36 ​​further includes a plurality of power sub-circuits 58 that are downstream of the FFT sub-circuit 56 and connected to the FFT sub-circuit 56.

[0109] Furthermore, the first processing circuit 36 ​​includes a correction subcircuit 60 that is provided downstream of the power subcircuit 58.

[0110] The functions of the first processing circuit 36 ​​and its individual subcircuits will be described in more detail below.

[0111] The aforementioned test and / or measurement system 10 is configured to perform a test and / or measurement method for testing the device under test 12, which will be described below with reference to Figure 3.

[0112] The aforementioned noise signal is generated by the noise circuit 14 (step S1).

[0113] The noise signal is transferred to the device under test 12 via the coupling circuit 20 and the first port 22.

[0114] Furthermore, the noise signal may be transferred to the first mixing circuit 26 via the coupling circuit 20.

[0115] The noise signal is processed by the device under test 12, thereby obtaining the test signal (step S2).

[0116] Therefore, the test signal contains noise, but is modified by the transfer function of the device under test 12.

[0117] Furthermore, the test signal includes noise generated in the device under test 12, that is, noise generated by the device under test 12 itself.

[0118] The test signal is transferred to the second receiving circuit 18 via the second port 24.

[0119] Optionally, the test signal is mixed with the LO signal generated by the LO signal generation circuit 42 by the second mixing circuit 40, thereby converting the test signal into an intermediate frequency (IF) band.

[0120] Furthermore, the test signal may be filtered by the second filter circuit 44.

[0121] It is understood that additional signal shaping circuitry, such as an amplifier capable of amplifying the test signal, may be provided to perform further signal shaping operations on the test signal.

[0122] In another variation, the second mixing circuit 40 and / or the second filtering circuit 44 may be bypassed. In this case, the test signal may be directly transferred from the second port 24 to at least one second ADC 46.

[0123] In fact, the second mixer 40 and filter circuit 44 may be bypassed up to a specific frequency or bandwidth threshold corresponding to the bandwidth of at least one second ADC 46, for example, up to 9 GHz. The second mixer 40 and filter circuit 44 may be involved if the bandwidth of the test signal exceeds that threshold.

[0124] The test signal is digitized by at least one second ADC46, thereby obtaining the digitized test signal (step S3).

[0125] In fact, the test signal may be received and digitized continuously, so that the digitized test signal is a digital data stream.

[0126] In this context, the digitized test signal may include IQ data relating to the test signal, such that the digitized test signal includes both amplitude and phase information of the test signal.

[0127] At least one second ADC46 has a specific bandwidth corresponding to a particular portion of the target frequency range.

[0128] In one modification, the bandwidth of at least one second ADC46 may cover the entire frequency range of interest. In this case, the digitization of the test signal can be performed simultaneously across the entire frequency range of interest. Therefore, the measurements described later may be performed simultaneously across the entire frequency range of interest.

[0129] If the bandwidth of at least one second ADC46 does not cover the entire frequency range of interest, the second receiving circuit 18 may sequentially adjust itself to multiple different parts of the frequency range of interest. Thus, the test signal may be sequentially digitized over parts of the frequency range of interest, and the measurements described later may be performed sequentially over parts of the frequency range of interest.

[0130] The digitized test signal may be stored in the data storage circuit 48 (step S4).

[0131] The second processing circuit 50 may read the digitized test signal from the data storage circuit 48, and may perform the steps described below in post-processing.

[0132] Furthermore, the processing circuit 50 may receive a digitized test signal directly from at least one second ADC 46, and may perform the steps described below in real time, or at least partially.

[0133] The digitized test signal may be weighted by a window function by the second processing circuit 50, or more precisely by the weighting sub-circuit 54 (step S5).

[0134] The window function may be a time-domain window function such that a specific time slice of the digitized test signal is selected by the window function.

[0135] In fact, the window function may correspond to the impulse response of the resolution filter, and the bandwidth of the resolution filter determines the length of the transformation to the frequency domain, as described later, and in particular the length of the corresponding Fast Fourier Transform.

[0136] The digitized test signal is converted to the frequency domain by the second processing circuit 50, and more precisely by the FFT sub-circuit 56, thereby obtaining a converted test signal having multiple frequency bins (step S6).

[0137] For example, the FFT sub-circuit 56 may perform a Fast Fourier Transform (FFT) on the digitized test signal, thereby obtaining the transformed test signal.

[0138] Multiple frequency bins correspond to at least part, and especially all, of the frequency range in question.

[0139] If multiple frequency bins do not correspond to the entire frequency range of the target, different parts of the target frequency range may be sequentially converted to the frequency domain.

[0140] In this context, the continuum transformations may have certain overlaps in the frequency domain to ensure that the continuum transformations can be correctly matched.

[0141] The second processing circuit 50 may be configured to interpolate the converted test signal such that the converted test signal includes frequency bins resulting from the conversion to the frequency domain and frequency bins resulting from the interpolation.

[0142] In fact, the frequency bins resulting from the conversion to the frequency domain and the frequency bins resulting from the interpolation may occur alternately.

[0143] The signal power of the converted test signal is determined simultaneously for at least two frequency bins by multiple power subcircuits 58 (step S7).

[0144] More precisely, the signal power of the converted test signal may be determined by calculating the magnitude of the square of the converted test signal for each frequency bin.

[0145] In fact, the signal power may be determined individually or simultaneously for each frequency bin.

[0146] The signal power of the converted test signal may be corrected by the second signal processing circuit 50, in particular by the correction sub-circuit 60, using a gain coefficient in the signal chain.

[0147] In fact, the correction subcircuit may perform further corrections, such as compensating for impedance mismatches in the device under test 12 and / or performing cross-correlation to average out techniques in order to reduce measurement errors and improve measurement sensitivity.

[0148] The determined signal power is then transferred to the processing circuit 52.

[0149] The noise power level of the noise generated by the device under test 12 is determined by the processing circuit 52 based on the signal power of the converted test signal determined by the second processing circuit 50 (step S8).

[0150] More precisely, the processing circuit 52 may subtract the signal power of the noise generated by the noise circuit 14 from the determined signal power of the converted test signal for each frequency bin.

[0151] Based on the determined noise power level of the noise generated by the device under test 12, the noise characteristics of the device under test 12, such as the noise figure, may be determined.

[0152] In fact, the noise figure F of the device under test 12 with respect to frequency f may be determined as follows:

[0153] JPEG2026053252000002.jpg20113

[0154] In this, N1(f) is the noise power level at the input of the device under test 12, i.e., the noise power level of the noise signal generated by the noise circuit 14; N2(f) is the noise power level at the output of the device under test 12 (measured as described above); and G(f) is the gain of the device under test 12, which may be determined by another measurement.

[0155] In step S7, the average signal power corresponding to the signal power of the test signal averaged over time may be determined, and in step S8, the average noise power level corresponding to the noise power level averaged over time may be determined.

[0156] In fact, the average may be a moving average over a predetermined number of past measurements.

[0157] The processing circuit 52 may further be configured to compensate for specific errors in the determined noise power level, such as by compensating for impedance mismatches of the device under test 12 and / or performing cross-correlation to average out the techniques, in order to reduce measurement errors and improve measurement sensitivity.

[0158] In step S8, the signal power of the noise signal must be known in order to determine the noise generated by the device under test 12.

[0159] For example, the signal power of the noise signal generated by the noise circuit 14 may be known from past calibration measurements or stored in memory 34.

[0160] In fact, the corresponding calibration measurements may be repeated at regular time intervals, particularly periodically.

[0161] It is also possible that the signal power of the noise signal may be determined in parallel with the measurement performed on the test signal mentioned above.

[0162] The corresponding calibration measurements and parallel measurements are described below. In fact, measurements with the noise signal generated by the noise circuit 14 may be performed in the same manner as measurements with the test signal described above.

[0163] The noise signal generated by the noise circuit 14 is transferred to the first mixing circuit 26 by the coupling circuit 20.

[0164] The noise signal may be mixed with the LO signal generated by the LO signal generation circuit 28, thereby converting the noise signal into the IF band.

[0165] The noise signal may then be filtered by the first filter circuit 30 and / or processed by other suitable signal shaping circuits.

[0166] The noise signal is digitized by at least one first ADC32, thereby obtaining the digitized noise signal.

[0167] In this context, the digitized noise signal may include IQ data relating to the noise signal, such that the digitized noise signal contains both amplitude and phase information of the test signal.

[0168] The digitized noise signal may be stored in memory 34.

[0169] Before conversion to the frequency domain, the digitized noise signal may be weighted with a corresponding window function.

[0170] The first processing circuit 36 ​​converts the digitized test signal into the frequency domain, particularly using FFT, and thereby obtains a converted noise signal having multiple frequency bins.

[0171] The first processing circuit 36 ​​may be configured to interpolate the converted noise signal such that the converted noise signal includes frequency bins resulting from interpolation and frequency bins resulting from conversion to the frequency domain.

[0172] In fact, the frequency bins resulting from the conversion to the frequency domain and the frequency bins resulting from the interpolation may occur alternately.

[0173] In this process, the first processing circuit 36 ​​may read the digitized noise signal from the memory 34.

[0174] Alternatively, or in addition, the first processing circuit 36 ​​may receive a digitized noise signal directly from at least one first ADC 32.

[0175] The signal power of the converted noise signal may be determined for each frequency bin by the first processing circuit 36.

[0176] More precisely, the signal power of the converted noise signal may be determined by calculating the square of the magnitude of the converted noise signal for each frequency bin.

[0177] The determined signal power of the converted noise signal may be corrected by the gain coefficient in the signal chain and / or the gain coefficient of the device under test 12.

[0178] The determined signal power of the converted noise signal may then be transferred to the processing circuit 52 and / or stored in the memory 34.

[0179] Figure 4 schematically shows a second modified example of the test and / or measurement system 10.

[0180] Below, only the differences compared to the first modified example described above will be explained.

[0181] The test and / or measurement system 10 further comprises a signal source 62 and a switching circuit 64.

[0182] Generally, the signal source 62 is configured to generate or receive radio frequency (RF) signals. In fact, the RF signal may be a continuous wave signal.

[0183] Therefore, the signal source 62 may be a continuous wave signal source.

[0184] Generally, the switching circuit 64 is configured to selectively connect the noise circuit 14 or the signal source 62 to the first port 22 and / or the first receiving circuit 16.

[0185] In the exemplary embodiment shown in Figure 4, the switching circuit 64 is configured to selectively connect the noise circuit 14 or the signal source 62 to the coupling circuit 20.

[0186] The aforementioned measurements, as shown in Figures 1 to 3, can be performed using the noise circuit 14 connected to the first port 22 and / or the first receiving circuit 16.

[0187] A further set of measurements, such as measuring the gain of the device under test 12, may be performed using the signal source 62 connected to the first port 22 and / or the first receiving circuit 16.

[0188] Figure 5 schematically shows a third modified version of the test and / or measurement system 10, and only the differences compared to the second modified version mentioned above, which is referenced in Figure 4, are described below.

[0189] In this exemplary embodiment, the switching circuit 64 is configured to selectively bypass or connect the noise circuit 14 between the signal source 62 and the first port 22 and / or the first receiving circuit 16.

[0190] In fact, the switching circuit 64 may be configured to selectively bypass the noise circuit 14 or connect the noise circuit 14 between the signal source 62 and the coupling circuit 20.

[0191] In this exemplary embodiment, the noise circuit 14 may be an attenuator configured to reduce RF signals, particularly CW signals, generated by the signal source 62, and may include such an attenuator.

[0192] For example, the noise circuit 14 may be configured to attenuate RF signals by 50 dB or more so that, essentially, only noise remains from the RF signal generated by the signal source 62.

[0193] Using the connected noise circuit 14, the aforementioned measurements, as shown in Figures 1 to 3, can be performed.

[0194] Using the bypassed noise circuit 14, a set of further measurements can be performed, such as measuring the gain of the device under test 12.

[0195] Figure 6 schematically shows a fourth modification of the test and / or measurement system 10, and only the differences compared to the second modification mentioned above, which is referenced in Figure 4, are described below.

[0196] In this modified example, the signal source 62 may be connected to the first receiving circuit 16 via the coupling circuit 20.

[0197] The switching circuit 64 may be configured to selectively connect a signal source or a noise circuit 14 to the first port 22 (via the coupling circuit 20).

[0198] In this configuration, the switching circuit 64 may be provided between the signal source 62 and the first port 22, and in particular between the coupling circuit 20 and the first port 22.

[0199] The noise circuit 14 may include a resistor 66 connected to a reference potential, in particular to ground potential.

[0200] The resistor 66 has a predetermined resistance value, for example, 50 ohms.

[0201] At a certain temperature, the resistor 66 generates a predetermined thermal noise signal that can be transferred to the device under test 12 via the first port 22.

[0202] Therefore, the aforementioned measurements, as shown in Figures 1 to 3, can be performed using the noise circuit 14 connected to the first port 22.

[0203] In this case, the noise signal is not transferred to the first receiving circuit 16 for analysis purposes. Instead, the signal power of the noise signal generated by the noise circuit 14 may be calculated based on the temperature and resistance value of the resistor 66, rather than being measured by the first receiving circuit 16.

[0204] A further set of measurements may be performed using the signal source 62 connected to the first port 22, for example, measuring the gain of the device under test 12. Certain embodiments disclosed herein, in particular, each module and / or unit implements the standards, protocols, methodologies, or techniques disclosed herein, and operably combines two or more components, utilizes (e.g., one or more) circuits for generating information, processing information, analyzing information, generating signals, encoding / decoding signals, converting signals, transmitting and / or receiving signals, controlling other devices, etc. Any form of circuit may be used.

[0205] In embodiments, the circuit includes, among other things, one or more computing devices such as a processor (e.g., a microprocessor), a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a system-on-a-chip (SoC), or any combination thereof, and may include individual digital or analog circuit elements or electronic devices, or combinations thereof. In embodiments, the circuit includes hardware circuit implementations (e.g., analog circuit implementations, digital circuit implementations, and similar, and combinations thereof).

[0206] In embodiments, the circuit includes a combination of circuit and computing program products having software or firmware instructions stored in one or more computer-readable memories that cooperate to cause a device to perform one or more protocols, methodologies, or techniques described herein. In embodiments, the circuit includes, for example, a microprocessor or part of a microprocessor that requires software, firmware, and similar operation. In embodiments, the circuit includes one or more processors or parts thereof, and accompanying software, firmware, hardware, and similar.

[0207] This application may refer to quantities and numerical values. Unless otherwise specified, such quantities and numerical values ​​are not intended to be limiting and are intended to be illustrative of possible quantities or numerical values ​​relating to this application. In this regard, this application may also use the term “plurality” to refer to quantities or numerical values. In this regard, the term “plurality” means any number greater than 1, for example, 2, 3, 4, 5, etc. Terms such as “about,” “approximately,” and “near” mean within 5 percent of the stated value.

Claims

1. A test and / or measurement system, The test and / or measurement system (10) comprises a noise circuit (14), a first port (22), a second port (24), at least one receiving circuit (16, 18), and at least one processing circuit (36, 50, 52), The noise circuit (14) is configured to generate a noise signal. The noise signal has a frequency spectrum that extends over a predetermined frequency band, The noise circuit (14) is connected to the first port (22), and the first port (22) is connectable to the first DUT port of the device under test (12) so that the noise signal can be supplied to the device under test (12). The second port (24) is connectable to the second DUT port of the device under test (12) to receive test signals from the device under test (12), The at least one receiving circuit (18) is connectable to the second port (24) to receive the test signal, The at least one receiving circuit (18) is configured to digitize the test signal, thereby acquiring the digitized test signal. The at least one processing circuit (50) is configured to convert the digitized test signal into the frequency domain, thereby obtaining a converted test signal having multiple frequency bins. The at least one processing circuit (50) is configured to simultaneously determine the signal power of the converted test signal for at least two of the plurality of frequency bins. Test and / or measurement systems.

2. The at least one processing circuit (52) is configured to subtract the signal power of the noise signal from the determined signal power of the converted test signal for each of the at least two frequency bins. The test and / or measurement system according to claim 1.

3. The at least one receiving circuit (16) is configured to digitize the noise signal, thereby acquiring the digitized noise signal. The at least one processing circuit (36) is configured to convert the digitized noise signal into the frequency domain, thereby obtaining a converted noise signal having multiple frequency bins. The at least one processing circuit (36) is configured to simultaneously determine the signal power of the converted noise signal for at least two of the plurality of frequency bins. The test and / or measurement system according to claim 1 or 2.

4. Furthermore, it is equipped with a coupling circuit (20), The coupling circuit (20) is connected between the noise circuit (14) and the first port (22), The coupling circuit (20) is further connected to the at least one receiving circuit (16), The coupling circuit (20) is configured to transmit the noise signal to both the first port (22) and the at least one receiving circuit (16). The test and / or measurement system according to claim 3.

5. Furthermore, it is equipped with memory (34), The signal power of the noise signal for the plurality of frequency bins is stored in the memory (34). A test and / or measurement system according to any one of claims 1 to 4.

6. The at least one receiving circuit (18) is a broadband receiving circuit such that the digitized test signal has a frequency spectrum that extends at least partially over the target frequency band. In particular, at least one processing circuit (50) is configured to simultaneously determine the signal power of the converted test signal for at least a portion of the plurality of frequency bins. Some of the aforementioned frequency bins extend, at least partially, across the frequency band in question. A test and / or measurement system according to any one of claims 1 to 5.

7. The receiving circuits (16, 18) are adjustable to different portions of the target frequency band. A test and / or measurement system according to any one of claims 1 to 6.

8. The at least one receiving circuit (18) includes a mixing circuit (40), The mixing circuit (40) is configured to mix the test signal with the local oscillator signal, thereby converting the test signal to an intermediate frequency IF. In particular, the at least one receiving circuit (18) includes at least one filter circuit (44) downstream of the mixing circuit (40) and connected to the mixing circuit (40). A test and / or measurement system according to any one of claims 1 to 7.

9. The at least one receiving circuit (18) comprises at least one analog-to-digital converter (46), that is, at least one ADC. The at least one ADC (46) is configured to digitize the test signal, The at least one ADC (46) is connected to the second port (24), The signal path between the second port (24) and the at least one ADC (46) includes a mixer (40) or does not include a mixer. A test and / or measurement system according to any one of claims 1 to 8.

10. Furthermore, it is equipped with a data storage circuit (48), The data storage circuit is connected to the at least one ADC (46), The data storage circuit (48) is configured to store the digitized test signal, In particular, the processing circuit (50) is configured to read the digitized test signal from the data storage circuit (48). The test and / or measurement system according to claim 9.

11. The processing circuit (50) is configured to weight the digitized test signal with a window function. and / or the processing circuit (50) is configured to determine the square of the magnitude of each of the at least two frequency bins of the converted test signal, thereby obtaining the signal power. A test and / or measurement system according to any one of claims 1 to 10.

12. The plurality of frequency bins include interpolated frequency bins, A test and / or measurement system according to any one of claims 1 to 11.

13. The at least one receiving circuit (18) is configured to repeatedly digitize the test signal, The processing circuit (50) is configured to repeatedly determine the signal power, The processing circuit (50) is configured to determine the average signal power corresponding to the signal power of the test signal that has been averaged over time. A test and / or measurement system according to any one of claims 1 to 12.

14. The digitized test signal includes IQ data relating to the test signal. A test and / or measurement system according to any one of claims 1 to 13.

15. The signal path between the noise circuit (14) and the first port (22) does not include an amplifier. A test and / or measurement system according to any one of claims 1 to 14.

16. The noise circuit (14) is either an active noise circuit or a passive noise circuit. And / or, the noise circuit (14) comprises a signal generator, an attenuator, and / or a resistor (66) having a predetermined resistance value. A test and / or measurement system according to any one of claims 1 to 15.

17. A test and / or measurement method for testing a device under test, The aforementioned test and / or measurement method is: A step in which a noise signal is generated by a noise circuit (14), The noise signal has a frequency spectrum that extends over a predetermined frequency band, and The steps include supplying the noise signal to the device under test (12) via the first port (22), The second port (24) receives a test signal corresponding to the noise signal from the device under test (12), The steps include: digitizing the test signal using at least one receiving circuit (18), and thereby acquiring the digitized test signal; The process involves converting the digitized test signal into the frequency domain using at least one processing circuit (50), thereby obtaining a converted test signal having multiple frequency bins. The steps include: simultaneously determining the signal power of the converted test signal with respect to at least two of the plurality of frequency bins using the at least one processing circuit (50); Test and / or measurement methods, including those mentioned above.

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