Semiconductor equipment

Abstract

To provide a display device that allows image rewriting only in an arbitrary area, or To simplify the circuit configuration, including wiring, in a display device that allows for partial drive. [Solution] The shift of the selection signal in the shift register of the scan line drive circuit and scanning The supply of selection signals to lines is controlled independently. This allows for drawing only to any desired region. It is possible to rewrite the image. Furthermore, the above operation can be controlled by a clock signal or a fixed potential. This is achieved by providing wiring that supplies a signal indicating this. The display device is capable of partial drive, while also simplifying the circuit configuration, including the wiring. It is a display device.

Description

[Technical Field]

[0001] This invention relates to a display device. [Background technology]

[0002] A display device that can reduce power consumption by partially rewriting the image has been developed. It is being emitted. Such display devices partially rewrite the image using some scan lines. It has a scan line drive circuit that is capable of driving only certain lines (also called partial drive).

[0003] Patent Document 1 describes a scan line drive circuit (gate drive unit) that can achieve partial drive. It is disclosed. Specifically, the scan line drive circuit (gate drive unit) disclosed in Patent Document 1. It is divided into multiple groups. And each of the divided groups has a different starting power The operation is controlled by the scan start signal (LS). That is, the scan disclosed in Patent Document 1 The scan line drive circuit (gate drive unit) receives the start pulse (scan start signal) input to each group. Partial drive is achieved through control. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2007-004176 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, in the display device disclosed in Patent Document 1, the image rewriting process is not performed for any region. Whether to perform the operation can only be selected for each group that is divided in advance. In other words, it is arbitrary. It is not possible to select image rewriting for each scan line (for example, per scan line). In the display device disclosed in Patent Document 1, the number of signals required to drive the scan line drive circuit is The scan line drive circuit increases in proportion to the number of groups into which it is divided. That is, the scan line drive circuit The number of wires that make up the circuit will increase in proportion to the number of such groups. Also, the scanning line drive circuit is divided When formed on the same substrate as the element, the number of the pixel groups corresponds to the number of substrates on which the pixel is formed and the external substrate. This will increase the number of connection points to the road.

[0006] In view of the above-mentioned problems, one embodiment of the present invention allows for image rewriting only in an arbitrary region. One of the objectives of this invention is to provide a display device capable of partial drive. In addition, one aspect of the present invention provides a display device capable of partial drive. One of the challenges in a functional display device is to simplify the circuit configuration, including the wiring. One aspect of the present invention addresses at least one of the above-mentioned problems. [Means for solving the problem]

[0007] The aforementioned problem is that the scan line driving circuit selectively selects a signal for each of the multiple scan lines. This can be solved by supplying a scan line drive circuit with multiple pulse output circuits. If the shift register is composed of the following, the pulse output circuit will receive the clock signal This is used to shift the selection signal to the subsequent pulse output circuit, and also the clock signal and By selectively using fixed potentials to supply signals to scan lines, multiple scans can be performed. It is possible to selectively supply a selection signal to a line. That is, a signal to a scan line. If the signal is a clock signal, it becomes a selection signal, and if it is a fixed potential, it becomes a deselection signal. By designing it in this way, it is possible to control the supply of selection signals to scan lines. .

[0008] Specifically, one aspect of the present invention includes a plurality of pixels arranged in m rows and n columns, and the plurality of pixels A first scanning line electrically connected to n pixels arranged in the first row among them, and up to the plurality of A m-th scanning line electrically connected to n pixels arranged in the m-th row among the plurality of pixels, and A first pulse output circuit electrically connected to the first scanning line, and up to the m-th pulse output circuit Electrically connected to the m-th scanning line, and has a k-th pulse output circuit (k is A natural number of 2 or more and less than m), one of the source and drain is electrically connected to a wiring that supplies a clock signal And the other of the source and drain is electrically connected to the (k + 1)-th pulse output circuit A first transistor, and one of the source and drain is electrically connected to the wiring that supplies the clock signal or Is electrically connected to a wiring that supplies a fixed potential, and the other of the source and drain is electrically connected to the k-th A second transistor electrically connected to the scanning line, and from the (k - 1)-th pulse output circuit According to the input signal, a control circuit that controls the potential of the gate of the first transistor and the potential of the gate of the second transistor Is a display device having

[0009] In this specification and the like, for those explicitly described as singular, it is desirable that they are singular. However, it is not limited to this, and it is also possible to be plural. Similarly For those explicitly described as plural, it is desirable that they are plural. However, it is not limited to this, and it is also possible to be singular. In this specification and the like, terms such as first, second, and third refer to various elements, members, regions, layers, And the like, and are used for the purpose of distinguishing one element, member, region, layer, etc. from another element, member, region, layer, etc.

[0010] And are used for the purpose of distinguishing one element, member, region, layer, etc. from another element, member, region, layer, etc. It is used to describe a region separately from others. Therefore, terms such as first, second, third, etc. do not limit the number of elements, members, regions, layers, areas, etc. Further, for example it is possible to replace "the first" with "the second" or "the third", etc.

Advantages of the Invention

[0011] In a display device according to one embodiment of the present invention, it is possible to independently control the shift of a selection signal in a shift register included in a scanning line driving circuit and the supply of the selection signal to a scanning line. Therefore, it is possible to selectively supply a selection signal to each of a plurality of scanning lines. That is, a display device according to one aspect of the present invention can rewrite an image only for an arbitrary region.

[0012] Also, a display device according to one aspect of the present invention can realize the above operation by providing a wiring for supplying a clock signal or a signal indicating a fixed potential. Therefore, a display device according to one aspect of the present invention is a display device capable of partial driving, but can simplify the circuit configuration including the wiring.

Brief Description of the Drawings

[0013] [Figure 1] (A) A diagram showing an example of a display device, (B) A circuit diagram showing an example of a pixel. [Figure 2] (A) A diagram showing a configuration example of a scanning line driving circuit, (B) A timing chart showing an operation example of the scanning line driving circuit, (C) A diagram showing a configuration example of a pulse output circuit. [Figure 3] (A) A circuit diagram showing an example of a pulse output circuit, (B), (C) Timing charts showing an example of the operation of the pulse output circuit. [Figure 4] A diagram showing a configuration example of a controller. [Figure 5] ​​​​​​A cross-sectional view showing an example of a transistor. [Figure 6] A diagram showing the characteristics of a transistor. [Figure 7] Circuit diagram of a component used for evaluating the characteristics of transistors. [Figure 8] Timing chart for transistor characteristic evaluation elements. [Figure 9] A diagram showing the characteristics of a transistor. [Figure 10] A diagram showing the characteristics of a transistor. [Figure 11] A diagram showing the characteristics of a transistor. [Figure 12] (A), (B) Circuit diagrams showing examples of pulse output circuits. [Figure 13] (A), (B) Circuit diagrams showing examples of pulse output circuits. [Figure 14] (A), (B) Circuit diagrams showing examples of pulse output circuits. [Figure 15] (A) to (C) Cross-sectional views showing an example of a transistor. [Figure 16] (A) to (F) Diagrams showing examples of electronic devices. [Modes for carrying out the invention]

[0014] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention The present invention is not limited to the following description, and its form may not depart from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the details can be modified in various ways. Therefore, The present invention is not limited to the embodiments described below.

[0015] (Regarding an example of a display device) In the following, a display device according to one aspect of the present invention will be described with reference to Figures 1 to 16.

[0016] Figure 1(A) shows an example of the configuration of a display device. The display device shown in Figure 1(A) has pixels The unit 10, the scan line drive circuit 11, the signal line drive circuit 12, and the controller 13, each m lines (m) are arranged in parallel or nearly parallel and whose potential is controlled by the scan line drive circuit 11. The scan lines 14 (which are 2 or more natural numbers) and the signal lines, each arranged in parallel or approximately parallel to the others. The potential of n signal lines 15 (where n is a natural number greater than or equal to 2) is controlled by the dynamic circuit 12, It has. Furthermore, the pixel section 10 has a plurality of pixels 16 arranged in a matrix (m rows and n columns). It has. Each scan line 14 is one of a plurality of pixels 16 arranged in a matrix. Multiple pixels 16 arranged in any row are electrically connected, and each signal line 15 is connected to a matrix Among the multiple pixels 16 arranged in a spiral shape, multiple pixels 16 arranged in any row are charged They are electrically connected. In addition, the scan line drive circuit 11 receives the scan line drive cycle from the controller 13. Road start signal (GSP), scan line drive circuit clock signal (GCK), scan line drive circuit Signals such as the Path Part Clock (PGCK), and the high power supply potential (Vdd) and low power supply potential. Power supplies such as (Vss) are input to drive the signal line. In addition, the signal line drive circuit 12 has a controller From Ra13, start signal (SP) for signal line drive circuit, clock signal (S) for signal line drive circuit. Signals such as CK, data signals (DATA), and high power supply potential (Vdd), low power supply potential ( Power supplies such as Vss are input to drive the device.

[0017] Figure 1(B) is a diagram showing an example of a circuit diagram of the pixel 16 of the display device shown in Figure 1(A). Yes. Pixel 16, shown in Figure 1(B), has a gate electrically connected to the scan line 14, and a source and One of the drains of the transistor 17 is electrically connected to the signal line 15, and one of the electrodes is The source and the other of the drain of transistor 17 are electrically connected, and the other electrode is capacitive. A capacitive element 18 electrically connected to a wiring (also called a capacitance line) that supplies capacitance, and one electrode (also called pixel electrodes) are the source and drain of transistor 17 and the other side of capacitive element 18 One electrode is electrically connected to the other electrode (also called the counter electrode), and the other electrode supplies the counter potential. It has a liquid crystal element 19 electrically connected to the wiring, and a transistor 17 is n It is a channel-type transistor. Furthermore, the capacitance potential and the counter potential can be made to be the same potential. It is possible.

[0018] (Example of the configuration of the scan line drive circuit 11) Figure 2(A) shows an example of the configuration of the scan line driving circuit 11 of the display device shown in Figure 1(A). This is a diagram. The scan line drive circuit 11 shown in Figure 2(A) is a clock signal for the first scan line drive circuit. Wiring supplying the signal (GCK1) or the clock signal (GCK4) for the fourth scan line drive circuit The wiring to be supplied and the wiring that supplies the partial clock signal (PGCK1) for the first scan line drive circuit. Wiring supplying a partial clock signal (PGCK4) for the line or fourth scan line drive circuit, and one line A first pulse output circuit 20_1, or, electrically connected to the scan line 14 arranged in the eye, The mth pulse output circuit 20_m is electrically connected to the scan line 14 located in the mth row, It has.

[0019] Figure 2(B) shows an example of a specific waveform of the above signal. The first signal shown in Figure 2(B) The clock signal (GCK1) for the scan line drive circuit periodically reaches a high potential (Figure 2(B) ) In this case, the high power supply potential (Vdd) is equivalent to the low level potential (Figure 2(B), the low power supply This is a signal with a duty cycle of 1 / 2 that repeatedly cycles between potential (Vss) and equipotential. The clock signal for the second scan line drive circuit (GCK2) is the same as the clock signal for the first scan line drive circuit. This signal is phase-shifted by 1 / 4 period from signal (GCK1). Also, the third scan line drive circuit The clock signal (GCK3) is derived from the clock signal (GCK1) for the first scan line drive circuit. This is a signal with a phase shift of 1 / 2 period (i.e., the clock signal for the first scan line drive circuit). This is the inverted signal of GCK1). Also, the clock signal for the fourth scan line drive circuit (GCK4). ) is a signal that is 3 / 4 period out of phase from the clock signal for the first scan line drive circuit (GCK1). This is the inverted signal of the clock signal for the second scan line drive circuit (GCK2). The partial clock signal (PGCK1) for the first scan line drive circuit is used for the first scan line drive circuit. The circuit clock signal (GCK1) and fixed potential (in Figure 2(B), the low power supply potential (Vss) and This is a signal that selectively indicates either of the following (equal potential). Note that the partial chromatic oscillator for the first scan line drive circuit The control determines which signal (GCK1 or fixed potential) the ping signal (PGCK1) represents. - Controlled by 13. Similarly, a partial clock signal (PG) for the second scan line drive circuit. CK2) is either the clock signal for the second scan line drive circuit (GCK2) or a fixed potential. This is a signal that selectively indicates, and the third scan line drive circuit partial clock signal (PGCK3) is , selectively using either the clock signal (GCK3) for the third scan line drive circuit or a fixed potential. The signal shown is the partial clock signal for the fourth scan line drive circuit (PGCK4), which is the fourth scan line drive A signal that selectively indicates either the clock signal (GCK4) for the probe drive circuit or a fixed potential. be.

[0020] In the display device described above, the first pulse output circuit 20_1 to the mth pulse output circuit Circuit 20_m can be used with circuits having the same configuration. However, the pulse output cycle The electrical connections between the multiple terminals of a circuit differ for each pulse output circuit. Specific connections The relationship will be explained with reference to Figures 2(A) and (C).

[0021] Each of the first pulse output circuit 20_1 to the mth pulse output circuit 20_m has terminals It has terminals 21 to 28. Note that terminals 21 to 25 and terminal 27 are input terminals, and terminal 28 is an input terminal. Child 26 and terminal 28 are output terminals.

[0022] First, let's discuss terminal 21. Terminal 21 of the first pulse output circuit 20_1 is a scan line Electrically connected to the wiring that supplies the start signal (GSP) for the drive circuit, and the second pulse output Terminal 21 of the pulse output circuit 20_m of the force circuit 20_2 is connected to the preceding pulse output circuit. It is electrically connected to terminal 28.

[0023] Next, we will discuss terminal 22. The pulse output circuit of the 4a+1 (a=0, 1, 2...) Terminal 22 of (m-4) / 4) supplies the clock signal (GCK1) for the first scan line drive circuit. Electrically connected to the supply wiring, terminal 22 of the 4a+2 pulse output circuit is the second scan Electrically connected to the wiring that supplies the clock signal (GCK2) for the line drive circuit, and 4a+3 Terminal 22 of the pulse output circuit supplies the clock signal (GCK3) for the third scan line drive circuit. Electrically connected to the supply wiring, terminal 22 of the 4a+4 pulse output circuit is the 4th scan It is electrically connected to the wiring that supplies the clock signal (GCK4) for the line drive circuit.

[0024] Next, we will discuss terminal 23. Terminal 23 of the pulse output circuit of 4a+1 is the second It is electrically connected to the wiring that supplies the clock signal (GCK2) for the scan line drive circuit, and is part of 4a Terminal 23 of the +2 pulse output circuit receives the clock signal (GCK3) for the third scan line drive circuit. The wiring that supplies the pulses is electrically connected, and terminal 23 of the 4a+3 pulse output circuit is the 4 It is electrically connected to the wiring that supplies the clock signal (GCK4) for the scan line drive circuit, and is part 4a Terminal 23 of the +4 pulse output circuit receives the clock signal (GCK1) for the first scan line drive circuit. It is electrically connected to the wiring that supplies power.

[0025] Next, we will discuss terminal 24. Terminal 24 of the pulse output circuit of 4a+1 is the third It is electrically connected to the wiring that supplies the clock signal (GCK3) for the scan line drive circuit, and is part of 4a Terminal 24 of the +2 pulse output circuit receives the clock signal (GCK4) for the fourth scan line drive circuit. The wiring that supplies the pulses is electrically connected, and terminal 24 of the 4a+3 pulse output circuit is the first It is electrically connected to the wiring that supplies the clock signal (GCK1) for the scan line drive circuit, and is part of the 4a Terminal 24 of the +4 pulse output circuit receives the clock signal (GCK2) for the second scan line drive circuit. It is electrically connected to the wiring that supplies power.

[0026] Next, we will discuss terminal 25. Terminal 25 of the 4a+1 pulse output circuit is the first It is electrically connected to the wiring that supplies the partial clock signal (PGCK1) for the scan line drive circuit, Terminal 25 of the pulse output circuit of 4a+2 is for the partial clock signal for the second scan line drive circuit. It is electrically connected to the wiring supplying PGCK2) and terminal 2 of the 4a+3 pulse output circuit. 5 supplies electrical wiring to the third scan line drive circuit's partial clock signal (PGCK3). The terminal 25 of the 4a+4 pulse output circuit is connected to the portion for the 4th scan line drive circuit. It is electrically connected to the wiring that supplies the lock signal (PGCK4).

[0027] Next, we will discuss terminal 26. The xth pulse output circuit (where x is between 1 and m) is a natural pulse output circuit between 1 and m. Terminal 26 of the number is electrically connected to the scan line 14 located in row x.

[0028] Next, we will discuss terminal 27. The pulse output circuit of type b (where b is between 1 and m-2) Terminal 27 (natural number) is electrically connected to terminal 28 of the b+2 pulse output circuit, and the m Terminal 27 of the pulse output circuit of -1 is for the stop signal (GSTP1) for the first scan line drive circuit. The terminal 27 of the mth pulse output circuit is electrically connected to the wiring that supplies the second scan It is electrically connected to the wiring that supplies the stop signal (GSTP2) for the line drive circuit. The stop signal (GSTP1) for the first scan line drive circuit is, hypothetically, the m+1th pulse output circuit. If provided, the signal output from terminal 28 of the m+1 pulse output circuit will be in phase This is the corresponding signal. Similarly, the stop signal for the second scan line drive circuit (GSTP2) is provisional. If a pulse output circuit of the (m+2)th order is provided, then the terminal of the (m+2)th pulse output circuit These are signals corresponding to the signals output from 28. Specifically, these signals are actually... The Mie circuit includes a pulse output circuit for the m+1th and a pulse output circuit for the m+2th. Alternatively, the controller 13 may directly output the signal to the scan line drive circuit 11. It can be supplied.

[0029] The connection relationships of terminal 28 of each pulse output circuit have already been described. Therefore, the explanation above will not be used here. We will use this as a reference.

[0030] (Example of a pulse output circuit configuration) Figure 3(A) shows an example of the configuration of the pulse output circuit shown in Figures 2(A) and (C). The pulse output circuit shown in 3(A) has transistors 31 to 41.

[0031] Transistor 31 has a source and drain that supply a high power supply potential (Vdd). It is electrically connected to the wire (hereinafter also referred to as the high power potential wire), and the gate is electrically connected to terminal 21. It will continue.

[0032] Transistor 32 has a source and drain that supply a low power supply potential (Vss). It is electrically connected to a wire (hereinafter also referred to as a low power potential wire), and the source and the other drain are connected to It is electrically connected to the source and the other drain of the transistor 31.

[0033] Transistor 33 has one of its sources and drains electrically connected to terminal 22, The other end of the pipe and drain is electrically connected to terminal 28.

[0034] Transistor 34 has one of its sources and drains electrically connected to a low power supply potential line. The source and the other drain are electrically connected to terminal 28, and the gate is of transistor 32. It is electrically connected to the gate.

[0035] Transistor 35 has one of its sources and drains electrically connected to a low power supply potential line. The source and the other drain are connected to the gate of transistor 32 and the gate of transistor 34. They are electrically connected, and the gate is electrically connected to terminal 21.

[0036] Transistor 36 has one of its sources and drains electrically connected to a high power supply potential line. The source and the other drain are the gate of transistor 32, the gate of transistor 34, and the other. The source and drain of transistor 35 are electrically connected to the other, and the gate is at terminal 2 It is electrically connected to 7. Note that one of the source and drain of transistor 36 is low current. A power supply that is at a higher potential than the source potential (Vss) and at a lower potential than the high power supply potential (Vdd). It can also be configured to be electrically connected to the wiring that supplies the electric potential (Vcc).

[0037] Transistor 37 has one of its sources and drains electrically connected to a high power supply potential line. The gate is electrically connected to terminal 24. Note that the source and drain of transistor 37 are also connected. One of them can also be configured to be electrically connected to the wiring that supplies the power potential (Vcc). Cut.

[0038] Transistor 38 has one of its sources and drains connected to the gate of transistor 32. The gate of transistor 34, the source and drain of transistor 35, and the other of the transistors The other end of the source and drain of the 36 is electrically connected, and the other end of the source and drain is The source and drain of the transistor 37 are electrically connected to the other, and the gate is electrically connected to terminal 23. They are connected by air.

[0039] Transistor 39 has one of its sources and drains connected to the source and drain of transistor 31. The other side of the input and the other side of the source and drain of transistor 32 are electrically connected, The other end of the drain and the other end of the transistor 33 are electrically connected to the gate, and the gate is high voltage It is electrically connected to the source potential line.

[0040] Transistor 40 has one of its sources and drains electrically connected to terminal 25, The other end of the drain is electrically connected to terminal 26, and the gate is connected to the gate of transistor 33. It is electrically connected to the source and drain of transistor 39.

[0041] Transistor 41 has one of its sources and drains electrically connected to a low power supply potential line. The source and the other drain are electrically connected to terminal 26, and the gate is of transistor 32 The gate, the gate of transistor 34, the source and drain of transistor 35, and the other side. The source and drain of transistor 36, and the other of transistor 38 It is electrically connected to one of the inputs.

[0042] In the following, the gate of transistor 33, the source and the drive of transistor 39 are used. The other end of the rainbow, and the node to which the gate of transistor 40 is electrically connected, is called node A. The gate of transistor 32, the gate of transistor 34, and the source of transistor 35 and the other side of the drain, the other side of the source and drain of transistor 36, transistor 38 The source and drain of the transistor, as well as the gate of transistor 41, are electrically connected to the No. Let's explain node B.

[0043] (Example of pulse output circuit operation) An example of the operation of the pulse output circuit described above will be explained with reference to Figures 3(B) and (C). Oh, Figure 3(B) shows the first scan line drive circuit, which is input to terminal 25 of the pulse output circuit. Partial clock signal for use (PGCK1) ~ Partial clock signal for the fourth scan line drive circuit (PGC Any one of K4) is the clock signal for the first scan line drive circuit (GCK1) to the fourth scan line drive circuit. Pulse output circuit when any of the line drive circuit clock signals (GCK4) are one. The diagram shows the potential of the signals input to each terminal, as well as the potentials of nodes A and B. 3(C) is the portion for the first scan line drive circuit that is input to terminal 25 of the pulse output circuit. Clock signal (PGCK1) to partial clock signal for the fourth scan line drive circuit (PGCK4) When any one of the following becomes a fixed potential (low power supply potential Vss), each of the pulse output circuits This shows the potential of the signal input to the terminal, as well as the potentials of nodes A and B. In Figures 3(B) and (C), the first pulse output circuit 20_1 under each respective condition is shown. The signals input to each terminal and the output from terminal 26 of the first pulse output circuit 20_1 The signal (Gout1) and the signal output from terminal 28 (SRout1) are indicated in parentheses. In addition, the output signal (Gout2) of terminal 26 of the second pulse output circuit 20_2 and The output signal (SRout2) of terminal 28, and terminal 2 of the third pulse output circuit 20_3. The output signal of terminal 6 (Gout3) and the output signal of terminal 28 (SRout3 = first pulse output) The input signal of terminal 27 of circuit 20_1 is also noted. Note that in the diagram, Gout is , represents the output signal for the scan line of the pulse output circuit, and SRout is the pulse output circuit This represents the output signal to the subsequent pulse output circuit.

[0044] First, referring to Figure 3(B), the first pulse input to terminal 25 of the pulse output circuit is Partial clock signal for scan line drive circuit (PGCK1) ~ Partial clock for the 4th scan line drive circuit Any one of the signals (PGCK4) is the clock signal (GCK1) for the first scan line drive circuit. ~Explanation of the case where it is one of the clock signals for the fourth scan line drive circuit (GCK4) I will reveal it.

[0045] During period t1, a high power supply potential (Vdd) is input to terminal 21 of the pulse output circuit. This causes transistors 31 and 35 to turn on. Therefore, the potential of node A is The level potential (from the high power supply potential (Vdd) to transistor 31 or transistor 39) The potential rises to a level (lowered by the key voltage), and the potential of node B drops to the low power supply potential (Vss). It turns down. Consequently, transistors 33 and 40 turn on, and transistor 32 , 34 and 41 are turned off. As a result, during period t1, the pulse output circuit The signal output from terminal 28 becomes the signal input to terminal 22, and is output from terminal 26. The signal is the signal input to terminal 25. Here, during period t1, the pulse The signals input to terminals 22 and 25 of the output circuit are both at the low power supply potential (Vss). Therefore, during period t1, the pulse output circuit is connected to terminal 2 of the subsequent pulse output circuit. 1. A low power supply potential (Vss) is output to the scan line electrically connected to terminal 26. Although it does not directly affect the output signal of the pulse output circuit during period t1, terminal 23 is low Because the power supply potential (Vss) is input, transistor 38 is in the off state, and high voltage is applied to terminal 24. Because the power supply potential (Vdd) is input, transistor 37 turns ON, and low voltage is applied to terminal 27. Because the power supply potential (Vss) is input, transistor 36 is in the off state.

[0046] During period t2, the high power supply potential (Vdd) is present at terminals 22 and 25 of the pulse output circuit. The input is received. Note that the potential of node A (the potential of the source of transistor 39) is set during period t1. The potential rises to a high level. Therefore, transistor 39 is in the off state. At this time, a high power supply potential (Vdd) is input to terminals 22 and 25, Capacitive coupling between the source and gate of transistor 33 and the source and gate of transistor 40 Therefore, the potential of node A (the potential of the gates of transistor 33 and transistor 40) The position rises further (bootstrap action). Also, the bootstrap action is performed By doing so, the potential output from terminals 28 and 26 is not reduced, and high power The source potential (Vdd) can be set. Therefore, in period t2, the pulse output cycle The path is connected to the scanning line electrically connected to terminals 21 and 26 of the subsequent pulse output circuit. The power supply potential (Vdd) is output. Note that this is the output signal of the pulse output circuit during period t2. Although it is not directly involved, a low power supply potential (Vss) is input to terminal 24, so the transistor 37 will be in the off state.

[0047] During period t3, a low power supply potential (Vss) is input to terminal 21 of the pulse output circuit. This causes transistors 31 and 35 to turn off. At this time, node A is in a floating state. To maintain this state, transistors 33 and 40 remain in the ON state. As described above, during period t3, the signal output from terminal 28 of the pulse output circuit is terminal The signal input to child 22, and the signal output from terminal 26, are input to terminal 25. This becomes a signal. Here, during period t3, terminals 22 and 25 of the pulse output circuit Both are input to a high power supply potential (Vdd). Therefore, during period t3, the pulse The output circuit is electrically connected to terminals 21 and 26 of the subsequent pulse output circuit. The line outputs a high power supply potential (Vdd). Note that the output of the pulse output circuit during period t3 Although it does not directly participate in the power signal, a high power supply potential (Vdd) is input to terminal 23, so the transistor The Zista 38 will be turned on.

[0048] During period t4, a high power supply potential (Vdd) is present at terminals 24 and 27 of the pulse output circuit. The input is received. This turns on transistors 36 and 37. Therefore, the node The potential of B is a high level potential (high power supply potential (Vdd) from transistor 36, transistor The potential rises to a level lowered by the threshold voltage of transistor 37 or transistor 38. Then, transistors 32, 34, and 41 turn on. Furthermore, transistor 32 turns off When this state is reached, the power to the source (either the source or the drain) of transistor 39 The voltage level becomes the low power supply potential (Vss). This causes transistor 39 to turn on. Therefore, the potential of node A drops to the low power supply potential (Vss). In conjunction with this, the transient The terminals 33 and 40 are turned off. As a result, during period t4, the pulse output circuit The signals output from terminal 28 and terminal 26 are at low power supply potential (Vss ) Therefore, during period t4, the pulse output circuit becomes the subsequent pulse output circuit A low power supply potential (Vss) is output to the scan lines electrically connected to terminals 21 and 26. ru.

[0049] During period t5 and beyond, a high power supply potential (Vdd) is input to terminal 21 of the pulse output circuit. Until then, node A maintains a low power potential (Vss), and node B maintains a high potential. To maintain. Therefore, during that period, the pulse output circuit is the subsequent pulse output circuit. A low power supply potential (Vss) is output to the scan lines electrically connected to terminals 21 and 26. ru.

[0050] Next, referring to Figure 3(C), the first input to terminal 25 of the pulse output circuit Partial clock signal for scan line drive circuit (PGCK1) ~ Partial clock for 4th scan line drive circuit When any one of the signals (PGCK4) is at a fixed potential (low power supply potential Vss) I will explain.

[0051] During period t1, a high power supply potential (Vdd) is input to terminal 21 of the pulse output circuit. As described above, during period t1, the signal output from terminal 28 of the pulse output circuit This becomes the signal input to terminal 22, and the signal output from terminal 26 is input to terminal 25. The signal is then generated. Here, during period t1, terminal 22 and terminal of the pulse output circuit The signals input to 25 are both at the low power supply potential (Vss). Therefore, during period t1, The pulse output circuit then electrically connects terminals 21 and 26 of the subsequent pulse output circuit. It outputs a low power supply potential (Vss) to the connected scan line.

[0052] During period t2, a high power supply potential (Vdd) is input to terminal 22 of the pulse output circuit. As described above, by performing the bootstrap operation, the power output from terminal 28 It is possible to achieve a high power supply potential (Vdd) without lowering the voltage. However, as mentioned above... Contrary to the description, the signal input to terminal 25 does not change from the low power supply potential (Vss). Therefore, the signal output from terminal 26 of the pulse output circuit remains at the low power supply potential (Vss). It even goes that far.

[0053] During period t3, a low power supply potential (Vss) is input to terminal 21 of the pulse output circuit. As described above, during period t3, the signal output from terminal 28 of the pulse output circuit This becomes the signal input to terminal 22, and the signal output from terminal 26 is input to terminal 25. This becomes the signal. Here, during period t3, high current is supplied to terminal 22 of the pulse output circuit. The power supply potential (Vdd) is input, and the low power supply potential (Vss) is input to terminal 25. Therefore, during period t3, the pulse output circuit sends high current to terminal 21 of the subsequent pulse output circuit. It outputs the source potential (Vdd) and supplies a low power supply potential (Vss) to the scan line electrically connected to terminal 26. Outputs ).

[0054] During period t4, a high power supply potential (Vdd) is present at terminals 24 and 27 of the pulse output circuit. It is input. As described above, during period t4, it is output from terminal 28 of the pulse output circuit. The powered signal and the signal output from terminal 26 will be at a low power supply potential (Vss). Therefore, during period t4, the pulse output circuit is connected to terminal 21 of the subsequent pulse output circuit, A low power supply potential (Vss) is output to the scan line electrically connected to terminal 26.

[0055] During period t5 and beyond, a high power supply potential (Vdd) is input to terminal 21 of the pulse output circuit. Until then, node A maintains a low power potential (Vss), and node B maintains a high potential. To maintain. Therefore, during that period, the pulse output circuit is the subsequent pulse output circuit. A low power supply potential (Vss) is output to the scan lines electrically connected to terminals 21 and 26. ru.

[0056] (Regarding the pulse output circuit and the scanning line drive circuit having said pulse output circuit) In the pulse output circuit described above, the period t2 and period are determined according to the signal input to terminal 25. At t3, it is selected whether or not to output a selection signal (high power supply potential (Vdd)) to the scan line. Specifically, the pulse output circuit is configured such that the signal input to terminal 25 corresponds to the first scan line drive cycle. If it is a circuit clock signal, it outputs a selection signal and a fixed potential (low power supply potential (Vss)). In that case, it is a circuit that outputs a non-selected signal. Furthermore, the pulse output circuit is as described above. It also has the function of shifting the selection signal to the subsequent pulse output circuit, regardless of its operation. Furthermore, by using multiple such pulse output circuits, it is possible to construct a shift register. ru.

[0057] The display device disclosed herein has a scan line drive circuit that includes the shift register. Therefore, the display device can control the supply of selection signals for each scan line. Furthermore, the display device disclosed herein performs image rewriting only in any region. It is a display device capable of doing so.

[0058] Furthermore, the display device disclosed herein performs the above operation using a first scan line drive circuit. Wiring that supplies a signal indicating a GCK1 or fixed potential (low power supply potential (Vss)). ~Clock signal for the fourth scan line drive circuit (GCK4) or fixed potential (low power supply potential (Vss This can be achieved by providing wiring that supplies a signal indicating ). Therefore, the display device disclosed herein is a partially driven display device, and does not require wiring. This is a display device that allows for a simplified configuration of the included circuitry.

[0059] Note that the choice of supplying a clock signal or a fixed potential to the wiring is determined by Controller 1. It is controlled by 3. The specific configuration of controller 13 and its wiring are described below. This section shows an example of how to select the output signal.

[0060] (Example configuration of controller 13) Figure 4 shows a controller with three modes: normal mode, partial drive mode, and standby mode. This figure shows an example of the configuration of roller 13. Note that the normal mode refers to the first scan line drive described above. Partial clock signal for the circuit (PGCK1) ~ Partial clock signal for the fourth scan line drive circuit (P GCK4) regardless of the period, the clock signal for the first scan line drive circuit (GCK1) to the fourth This mode uses the same signal as the clock signal (GCK4) for the scan line drive circuit. The minute drive mode refers to the partial clock signal (PGCK1) for the first scan line drive circuit described above. The fourth scan line drive circuit partial clock signal (PGCK4) is used for the first scan line drive circuit The lock signal (GCK1) is the same signal as the clock signal for the fourth scan line drive circuit (GCK4). This is a mode in which the signal is either a fixed or constant potential. Furthermore, the standby mode refers to the scanning line drive circuit 11 and the signal This is a mode in which no clock signal or other signals are supplied to the line drive circuit 12. (Figure 4 shows...) The controller 13 includes a signal generation circuit 131, a memory circuit 132, a comparison circuit 133, and a selection circuit. It has a circuit 134 and a display control circuit 135.

[0061] The signal generation circuit 131 operates the scan line drive circuit 11 and the signal line drive circuit 12, and pixels This is a circuit that generates signals for forming an image in part 10. Specifically, it generates signals for forming an image in the pixel part 10. Image signals (Data) input to multiple pixels arranged in a trix pattern, scan line drive A signal that controls the operation of the drive circuit 11 or the signal line drive circuit 12 (for example, a start signal (SP ), clock signals (CK, etc.), and power supply voltages, such as high power supply potential (Vdd) and low power supply voltage. This is a circuit that generates and outputs the source potential (Vss), etc. Note that the controller 1 shown in Figure 4 is... In step 3, the signal generation circuit 131 sends an image signal (Data) to the memory circuit 132. Outputs and controls the operation of the scan line drive circuit 11 or signal line drive circuit 12 to the display control circuit 135. It outputs a control signal. It also outputs from the signal generation circuit 131 to the memory circuit 132. If the image signal (Data) being processed is an analog signal, an A / D converter or similar device is used. Furthermore, the image signal (Data) can be converted into a digital signal.

[0062] The memory circuit 132 processes an image signal to form a first image in the pixel section 10. Multiple memories 13 for storing image signals to form an image of n (where n is a natural number) It has 6. Note that memory 136 is DRAM (Dynamic Random Acc ess Memory), SRAM (Static Random Access Me It can be constructed using memory elements such as mory. Also, the memory 136 is the pixel section 10 Any configuration that stores an image signal for each image formed in the memory 136 is sufficient, and the number of memory 136 is It is not limited to a specific number. In addition, the image signals stored in multiple memories 136 are compared multiple times. The data is selectively read by path 133 and selection circuit 134.

[0063] The comparison circuit 133 compares the k-th image (where k is between 1 and n) stored in the memory circuit 132. Selectively forming an image signal for the natural number and an image signal for forming k+1 images This circuit reads out the image signals, compares them, and detects the difference. The image and the image of k+1 are images that are displayed consecutively in the pixel section 10. Comparison circuit The difference is detected by comparing the image signals at 133. Based on this difference, controller 1 It is determined whether mode 3 is normal mode, partial drive mode, or standby mode. ru.

[0064] The selection circuit 134, based on the difference detected by the comparison circuit 133, outputs an image signal to the pixel unit 10. This is a circuit that selects the output. Specifically, the selection circuit 134 is normally controlled by the comparison circuit 133. If it is determined to be a mode, it outputs an image signal for one frame, and if it is determined to be a partial drive mode... If it is determined to be in standby mode, it will selectively output an image signal, and if it is determined to be in standby mode, it will not output an image signal. It is a circuit.

[0065] The display control circuit 135 receives the start signal (SP), the clock signal (CK), and the high power supply potential ( Scan line drive circuit 11 and signal line drive for control signals such as Vdd and low power supply potential (Vss) This is a circuit that controls the supply to the power circuit 12.

[0066] Specifically, if the comparison circuit 133 determines that it is in normal mode, the selection circuit 134 The image signal (Data) supplied from is output to the signal line drive circuit 12, and the scan line Control signals (start signal (SP), crossover signal) are applied to the drive circuit 11 and the signal line drive circuit 12. It supplies the CK signal (CK), high power potential (Vdd), and low power potential (Vss), etc. At this time, the first scan line drive circuit partial crossover supplied to the scan line drive circuit 11 The clock signal (PGCK1) to the partial clock signal (PGCK4) for the fourth scan line drive circuit are as follows: The clock signal for the first scan line drive circuit (GCK1) to the fourth scan line drive clock signal (GCK1) This will be the same signal as CK4).

[0067] Furthermore, if the comparison circuit 133 determines that it is in partial drive mode, the selection circuit 134 The supplied image signal (Data) is selectively output to the signal line drive circuit 12, Control signals (start signal (SP)) are applied to the scan line drive circuit 11 and the signal line drive circuit 12. (and other signals such as the clock signal (CK), high power supply potential (Vdd), and low power supply potential (Vss) are supplied.) It supplies. At this time, the first part for the scan line drive circuit is supplied to the scan line drive circuit 11. Clock signal (PGCK1) to partial clock signal for the fourth scan line drive circuit (PGCK4) This selectively outputs image signals (Data) and controls the first scan line drive circuit's clock. The clock signal (GCK1) is the same signal as the clock signal (GCK4) for the fourth scan line drive circuit. This becomes a signal that selectively indicates a fixed potential.

[0068] Furthermore, if the comparison circuit 133 determines that the mode is standby, the selection circuit 134 will output an image. The image signal (Data) is not supplied, and the scan line drive circuit 11 and the signal line drive circuit 1 2. Control signals (start pulse signal (SP), clock signal (CK), high power supply It does not supply a voltage (Vdd) and a low power supply potential (Vss), etc. That is, the comparison circuit 13 If it is determined by 3 that it is in standby mode, the scan line drive circuit 11 and the signal line drive circuit 12 Completely stop its operation.

[0069] However, if the period determined to be in standby mode is short, the high power supply potential (Vdd) and low power supply may be used. It is also possible to configure the system to continuously supply the source potential (Vss). And when a low power supply potential (Vss) is supplied, it means that the potential of a certain wire is high power supply potential (Vdd) or This means that the power supply is fixed at a low potential (Vss). Therefore, the power supply in a certain potential state The line will change to either a high power supply potential (Vdd) or a low power supply potential (Vss). Because changes in this voltage are accompanied by power consumption, high power supply potential (Vdd) and low power supply potential (Vss) are frequently used. By stopping and restarting the supply, power consumption may increase as a result. In such cases, the configuration continues to supply both a high power potential (Vdd) and a low power potential (Vss). It is preferable to do so. In the above explanation, "not supplying a signal" means the In wiring that supplies a signal, a potential different from a predetermined potential is supplied, or electricity is supplied to the wiring. This refers to a state where nodes connected by air are floating.

[0070] Furthermore, if the standby mode is prolonged, or if the vehicle is included in a specific area in the partial drive mode, If the indicator line remains in a non-selective state for a long period of time, the liquid crystal element 19 will remain in a direct position for a long period of time. A current voltage will continue to be applied. This could cause burnout. Therefore, regardless of the mode, the voltage applied to the liquid crystal element at predetermined frame intervals or predetermined time intervals is polar It is preferable to reverse the gender.

[0071] In the controller 13, as described above, the scan line drive circuit 11 and the signal line drive circuit 1 By controlling the operation of step 2, it is possible to reduce the power consumption of the display device.

[0072] (An example of a transistor 17 provided in pixel 16) The transistor 17 provided in the pixel 16 of the above-mentioned display device remains in an off state for a long period of time. It may maintain the state. Therefore, transistor 17 is selected, which has excellent off-characteristics (off A transistor with low current is preferred. In the following, transistor 17 is preferred. An example of a transistor will be explained with reference to Figure 5. Specifically, it comprises an oxide semiconductor layer. The transistor is described below. The transistor has a high purity oxide semiconductor layer. By doing so, it is possible to drastically reduce the off-current (details below). Therefore, it is possible that an image signal may not be input to a particular pixel for an extended period of time, as disclosed herein. A preferred transistor is the transistor 17 provided in the pixel 16 of the display device. Yes, it is possible to construct the aforementioned pulse output circuit using the transistor in question. In other words, these transistors can also be used as transistors 31 to 41. In this case, cost reduction and yield improvement can be achieved by reducing the number of manufacturing processes.

[0073] The transistor 211 shown in Figure 5 is a gate provided on a substrate 220 having an insulating surface. Layer 221, gate insulating layer 222 provided on gate layer 221, and gate insulating layer 222 An oxide semiconductor layer 223 provided on top, and a source layer provided on the oxide semiconductor layer 223 It has 224a and a drain layer 224b. Also, in Figure 5, transistor 21 An insulating layer 225 that covers 1 and is in contact with the oxide semiconductor layer 223, and provided on the insulating layer 225 A protective insulating layer 226 is shown in the diagram.

[0074] As described above, the transistor 211 shown in Figure 5 has an oxide semiconductor layer 223 as its semiconductor layer. It is equipped with the following. The oxide semiconductor used in the oxide semiconductor layer 223 is a quaternary metal oxide. In-Sn-Ga-Zn-O system, a ternary metal oxide, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-G a-Zn-O system, Sn-Al-Zn-O system, and binary metal oxide system In-Zn-O system. Sn-Zn-O series, Al-Zn-O series, Zn-Mg-O series, Sn-Mg-O series, In-M gO-based, or single-system metal oxides such as In-O-based, Sn-O-based, and Zn-O-based are used. It is possible to include it. Furthermore, the above oxide semiconductor may also contain SiO2. Here, for example... In-Ga-Zn-O oxide semiconductors are oxides containing at least In, Ga, and Zn. There are no particular restrictions on the composition ratio. Furthermore, it may contain elements other than In, Ga, and Zn. stomach.

[0075] Furthermore, the oxide semiconductor layer 223 has the chemical formula InMO3(ZnO) m (m>0) A thin film can be used. Here, M is selected from Ga, Al, Mn, and Co. This indicates one or more metallic elements. For example, M could be Ga, Ga and Al, Ga and Mn, Alternatively, Ga and Co can be selected.

[0076] Furthermore, when using an In-Zn-O based material as an oxide semiconductor, the target used is The composition ratio is in terms of atomic ratio, In:Zn = 50:1 to 1:2 (which converts to a mole ratio of In2O). 3:ZnO = 25:1 to 1:4), preferably In:Zn = 20:1 to 1:1 (molar ratio) Converted to this ratio, In2O3:ZnO = 10:1 to 1:2), and more preferably In:Zn = 15:1 to 1.5:1 (Converted to a mole ratio of In2O3:ZnO = 15:2 to 3:4) For example, the target used for forming In-Zn-O oxide semiconductors is the atomic ratio. When In:Zn:O=X:Y:Z, let Z>1.5X+Y.

[0077] The oxide semiconductors mentioned above suppress variations in electrical properties by reducing the presence of hydrogen and moisture, which are factors that cause these variations. By intentionally removing impurities such as hydroxyl groups or hydrides (also called hydrogen compounds), high It is a purified oxide semiconductor that has been electrically converted to type I (intrinsic).

[0078] Therefore, the less hydrogen in oxide semiconductors, the better. Also, highly purified oxide The semiconductor layer contains very few (close to zero) carriers originating from hydrogen and oxygen vacancies, etc. The carrier density is 1 × 10⁻⁶ 12 / cm 3 Less than 1 × 10 11 / cm 3 Less than In other words, the carrier density originating from hydrogen and oxygen vacancies in the oxide semiconductor layer is brought as close to zero as possible. Because there are very few carriers originating from hydrogen or oxygen vacancies in the oxide semiconductor layer, This can reduce the leakage current (off-current) when the transistor is in the off state. Furthermore, due to the low number of impurity levels derived from hydrogen and oxygen deficiencies, light irradiation, temperature changes, and This reduces fluctuations and degradation of electrical characteristics caused by the application of ignition current, etc. The less of it there is, the better. Transition using the above oxide semiconductor as a semiconductor layer The current value per 1 μm of channel width (w) is 100 zA (zeptoamperes) or less. The current is preferably 10 zA or less, and more preferably 1 zA or less. Furthermore, there is no pn junction, Because there is no degradation of the lead carrier, the electrical characteristics of the transistor are not affected by these factors. .

[0079] By thoroughly removing the hydrogen contained in the oxide semiconductor layer in this way, the purity is increased. Transistors using oxide semiconductors in the channel formation region have extremely low off-currents. This is possible. In other words, in the non-conductive state of the transistor, the oxide semiconductor layer acts as an insulator. Circuit design can be carried out by considering it in this way. On the other hand, the oxide semiconductor layer is the guide of the transistor. Under normal conditions, it is expected to have a higher current supply capability than a semiconductor layer formed from amorphous silicon. It is possible.

[0080] As the substrate 220 having an insulating surface, for example, barium borosilicate glass or alumino Glass substrates such as gynosilicate glass can be used.

[0081] In transistor 211, an insulating film that serves as the base layer is placed between the substrate 220 and the gate layer 221. It may also be provided. The undercoat has the function of preventing the diffusion of impurity elements from the substrate, and nitride Selected from silicon dioxide film, silicon oxide film, silicon nitride-oxide film, or silicon oxide-nitride film. It can be formed by a laminated structure of one or more films.

[0082] The material of the gate layer 221 is molybdenum, titanium, chromium, tantalum, tungsten, and Metal materials such as luminium, copper, neodymium, scandium, or alloys primarily composed of these materials. It can be formed using materials in a single layer or in layers.

[0083] The gate insulating layer 222 is formed using plasma CVD or sputtering, etc. Cone layer, silicon nitride layer, silicon oxide nitride layer, silicon nitride oxide layer, aluminum oxide Layer, aluminum nitride layer, aluminum oxide nitride layer, aluminum oxide nitride layer, or oxide Hafnium layers can be formed as a single layer or in stacked layers. For example, a first gate insulating layer. A silicon nitride layer (Si) with a thickness of 50 nm to 200 nm is formed by plasma CVD. N y(y>0)) is formed, and a second gate insulating layer with a thickness of 5n is applied on the first gate insulating layer. silicon oxide layer (SiO) of m or more and less than 300 nm x (x>0) can be stacked. .

[0084] Examples of conductive films used for the source layer 224a and drain layer 224b include Al and Cr. , elements selected from Cu, Ta, Ti, Mo, W, or alloys containing the above elements. Alternatively, alloy films combining the elements mentioned above can be used. Also, Al, Cu, etc. A high-melting-point metal layer such as Ti, Mo, or W is laminated on either the lower or upper side, or both, of the metal layer. It can also be used in this configuration. Furthermore, it is a source that prevents the formation of hillocks and whiskers on the Al film. Heat resistance is improved by using aluminum materials with added elements (such as Si, Nd, and Sc). This becomes possible.

[0085] Furthermore, the source layer 224a and drain layer 224b (the wiring layer formed from the same layers) The conductive film (including) may be formed from a conductive metal oxide. Examples include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO). Indium tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium oxide Zinc oxide alloy (In2O3-ZnO) or silicon oxide in these metal oxide materials A product containing this can be used.

[0086] The insulating layer 225 is typically made of silicon oxide film, silicon oxide nitride film, or aluminum oxide. A film, or an inorganic insulating film such as an aluminum oxide nitride film, can be used.

[0087] The protective insulating layer 226 can use an inorganic insulating film such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, an aluminum oxynitride film, etc.

[0088] Also, in order to reduce the surface unevenness caused by the transistor on the protective insulating layer 226, a planarizing insulating film may be formed. As the planarizing insulating film, an organic material such as polyimide, acrylic, benzocyclobutene, etc. can be used. In addition to the above organic materials, a low dielectric constant material (low-k material), etc. can also be used. Note that a planarizing insulating film may be formed by laminating a plurality of insulating films formed of these materials.

[0089] <Regarding the off-current of the transistor> Next, the results of obtaining the off-current of a transistor including a highly purified oxide semiconductor layer will be described.

[0090] First, considering that the off-current of a transistor including a highly purified oxide semiconductor layer is sufficiently small, a transistor with a sufficiently large channel width W of 1 m was prepared and the off-current was measured. The results of measuring the off-current of a transistor with a channel width W of 1 m are shown in FIG. 6. In FIG. 6, the horizontal axis is the gate voltage VG and the vertical axis is the drain current ID. When the drain voltage VD is +1 V or +10 V, in the range where the gate voltage VG is from -5 V to -20 V, it was found that the off-current of the transistor is 1×10 A or less, which is the detection limit. Also, it was found that the off-current of the transistor (here, the value per channel width of 1 μm) is 1 a A / μm (1×10 -12 A / μm) or less. -18

[0091] Next, we will further refine the off-current of the transistor equipped with a highly purified oxide semiconductor layer. The results obtained will be explained. As mentioned above, the oxide semiconductor layer is made highly purified. The off-current of the transistor is 1 × 10⁻¹⁰, which is the detection limit of the measuring instrument. -12 A or less This was discovered. Therefore, a characteristic evaluation element was fabricated to obtain a more accurate value of the off-current (for the above measurement). This section explains the results of determining values ​​below the detection limit of the measuring instrument.

[0092] First, the characteristic evaluation elements used in the current measurement method will be explained with reference to Figure 7.

[0093] The characteristic evaluation element shown in Figure 7 consists of three measurement systems 800 connected in parallel. 0 represents the capacitive element 802, transistor 804, transistor 805, and transistor 806. It has transistor 808. Transistors 804 and 808 have high purity A transistor comprising a modified oxide semiconductor layer was applied.

[0094] In the measurement system 800, one of the source and drain of transistor 804 and a capacitive element One terminal of 802 and one of the source and drain terminals of transistor 805 are connected to the power supply (V2 It is connected to the power supply that provides it. In addition, the source and drain of transistor 804 One terminal is the source and drain of transistor 808, and the other terminal is the other terminal of capacitive element 802. And it is electrically connected to the gate of transistor 805. Also, transistor 8 The other source and drain of transistor 08, and one source and drain of transistor 806 The gate of transistor 806 is electrically connected to the power supply (the power supply that provides V1). Also, the source and drain of transistor 805 and the other side of transistor 806 The other end of the drain is electrically connected to the output terminal.

[0095] The gate of transistor 804 has two states: ON state and OFF state. A control voltage Vext_b2 is supplied to the gate of transistor 808, The potential Vext_b1, which controls the ON and OFF states of the STA808, is supplied. The output terminal outputs a voltage, Vout.

[0096] Next, a method for measuring current using the above-mentioned characteristic evaluation element will be described.

[0097] First, we will briefly describe the initial period during which a potential difference is applied to measure the off-current. In the initial period, the gate of transistor 808 is set to the ON state. The potential Vext_b1 is input to the source and drain of transistor 804. The electrically connected nodes (i.e., the source and drain of transistor 808) The other terminal of the capacitive element 802 and the gate of the transistor 805 are electrically connected. A potential V1 is applied to node A, which is a node. Here, the potential V1 is, for example, a high potential. Also, keep transistor 804 in the OFF state.

[0098] Subsequently, a potential V is applied to the gate of transistor 808, which turns transistor 808 off. Enter ext_b1 to turn off transistor 808. Transistor 808 After being turned off, the potential V1 is set to a low potential. Here too, transistor 804 is in the off state. Let's assume this state. Also, let's assume that potential V2 is the same potential as potential V1. Thus, the initial period ends. Completed. In the state after the initial period has ended, the source and drain of node A and transistor 804 A potential difference is generated between one of the inputs, and also between the source and the output of node A and transistor 808. A potential difference will be created between the other side of Rain, so transistor 804 and Trans A small charge flows through the STA808. In other words, an off-current is generated.

[0099] Next, we will briefly explain the measurement period for the off-current. During the measurement period, the transistor The potential (V2) of one of the source and drain of transistor 804, and the potential of the source of transistor 808. The potential (V1) of the other side of the drain and the pipe are kept fixed at a low potential. Meanwhile, during the measurement period, The potential of node A is not fixed (it is in a floating state). This allows the transient Charge flows through sta 804 and transistor 808, and over time it is retained at node A. The amount of charge fluctuates. And, as the amount of charge held at node A fluctuates, the charge at node A changes. The position fluctuates. In other words, the output potential Vout at the output terminal also fluctuates.

[0100] Detailed information on the relationship between each potential during the initial period in which the above potential difference is applied, and during the subsequent measurement period. A detailed (timing chart) is shown in Figure 8.

[0101] In the initial period, first, the potential Vext_b2 is set when transistor 804 is in the ON state. This will result in a potential (high potential) such that the potential of node A becomes V2, i.e., a low potential. This results in VSS. Note that applying a low potential (VSS) to node A is not essential. The potential Vext_b2 is set to a potential (low potential) such that transistor 804 is in the off state. Next, turn off transistor 804. Then, set the potential Vext_b1 to Let the potential (high potential) be such that the transistor 808 is in the on state. As a result, the potential of node A becomes V1, that is, the high potential (VDD). Then, set Vext_b1 to a potential such that the trans istor 808 is in the off state. Thereby, node A becomes in a floating state, and the initial period ends.

[0102] In the subsequent measurement period, set the potential V1 and the potential V2 to be potentials such that charge flows into or out of node A. Here, set the potential V1 and the potential V2 to the low potential (VSS). However, at the timing of measuring the output potential Vout, since it is necessary to operate the output circuit, there is a case where V1 is temporarily set to the high potential (VDD). Note that the period during which V1 is at the high potential (VDD) is a short period that does not affect the measurement.

[0103] When a potential difference is applied as described above and the measurement period starts, as time passes, the amount of charge held in node A varies, and accordingly, the potential of node A varies. This means that the potential of the gate of the transistor 805 varies, so as time passes, the output terminal potential Vout of the device also changes.

[0104] A method for calculating the off-current from the obtained output potential Vout will be described below.

[0105] Prior to calculating the off-current, obtain the relationship between the potential VA of node A and the output potential Vout. Thereby, the potential VA of node A can be obtained from the output potential Vout. From the above relationship, the potential VA of node A can be expressed as a function of the output potential Vout as follows.

[0106]

number

[0107] Furthermore, the charge QA at node A is given by the potential VA at node A and the capacitance CA connected to node A. Using a constant (const), it can be expressed as follows: Here, the capacity connected to node A The quantity CA is the sum of the capacitance of the capacitive element 802 and the other capacitances.

[0108]

number

[0109] The current IA at node A is the charge flowing into node A (or the charge flowing out of node A). Since it is the time derivative of , the current IA at node A is expressed by the following equation.

[0110]

number

[0111] Thus, from the capacitance CA connected to node A and the output potential Vout of the output terminal, The current IA of code A can be calculated.

[0112] As described above, the flow between the source and drain of the transistor in the off state It can measure leakage current (off-current).

[0113] Here, a highly purified oxidation with a channel length L=10μm and a channel width W=50μm is used. A transistor 804 having a material semiconductor layer, and a transistor having a highly purified oxide semiconductor layer A transistor 808 was fabricated. In addition, in each of the parallel measurement systems 800, a capacitive element 80 Each capacitance value of 2 was set to 100 fF, 1 pF, and 3 pF.

[0114] In the above measurement, VDD = 5V and VSS = 0V. Also, during the measurement period the potential V1 was set to VSS as a principle, and every 10 to 300 seconds, Vout was measured as VDD only for a period of 100 msec. Also, the Δt used for calculating the current I flowing through the element was set to about 30000 sec. was set to about 30000 sec.

[0115] Fig. 9 shows the relationship between the elapsed time Time related to the above current measurement and the output potential Vout. From Fig. 9, it can be confirmed that the potential is changing as time passes.

[0116] Fig. 10 shows the off-current at room temperature (25°C) calculated by the above current measurement. Note that Fig. 10 represents the relationship between the source-drain voltage V of the transistor 804 or the transistor 808 and the off-current I. From Fig. 10, it was found that the off-current is about 40 zA / μm under the condition that the source-drain voltage is 4V. Also, it was found that the off-current is 10 zA / μm or less under the condition that the source-drain voltage is 3.1V. Note that 1 zA represents 10 A. -21 A.

[0117] Furthermore, Fig. 11 shows the off-current in the temperature environment of 85°C calculated by the above current measurement. Fig. 11 represents the relationship between the source-drain voltage V of the transistor 804 or the transistor 808 and the off-current I in the temperature environment of 85°C. From Fig. 11, it was found that the off-current is 100 zA / μm or less under the condition that the source-drain voltage is 3.1V. or less.

[0118] ​​Therefore, in a transistor equipped with a highly purified oxide semiconductor layer, the off-current is It was confirmed that it becomes sufficiently small.

[0119] (A modified example of a display device) The display device having the above-described configuration is one aspect of the present invention, and differs from the said display device in the following respects. Display devices are also included in the present invention.

[0120] <Modified example of a pulse output circuit> For example, as a pulse output circuit, the pulse output circuit shown in Figure 3(A) has a source and a dash. One end of the rain is electrically connected to a high power potential line, and the other end of the source and drain is a transient The gate of transistor 32, the gate of transistor 34, and the source and drain of transistor 35. On the other hand, the source and drain of transistor 36, and the source and drain of transistor 38. One of the drains, and electrically connected to the gate of transistor 41, when the gate is reset A configuration in which a transistor 50 electrically connected to the reset terminal is added (Figure 12) A) can be applied. Note that the reset terminal has a vertical retrace period. A high-level potential is input during certain periods, and a low-level potential is input during other periods. In other words, transistor 50 is an ON state during the vertical retrace period. This allows the potential of each node to be initialized during the vertical retrace period. Therefore, it becomes possible to prevent malfunctions.

[0121] Furthermore, as a pulse output circuit, from the pulse output circuit shown in Figure 3(A), a transistor It is also possible to apply a configuration with 36 removed (see Figure 12(B)). This allows the The number of transistors constituting the pulse output circuit can be reduced. Therefore, the pulse This allows for a reduction in the layout area of ​​the output circuit and an improvement in yield.

[0122] Furthermore, as a pulse output circuit, from the pulse output circuit shown in Figure 3(A), a transistor It is also possible to apply a configuration with 39 removed (see Figure 13(A)). This allows the The number of transistors constituting the pulse output circuit can be reduced. Therefore, the pulse This allows for a reduction in the layout area of ​​the output circuit and an improvement in yield.

[0123] Furthermore, as a pulse output circuit, the pulse output circuit shown in Figure 3(A) has a source and a drain. One side of the input is the gate of transistor 33 and the source and drain of transistor 39. The other side is electrically connected, and the source and drain of the other side are electrically connected to the gate of transistor 40. A transistor 51 was added, which was connected to the same point and whose gate was electrically connected to the high power supply potential line. The configuration (see Figure 13(B)) can be applied. Note that transistor 51 is shown in Figure The system is in the off state during periods t2 and t3, as shown in 3(B) and (C). Therefore, the transition By adding transistor 51 to the configuration, the gate of transistor 33 occurs during periods t2 and t3. This makes it possible to disconnect the electrical connection between the gate and the gate of transistor 40. The pulse output circuit is configured to include a transistor 51 (see Figure 13(B)). We will compare the configurations that do not allow this (see Figure 3(A)) and detail the advantages of the former configuration.

[0124] First, let's explain the case where transistor 51 is not provided. Input to terminal 25 If the signal alternates between high power supply potential (Vdd) and low power supply potential (Vss), then during periods t2 and t3 In this configuration, the output signal of terminal 28 and the output signal of terminal 26 are both at the high power supply potential (Vdd) Yes. In this case, the gate potentials of transistors 33 and 40 (the potential of node A) are Capacitive coupling of the source and gate of transistor 33 and capacitive coupling of the source and gate of transistor 40. This results in a potential higher than the high power supply potential (Vdd). Meanwhile, the signal input to terminal 25 If the low power supply potential (Vss) is fixed, then during periods t2 and t3, the output of terminal 28 The signal is at the high power supply potential (Vdd), and the output signal of terminal 26 is at the low power supply potential (Vss). Yes. In this case, the gate potentials of transistors 33 and 40 (the potential of node A) are The source and gate of sta33 are capacitively coupled only, resulting in a potential higher than the high power supply potential (Vdd). This is necessary. In addition, transistor 40 drives the scan line, Compared to 36, it is often designed to have a larger channel width. The gate of ZISTA 40 becomes a significant load when the potential is increased by the capacitive coupling. Therefore, in order to operate the pulse output circuit, the channel length of transistor 33 is The channel width (W / L) needs to be increased.

[0125] In contrast, when transistor 51 is provided, the transistor in periods t2 and t3 The electrical connection between the gate of transistor 33 and the gate of transistor 40 is interrupted. Therefore, The potential of only the gate of transistor 33 can be increased by capacitive coupling. This reduces the load in the capacitive coupling. Therefore, the pulse output circuit is improved. This makes it possible to operate it smoothly. Also, the channel length of transistor 36 Since there is no need to increase the width (W / L), the layout area can be reduced. .

[0126] Note that in Figure 13(B), the gate of transistor 51 is electrically connected to the high power supply potential line. The configuration shown is that the gate is electrically connected to the block terminal (Block). A configuration in which the terminals are electrically connected (see Figure 14(A)) or a configuration in which the terminals are electrically connected (see Figure 14(B)) It is possible to do this. Note that the block terminal (Block) has terminal 25, Clock signals for scan line drive circuits 1 (GCK1) to 4th scan line drive circuits When the same signal as either (GCK4) is input, a high-level potential is input. When a fixed potential (low power supply potential (Vss)) is input, if a low-level potential is input... Good. That is, transistor 51 sends a clock signal for the first scan line drive circuit to terminal 25. The same as any of the clock signals for the fourth scan line drive circuit (GCK4) from (GCK1) to (GCK4). It turns on when a signal is input, and a fixed potential (low power supply potential (Vss)) is input. It should be controlled so that it turns off when necessary. This will allow the transistor 33 gate and the transistor to be controlled. This allows for an earlier timing of the electrical connection being interrupted at the gate of the inverter 40. Furthermore, the gate of transistor 51 is electrically connected to terminal 25 (see Figure 14(B)). The advantage of this method is that it does not require the addition of any new signals.

[0127] Furthermore, in the display device described above, the transistor 17 provided in the pixel 16 is, A configuration using a bottom-gate transistor 211 called a channel-etched type (Figure) As shown in (see 5), the transistor 17 is not limited to this configuration. For example, Figure 1 The transistors shown in 5(A) to (C) can be used.

[0128] The transistor 510 shown in Figure 15(A) is a channel protection type (also known as a channel stop type). It is one of the bottom gate structures known as (or).

[0129] The transistor 510 has a gate layer 221 and a gate insulating layer on a substrate 220 having an insulating surface. Edge layer 222, oxide semiconductor layer 223, channel formation region of oxide semiconductor layer 223 An insulating layer 511, a source layer 224a, and a drain layer 224b function as channel protective layers. It also covers and protects the source layer 224a, the drain layer 224b, and the insulating layer 511. An insulating layer 226 is formed.

[0130] The transistor 520 shown in Figure 15(B) is a bottom-gate type transistor, and is an insulating transistor. A gate layer 221, a gate insulating layer 222, and a source are placed on a substrate 220 which is a substrate having a surface. It includes layer 224a, drain layer 224b, and oxide semiconductor layer 223. Also, source layer 2 An insulating layer 225 is provided that covers 24a and the drain layer 224b and is in contact with the oxide semiconductor layer 223. It is being applied. A protective insulating layer 226 is further formed on the insulating layer 225.

[0131] In transistor 520, the gate insulating layer 222 is connected to the substrate 220 and the gate layer 221 A source layer 224a and a drain layer 224b are provided in contact with the gate insulating layer 222. They are provided in contact with each other. And the gate insulating layer 222, the source layer 224a, and the drain An oxide semiconductor layer 223 is provided on layer 224b.

[0132] The transistor 530 shown in Figure 15(C) is one of the top-gate transistors. Yes. Transistor 530 has an insulating layer 531 and an oxide layer on a substrate 220 having an insulating surface. Semiconductor layer 223, source layer 224a, drain layer 224b, gate insulating layer 222, The source layer 221 is included, and the source layer 224a and drain layer 224b each have wiring layers 532a The wiring layer 532b is provided in contact with it and is electrically connected.

[0133] The insulating layers 511 and 531 are typically silicon oxide films, silicon oxide nitride films, and acid Inorganic insulating films such as aluminum oxide films or aluminum oxide nitride films can be used. Furthermore, the conductive film used for the wiring layer 532a and wiring layer 532b may be, for example, Al, C Elements selected from r, Cu, Ta, Ti, Mo, and W, or compounds containing the above elements. Gold or alloy films combining the aforementioned elements can be used. Also, Al, Cu, etc. A high-melting-point metal layer such as Ti, Mo, or W is laminated on either the underside or the upperside of any metal layer, or both. This configuration is also acceptable. Furthermore, it prevents the formation of hillocks and whiskers on the Al film. Heat resistance is improved by using aluminum materials to which elements (such as Si, Nd, and Sc) are added. It becomes possible to do so.

[0134] (Regarding various electronic devices equipped with display devices) In the following section, an example of an electronic device equipped with a display device disclosed herein is shown in Figure 16. I will explain by referring to it.

[0135] Figure 16(A) shows a notebook-type personal computer, and the main unit 2201, It consists of a casing 2202, a display unit 2203, a keyboard 2204, and the like.

[0136] Figure 16(B) shows a personal digital assistant (PDA), and the main unit 2211 has a display unit 2 213, an external interface 2215, and operation buttons 2214 are provided. Additionally, a stylus 2212 is included as an accessory for operation.

[0137] Figure 16(C) shows the eBook 2220 as an example of electronic paper. Book 2220 consists of two enclosures: enclosure 2221 and enclosure 2223. 2221 and the housing 2223 are integrated by the shaft portion 2237, and the shaft portion 2237 It can perform opening and closing operations using this as an axis. With this configuration, the e-book 2220 can It can be used just like a physical book.

[0138] The display unit 2225 is incorporated into the casing 2221, and the display unit 2227 is incorporated into the casing 2223. It is included. Display units 2225 and 2227 are configured to display a continuation screen. Alternatively, a configuration that displays different screens is also acceptable. For example, text is displayed on the right-hand display unit (display unit 2225 in Figure 16(C)), and on the left Images can be displayed on the display unit (display unit 2227 in Figure 16(C)).

[0139] Furthermore, Figure 16(C) shows an example in which the housing 2221 is equipped with an operating section, etc. The enclosure 2221 is equipped with a power supply 2231, operation keys 2233, speaker 2235, etc. It is located on the same surface as the display unit of the casing. Pages can be advanced using operation key 2233. The configuration may also include a keyboard and a pointing device. On the side, there are external connection terminals (earphone jack, USB terminal, or AC adapter and USB terminal). A structure that includes terminals that can connect to various cables such as B cables, a recording medium insertion section, etc. It may also be considered complete. Furthermore, the e-book 2220 has a configuration that gives it the functionality of an electronic dictionary. You may do so.

[0140] Furthermore, the e-book 2220 may be configured to transmit and receive information wirelessly. The system will be configured to purchase and download desired book data from an e-book server. It is also possible.

[0141] Furthermore, electronic paper can be applied to any field that displays information. It is possible. For example, in addition to ebooks, posters, in-vehicle advertisements such as trains, and credit cards This can be applied to displays on various types of cards, such as credit cards.

[0142] Figure 16(D) shows a mobile phone. The mobile phone consists of a housing 2240 and It consists of two enclosures, enclosure 2241. Enclosure 2241 is a display panel 2242, Speaker 2243, microphone 2244, pointing device 2246, camera It is equipped with a lens 2247, an external connection terminal 2248, etc. Furthermore, the housing 2240 is The mobile phone is equipped with a solar cell 2249 for charging, an external memory slot 2250, and the like. It is equipped with an antenna, which is built into the casing 2241.

[0143] The display panel 2242 has a touch panel function, and the image displayed in Figure 16(D) is The multiple operation keys 2245 are indicated by dotted lines. Note that this mobile phone is solar-powered. A boost circuit is implemented to increase the voltage output from the RU2249 to the voltage required for each circuit. In addition to the above configuration, it also incorporates a contactless IC chip, a small recording device, and other components. It can also be done this way.

[0144] The display panel 2242 changes its orientation as appropriate depending on the usage mode. Since the camera lens 2247 is located on the same plane as the 2242, video calls are possible. Yes. Speaker 2243 and microphone 2244 are not limited to voice calls, but also television broadcasts. It is capable of speaking, recording, and playing back. Furthermore, the casings 2240 and 2241 slide apart. As shown in Figure 16(D), it can be changed from an unfolded state to an overlapping state, and can be used on a mobile phone. Suitable miniaturization is possible.

[0145] External connection terminal 2248 can be connected to various cables such as AC adapters and USB cables. It is capable of charging and data communication. Also, the external memory slot 2250 is marked By inserting recording media, it can handle the storage and transfer of larger amounts of data. In addition to the above functions... Furthermore, it may also be equipped with infrared communication functions, television reception functions, etc.

[0146] Figure 16(E) shows a digital camera. The digital camera has a main unit 226 1. Display unit (A) 2267, eyepiece unit 2263, operation switch 2264, display unit (B) 22 It consists of components such as 65 and battery 2266.

[0147] Figure 16(F) shows a television system. In television system 2270, The display unit 2273 is integrated into the housing 2271. The display unit 2273 displays video. It is possible to do so. In this case, the stand 2275 supports the housing 2271. This shows the configuration.

[0148] The television device 2270 is operated using the control switches on the housing 2271, or a separate control unit. This can be done using the remote control unit 2280. The remote control unit 2280 has an operating key -2279 allows you to control the channel and volume, and the information is displayed on the display unit 2273. The video can be controlled. Furthermore, the remote control unit 2280 can control the remote control operation. A display unit 2277 that displays information output from the unit 2280 may also be provided.

[0149] Furthermore, it is preferable that the television equipment 2270 be configured to include a receiver, modem, and the like. The receiver can receive general television broadcasts. Also, via a modem... By connecting to a wired or wireless communication network, one-way communication (from the sender to the receiver) is possible. Information communication is conducted either by the recipient or in both directions (between the sender and recipient, or between recipients). It is possible to do so. [Explanation of Symbols]

[0150] 10 pixel section 11 Scan line drive circuit 12. Signal line drive circuit 13 Controllers 14 scan lines 15 signal line 16 pixels 17 transistors 18 Capacitive elements 19 Liquid crystal elements 20_1~20_m Pulse Output Circuit 20_x pulse output circuit Terminals 21-28 31-41 Transistors 50, 51 transistors 131 Signal generation circuit 132 Memory circuit 133 Comparison circuit 134 Selection Circuit 135 Display control circuit 136 memory 211 transistors 220 circuit boards 221 Gate Layer 222 Gate Insulation Layer 223 Oxide semiconductor layer 224a Source layer 224b Drain layer 225 Insulating layer 226 Protective insulating layer 510 transistors 511 Insulating layer 520 transistors 530 transistors 531 Insulating layer 532a wiring layer 532b wiring layer 800 Measurement System 802 Capacitive element 804 Transistor 805 Transistor 806 Transistors 808 transistors 2201 Main Unit 2202 enclosure 2203 Display section 2204 Keyboard 2211 Main Unit 2212 Stylus 2213 Display section 2214 Operation Buttons 2215 External Interface 2220 eBooks 2221 enclosure 2223 Casing 2225 Display section 2227 Display section 2231 Power supply 2233 Operation Keys 2235 Speaker 2237 Shaft 2240 enclosure 2241 enclosure 2242 Display Panel 2243 Speaker 2244 Microphone 2245 Operation Keys 2246 Pointing device 2247 Camera Lens 2248 External connection terminal 2249 solar cells 2250 External Memory Slots 2261 Main Unit 2263 Eyepiece 2264 Operation switch 2265 Display section (B) 2266 Battery 2267 Display section (A) 2270 Television equipment 2271 enclosure 2273 Display section 2275 Stand 2277 Display section 2279 Operation Keys 2280 Remote Control Unit

Claims

1. A circuit comprising a first transistor to an eleventh transistor and a first wiring to a fifth wiring, The aforementioned circuit has the function of outputting a first signal to the first wiring, Either the source or the drain of the first transistor is always in electrical contact with the first wiring. The source or drain of the first transistor is always in electrical contact with the second wiring. Either the source or the drain of the second transistor is always in electrical contact with the third wiring. The source or drain of the second transistor is always in electrical contact with the first wiring. Either the source or drain of the third transistor is always in contact with the gate of the first transistor. The source or drain of the third transistor is always in contact with the gate of the fourth transistor. The source or drain of the fourth transistor is always in electrical contact with the other source or drain of the fifth transistor. The source or drain of the fourth transistor is always in electrical contact with the fourth wiring. Either the source or drain of the fifth transistor is always in electrical contact with the third wiring. The gate of the fifth transistor is always in contact with either the source or the drain of the sixth transistor. The first power supply potential is supplied to the other of the source or drain of the sixth transistor. Either the source or drain of the seventh transistor is always in contact with the gate of the fourth transistor. The source or drain of the seventh transistor is always in electrical contact with the source or drain of the eighth transistor. The gate of the seventh transistor is supplied with the first power supply potential. The gate of the eighth transistor is always in electrical contact with the fifth wiring. Either the source or drain of the ninth transistor is always in electrical contact with the third wiring. The source or drain of the ninth transistor is always in contact with the gate of the second transistor. Either the source or drain of the 10th transistor is always in contact with the gate of the second transistor. The source or drain of the 10th transistor is always in electrical contact with the source or drain of the 11th transistor. Different signals are supplied to the gates of the 10th transistor and the 11th transistor. Semiconductor equipment.

2. A circuit comprising at least one transistor to an eleventh transistor and a first to a fifth wiring, The aforementioned circuit has the function of outputting a first signal to the first wiring, The first wiring is always in electrical contact with the gate of the pixel transistor. Either the source or the drain of the first transistor is always in electrical contact with the first wiring. The source or drain of the first transistor is always in electrical contact with the second wiring. Either the source or the drain of the second transistor is always in electrical contact with the third wiring. The source or drain of the second transistor is always in electrical contact with the first wiring. Either the source or drain of the third transistor is always in contact with the gate of the first transistor. The source or drain of the third transistor is always in contact with the gate of the fourth transistor. The source or drain of the fourth transistor is always in electrical contact with the other source or drain of the fifth transistor. The source or drain of the fourth transistor is always in electrical contact with the fourth wiring. Either the source or drain of the fifth transistor is always in electrical contact with the third wiring. The gate of the fifth transistor is always in contact with either the source or the drain of the sixth transistor. The first power supply potential is supplied to the other of the source or drain of the sixth transistor. Either the source or drain of the seventh transistor is always in contact with the gate of the fourth transistor. The source or drain of the seventh transistor is always in electrical contact with the source or drain of the eighth transistor. The gate of the seventh transistor is supplied with the first power supply potential. The gate of the eighth transistor is always in electrical contact with the fifth wiring. Either the source or drain of the ninth transistor is always in electrical contact with the third wiring. The source or drain of the ninth transistor is always in contact with the gate of the second transistor. Either the source or drain of the 10th transistor is always in contact with the gate of the second transistor. The source or drain of the 10th transistor is always in electrical contact with the source or drain of the 11th transistor. Different signals are supplied to the gates of the 10th transistor and the 11th transistor. Semiconductor equipment.

3. A circuit comprising at least one transistor to an eleventh transistor and a first to a fifth wiring, The aforementioned circuit has the function of outputting a first signal to the first wiring, Either the source or the drain of the first transistor is always in electrical contact with the first wiring. The source or drain of the first transistor is always in electrical contact with the second wiring. Either the source or the drain of the second transistor is always in electrical contact with the third wiring. The source or drain of the second transistor is always in electrical contact with the first wiring. Either the source or drain of the third transistor is always in contact with the gate of the first transistor. The source or drain of the third transistor is always in contact with the gate of the fourth transistor. The source or drain of the fourth transistor is always in electrical contact with the other source or drain of the fifth transistor. The source or drain of the fourth transistor is always in electrical contact with the fourth wiring. Either the source or drain of the fifth transistor is always in electrical contact with the third wiring. The gate of the fifth transistor is always in contact with either the source or the drain of the sixth transistor. The first power supply potential is supplied to the other of the source or drain of the sixth transistor. Either the source or drain of the seventh transistor is always in contact with the gate of the fourth transistor. The source or drain of the seventh transistor is always in electrical contact with the source or drain of the eighth transistor. The gate of the seventh transistor is supplied with the first power supply potential. The gate of the eighth transistor is always in electrical contact with the fifth wiring. Either the source or drain of the ninth transistor is always in electrical contact with the third wiring. The source or drain of the ninth transistor is always in contact with the gate of the second transistor. Either the source or drain of the 10th transistor is always in contact with the gate of the second transistor. The source or drain of the 10th transistor is always in electrical contact with the source or drain of the 11th transistor. Different signals are supplied to the gates of the 10th transistor and the 11th transistor. The third wiring has the function of supplying a second power potential, The fourth wiring has the function of supplying a clock signal. Semiconductor equipment.

4. A circuit comprising a first transistor to an eleventh transistor and a first wiring to a fifth wiring, The aforementioned circuit has the function of outputting a first signal to the first wiring, The first wiring is always in electrical contact with the gate of the pixel transistor. Either the source or the drain of the first transistor is always in electrical contact with the first wiring. The source or drain of the first transistor is always in electrical contact with the second wiring. Either the source or the drain of the second transistor is always in electrical contact with the third wiring. The source or drain of the second transistor is always in electrical contact with the first wiring. Either the source or drain of the third transistor is always in contact with the gate of the first transistor. The source or drain of the third transistor is always in contact with the gate of the fourth transistor. The source or drain of the fourth transistor is always in electrical contact with the other source or drain of the fifth transistor. The source or drain of the fourth transistor is always in electrical contact with the fourth wiring. Either the source or drain of the fifth transistor is always in electrical contact with the third wiring. The gate of the fifth transistor is always in contact with either the source or the drain of the sixth transistor. The first power supply potential is supplied to the other of the source or drain of the sixth transistor. Either the source or drain of the seventh transistor is always in contact with the gate of the fourth transistor. The source or drain of the seventh transistor is always in electrical contact with the source or drain of the eighth transistor. The gate of the seventh transistor is supplied with the first power supply potential. The gate of the eighth transistor is always in electrical contact with the fifth wiring. Either the source or drain of the ninth transistor is always in electrical contact with the third wiring. The source or drain of the ninth transistor is always in contact with the gate of the second transistor. Either the source or drain of the 10th transistor is always in contact with the gate of the second transistor. The source or drain of the 10th transistor is always in electrical contact with the source or drain of the 11th transistor. Different signals are supplied to the gates of the 10th transistor and the 11th transistor. The third wiring has the function of supplying a second power potential, The fourth wiring has the function of supplying a clock signal. Semiconductor equipment.

5. In any one of Claims 1 to 4, The third transistor has the function of controlling the conduction state between the gate of the first transistor and the gate of the fourth transistor. Semiconductor equipment.

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