Data transfer device, data transfer method, and program

Abstract

This invention provides a data transfer device, data transfer method, and program that enable multi-core writing and data transfer with lighter processing loads. [Solution] The control device (10) as a data transfer device comprises a plurality of cores (111-114) and a FIFO (14) having a plurality of array elements, in which the contents written to the plurality of array elements are output in the order in which they were written. The number of array elements in the FIFO (14) is greater than the number of cores (111-114). The plurality of cores (111-114) can write to the FIFO (14) in parallel on an array element basis, and if the number of writable array elements is less than the number of cores (111-114), no new writing is performed.

Description

Technical Field

[0001] This invention relates to a data transfer device, a data transfer method, and a program.

Background Art

[0002] When a processor that performs arithmetic processing in a computer has a plurality of processing units (cores) and can execute multitasking, problems occur when trying to use common resources such as memory among multiple threads. Therefore, there is a technique that uses an exclusive lock (spin lock) that prohibits the processing operation of another thread by another processing unit during the processing operation of a certain processing unit by a certain thread.

[0003] While the exclusive lock is a simple and robust mechanism, there is a problem that the load related to monitoring increases because the lock state continues to be monitored from the thread whose processing is prohibited until the locked resource is released. Patent Document 1 discloses a technique for reducing the processing load of monitoring.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, as long as monitoring is necessary, there is a problem that the processing load of monitoring occurs. An object of this invention is to provide a data transfer device, a data transfer method, and a program capable of writing and data transfer by a multi-core with lighter processing.

Means for Solving the Problems

[0006] To achieve the above object, the present invention Multiple processing units, A FIFO (First-In First-Out) buffer having multiple array elements, in which the contents written to the multiple array elements are output in the order in which they were written, Equipped with, The number of array elements in the FIFO buffer is greater than the number of processing units. The aforementioned plurality of processing units are capable of writing to the FIFO buffer in parallel, using the array elements as units, and if the number of writable array elements is less than the number of processing units, no new writing is performed. It is a data transfer device. [Effects of the Invention]

[0007] According to the present invention, it is possible to perform multi-core writing and data transfer with lighter processing. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram showing the functional configuration of an electronic musical instrument. [Figure 2] This diagram explains the data output. [Figure 3] This flowchart shows the control procedure for the data writing control process to the FIFO. [Figure 4] This flowchart shows the control procedure for data output control processing from the FIFO. [Figure 5] This flowchart shows another example of data writing control processing to a FIFO. [Figure 6] This flowchart shows another example of the control procedure for data output control processing from a FIFO. [Modes for carrying out the invention]

[0009] Embodiments of the present invention will be described below with reference to the drawings. As shown in the block diagram of Figure 1, the electronic musical instrument 100 may include a control device 10, which is an embodiment of a data transfer device, a performance reception unit 20, and a data processing unit 30. The output destination of the data from the control device 10 may be a sound output device such as a speaker. The performance reception unit 20 may be, for example, the keyboard of an electronic piano. The performance reception unit 20 detects key operations and other actions related to performance by the performer and outputs an operation signal. Performance here includes all key operations.

[0010] The control device 10 includes a CPU 11 (Central Processing Unit), RAM 12 (Random Access Memory), a storage unit 13, a FIFO 14 (First-In First-Out), a UART 15 (Universal Asynchronous Receiver / Transmitter), a communication unit 16, a data generation unit 17, and the like.

[0011] The CPU 11 is a processor that performs arithmetic processing and provides overall control over the operation of the control device 10. The CPU 11 provides overall control over the operation of multiple processing units, such as the first core 111, the second core 112, the third core 113, and the fourth core 114. Hereafter, the first core 111, the second core 112, the third core 113, and the fourth core 114 will be collectively referred to as cores 111-114. Cores 111-114 can perform arithmetic processing in parallel. That is, the control device 10 can execute multitasks in parallel. The number of threads in the CPU 11 may be the same as the number of cores 111-114, or it may be more than the number of cores, for example, twice the number of cores.

[0012] RAM12, or volatile memory, provides the CPU11 with a working memory space and stores temporary data. RAM12 may include control registers. The control registers may be flip-flops, and other RAM12 may be DRAM, etc.

[0013] The memory unit 13 is a non-volatile memory that stores and holds the program 131, configuration data, and the like. The non-volatile memory may be, for example, flash memory.

[0014] FIFO14 (FIFO buffer) may be a memory that receives specific data to be output to the outside in sequence in the order of output and holds it until output. The memory may be a dedicated hardware chip or an area set in general-purpose memory. FIFO14 has multiple array elements of fixed capacity. In FIFO14, the starting position of the ring buffer, i.e., the area information to be stored, may be switched in the order of writing, i.e., the input order. FIFO14 allows data to be written in parallel by multiple cores 111-114, for example, by setting data order information and write area information at the time a write request is received. On the other hand, read requests may be made periodically in synchronization with a clock signal of a predetermined frequency. In response to a read request, the area information that stores the oldest data currently held is obtained, and that data is read and output from FIFO14. Writing and reading do not need to be synchronized. The number of array elements may be greater than the number of cores and may be an integer multiple of the number of cores of 2 or more. For example, the number of array elements may be 32, which is 8 times the number of cores. The capacity of each array element is greater than or equal to the data length of the data generated by the data generation unit 17. For example, the capacity of each array element may be 4 bytes (32 bits).

[0015] As a communication control unit, UART15 converts the data to be output into serial data in a preset bit length unit, generates unit data with start bits, stop bits, etc. for communication added, and outputs it to the outside. UART15 may be packaged together with CPU11, RAM12, etc. The data output length, which is the preset bit length per data output, is 5 to 9 bits, and this is often shorter than the data length of the data generated by data generation unit 17. Therefore, the capacity of each array element of FIFO14 is larger than this data length. The data output from UART15 may be performed via a MIDI (Musical Instruments Digital Interface) terminal, which is a 5-pin DIN connector.

[0016] Communication unit 16 controls communication with external devices. Communication unit 16 may, for example, control the reception of data, settings, etc. acquired from external devices, or control the transmission of status and information. Communication unit 16 may, for example, be able to control communication via a LAN (Local Area Network), a wireless LAN, etc. Also, communication unit 16 may be able to control data transmission and reception by one-to-one communication such as USB (Universal Serial Bus). Communication unit 16 may be able to further convert the data converted by UART15 into a USB format and output it to outside data processing unit 30.

[0017] Data generation unit 17 generates output sound data based on the operation signal received by performance reception unit 20. The generated data may be, for example, MIDI data, which is a common standard defining performance data of an electronic musical instrument. The generation of MIDI data may be performed by 2 to 4 of the above-mentioned plurality of cores 111 to 114. The generated data may be sequentially input to FIFO14 for output by UART15, or may be once stored and held in storage unit 13.

[0018] The data processing unit 30 may be a MIDI device capable of performing sound output and editing operations on MIDI data. The data processing unit 30 may be a part of the electronic musical instrument 100, or may be an electronic device independent of the electronic musical instrument 100. The data processing unit 30 includes a UART 31, receives the serial data converted by the UART 15 via a serial wiring, and restores it to the original data by the UART 31. The restored original data, for example, MIDI data, may be used for signal generation for sound output, or may be stored and held in a storage unit or the like as it is.

[0019] Next, the output of data will be described. As shown in FIG. 2, it is possible to perform the process of writing MIDI messages to the FIFO 14 in parallel by the four cores 111 to 114. In each process, a writing area is set and assigned in the order in which the writing requests are made. The data to be written may have a variable length, but a normal maximum length is defined. In a MIDI message, the normal data length is 24 bits. Each array element of the FIFO 14 is larger than this, and for example, each array element may be 32 bits (4 bytes). Each array element may be divided into 4 blocks of 8 bits each. The cores 111 to 114 may divide the MIDI message into 8-bit portions, and input them into each block in a predetermined format in which portions that can be restored later are deleted or necessary additional information is added as necessary.

[0020] FIFO14 outputs four blocks of data for each array element in the order they are received, and the data from these four blocks may be combined back into the original MIDI message. The resulting MIDI message is output to UART15. UART15 divides the MIDI message into predetermined number of bits, for example 8 bits, from the beginning and outputs them sequentially. This prevents multiple divided MIDI messages from being mixed together, making the order and combination unclear. The control register of RAM12 stores the number of data points stored in FIFO14, or the number of data points that have not been written and can be newly stored. The number of data points in the control register should be updated each time data is written to the write area allocated to FIFO14, or data is read from the read area.

[0021] Furthermore, if an interrupt occurs and another MIDI message is written while individual cores 111-114 are writing multi-byte data as described above, the original MIDI message cannot be restored. Therefore, while the process of writing a MIDI message is in progress, cores 111-114 performing the writing are configured to prohibit the acceptance of other interrupts.

[0022] Cores 111-114 are unaware of the processing performed by other cores 111-114 running in parallel, and cannot pause or adjust the timing of processing performed by other cores 111-114. Therefore, the maximum number of write operations to FIFO14 that can be performed simultaneously is the number of cores 111-114. If more write operations are performed than the number of remaining array elements in FIFO14 due to such parallel processing, the executed write operations may prevent writing to FIFO14 or erase data before output. Before cores 111-114 perform write operations to FIFO14, the control device 10 checks whether there are more array elements available for writing than the number of cores, i.e., free. This ensures that writing to FIFO14 is successful. If the number of remaining array elements is less than the number of cores, the write operation is not performed. The control device 10 may also be configured to allow for a margin of safety, such as not performing a new write operation if the number of writable array elements is less than a predetermined number greater than the number of cores, and performing a new write operation if the number of writable array elements is greater than or equal to the predetermined number. The predetermined number may be set as appropriate, for example, the number of cores + 1, the number of cores + 2, or 1.5 times the number of cores.

[0023] The data writing process to FIFO14 is controlled by each core, as shown in Figure 3. This control is defined by program 131, and each core 111-114 executes program 131. Here, we will explain assuming that the input data is a MIDI message. Each core 111-114 obtains a MIDI message from the data generation unit 17, the storage unit 13, or an external source. Each core 111-114 converts the MIDI message into 8-bit data (S1). Here, the statement "each core 111-114" does not mean that all cores 111-114 perform the operation. It is sufficient for at least one core among cores 111-114 that is assigned the data writing process to FIFO14 to selectively execute the process.

[0024] Cores 111-114 disable interrupt handling for themselves (S2). Cores 111-114 determine whether there are more or fewer free array elements in FIFO14 that can be written to than the number of cores (S3; determination means). If it is determined that there are fewer or fewer free array elements than the number of cores (S3; N), cores 111-114 repeat the process of step S3. Note that cores 111-114 may wait for a predetermined time before proceeding to step S3.

[0025] If it is determined that there are more empty array elements than the number of cores (S3; Y), cores 111-114 obtain the data length of the data to be written (S4). Cores 111-114 write the data to be written and the data length information to the write area of ​​FIFO14 (S5). As described above, in response to a write request to FIFO14, a write area (address) is set from among the empty array elements, and data is written to that write area. The data to be written is, as described above, the FIFO data converted from MIDI messages. After the writing is complete, cores 111-114 release the interrupt processing disable setting (S6). Then, cores 111-114 terminate the data writing control process.

[0026] The data written to FIFO14 is read out sequentially and output. The reading should be synchronized with a synchronization signal of an appropriate frequency, and not with the timing of the writing. The reading process is executed continuously and repeatedly, but the core executing the process may be changed during the repetition. As shown in Figure 4, cores 111 to 114 refer to the control register to determine whether or not there is data to be read from FIFO14 (S11). If it is determined that there is no data to be read (S11;N), cores 111 to 114 repeat the process of step S11. The repeated process should be started in synchronization with the next synchronization signal, as described above.

[0027] If it is determined that there is data to be read in FIFO14 (S11;Y), cores 111-114 read the target data from the read area of ​​FIFO14 (S12). Cores 111-114 obtain area information where the data to be read is located in response to the read request to FIFO14, and read the data from that area. At this point, the array elements of the area from which the data was read will be managed as writable, free array elements. Cores 111-114 convert the data converted for FIFO back to the original MIDI message (S13). Cores 111-114 divide the returned MIDI message into data with the number of bits set for transmission by UART15, ​​for example, 8-bit data, add start bits and stop bits, and output it externally (S14). Note that parity bit data for checking may be added to the output data. Then, the data output control process returns to step S11. The processing of step S11, which has returned in the same manner as above, should be executed according to the next synchronization signal. These data writing control processes and data output control processes correspond to a data transfer method according to one embodiment.

[0028] In MIDI data, as described above, there is generally a maximum data length for messages, but exceptionally long messages may be generated. Long data may include, for example, pitch bend data or program change data. If this long message is larger than the size of the array elements in FIFO14, the control device 10 cannot write the message to FIFO14. In this case, the control device 10 may temporarily allocate a write area on RAM12 to store the data of the long message, and store information about the write area, such as a pointer *a, in FIFO14.

[0029] As shown in the flowchart in Figure 5, if there is a large amount of data to be written to RAM 12, the processes S21 to S24 are added. Also, the process of process S1 is divided into processes S1a and S1b, and the position of process S4 is changed to S4a. The other processes are the same as those shown in the above embodiment, and the same reference numerals are used for processes with the same content, and detailed explanations are omitted.

[0030] Cores 111-114 acquire data (S1a). Cores 111-114 acquire the data length of the acquired data (S4a). Cores 111-114 determine whether the data length is less than or equal to the size of each array element in FIFO14 (S21). If it is determined that the data length is less than or equal to the size of the array elements in FIFO14 (S21; Y), cores 111-114 convert the acquired data into data for FIFO (S1b). Then, the processing of cores 111-114 proceeds to step S2.

[0031] If it is determined that the data length is greater than the size of the array elements of FIFO14 (S21;N), cores 111-114 allocate memory in RAM12 and set pointer *a (S22). The size of the allocated memory may be dynamically determined according to the data length. Cores 111-114 write the FIFO data to be written to the area corresponding to pointer *a (S23). Cores 111-114 set the information of pointer *a in the FIFO data (S24). Then, the processing of cores 111-114 moves to process S2. If the process branches to "Y" in process S3, the processing of cores 111-114 moves to process S5.

[0032] The data output control process corresponding to this data writing control process has additional steps S31 to S33, as shown in Figure 6. The processing content of the other steps is the same, and steps with the same processing content are given the same reference numerals, and detailed explanations are omitted.

[0033] After processing in step S12, cores 111-114 determine whether the read data is information about pointer *a (S31). If it is determined that the data is not information about pointer *a (S31; N), cores 111-114 proceed to step S13. If it is determined that the data is information about pointer *a (S31; Y), cores 111-114 read the data from the memory area of ​​RAM 12 corresponding to pointer *a (S32). Cores 111-114 then release the memory area allocated to pointer *a (S33). After that, cores 111-114 proceed to step S14.

[0034] As described above, the control device 10 of this embodiment includes a plurality of cores 111 to 114 and a FIFO 14 having a plurality of array elements, in which the contents written to the plurality of array elements are output in the order in which they were written. The number of array elements in the FIFO 14 is greater than the number of cores in the CPU 11. The plurality of cores 111 to 114 can execute the write process to the FIFO 14 in parallel on an array element basis. If the number of writable array elements in the FIFO 14 is less than the number of cores, no new write is performed. In this way, the control device 10 only needs to determine whether there is free capacity in the FIFO 14 that can be stored even if the plurality of cores 111 to 114 write simultaneously. Therefore, the control device 10 does not need to perform processing to frequently check whether a spinlock is set on each core 111 to 114, etc., and increases in the load on each core 111 to 114 and increases in path usage are avoided. Therefore, the control device 10 can write and transfer serial data using multiple cores with lighter processing than conventional methods. As a result, the power consumption of the control device 10 is also reduced.

[0035] Furthermore, the multiple cores 111 to 114 may refrain from performing new write operations if the number of writable array elements is less than a predetermined number greater than the number of cores 111 to 114. By providing a margin of error beyond the number of cores 111 to 114, the control device 10 can write and transfer serial data more safely, as it is less susceptible to problems such as those with the FIFO 14.

[0036] More specifically, multiple cores 111 to 114 may determine whether the number of writable array elements is less than the number of cores 111 to 114. Cores 111 to 114 may not perform a new write operation if they determine that the number is less than the number of cores 111 to 114, and may perform a new write operation if they determine that the number is equal to or greater than the number of cores 111 to 114. The criterion for this determination may be a predetermined number greater than the number of cores 111 to 114, as described above. In other words, since the feasibility of a write operation is simply determined according to the result of the determination process regarding the number of writable array elements, the control device 10 can easily determine whether to write and switch between executing or waiting for a write operation with a simple process.

[0037] Multiple cores 111-114 may be prohibited from accepting other interrupts while performing a write operation to FIFO14. In addition to controlling writes between multiple cores, prohibiting interrupts between write operations on each core 111-114 allows for more efficient writes to FIFO14.

[0038] Multiple cores 111-114 may be able to write variable-length data to FIFO14. They can also write data in parallel, appropriately storing the information of the written data length into new array elements.

[0039] The control device 10 may be equipped with RAM 12. Each core 111 to 114 may be able to store data larger than the capacity of the array elements of FIFO 14 in a designated area of ​​RAM 12. Even if the data length of the data to be stored in FIFO 14 is variable and includes data larger than the size of the array elements of FIFO 14, this can be flexibly handled by using the external memory of FIFO 14 in this way.

[0040] The number of array elements in FIFO14 may be an integer multiple of 2 or more of the number of cores 111-114. When processing is generally distributed among cores 111-114, each core can write an appropriate number of times, and the writing process to FIFO14 is not biased.

[0041] Furthermore, the control device 10 has a control register in the RAM 12. The control register may store the number of writable or non-writable array elements of the FIFO 14. Multiple cores 111 to 114 can determine whether or not to perform a write operation by referring to the control register. This allows each core 111 to 114 to easily and independently determine whether or not to perform a write operation, regardless of the write operations of other cores 111 to 114.

[0042] Furthermore, the control device 10 may also be equipped with a UART 15. The UART 15 may output data read from the FIFO 14 in units of a predetermined data length of about 8 bits. The capacity of each array element of the FIFO 14 may be greater than the data output length per transaction set in the UART 15. In this way, when the data length per MIDI message is greater than the data length of a single output transaction by the UART 15, the control device 10 can output the data appropriately without changing the order of output or corrupting the data.

[0043] Furthermore, multiple cores 111 to 114 may convert the data to be written to FIFO 14 into a predetermined format when writing to FIFO 14, and convert it back to that format when reading from FIFO 14. In other words, since MIDI data is not stored directly in FIFO 14, the control device 10 can store and retain standardized data more efficiently.

[0044] Furthermore, the data transfer method of this embodiment is a data transfer method using multiple cores 111 to 114. The multiple cores 111 to 114 have more array elements than the number of cores, and the writing process to the FIFO 14, which outputs the contents stored in the multiple array elements in the order they are written, can be executed in parallel on an array element-by-array basis. In this data transfer method, if the number of array elements that can be written is less than the number of cores 111 to 114, no new writing process is performed. Therefore, regardless of the status of the writing process to the FIFO 14 performed by the other cores 111 to 114, data can be written to the FIFO 14 in parallel. Consequently, since there is no need for resource-intensive mutual exclusion processing such as spinlocks between cores 111 to 114, serial data can be transferred efficiently with lighter processing.

[0045] Furthermore, the program 131 relating to the above data transfer method can be installed and executed on a computer equipped with multiple cores 111 to 114. This allows the computer of the control device 10 to efficiently perform parallel processing of input data and serial data transfer output using multiple cores 111 to 114 with minimal processing effort.

[0046] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are possible. For example, in the above example, the data transferred was described as performance data corresponding to the content received by the performance reception unit 20 of the electronic instrument 100, but it is not limited to this. It may also be output of MIDI data that was originally stored, or MIDI data that was temporarily input from another instrument, etc. Furthermore, it may be data that integrates external input data and performance data from the electronic instrument 100.

[0047] Furthermore, the specific structure of FIFO14 is not limited to the description above. It is sufficient that it can perform parallel writing operations from multiple cores 111-114 and that it can hold and output data in the order it is written.

[0048] Furthermore, if the data length of the data to be written is a fixed size, it is not necessary to store the data length in FIFO14. FIFO14 may simply store only the data to be written. Alternatively, each array element of FIFO14 may also store other additional information. The data to be written is not limited to MIDI messages and may be determined as appropriate depending on the content of the data.

[0049] Furthermore, while the above describes storing data in an external RAM 12 and storing RAM 12 area information in FIFO 14 when the data length of the written data is greater than the capacity of the array elements, this is not the only approach. For example, if the data length may exceed the capacity of the array elements depending on the type of written data, it may be stored in RAM 12 regardless of whether it is actually greater than the capacity of the array elements. Alternatively, all written data may be uniformly stored in RAM 12, and RAM 12 area information may always be stored in FIFO 14. In such cases, a fixed data storage area may be allocated to RAM 12. Alternatively, the storage area may be set to a dedicated volatile memory instead of general-purpose RAM 12. If the data storage area is fixed, it is not necessary to store area information in FIFO 14. For example, whether or not FIFO data is stored in FIFO 14 may be determined by whether or not a specific flag is set.

[0050] Furthermore, the number of array elements in FIFO14 does not have to be an integer multiple of the number of cores 111-114. It is sufficient if it is greater than the number of cores 111-114. Also, the capacity of each array element in FIFO14 can be appropriately determined according to the input data.

[0051] Furthermore, although the above describes a data format conversion when writing data to FIFO14, this conversion is not required. Fixed-bit length data may be written directly to FIFO14. Also, output data from FIFO14 is not limited to being transmitted via UART. Data may be output according to other standards.

[0052] Furthermore, while the above description has used a storage unit 13 consisting of non-volatile memory such as flash memory as an example of a computer-readable medium for storing the program 131 related to data transfer control of the present invention, the invention is not limited to these. Other computer-readable mediums that can be used include other non-volatile memories such as MRAM and HDD, and portable recording media such as CD-ROMs and DVD discs. In addition, a carrier wave can also be used as a medium for providing the program data according to the present invention via a communication line. Furthermore, the specific configurations, processing operations, and procedures shown in the above embodiments can be modified as appropriate without departing from the spirit of the present invention. The scope of the present invention includes the scope of the invention described in the claims and its equivalents. [Explanation of Symbols]

[0053] 10 Control unit, 11 CPU, 111 First core, 112 Second core, 113 Third core, 114 Fourth core, 14 FIFO

Claims

1. Multiple processing units, A FIFO (First-In First-Out) buffer having multiple array elements, in which the contents written to the multiple array elements are output in the order in which they were written, Equipped with, The number of array elements in the FIFO buffer is greater than the number of processing units. The aforementioned plurality of processing units are capable of writing to the FIFO buffer in parallel, using the array elements as units, and if the number of writable array elements is less than the number of processing units, no new writing is performed. Data transfer device.

2. The data transfer device according to claim 1, wherein the plurality of processing units do not perform a new write operation when the number of writable array elements is less than a predetermined number greater than the number of processing units.

3. The data transfer device according to claim 1, wherein the plurality of processing units determine whether the number of writable array elements is less than the number of processing units, and if it is determined that the number is less than the number of processing units, no new writing process is performed, and if it is determined that the number is equal to or greater than the number of processing units, a new writing process is performed.

4. The data transfer device according to claim 2, wherein the plurality of processing units determine whether the number of writable array elements is less than a predetermined number, and if it is determined that the number is less than the number of processing units, no new writing process is performed, and if it is determined that the number is equal to or greater than the predetermined number, a new writing process is performed.

5. The data transfer device according to claim 1, wherein the plurality of processing units prohibit the acceptance of other interrupt processing to the processing unit while the writing process to the FIFO buffer is being performed.

6. The data transfer device according to claim 1, wherein the processing unit writes variable-length data to the FIFO buffer and also writes information of the length of the written data to the array element.

7. Equipped with memory, The processing unit is capable of storing data larger than the capacity of each array element of the FIFO buffer in a predetermined area of ​​the memory. The data transfer device according to claim 1.

8. The data transfer device according to claim 1, wherein the number of array elements in the FIFO buffer is an integer multiple of 2 or more of the number of processing units.

9. Equipped with memory, The memory stores the number of writable or unwritable array elements of the FIFO buffer. The aforementioned plurality of processing units refer to the memory to determine whether or not to perform a write operation. The data transfer device according to claim 1.

10. The system includes a communication control unit that controls the external output of data read from the FIFO buffer, The communication control unit outputs the data read from the FIFO buffer based on the UART (Universal Asynchronous Receiver / Transmitter). The capacity of each array element of the FIFO buffer is greater than the data output length per transaction set in the communication control unit. The data transfer device according to claim 1.

11. The data transfer device according to claim 1, wherein the plurality of processing units convert the data to be written to the FIFO buffer during the write operation to the FIFO buffer into a predetermined format, and convert it back to the original format during the read operation from the FIFO buffer.

12. A data transfer method using multiple processing units, The aforementioned plurality of processing units have a plurality of array elements, which is greater than the number of processing units, and the contents written to the plurality of array elements are output in a FIFO (First-In First-Out) buffer in the order in which they were written, and the processing is performed in parallel on a unit basis of the array elements. If the number of writable array elements is less than the number of processing units, no new write operation is performed. Data transfer method.

13. A computer having multiple processing units, each of which has more array elements than the number of processing units, and capable of parallel writing of the contents written to the array elements to a FIFO (First-In First-Out) buffer, where the contents written to the array elements are output in the order they were written, is provided. If the number of writable array elements is less than the number of processing units, a determination means for not performing a new write operation. A program that makes it function as such.

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