Optical scanning apparatus and image forming apparatus

Abstract

Compared to the case where the non-scanning period is the same for multiple groups of light-emitting elements, this suppresses light intensity fluctuations caused by variations in the drive voltage. [Solution] The scanning means comprises a plurality of groups of light-emitting elements, each consisting of multiple light-emitting elements arranged along the main scanning direction, facing the object to be scanned and arranged along the main scanning direction, and scanning by emitting light from each of the light-emitting elements based on image information, and a driving means that drives each of the light-emitting elements of the scanning means for each scanning period, wherein the driving means divides the plurality of light-emitting elements into a plurality of sets, and sets the timing of the non-scanning period set during the scanning period to be different for at least two of the light-emitting elements divided into the plurality of sets.

Description

Technical Field

[0001] This invention relates to an optical scanning device and an image forming apparatus.

Background Art

[0002] Conventionally, as technologies related to optical scanning devices, for example, those disclosed in Patent Documents 1 and 2 have already been proposed.

[0003] Patent Document 1 includes a lighting unit in which a plurality of lighting chips each having a plurality of lighting elements are arranged, and a driving unit configured to sequentially light the plurality of lighting elements in the plurality of lighting chips. The driving unit is configured to shift the lighting timings between the plurality of lighting chips within the range of the lighting cycle of one lighting element.

[0004] Patent Document 2 includes a plurality of light emitting element array members in which a plurality of light emitting elements are arranged in a row, and driving means for transferring signals for sequentially lighting each of the plurality of light emitting elements arranged in each of the plurality of light emitting element array members at a predetermined transfer period in the array direction. The driving means is configured to be able to change the transfer period when transferring the signals.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] An object of this invention is to suppress fluctuations in the amount of light caused by fluctuations in the driving voltage as compared with the case where the non-scanning periods in a plurality of light emitting element groups are the same.

Means for Solving the Problems

[0007] The invention described in claim 1 is a scanning means that scans by arranging multiple groups of light-emitting elements, each of which is arranged along the main scanning direction, facing the object to be scanned along the main scanning direction, and causing each of the light-emitting elements to emit light based on image information, A driving means for driving each of the light-emitting element groups of the scanning means for each scanning period, Equipped with, The driving means is an optical scanning device that divides the plurality of light-emitting element groups into a plurality of sets, and sets different timings for the non-scanning period during the scanning period in at least two of the plurality of sets of light-emitting element groups.

[0008] The invention described in claim 2 is an optical scanning device according to claim 1, wherein the plurality of sets are adjacent groups of light-emitting elements among the plurality of light-emitting elements that make up the same set.

[0009] The invention described in claim 3 is an optical scanning device according to claim 2, wherein the driving means is arranged for each set of the plurality of light-emitting elements.

[0010] The invention described in claim 4 is an optical scanning apparatus according to claim 3, wherein the driving means divides the interval from one scanning period to the next scanning period into equal parts according to the number of sets of the light-emitting element groups, and the timing of the non-scanning period differs by the amount of the divided intervals.

[0011] The invention described in claim 5 is an optical scanning apparatus according to claim 1, wherein the driving means varies the timing of the non-scanning period in order to suppress fluctuations in the driving voltage that occur during the non-scanning period.

[0012] The invention described in claim 6 is an optical scanning apparatus according to claim 5, wherein the fluctuation of the drive voltage occurring during the non-scanning period increases to a value exceeding a specified value and then decreases to a value below the specified value and converges.

[0013] The invention described in claim 7 is an optical scanning device according to claim 6, wherein the driving means drives each set of light-emitting elements after the fluctuation of the driving voltage has converged.

[0014] The invention described in claim 8 is an optical scanning device according to claim 6, wherein the driving means causes each of the subsequent sets of light-emitting elements to emit light just before the driving voltage falls below the specified value.

[0015] The invention described in claim 9 comprises an image holder and An exposure means for exposing the image holder based on image information, Equipped with, The exposure means is an image forming apparatus using the optical scanning apparatus described in any one of claims 1 to 8. [Effects of the Invention]

[0016] According to the invention described in claim 1, it is possible to suppress fluctuations in light intensity caused by fluctuations in the driving voltage compared to the case where the non-scanning period is the same in multiple groups of light-emitting elements.

[0017] According to the invention described in claim 2, the configuration of the driving means becomes simpler compared to the case where multiple spaced-apart groups of light-emitting elements are grouped together as one set.

[0018] According to the invention described in claim 3, it becomes easier to set the non-scanning period compared to the case in which all sets of multiple light-emitting elements are driven by the same driving means.

[0019] According to the invention described in claim 4, the driving means can reduce the impact on image quality caused by different scanning periods for each set of light-emitting elements, compared to the case where the interval from one scanning period to the next scanning period is divided unevenly according to the number of sets of light-emitting elements.

[0020] According to the invention described in claim 5, the driving means can further reduce the influence of fluctuations in the driving voltage compared to a case where the timing of different non-scanning periods is not considered in relation to fluctuations in the driving voltage.

[0021] According to the invention described in claim 6, the influence of the fluctuation of the driving voltage can be easily reduced as compared with the case where the fluctuation of the driving voltage generated during the non-scanning period is unknown.

[0022] According to the invention described in claim 7, the driving means can further reduce the influence of the fluctuation of the driving voltage as compared with the case where each group of light-emitting element groups is driven before the fluctuation of the driving voltage converges.

[0023] According to the invention described in claim 8, the driving means can cancel the influence caused by the driving voltage falling below the specified value as compared with the case where each light-emitting element group of the next group is caused to emit light when the driving voltage exceeds the specified value.

[0024] According to the invention described in claim 9, the fluctuation of the light amount caused by the fluctuation of the driving voltage can be suppressed and the image quality can be improved as compared with the case where the optical scanning device described in any one of claims 1 to 8 is not used as the exposure means.

Brief Description of the Drawings

[0025] [Figure 1] It is an overall configuration diagram showing an image forming apparatus to which an example of an optical scanning device according to Embodiment 1 of this invention is applied. [Figure 2] It is a cross-sectional configuration diagram showing an LED print head as an example of an optical scanning device according to Embodiment 1 of this invention. [Figure 3] It is a configuration diagram showing an LED circuit board according to Embodiment 1 of this invention. [Figure 4] It is a configuration diagram showing the arrangement state of LEDs in an SLED chip. [Figure 5] It is an explanatory diagram showing the scanning exposure state of a photosensitive drum by an LED print head. [Figure 6] It is an equivalent circuit diagram showing an SLED chip. [Figure 7] It is a circuit diagram showing a transfer thyristor. [Figure 8]This is a timing chart showing the operating status of the SLED chip. [Figure 9] This is a timing chart showing the operating status of the SLED chip. [Figure 10] This is a block diagram of a signal generation circuit. [Figure 11] This is a wiring diagram showing the connection of the SLED chip to the signal generation circuit. [Figure 12] This graph shows the control of exposure levels in an SLED chip. [Figure 13] This graph shows the increased exposure speed in LED print heads. [Figure 14] This is an explanatory diagram illustrating image defects in conventional LED print heads. [Figure 15] This is a schematic diagram illustrating an example of an image defect. [Figure 16] This is a schematic diagram showing an LED print head according to Embodiment 1 of the present invention. [Figure 17] This is a timing chart showing the line sync signal of an LED print head according to Embodiment 1 of this invention. [Figure 18] This graph shows the change in the drive voltage of the LED print head according to Embodiment 1 of this invention. [Figure 19] This is a schematic diagram showing an LED print head according to Embodiment 2 of the present invention. [Figure 20] This graph shows the change in the drive voltage of the LED print head according to Embodiment 2 of this invention. [Figure 21] This graph shows the change in the drive voltage of a conventional LED print head. [Modes for carrying out the invention]

[0026] Embodiments of this invention will be described below with reference to the drawings.

[0027] [Embodiment 1] Figure 1 is a schematic diagram showing the overall configuration of an image forming apparatus to which the optical scanning device according to Embodiment 1 of this invention is applied. In the figure, the reference numeral X indicates the horizontal direction of the image forming apparatus, Y indicates the depth direction of the image forming apparatus, and Z indicates the vertical direction of the image forming apparatus.

[0028] <Overall configuration of the image forming apparatus> The image forming apparatus 1 according to Embodiment 1 is configured, for example, as a so-called tandem-type color printer. As shown in Figure 1, this image forming apparatus 1 is broadly composed of an image processing unit 2, an image forming unit 3, and a control unit 4. The image forming apparatus 1 is connected to, for example, an external device such as an image reader 5 or a personal computer (PC) 6. The image forming apparatus 1 may also have the image reader 5 integrated into the top of the main body of the apparatus. The image processing unit 2 performs predetermined image processing on image data (image information) input from the image reader 5 or personal computer (PC) 6. The image forming unit 3 performs image formation corresponding to the image data of each color that has been processed by the image processing unit 2. The control unit 4 acquires various information indicating the operating status of the image forming apparatus 1 and comprehensively controls the operation of the image forming apparatus 1.

[0029] The image forming unit 3 comprises a plurality of image forming units 10, an intermediate transfer device 20, a paper transport device 50, a fixing device 40, etc. The plurality of image forming units 10 form toner images that are developed with toner constituting the developer. The intermediate transfer device 20 holds the toner images formed by each image forming unit 10 and transports them to a secondary transfer position where they are ultimately transferred to recording paper 7, which is an example of a recording medium. The paper transport device 50 transports the required amount of recording paper 7 to be transported to the secondary transfer position of the intermediate transfer device 20. The recording paper 7 is supplied from a paper feed device (not shown). The fixing device 40 fixes the toner images on the recording paper 7.

[0030] The image forming unit 10 consists of four image forming units 10Y, 10M, 10C, and 10K, each dedicated to forming toner images of four colors: yellow (Y), magenta (M), cyan (C), and black (K). These four image forming units 10 (Y, M, C, K) are arranged along the horizontal direction X in the internal space of the image forming apparatus 1.

[0031] Each image forming unit 10 (Y, M, C, K) includes a photoreceptor drum 11 as an example of an image holder, a charging device 12, an exposure device 13 as an example of an exposure means, a developing device 14, a primary transfer device 15, a drum cleaning device 16, etc. The charging device 12 charges the image-forming surface (image-holding surface) of the photoreceptor drum 11 to the required potential. The exposure device 13 irradiates the charged surface of the photoreceptor drum 11 with light based on image data to form electrostatic latent images for each color with potential differences. The developing device 14 develops the electrostatic latent images with toners of the corresponding color (Y, M, C, K) to form toner images. The primary transfer device 15 transfers each toner image to the intermediate transfer device 20 at the primary transfer position. The drum cleaning device 16 cleans the image-holding surface of the photoreceptor drum 11 by removing any toner or other deposits that remain after the primary transfer.

[0032] As shown in Figure 1, the intermediate transfer device 20 is positioned below each image forming unit 10 (Y, M, C, K) along the vertical Z direction. This intermediate transfer device 20 mainly consists of an intermediate transfer belt 21, a plurality of belt support rolls 22-24, a secondary transfer device 30, and a belt cleaning device (not shown).

[0033] The paper transport device 50 transports the recording paper 7 supplied from a paper feeder (not shown) to the secondary transfer position. The paper transport device 50 also transports the recording paper 7, on which the toner images of each color have been transferred at the secondary transfer position, to the fuser device 40. In the illustrated example, the paper transport device 50 is shown as a belt-type device equipped with a paper transport belt 51, but the paper transport device 50 may also be equipped with multiple pairs of paper transport rolls or the like.

[0034] The fixing device 40 is composed of a heating rotating body 41 and a pressurizing rotating body 42, among other components. In the fixing device 40, the contact area where the heating rotating body 41 and the pressurizing rotating body 42 come into contact becomes the fixing processing unit where the required fixing process (heating and pressurizing) is performed.

[0035] <Operation of the image forming apparatus> The following describes the basic image forming operation of the image forming apparatus 1.

[0036] This section describes the operation in full-color mode, in which a full-color image is formed by combining four toner images (Y, M, C, K) using the four image forming units 10 (Y, M, C, K).

[0037] The image forming apparatus 1 receives image data and command information requesting full-color image forming operations (printing) from the image reading device 5, personal computer 6, etc. Then, the control unit 4 starts the four image forming units 10 (Y, M, C, K), intermediate transfer device 20, secondary transfer device 30, fixing device 40, etc.

[0038] In each image forming unit 10 (Y, M, C, K), as shown in Figure 1, first each photoreceptor drum 11 rotates in the direction indicated by the arrow. Then, each charging device 12 charges the surface of each photoreceptor drum 11 to the required polarity and potential. Subsequently, the exposure device 13 irradiates the charged surface of the photoreceptor drum 11 with light emitted based on image data obtained by converting it into each color component (Y, M, C, K). Then, electrostatic latent images of each color component, composed of the required potential difference, are formed on the surface of each photoreceptor drum 11.

[0039] Next, the developing device 14 for each image forming unit 10 (Y, M, C, K) performs development. Development is performed by supplying toner of the corresponding color (Y, M, C, K), charged with the required polarity, from the developing roll 141 to electrostatically adhere to the electrostatic latent images of each color component formed on the photoreceptor drum 11. Through this development, the electrostatic latent images of each color component formed on each photoreceptor drum 11 are revealed as four toner images of the corresponding colors (Y, M, C, K), which have been developed with the toner of their respective colors.

[0040] Next, the toner images of each color formed on the photoreceptor drum 11 of each image forming unit 10 (Y, M, C, K) are transported to the primary transfer position. Then, the primary transfer device 15 performs a primary transfer, sequentially overlapping the toner images of each color onto the intermediate transfer belt 21 of the intermediate transfer device 20, which rotates in the direction indicated by the arrow.

[0041] Furthermore, in each image forming unit 10 (Y, M, C, K) after the primary transfer is completed, the drum cleaning device 16 cleans the surface of the photoreceptor drum 11 by scraping off any attached material. This prepares each image forming unit 10 (Y, M, C, K) for the next image formation operation.

[0042] Next, the intermediate transfer device 20 holds the toner image transferred in the first stage by the rotation of the intermediate transfer belt 21 and transports it to the secondary transfer position. Meanwhile, the paper transport device 50 feeds and supplies the required recording paper 7 to the secondary transfer position in accordance with the image formation operation and the transfer timing.

[0043] At the secondary transfer position, the secondary transfer device 30 transfers the toner image on the intermediate transfer belt 21 onto the recording paper 7 in one go. After the secondary transfer is complete, the intermediate transfer device 20 uses a belt cleaning device (not shown) to remove any toner or other deposits remaining on the surface of the intermediate transfer belt 21 after the secondary transfer.

[0044] Next, the recording paper 7 on which the toner image has been secondarily transferred is transported to the fuser unit 40 by the paper transport belt 51. In the fuser unit 40, the necessary fixing process (heating and pressurizing) is performed by the heating rotating body 41 and the pressurizing rotating body 42 to fix the unfixed toner image to the recording paper 7. Finally, the recording paper 7 on which fixing is complete is discharged to a paper discharge unit (not shown).

[0045] Through the above operations, a recording sheet 7 is output, on which a full-color image composed of four toner images is formed.

[0046] <Configuration of the exposure system> As shown in Figure 2, the image forming apparatus 1 according to this embodiment 1 includes an exposure apparatus 13 as an example of an optical scanning apparatus.

[0047] The exposure apparatus 13 is positioned across an image forming area along the axial direction (perpendicular to the drawing) of the photoreceptor drum 11, which is an example of an object to be scanned, so as to face the photoreceptor drum 11. The exposure apparatus 13 consists of an LED print head 60, which is an example of a scanning means, in which a plurality of LEDs (Light Emitting Diodes) as light-emitting elements are arranged along the main scanning direction, which is the axial direction of the photoreceptor drum 11. The LED print head 60 scans and exposes the surface of the photoreceptor drum 11, which is charged to a required potential by the charging device 12 and rotated at a required rotational speed (peripheral speed), with light corresponding to the image information to form an electrostatic latent image.

[0048] The LED print head 60 comprises a housing 61 as a support, an LED circuit board 62, a rod lens array 64, etc. As shown in Figure 3, the LED circuit board 62 is equipped with an LED array 63 in which a plurality of LEDs are arranged along the main scanning direction, and a signal generation circuit 100 as an example of a driving means for driving the LED array 63.

[0049] The LED print head 60 uses a self-scanning light-emitting device (SLED) 65 as the LED array 63.

[0050] The rod lens array 64 is an optical component that projects light from the SLED 65 onto the surface of the photoreceptor drum 11. The housing 61 holds the rod lens array 64 and shields and protects the SLED 65 from the outside.

[0051] The housing 61 is formed from a metal such as aluminum or stainless steel, or a heat-resistant synthetic resin, and is a long, frame-like or block-like structure extending in a direction intersecting the drawing. An LED circuit board 62 is positioned on the end face of the housing 61 facing the photosensitive drum 11. The housing 61 holds the LED circuit board 62 and the rod lens array 64. In this configuration, the housing 61 aligns the light-emitting point of the SLED 65 provided on the LED circuit board 62 with the focal point of one end of the rod lens array 64 along the optical axis direction (vertical direction in the drawing).

[0052] The LED print head 60 configured in this way is movable along the optical axis direction of the rod lens array 64 by an adjustment screw (not shown). The LED print head 60 is set so that the imaging position (focal plane) of the other end of the rod lens array 64 along the optical axis direction is located on the surface of the photoreceptor drum 11.

[0053] As shown in Figure 3, the LED circuit board 62 has SLED chips 67-1 to 67-40 arranged in a straight line with precision parallel to the axis direction of the photoreceptor drum 11, as an example of a group of multiple (e.g., 40) light-emitting elements that make up the SLED 65. Each SLED chip 67-1 to 67-40 has LEDs arranged on it as an example of a group of multiple (e.g., 256) light-emitting elements. The SLED chips 67-1 to 67-40 are arranged alternately in a staggered pattern. In this case, as shown in Figure 4, the LEDs of each SLED chip 67-1 to 67-40 are arranged to be continuous at equal intervals at adjacent ends.

[0054] Furthermore, as shown in Figure 3, the LED circuit board 62 includes a signal generation circuit 100, a power supply circuit 101, an EEPROM 102 as an example of a storage means, and a harness 103 at one end along the longitudinal direction of the SLED chips 67-1 to 67-40. The signal generation circuit 100 generates a signal (lighting signal) to drive each of the SLED chips 67-1 to 67-40. The power supply circuit 101 consists of a constant voltage power supply such as a three-terminal regulator that outputs a predetermined voltage to each of the SLED chips 67-1 to 67-40. The EEPROM 102 stores light intensity unevenness correction values ​​for each of the SLED chips 67-1 to 67-40. The harness 103 transmits and receives various signals between the signal generation circuit 100 and the control unit 4 and the image processing unit 2.

[0055] As shown in Figures 5(a) and 5(b), when the LED print head 60 performs image exposure on the surface of the photoreceptor drum 11 based on image data, each SLED chip 67-1 to 67-40 is driven simultaneously for each line. When scanning exposure of one line is completed, each SLED chip 67-1 to 67-40 starts scanning exposure of the next line after a required pause period. In Figure 5(b), the dashed arrows indicate the state in which the scanning exposure position moves with the pause period in between.

[0056] In the illustrated example, as shown in Figure 5(b), the case where each SLED chip 67-1 to 67-40 scans in the same direction, that is, from the left end to the right end in the figure. However, it is not limited to this, and each SLED chip 67-1 to 67-40 may be configured so that adjacent SLED chips 67-1 to 67-40 scan in opposite directions, for example, the first SLED chip 67-1 scans from the left end to the right end in the figure, and the second SLED chip 67-2 scans from the right end to the left end in the figure.

[0057] <SLEDチップ> Figure 6 is an equivalent circuit diagram showing the circuit configuration of an SLED chip mounted on an LED print head according to this embodiment 1. As shown in Figure 6, the SLED chip 67 has multiple (four in the illustrated example) terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) on the substrate 68. In addition, a Vsub terminal is provided on the back surface of the substrate 68. Here, the first SLED chip 67-1 will be used as an example to explain its relationship with the signal generation circuit 100. The other SLED chips 67-2 to 67-40 are configured similarly to SLED chip 67-1.

[0058] As shown in Figure 6, the SLED chip 67-1 is broadly divided into a light-emitting section 201 and a transfer section 202. The light-emitting section 201 of the SLED chip 67-1 includes a plurality of light-emitting thyristors L1, L2, L3, ... as an example of a plurality of light-emitting elements arranged linearly on the substrate 68. The transfer section 202 of the SLED chip 67-1 includes a plurality of transfer thyristors T1, T2, T3, ... arranged linearly on the substrate 68 corresponding to the plurality of light-emitting thyristors L1, L2, L3, ...

[0059] Multiple light-emitting thyristors L1, L2, L3... and multiple transfer thyristors T1, T2, T3... are formed on a substrate 68 made of a Si substrate or the like as semiconductor elements, each having a second gate Gts on the anode side in addition to the usual first gates Glf and Gtf on the cathode side. Figure 7 is a circuit diagram in which the transfer thyristor T1 is replaced with a transistor. Note that the second gates Gls of the light-emitting thyristors L1, L2, L3... are not connected to other elements and are therefore not shown.

[0060] Multiple light-emitting thyristors L1, L2, L3... and multiple transfer thyristors T1, T2, T3... are connected to Vsub terminals, each with an anode wired to the back surface of the substrate 68, as shown in Figure 6. The Vsub terminals are connected to the power supply circuit 101 of the LED circuit board 62 via power line 200. In this embodiment 1, the power supply circuit 101 is set to "H" (3.3V). Therefore, the potential of the Vsub terminals is "H" (3.3V). From the power supply circuit 101, a lighting current flows to the Vsub terminal of the SLED chip 67-1 via power line 200. The ignition current for the multiple light-emitting thyristors L1, L2, L3, etc. flows from the Vsub terminal to the anode of each light-emitting thyristor L1, L2, L3, etc., and then flows from the cathode through each light-emitting thyristor L1, L2, L3, etc., through the ignition signal line 70 and the ignition time control / drive units 118-1 to 118-40 of the signal generation circuit 100 to the reference potential supply unit 69 which serves as a return power supply. Here, the potential of the Vsub terminal is assumed to be "H" (3.3V) and the potential of the Vga terminal is assumed to be "L" (0V). However, in order to explain the operation of the SLED chip 67-1, the potential of the Vsub terminal may be assumed to be "H" (0V) and the potential of the Vga terminal may be assumed to be "L" (-3.3V).

[0061] The cathodes of multiple light-emitting thyristors L1, L2, L3, etc. are connected to the illumination signal line 70. The illumination signal line 70 is connected to the φI1 terminal of the SLED chip 67-1. The φI1 terminal of the SLED chip 67-1 is connected to the illumination time control / drive unit 118 of the signal generation circuit 100 via a current limiting resistor RI. The illumination time control / drive unit 118 transmits an illumination signal φI1 that controls whether each light-emitting thyristor L1, L2, L3, etc. is illuminated and the illumination time. The illumination signal φI1 supplies current to the light-emitting thyristors L1, L2, L3, etc. for illumination. For convenience, terminals and signals, or terminals and the voltage applied to those terminals, etc., will be indicated by the same symbol here.

[0062] The first gates Glfn of the multiple light-emitting thyristors L1, L2, L3, etc., are connected to the power line 71 via resistors Rgn, as shown in Figure 6. The power line 71 is connected to the Vga terminal of the SLED chip 67-1. The Vga terminal is connected to the reference potential supply unit 69, which serves as a return power supply, via the reference potential line 206. The reference voltage Vga of the reference potential supply unit 69 is set to, for example, -3.3V.

[0063] Meanwhile, among the multiple transfer thyristors T1, T2, T3, etc., the cathodes of the odd-numbered transfer thyristors T1, T3, T5, etc. are connected to the first transfer signal line 72 to which the first transfer signal φ1 is transmitted. The first transfer signal line 72 is connected to the φ1 terminal of the SLED chip 67 via a current limiting resistor R1 to prevent excessive current from flowing. The first transfer signal φ1 is transmitted to the φ1 terminal of the SLED chip 67 from the timing signal generation unit 114 of the signal generation circuit 100.

[0064] Among a plurality of transfer thyristors T1, T2, T3 ···, the cathodes of the even-numbered transfer thyristors T2, T4, T6 ··· are connected to a second transfer signal line 73 to which a second transfer signal φ2 is transmitted. The second transfer signal line 73 is connected to the φ2 terminal of the SLED chip 67 via a current limiting resistor R2 for preventing excessive current from flowing. The second transfer signal φ2 is transmitted from the timing signal generation unit 114 of the signal generation circuit 100 to the φ2 terminal of the SLED chip 67.

[0065] For the SLED chip 67-1, coupling transistors Q1, Q2, Q3 ··· are respectively arranged between two adjacent transfer thyristors Tn, Tn+1. The bases of each of the coupling transistors Q1, Q2, Q3 ··· are connected to the second gate Gtsn of the transfer thyristor Tn located in the previous stage. Also, the collector terminals of each of the coupling transistors Q1, Q2, Q3 ··· are connected to the first gate Gtfn+1 of the transfer thyristor Tn+1 located in the subsequent stage via a resistor Rcn. Note that the bases of each of the coupling transistors Q1, Q2, Q3 ··· are connected to a Vsub terminal wired on the back surface of the substrate 68.

[0066] Furthermore, for the first transfer thyristor T1, its first gate Gtf1 is connected to the second transfer signal line 73 located at the subsequent stage of the current limiting resistor R2 via a start resistor Rs.

[0067] <Operation of SLED Chip> FIG. 8 is a timing chart showing the operation of the SLED chip 67 of the LED print head 60 according to this Embodiment 1.

[0068] In FIG. 8, a timing chart for controlling the lighting or non-lighting of the first to fifth of a plurality (for example, 256) of light emitting thyristors L1 to L256 of the SLED chip 67 is shown. In FIG. 8, the light emitting thyristors L1, L2, L3, L5 of the SLED chip 67 are lit, and the light emitting thyristor L4 is not lit.

[0069] Of the multiple SLED chips 67-1 to 67-40 arranged on the LED circuit board 62, the other SLED chips 67-2 to 67-40 are driven simultaneously with SLED chip 67-1, as shown in Figure 5. Here, we will describe the operation of the first SLED chip 67-1.

[0070] First, when image exposure by the LED print head 60 is started, the control unit 4 transmits a line sync signal Lsync to the timing signal generation unit 114 of the signal generation circuit 100. The line sync signal Lsync consists of a signal that rises from a "L" state to a "H" state for each line when scanning and exposing the surface of the photoreceptor drum 11, and then falls from a "H" state to a "L" state. Before the line sync signal Lsync falls, as shown at time a in Figure 8, the first and second transfer signals φ1, φ2 and the lighting signal φI1 are all "H" (0V).

[0071] At this time, as shown in Figure 6, the transfer section 202 of the SLED chip 67 is connected to the first transfer signal line 72, where the cathodes of the odd-numbered transfer thyristors T1, T3, T5, etc. are set to "H". Similarly, the cathodes of the even-numbered transfer thyristors T2, T4, T6, etc. are connected to the second transfer signal line 73, which is set to "H". Therefore, the transfer thyristors T1, T3, T5, etc. and the transfer thyristors T2, T4, T6, etc. are in the off state because both their anodes and cathodes are "H".

[0072] On the other hand, the cathodes of the light-emitting thyristors L1, L2, L3, etc. are connected to the illumination signal line 70, which is set to "H". Therefore, the light-emitting thyristors L1, L2, L3, etc. are also in the off state because both their anode and cathode are set to "H".

[0073] In this case, the first transfer thyristor T1 in the transfer unit 202 has its first gate Gtf1 connected to the "L" (-3.3V) power line 71 via resistor Rg1, as shown in Figure 6. Furthermore, the first transfer thyristor T1 has its first gate Gtf1 connected to the "H" (0V) second transfer signal line 73 via start resistor Rs.

[0074] Therefore, the potential of the first gate Gtf1 of the first transfer thyristor T1 is the potential obtained by dividing the potential difference between the "L" (-3.3V) of the power line 71 and the "H" (0V) of the second transfer signal line 73 by resistor Rg1, start resistor Rs, and current limiting resistor R2. If we set resistor Rg1 to 10kΩ, start resistor Rs to 2kΩ, and current limiting resistor R2 to 300Ω, the potential of the first gate Gtf1 will be -0.62V. The threshold voltage of the first transfer thyristor T1 is Vgtf-Vd, so it is -0.62-1.5=-2.12V. Here, Vd is the diffusion potential of the first transfer thyristor T1 (for example, 1.5V). The potential of the first gate Gtf1 of the first transfer thyristor T1 is set, as described above, by the voltage of "L" (-3.3V) on the power line 71 and the resistance values ​​of resistor Rg1, start resistor Rs, and current limiting resistor R2. Also, the first light-emitting thyristor L1 has a threshold voltage of -2.12V because its first gate Glf1 is connected to the first gate Vgtf1 of the first transfer thyristor T1.

[0075] At this time, the first transfer thyristor T1 is in the off state, so the coupling transistor Q1 is also in the off state. Therefore, the first gate Gtf2 of the second transfer thyristor T2 is connected to the potential of the power line 71, "L" (-3.3V), via resistor Rg2. Thus, the threshold voltage for the second transfer thyristor T2 is -3.3V - 1.5 = -4.8V. Similarly, the threshold voltages for the third and subsequent transfer thyristors T3, T4, and T5 are also -4.8V.

[0076] Next, as shown at time b in Figure 8, when the line sync signal Lsync falls to the "L" state, the first transfer signal φ1 output from the timing signal generator 114 of the signal generation circuit 100 changes from "H" to "L" in synchronization with the SLED chip 67. Then, the first transfer thyristor T1, whose threshold voltage is -2.12V, turns on as shown in Figure 6, because the first transfer signal line 72, i.e., the cathode, becomes "L" (-3.3V). However, the odd-numbered transfer thyristors T from the third onward have their cathodes connected to the first transfer signal line 72, but as mentioned above, their threshold voltage is -4.8V, so they do not turn on and remain in the off state. On the other hand, the even-numbered transfer thyristors T2, T4, T6, etc. do not turn on because the second transfer signal line 73 remains "H" (0V).

[0077] In the first transfer thyristor T1, which is in the ON state, the first gate Gtf1 becomes the saturation potential Vc of transistor Tr1, as shown in Figure 7. Here, the saturation potential Vc is assumed to be -0.2V as an example. Therefore, in the first transfer thyristor T1, the first gate Gtf1 becomes -0.2V, and the second gate Gts1 becomes the potential obtained by subtracting the diffusion potential Vd (1.5V) from the anode A1 ("H" (0V)) (-1.5V).

[0078] Furthermore, in the first transfer thyristor T1 when it is ON, current flows from the anode A1 ("H" (0V)) towards the terminal φ1 ("L" (-3.3V)) to which the cathode K1 is connected. Therefore, the potential Vk of the cathode K1 of the first transfer thyristor T1 when it is ON is expressed by the following equation (1), using the internal resistance rk (let the resistance value be rk), current limiting resistor R1 (let the resistance value be R1), and diffusion potential Vd of the first transfer thyristor T1 when it is ON.

[0079] Vk=(Vga+Vd)×{rk / (R1+rk)}-Vd (1)

[0080] For example, if the current limiting resistor R1 is 300Ω and the internal resistance rk is 60Ω, the potential Vk of cathode K1 will be -1.8V. Note that the potential Vk of cathode K1 is the potential of the first transfer signal line 72.

[0081] Then, as mentioned above, the first transfer thyristor T1 has a first gate Gtf1 of -0.2V. The first light-emitting thyristor L1 has a first gate Glf1 connected to the first gate Gtf1 (0.2V) of the transfer thyristor T1, so the threshold voltage is -0.2 - 1.5 = -1.7V.

[0082] On the other hand, when the first transfer thyristor T1 turns on, the coupling transistor Q1 transitions from the off state to the on state. As a result, the first gate Gtf2 of the second transfer thyristor T2 transitions to -0.72V, and the threshold voltage for the second transfer thyristor T2 and the second light-emitting thyristor L2 becomes -2.22V. However, since the second transfer signal line 73 is "H" (0V), the second transfer thyristor T2 does not turn on. Also, since the illumination signal line 70 is "H" (0V), the second light-emitting thyristor L2 does not turn on either.

[0083] Since the second transfer thyristor T2 is in the off state, the coupling transistor Q2 is also in the off state. Therefore, the first gate Gtf3 of the third transfer thyristor T3 is "L" (-3.3V), and the threshold voltage for the third transfer thyristor T3 and the third light-emitting thyristor L3 is -4.8V. Similarly, the threshold voltage for transfer thyristors T and light-emitting thyristors L numbered 4 or higher is also -4.8V.

[0084] Immediately after time b (here, this refers to the time when a steady state is reached after changes in thyristors, etc., have occurred due to the change in signal potential at time b), the first transfer thyristor T1 and coupling transistor Q1 are in the ON state, while the other transfer thyristors T and coupling transistor Q, and all light-emitting thyristors L are in the OFF state.

[0085] Subsequently, as shown in Figure 8, at time c, the illumination signal φI1 transitions from "H" to "L". Then, as shown in Figure 6, the illumination signal line 70 transitions from "H" (0V) to "L" (-3.3V) via the current limiting resistor RI and the φI terminal. At this point, the first light-emitting thyristor L1, which has a threshold voltage of -1.7V, turns on and lights up (emits light). As a result, the illumination signal line 70 becomes -1.86V.

[0086] As mentioned above, the second light-emitting thyristor L2 has a threshold voltage of -2.22V, but the first light-emitting thyristor L1, which has a higher threshold voltage of -1.7V, turns on and raises the illumination signal line 70 to -1.86V, so the second light-emitting thyristor L2 does not turn on.

[0087] Immediately after time c, the first transfer thyristor T1 and the first coupling transistor Q1 are ON, and the first light-emitting thyristor L1 is ON and illuminated.

[0088] Next, at time d, the illumination signal φI1 transitions from "L" to "H". Then, via the current limiting resistor RI and the φI terminal, the illumination signal line 70 transitions from -1.86V to "H" (0V). As a result, the first light-emitting thyristor L1 turns off as both its anode and cathode become "H". The illumination period t1 of the first light-emitting thyristor L1 is the period from time c, when the illumination signal φI1 transitions from "H" to "L", to time d, when the illumination signal φI1 transitions from "L" to "H". Therefore, the illumination period t1 of the first light-emitting thyristor L1 is controlled by the time the illumination signal φI1 remains in the "L" state, based on image data, etc. Immediately after time d, the first transfer thyristor T1 and the first coupling transistor Q1 are in the ON state.

[0089] Furthermore, at time e, the second transfer signal φ2 transitions from "H" to "L". At this point, the period T(1) for controlling the illumination of the first light-emitting thyristor L1 ends, and the period T(2) for controlling the illumination of the second light-emitting thyristor L2 begins. Then, the φ2 terminal transitions from "H" to "L" (-3.3V). Since the first transfer thyristor T1 is in the ON state, the first gate Gtf1 of the first transfer thyristor T1 is -0.2V. Therefore, the second transfer signal line 73 is the value obtained by dividing the potential difference between "L" (-3.3V) and -0.2V by the start resistor Rs (2kΩ) and the current limiting resistor R2 (300Ω). That is, the second transfer signal line 73 becomes -2.9V.

[0090] At time b, the second transfer thyristor T2 turns on because its threshold voltage is -2.22V. As a result, the first gate Gtf2 (first gate Glf2) of the second transfer thyristor T2 becomes -0.2V, and the threshold voltage of the second light-emitting thyristor L2 becomes -1.7V. When the second transfer thyristor T2 turns on, the second transfer signal line 73 becomes -1.8V.

[0091] Furthermore, when the second transfer thyristor T2 turns on, the second coupling transistor Q2 transitions from the off state to the on state, and the first gate Gtf3 of the third transfer thyristor T3 becomes -0.72V. Therefore, the threshold voltage for the third transfer thyristor T3 and the third light-emitting thyristor L3 becomes -2.22V. Transfer thyristors T and light-emitting thyristors L numbered 4 or higher maintain a threshold voltage of -4.8V. Note that the lighting signal φI1 is "H" (0V), so none of the light-emitting thyristors L turn on. Immediately after time e, the first and second transfer thyristors T1, T2 and the first and second coupling transistors Q1, Q2 are in the on state.

[0092] Subsequently, at time f, the first transfer signal φ1 transitions from "L" to "H". Then, the potential of the first transfer signal line 72 via terminal φ1 transitions from "L" to "H". As a result, the ON transfer thyristor T1 turns off, with both its anode and cathode becoming "H".

[0093] The first gate Gtf1 (first gate Glf1) is connected to the power line 71 ("L" (-3.3V)) via resistor Rg1, and also to the second transfer signal line 73, which is "L" (-3.3V), via start resistor Rs. Therefore, the first transfer thyristor T1 is turned on when the first gate Gtf1 (first gate Glf1) changes from -0.2V to "L" (-3.3V), and the threshold voltage between the first transfer thyristor T1 and the first light-emitting thyristor L1 becomes -4.8V. Immediately after time f, the second transfer thyristor T2 is turned on.

[0094] Subsequently, at time g, when the illumination signal φI1 changes from "H" to "L", the second light-emitting thyristor L2 turns on and lights up, similar to the first light-emitting thyristor L1 at time c. Then, at time h, when the illumination signal φI1 changes from "L" to "H", the second light-emitting thyristor L2 turns off and turns off, similar to the light-emitting thyristor L1 at time d.

[0095] Furthermore, at time i, when the first transfer signal φ1 transitions from "H" to "L", the third transfer thyristor T3, with a threshold voltage of -2.22V, turns on, similar to the first transfer thyristor T1 at time b or the second transfer thyristor T2 at time e. At this time, the first transfer thyristor T1 does not turn on because its threshold voltage is -4.8V. At time i, the period T(2) for controlling the illumination of the second light-emitting thyristor L2 ends, and the period T(3) for controlling the illumination of the third light-emitting thyristor L3 begins.

[0096] Furthermore, if you want to keep the light-emitting thyristor L off-light, you can simply keep the lighting signal φI1 at "H" (0V) as shown in Figure 8, during the lighting control period T(4) for light-emitting thyristor L4. In this way, the fourth light-emitting thyristor L4 will remain off-light even if the threshold voltage remains at -1.7V.

[0097] From this point onward, the process repeats as described above until the illuminating / deactivating of the 256th light-emitting thyristor, L256, is controlled. Once the illuminating / deactivating control of the 256th light-emitting thyristor, L256, is complete, the first and second transfer signals φ1, φ2, and the illumination signal φI1 all become "H" (0V), and the process transitions to a pause period.

[0098] At this time, as shown in Figure 6, a Vsub (0V) is applied to the Vsub terminal of each SLED67 via the power supply line 200 by the power supply circuit 101 consisting of a constant voltage power supply. At the φI1 terminal, a lighting current flows from the anode, which is "H" (0V), of the light-emitting thyristors L1, L2, L3, etc., which light up when the lighting signal φI1 of each SLED67 transitions to "L" via the lighting signal line 70.

[0099] The ignition current flowing to these light-emitting thyristors L1, L2, L3... varies depending on the number of light-emitting thyristors L1, L2, L3... among the SLED chips 67-1 to 67-40 that are lit simultaneously, the lighting time, and the lighting intensity. For the sake of simplicity, the lighting intensity of light-emitting thyristors L1, L2, L3... is assumed to be constant in this explanation.

[0100] Therefore, in the SLED chips 67-1 to 67-40 of the LED print head 60, depending on the lighting state of the light-emitting thyristor L located immediately before the rest period, a large lighting current may flow to the Vsub terminal via the power line 200 through the power supply circuit 101 consisting of a constant voltage power supply. This large lighting current is then cut off simultaneously with the start of the rest period.

[0101] Figure 10 is a block diagram showing the configuration of the signal generation circuit.

[0102] As shown in Figure 10, the signal generation circuit 100 includes an image data unpacking unit 110 that receives image data from the image processing unit 2. The image data unpacking unit 110 unpacks the image data input from the image processing unit 2 into image data of 256 pixels each, corresponding to each SLED chip 67-1 to 67-40, for each line. The image data unpacked by the image data unpacking unit 110 is transmitted to the lighting time control and driving units 118-1 to 118-40, which are provided corresponding to each SLED chip 67-1 to 67-40.

[0103] Furthermore, the signal generation circuit 100 includes a correction value calculation unit 112 that receives a correction value for light intensity unevenness from the EEPROM 102 on the LED circuit board 62. Image data is input to the correction value calculation unit 112 from the image processing unit 2. The correction value for light intensity unevenness is determined in advance, for example, by actually lighting each SLED chip 67-1 to 67-40 and measuring the light intensity unevenness at the time of shipment. The correction value calculation unit 112 calculates the correction value for light intensity unevenness and transmits the light intensity unevenness correction value to the lighting time control / drive units 118-1 to 118-40 that drive the corresponding SLED chips 67-1 to 67-40.

[0104] Furthermore, the signal generation circuit 100 includes a timing signal generation unit 114 and a reference clock generation unit 116. The timing signal generation unit 114 receives a line sync signal Lsync, thyristor transfer period setting data, and light intensity adjustment data from the control unit 4. The thyristor transfer period setting data is data for appropriately setting the thyristor transfer period according to the print speed, etc. The timing signal generation unit 114 outputs a data readout signal to the image data development unit 110 and the correction value calculation unit 112. The timing signal generation unit 114 also outputs a trigger signal TRG to the lighting time control / drive units 118-1 to 118-40 for synchronization. Furthermore, the timing signal generation unit 114 outputs first and second transfer signals φ1 and φ2 to each SLED chip 67-1 to 67-40. The lighting time control and drive units 118-1 to 118-40 output lighting signals φI1 to φI40 to each SLED chip 67-1 to 67-40 according to the image data and light intensity unevenness correction value data.

[0105] The reference clock generation unit 116 outputs a reference clock signal to the timing signal generation unit 114 and the lighting time control / drive unit 118.

[0106] Figure 11 is a circuit diagram showing the wiring between the signal generation circuit 100 and each of the SLED chips 67-1 to 67-40.

[0107] Each SLED chip 67-1 to 67-40 has a φI terminal connected to the corresponding lighting time control / drive unit 118-1 to 118-40 of the signal generation circuit 100 via a current limiting resistor RI through a lighting signal line 203-1 to 203-40. In addition, the φ1 and φ2 terminals of each SLED chip 67-1 to 67-40 are connected to the timing signal generation unit 114 of the signal generation circuit 100 via first and second transfer signal lines 204 and 205, respectively. Furthermore, each SLED chip 67-1 to 67-40 has a Vsub terminal connected to the power supply circuit 101 via a power supply line 200, and a Vga terminal connected to the reference potential supply unit 69 via a reference potential line 206.

[0108] Incidentally, in the image forming apparatus 1 to which the LED print head 60 configured as described above is applied, high speed is required in order to increase the number of prints per unit time and achieve high productivity. To meet the demand for high speed in the image forming apparatus 1, it is necessary to increase the process speed, which is defined by the rotation speed of the photoreceptor drum 11 in each image forming unit 10 (Y, M, C, K). Furthermore, the LED print head 60 that exposes the surface of the photoreceptor drum 11 to images is required to meet the demand for high speed by increasing the number of lights illuminated per unit time.

[0109] As shown in Figure 12, the LED print head 60 adjusts the exposure amount when exposing the surface of the photoreceptor drum 11 according to the image data, by adjusting at least one of the maximum light output determined by the drive voltage applied to each LED of the LED print head 60 and the light emission time of each LED. In order to meet the demand for higher speed in the LED print head 60, it is desirable to increase the drive voltage applied to each LED and to shorten the scanning time required to expose one line of the photoreceptor drum 11.

[0110] As shown in Figure 13, with the LED print head 60, as the speed increases, it is necessary to shorten the idle period, which is the non-scanning period set between scanning periods, in order to reduce the scanning time required to expose one line of the photoreceptor drum 11.

[0111] As a result, the LED print head 60 increases the relative current flowing through each LED as the driving voltage to each LED is increased. In addition, during the pause period set between scanning periods, the relatively large current flowing through each LED is instantaneously cut off.

[0112] As shown in Figure 10, the LED print head 60 has inductance, including capacitance, in the power supply line 200 that applies the drive voltage to each LED from the power supply circuit 101, which consists of a DC-DC converter, etc. Therefore, as shown in Figure 14, in the LED print head 60, even if the relatively large current flowing to each LED is instantaneously interrupted by the inductance of the power supply line 200, the supply current decreases gradually, causing the voltage of the power supply circuit 101 to rise sharply due to excessive current. As a result, when the rest period ends and the next line exposure starts in the LED print head 60, the voltage of the power supply circuit 101 is high, then drops sharply, and then returns to the normal voltage.

[0113] In conventional LED print heads 60, the drive voltage fluctuates at the start of the scanning period immediately after the end of the rest period, causing the light intensity of the LEDs in the LED print head 60 to fluctuate. Therefore, at the start of scanning by the exposure device 13, there was a technical problem in that density unevenness, such as white streaks of low density and black streaks of high density, may occur in the halftone image, as shown in Figure 15.

[0114] Therefore, in the optical scanning apparatus according to this embodiment, the driving means is configured to divide a plurality of light-emitting element groups into a plurality of sets, and to make the timing of the non-scanning period set during the scanning period different in at least two of the light-emitting element groups divided into the plurality of sets.

[0115] Furthermore, in the optical scanning device according to this embodiment, the driving means is configured to drive each group of light-emitting elements after the fluctuations in the driving voltage have subsided.

[0116] In other words, the LED print head 60, as an example of an optical scanning device according to this embodiment 1, is shown in Figure 16, in which multiple SLED chips 67-1 to 67-40 mounted on an LED circuit board 62 are divided into multiple groups (four in the illustrated example) of multiple chips (ten in the illustrated example). The first group of SLED chips 301 consists of SLED chips 67-1 to 67-10. The second group of SLED chips 302 consists of SLED chips 67-11 to 67-20. The third group of SLED chips 303 consists of SLED chips 67-21 to 67-30. The fourth group of SLED chips 304 consists of SLED chips 67-31 to 67-40. In the illustrated example, there is a gap between adjacent groups of SLED chips, but adjacent groups of SLED chips are arranged in a continuous fashion, as shown in Figure 4.

[0117] Each group of SLED chips 301-304 is equipped with multiple (four in the illustrated example) signal generation circuits 1001-1004, which are examples of driving means mounted on the LED circuit board 62 corresponding to each group of SLED chips 301-304. The first group of SLED chips 301 is driven by signal generation circuit 1001. The second group of SLED chips 301 is driven by signal generation circuit 1002. The third group of SLED chips 301 is driven by signal generation circuit 1003. The fourth group of SLED chips 301 is driven by signal generation circuit 1004. Each of the signal generation circuits 1001-1004 is similarly configured as an ASIC (Application Specific Integrated Circuit). Each of the signal generation circuits 1001-1004 has a different timing for the idle period, which is a non-scanning period set during the scanning period.

[0118] To explain further, each signal generation circuit 1001 to 1004 starts scanning exposure for one line at a time, based on the line sync signal Lsync output from the control unit 4, as shown in Figure 9. At this time, as shown in Figure 17, the control unit 4 is configured to shift the timing of outputting line sync signals Lsync1 to Lsync4 to each signal generation circuit 1001 to 1004 by a time S / 4, which is the time obtained by dividing the scanning period S required to scan one line on the surface of the photoreceptor drum 11 into several m (=4) SLED chip groups 301 to 304. The scanning period S includes the lighting period and the rest period for each SLED chip 67-1 to 67-40, as shown in Figure 9.

[0119] The SLED chips 67-1 to 67-10 belonging to the first group of SLED chips 301 are controlled to light up by the signal generation circuit 1001 based on the first line sync signal Lsync1 output from the control unit 4. The SLED chips 67-11 to 67-20 belonging to the second group of SLED chips 302 are controlled to light up by the signal generation circuit 1002 based on the second line sync signal Lsync2 output from the control unit 4. Furthermore, the SLED chips 67-21 to 67-30 belonging to the third group of SLED chips 303 are controlled to light up by the signal generation circuit 1003 based on the third line sync signal Lsync3 output from the control unit 4. Similarly, the SLED chips 67-31 to 67-40 belonging to the fourth group of SLED chips 304 are controlled to light up by the signal generation circuit 1004 based on the fourth line sync signal Lsync4 output from the control unit 4.

[0120] <Operation of the exposure device> In the above configuration, the image forming apparatus to which the LED print head according to this embodiment 1 is applied can suppress fluctuations in light intensity caused by fluctuations in drive voltage, compared to the case where the non-scanning periods in multiple light-emitting element groups are the same, in the following manner.

[0121] In other words, in the image forming apparatus 1 according to this embodiment 1, as shown in Figure 1, it receives image data and command information requesting a full-color image forming operation (print) from an image reading device 5, a personal computer 6, etc. Then, the control unit 4 drives the photoreceptor drum 11 of each image forming unit 10 (Y, M, C, K) and charges the surface of each photoreceptor drum 11 with a charging device 12. After that, the surface of each photoreceptor drum 11 is irradiated with light emitted based on image data obtained by converting each color component (Y, M, C, K) by the LED print head 60.

[0122] In this process, as shown in Figures 10 and 16, the LED print head 60 is driven by signal generation circuits 1001 to 1004 corresponding to each set of SLED chips 301 to 304, with SLED chips 67-1 to 67-40 belonging to each set of SLED chips 301 to 304 being driven. Each signal generation circuit 1001 to 1004 controls the illumination / de-illumination and illumination time of the 256 light-emitting thyristors L1 to L256 of each SLED chip 67-1 to 67-40 according to the illumination signal φI flowing through the illumination signal lines 203-1 to 203-40, based on the first to fourth line sync signals Lsync1 to Lsync4 and image data transmitted individually from the control unit 4.

[0123] At this time, the first to fourth line sync signals Lsync1 to Lsync4, which are individually transmitted from the control unit 4, are output sequentially with a shift of time (S / 4) equal to four equal parts of the scanning period S, which includes the pause period required to scan one line on the surface of the photoreceptor drum 11, as shown in Figure 17.

[0124] Therefore, when the LED print head 60 exposes the surface of the photosensitive drum 11 to an image according to the image data, the SLED chips 67-1 to 67-10 belonging to the first group of SLED chips 301 are first driven by the signal generation circuit 1001. Subsequently, the LED print head 60 drives the SLED chips 67-11 to 67-20 belonging to the second group of SLED chips 302 by the signal generation circuit 1002 based on the second line sync signal Lsync2 output from the control unit 4 with a delay of time (S / 4).

[0125] Subsequently, similarly, the LED print head 60 is driven by the signal generation circuit 1003 based on a third line sync signal Lsync3 output from the control unit 4 with a time delay of (S / 4), and the SLED chips 67-21 to 67-30 belonging to the third group of SLED chips 303 are driven. Finally, the LED print head 60 is driven by the signal generation circuit 1004 based on a fourth line sync signal Lsync4 output from the control unit 4 with a time delay of (S / 4), and the SLED chips 67-31 to 67-40 belonging to the fourth group of SLED chips 304 are driven.

[0126] Subsequently, the surface of the photosensitive drum 11 is exposed to an image by the LED print head 60, with a number of lines equivalent to one page of recording paper 7.

[0127] Incidentally, in the LED print head 60, as described above, during the pause period set between scanning periods, the lighting operation of each SLED chip 67-1 to 67-10, SLED chip 67-11 to 67-20, SLED chip 67-21 to 67-30, and SLED chip 67-31 to 67-40 belonging to each set of SLED chip groups 301 to 304 is terminated, and the relatively large current flowing to each SLED chip 67 for each set of SLED chip groups 301 to 304 is instantaneously cut off.

[0128] In contrast, with conventional LED print heads 60, as shown in Figure 14(b), the inductance of the power line 200 causes the supply current to decrease gradually even if the relatively large current flowing to each LED is instantaneously interrupted. As a result, the voltage of the power circuit 101 rises sharply above the specified value due to excessive current. Subsequently, the voltage of the power circuit 101 drops sharply below the specified value before returning to the normal voltage. Therefore, at the start of scanning with the LED print head 60, density unevenness may occur in the halftone image, such as white streaks of low density or black streaks of high density, as shown in Figure 15.

[0129] In contrast, the LED print head 60 according to this embodiment 1, as shown in Figure 16, has multiple SLED chips 67-1 to 67-40 divided into four SLED chip groups 301 to 304. Moreover, the SLED chips 67-1 to 67-40 in each SLED chip group 301 to 304 are set to have different rest periods.

[0130] Therefore, the supply current that is energized and then cut off by transitioning during the shutdown period is about 1 / 4 of the conventional current, as it is supplied to each SLED chip 67-1 to 67-40 via the power line 200.

[0131] As a result, in the LED print head 60 according to this embodiment 1, as shown in Figure 18, the voltage fluctuation of the power supply circuit 101 can be kept small because the interrupted supply current is small. Therefore, when scanning of the LED print head 60 starts, as shown in Figure 15, the occurrence of density unevenness in the halftone image, such as white streaks of low density and black streaks of high density, is suppressed.

[0132] Therefore, with this LED print head 60, the supply current supplied to each SLED chip 67-1 to 67-40 can be relatively increased, thereby achieving a wide range of light output.

[0133] [Embodiment 2] Figure 19 is a configuration diagram showing an optical scanning device according to Embodiment 2 of this invention.

[0134] In this second embodiment, the driving means is configured to vary the timing of the non-scanning period in order to suppress fluctuations in the driving voltage that occur during the non-scanning period.

[0135] Furthermore, in this second embodiment, the driving means is configured to vary the timing of the non-scanning period in order to suppress fluctuations in the driving voltage that occur during the non-scanning period. Here, the fluctuations in the driving voltage that occur during the non-scanning period are such that the driving voltage increases to a value exceeding a specified value, and then decreases to a value below the specified value and converges.

[0136] In other words, the LED print head 60, as an example of an optical scanning device according to Embodiment 2, differs from Embodiment 1 in that, as shown in Figure 19, does not divide the multiple SLED chips 67-1 to 67-40 into four groups, but rather divides the multiple SLED chips 67-1 to 67-40 into two groups. The first group of SLED chips 311 consists of SLED chips 67-1 to 67-20. The second group of SLED chips 312 consists of SLED chips 67-21 to 67-40.

[0137] Furthermore, in the LED print head 60 according to this second embodiment, as shown in Figure 20, instead of setting the rest periods of the first set of SLED chips 311 and the second set of SLED chips 312 to be equal, the first and second line sync signals Lsync1 and Lsync2 output from the control unit 4 have different rest periods to suppress fluctuations in the drive voltage that occur during the rest period.

[0138] To explain further, in a conventional LED print head 60, the fluctuation in the drive voltage that occurs during the idle period, as shown in Figure 21, rapidly increases to a value exceeding the specified value, then decreases to a value below the specified value and converges to the specified value. The range of this drive voltage fluctuation changes depending on the illumination rate, which is determined by the number of light-emitting thyristors of the SLED chips 67-1 to 67-40 lit immediately before the idle period, and the amount of current supplied to the light-emitting thyristors.

[0139] If the illumination rate of the light-emitting thyristors of SLED chips 67-1 to 67-40 is high and / or the amount of current supplied to the light-emitting thyristors is high immediately before the shutdown period, the fluctuation range of the drive voltage also tends to be large.

[0140] In this second embodiment, as shown in Figure 20, the LED print head 60 is configured such that fluctuations in the driving voltage caused by the SLED chips 67-1 to 67-20 of the first set of SLED chips 311 are suppressed by fluctuations in the driving voltage caused by the SLED chips 67-21 to 67-40 of the second set of SLED chips 312, and a rest period is set for the SLED chips 67-21 to 67-40 of the second set of SLED chips 312.

[0141] In the LED print head 60, as shown in Figure 20, after the rest period has elapsed, the drive voltage, which reached its maximum value at the start of the scanning period, drops sharply, falls below the specified value, and then slowly returns to the specified value.

[0142] Therefore, the control unit 4 outputs a second line sync signal Lsync2 to the second set of SLED chips 312 so as to synchronize the idle period of the SLED chips 67-21 to 67-40 in the second set of SLED chips 312 with the time when the drive voltage of the SLED chips 67-1 to 67-20 in the first set of SLED chips 311 drops sharply to a specified value.

[0143] Thus, in the LED print head 60 according to Embodiment 2, the drive current itself is reduced by dividing the SLED chips 67-1 to 67-40 into two sets. Furthermore, by synchronizing the output timing of the second line sync signal Lsync2 for the second set of SLED chips 312 with the timing when the drive voltage of the SLED chips 67-1 to 67-20 in the first set of SLED chips 311 falls below a specified value, the decrease in the drive voltage of the first set of SLED chips 311 below a specified value and the rapid increase in the drive voltage of the second set of SLED chips 312 are offset, making it possible to suppress the rapid increase in the drive voltage of the second set of SLED chips 312 to be smaller than that of the first set of SLED chips 311.

[0144] The other configurations and operations are the same as in Embodiment 1, so their description will be omitted.

[0145] Although the above embodiment described the case where the method is applied to a full-color image forming apparatus, it goes without saying that the same method can be applied to a monochrome image forming apparatus as well.

[0146] Furthermore, although the above embodiment described the case in which an optical scanning device is applied to an image forming apparatus, the apparatus to which the optical scanning device is applied is not limited to an image forming apparatus.

[0147] Furthermore, although the above embodiment described the case in which the light-emitting thyristor of the SLED chip is driven with the anode set to H (0V) and the cathode set to L (-3.3V) as the optical scanning device, it is of course also possible to drive the light-emitting thyristor of the SLED chip with the anode set to H (a positive electrode of approximately +3.3V) and the cathode set to L (0V).

[0148] (Note) (((1))) A scanning means that arranges multiple groups of light-emitting elements, each consisting of multiple light-emitting elements arranged along the main scanning direction, facing the object to be scanned and along the main scanning direction, and scans by emitting light from each of the light-emitting elements based on image information, A driving means for driving each of the light-emitting element groups of the scanning means for each scanning period, Equipped with, The driving means is an optical scanning device that divides the plurality of light-emitting element groups into a plurality of sets, and sets different timings for the non-scanning period set during the scanning period in at least two of the plurality of sets of light-emitting element groups. (((2))) The optical scanning apparatus according to (((1))), wherein the plurality of sets are defined as a plurality of adjacent groups of light-emitting elements among the plurality of light-emitting element groups. (((3))) The driving means is arranged for each set of the plurality of light-emitting elements in the optical scanning device described in (((2))). (((4))) The optical scanning apparatus according to (((3))), wherein the driving means divides the interval from one scanning period to the next scanning period into equal parts according to the number of sets of the light-emitting element groups, and the timing of the non-scanning period differs by the amount of the divided intervals. (((5))) The optical scanning apparatus according to (((1))), wherein the driving means varies the timing of the non-scanning period in order to suppress fluctuations in the driving voltage that occur during the non-scanning period. (((6))) The optical scanning apparatus according to (((5))), wherein the fluctuation of the drive voltage that occurs during the non-scanning period increases to a value exceeding a specified value and then decreases to a value below the specified value and converges. (((7))) The optical scanning apparatus according to (((6))), wherein the driving means drives each set of light-emitting elements after the fluctuation of the driving voltage has subsided. (((8))) The optical scanning apparatus according to (((6))), wherein the driving means causes each of the next set of light-emitting elements to emit light just before the driving voltage falls below the specified value. (((9))) Image holder and, An exposure means for exposing the image holder based on image information, Equipped with, An image forming apparatus using an optical scanning device as described in any of (((1))) to (((8))) as the exposure means.

[0149] According to the optical scanning device described in (((1))), fluctuations in light intensity caused by fluctuations in the drive voltage can be suppressed compared to the case where the non-scanning periods in multiple groups of light-emitting elements are the same. According to the optical scanning device described in (((2))), the configuration of the driving means becomes simpler compared to the case where multiple spaced-apart light-emitting groups are made into the same set. According to the optical scanning device described in (((3))), setting the non-scanning period becomes easier compared to the case where all sets of multiple light-emitting elements are driven by the same driving means. According to the optical scanning apparatus described in (((4))), the driving means can reduce the impact on image quality caused by different scanning periods for each set of light-emitting elements, compared to the case where the interval from one scanning period to the next scanning period is divided unevenly according to the number of sets of light-emitting elements. According to the optical scanning apparatus described in (((5))), the driving means can further reduce the influence of fluctuations in the driving voltage compared to the case where the timing of different non-scanning periods is not considered. According to the optical scanning apparatus described in (((6))), the effects of fluctuations in the drive voltage can be easily reduced compared to the case where fluctuations in the drive voltage occurring during the non-scanning period are unknown. According to the optical scanning device described in (((7))), the driving means can further reduce the influence of fluctuations in the driving voltage compared to the case in which each group of light-emitting elements is driven before the fluctuations in the driving voltage converge. According to the optical scanning device described in ((8)), the driving means can compensate for the effects of the driving voltage falling below a specified value, compared to the case where each of the subsequent sets of light-emitting elements is made to light up when the driving voltage exceeds a specified value. According to the image forming apparatus of (((9))), compared to the case in which no optical scanning apparatus described in any of (((1))) to (((8))) is used as the exposure means, fluctuations in the amount of light caused by fluctuations in the drive voltage can be suppressed, and image quality can be improved. [Explanation of Symbols]

[0150] 1…Image forming apparatus 13… Exposure equipment 60…LED print head 100...Signal generation circuit

Claims

1. A scanning means that arranges multiple groups of light-emitting elements, each consisting of multiple light-emitting elements arranged along the main scanning direction, facing the object to be scanned and along the main scanning direction, and scans by emitting light from each of the light-emitting elements based on image information, A driving means for driving each of the light-emitting element groups of the scanning means for each scanning period, Equipped with, The driving means is an optical scanning device that divides the plurality of light-emitting element groups into a plurality of sets, and sets different timings for the non-scanning period set during the scanning period in at least two of the plurality of sets of light-emitting element groups.

2. The optical scanning apparatus according to claim 1, wherein the plurality of sets are defined as a plurality of adjacent groups of light-emitting elements among the plurality of light-emitting element groups.

3. The optical scanning apparatus according to claim 2, wherein the driving means is arranged for each set of the plurality of light-emitting element groups.

4. The optical scanning apparatus according to claim 3, wherein the driving means divides the interval from one scanning period to the next scanning period into equal parts according to the number of sets of the light-emitting element groups, and the timing of the non-scanning period differs by the amount of the divided intervals.

5. The optical scanning apparatus according to claim 1, wherein the driving means varies the timing of the non-scanning period in order to suppress fluctuations in the driving voltage that occur during the non-scanning period.

6. The optical scanning apparatus according to claim 5, wherein the fluctuation of the drive voltage occurring during the non-scanning period increases to a value exceeding a specified value, and then decreases to a value below the specified value and converges.

7. The optical scanning apparatus according to claim 6, wherein the driving means drives each set of light-emitting elements after the fluctuation of the driving voltage has converged.

8. The optical scanning apparatus according to claim 6, wherein the driving means causes each of the next set of light-emitting elements to emit light just before the driving voltage falls below the specified value.

9. Image holder and, An exposure means for exposing the image holder based on image information, Equipped with, An image forming apparatus using the optical scanning apparatus described in any one of claims 1 to 8 as the exposure means.

Images