Inverter circuits, power converters, and distributed power systems

Abstract

This invention provides a single-phase three-wire grid-connected inverter circuit that can suppress common noise more effectively than conventional circuits. [Solution] A single-phase three-wire inverter circuit comprising: a voltage divider circuit comprising two capacitors, with the neutral AC side connection terminal connected between the two capacitors; a first leg comprising two switching elements, connected to the first AC side connection terminal via a first inductor between the two switching elements; a second leg comprising two switching elements, connected to the second AC side connection terminal via a second inductor between the two switching elements; and a third leg comprising two sets of two switching elements, each with a diode facing in opposite directions, connected to the neutral AC side terminal via a third inductor between the two sets of switching elements, passing through the midpoint of the voltage divider path.

Description

Technical Field

[0001] The present invention relates to an inverter circuit, a power conversion device, and a distributed power system.

Background Art

[0002] In recent years, distributed power systems that include solar power generation devices, storage batteries, fuel cells, etc. and are operated in connection with commercial power systems have become widespread. In such a distributed power system, a power conversion device (PCS: Power Conditioning Subsystem) is used to convert the DC power obtained by a solar power generation device, a storage battery, a fuel cell, etc. into AC power and supply it to a load or the connected power system.

[0003] As such a power conversion device, conventionally, a single-phase three-wire system-connected inverter circuit has been used to convert DC into an AC waveform and output it by varying the switching pulse width (duty cycle) of a switching element such as a transistor (PWM modulation) (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] By the way, in a conventional inverter circuit as described in Patent Document 1, due to the switching operation of the switching element, the DC bus voltage fluctuates greatly with respect to the ground potential, so there is a problem that a large amount of common noise is generated at the AC side terminals.

[0006] This invention has been made in view of the circumstances described above, and aims to provide a technology that can suppress common noise in a single-phase three-wire grid-connected inverter. [Means for solving the problem]

[0007] To solve the aforementioned problems, one aspect of the present invention adopts the following configuration. That is, A single-phase three-wire inverter circuit that converts DC power input to the first and second input terminals into AC power and outputs it, A voltage divider circuit comprising a first capacitor and a second capacitor in series, with one end connected to the first input terminal and the other end connected to the second input terminal, and connected to the neutral AC side terminal midway between the first capacitor and the second capacitor, The first switching element and the second switching element are provided in series, and one end of the first leg is connected to the first input terminal and the other end is connected to the second input terminal on the AC output side of the capacitor circuit, and the first leg is connected to the first phase AC side terminal via a first inductor between the first switching element and the second switching element, The third switching element and the fourth switching element are provided in series, and one end of the second leg is connected to the first input terminal and the other end is connected to the second input terminal on the AC output side of the capacitor circuit, and the second leg is connected to the second phase AC side terminal via a second inductor between the third switching element and the fourth switching element, A set consisting of a fifth switching element and a sixth switching element connected in series, and a set consisting of a seventh switching element and an eighth switching element connected in series are provided in series, one end connected between the intermediate point of the first switching element and the second switching element and the first inductor, and the other end connected to the third switching element and the fourth switching element A third leg is connected between the middle of the switching element and the second inductor, and between the sixth switching element and the seventh switching element, and is connected to the midpoint of the first capacitor and the second capacitor via a third inductor. It is an inverter circuit having [a certain feature].

[0008] In this specification, terms such as "First," "Second," etc., are used solely to distinguish one component from another, and unless otherwise specified, do not imply any order or hierarchy.

[0009] In the above, "leg" refers to a set of arms containing multiple switching elements connected in series. Furthermore, in the above, the first input terminal and the second input terminal only need to be terminals to which at least DC power is input, and input / output terminals capable of outputting DC power are also included. Similarly, the "inverter circuit" that "converts DC power to AC power and outputs it" only needs to be one that at least converts DC power to AC power and outputs it, and bidirectional AC / DC inverters that can also convert AC power to DC power and output it are also included.

[0010] With the above configuration, a simple circuit design can be adopted while suppressing fluctuations in the voltage to ground during power conversion, thereby effectively suppressing common noise.

[0011] Furthermore, at the timing when each switching element of one of the first and second legs and at least one switching element of the other leg are turned OFF, power may be recirculated through a path including each switching element of the third leg and at least the first and second inductors to output AC power.

[0012] Furthermore, the inverter circuit may further include a first short-circuiting means that enables short-circuiting between the fifth and sixth switching elements and between the seventh and eighth switching elements. Here, "short-circuiting" refers to an intentional shortcut, not an unintended conduction state. With such a configuration, the sixth switching element or the seventh switching element or diodes connected in parallel to these switching elements can be short-circuited during switching control, thereby improving the efficiency and reducing the losses of the inverter.

[0013] Furthermore, the inverter circuit may further include a second short-circuiting means that enables short-circuiting between the intermediate point between the sixth and seventh switching elements and the neutral AC side terminal. With such a configuration, a multi-level inverter can be realized, reducing the switching loss of the switching elements and the iron loss of the reactor, thereby improving the efficiency and reducing the losses of the inverter.

[0014] Furthermore, the inverter circuit may also have a third short-circuiting means arranged in parallel with the third inductor, which enables short-circuiting between the intermediate points of the sixth and seventh switching elements and between the intermediate points of the first and second capacitors. This allows the energy stored in the third inductor to be consumed by the relay when the inverter stops, thereby enhancing safety.

[0015] Furthermore, the inverter circuit may have fuses between the first input terminal and the first leg, between the second input terminal and the first leg, and between the intermediate point between the first and second capacitors and the third inductor. With such a configuration, the inverter can be safely stopped by blowing the fuse when a short circuit occurs due to a failure of the switching element.

[0016] Further, the first inductor and the second inductor may be realized using a common core. Also, the first inductor and the second inductor may be connected in series. With such a configuration, the inductor as hardware can be miniaturized.

[0017] Further, the present invention can also be regarded as the following power conversion device. That is, the above inverter circuit, a control unit that controls the opening and closing of each of the above switching elements, a first DC voltage meter that detects a first DC voltage which is the voltage between the first input terminal and the second input terminal, a second DC voltage meter that detects a second DC voltage which is the voltage between the middle of the first capacitor and the second capacitor and the first input terminal, a third DC voltage meter that detects a third DC voltage which is the voltage between the middle of the first capacitor and the second capacitor and the second input terminal, a first AC voltage meter that detects a first AC voltage which is the voltage between the first-phase AC side terminal and the neutral line AC side terminal, a second AC voltage meter that detects a second AC voltage which is the voltage between the second-phase AC side terminal and the neutral line AC side terminal, and having, the control unit performs opening and closing control of each of the above switching elements so that any one of the first AC voltage, the second AC voltage, the sum of the first AC voltage and the second AC voltage, the second DC voltage, the third DC voltage, the difference between the second DC voltage and the third DC voltage becomes a target value. It is a power conversion device.

[0018] Further, the present invention includes the above inverter circuit, a control unit that controls the opening and closing of each of the above switching elements, a DC ammeter that measures a DC current which is the current of the DC power, a first AC ammeter that detects a first AC current which is the current between the first inductor and the first-phase AC side terminal, A second AC ammeter that detects a second AC current, which is the current between the second inductor and the second-phase AC side terminal; A third AC ammeter that detects a third AC current, which is the current between the third inductor and the neutral-line AC side terminal; and has The control unit performs opening and closing control of each of the switching elements so that any one of the first AC current, the second AC current, and the third AC current becomes a target value. It can also be regarded as a power conversion device.

[0019] Also, the control unit When the power supplied to the load via the first phase and the power supplied to the load via the second phase are unbalanced, in addition to the power output path via the first inductor and the second inductor, the third inductor The opening and closing control of each of the switching elements may be performed so as to reflux the power corresponding to the first phase and the second phase using the path via the inductor.

[0020] Also, the present invention can also be regarded as the following distributed power supply system. That is, A distributed power supply system that is connected to a commercial power system and includes the above power conversion device, a distributed power supply, and a load.

[0021] In addition, each of the above configurations can be used in combination within a range without contradiction.

Effect of the Invention

[0022] According to the present invention, in a single-phase three-wire system-connected inverter, common noise can be suppressed more than before.

Brief Description of the Drawings

[0023] [Figure 1] FIG. 1 is a circuit diagram schematically showing the configuration of an inverter circuit according to an application example. [Figure 2]Figure 2 is a schematic diagram showing the configuration of a distributed power supply system according to the embodiment. [Figure 3] Figure 3 is a schematic diagram illustrating the configuration of an inverter according to this embodiment. [Figure 4] Figure 4 is a block diagram showing an example of the hardware configuration of the control unit according to the embodiment. [Figure 5] Figure 5 is an explanatory diagram illustrating the switching control sequence during load balancing of the control unit according to the embodiment. [Figure 6] Figure 6 is an explanatory diagram illustrating the current path of the inverter circuit according to the embodiment during load balancing. [Figure 7] Figure 7 is an explanatory diagram illustrating the switching control sequence of the control unit according to the embodiment when the U-phase load > W-phase load. [Figure 8] Figure 8A is a first explanatory diagram illustrating the current path of the inverter circuit according to the embodiment when the U-phase load > W-phase load. Figure 8B is a second explanatory diagram illustrating the current path of the inverter circuit according to the embodiment when the U-phase load > W-phase load. [Figure 9] Figure 9A is a third explanatory diagram illustrating the current path of the inverter circuit according to the embodiment when the U-phase load > W-phase load. Figure 9B is a fourth explanatory diagram illustrating the current path of the inverter circuit according to the embodiment when the U-phase load > W-phase load. [Figure 10] Figure 10 is an explanatory diagram illustrating the switching control sequence of the control unit according to the embodiment when the W-phase load > U-phase load. [Figure 11] Figure 11A is a first explanatory diagram illustrating the current path of the inverter circuit according to the embodiment when the W-phase load > U-phase load. Figure 11B is a second explanatory diagram illustrating the current path of the inverter circuit according to the embodiment when the W-phase load > U-phase load. [Figure 12]Figure 12A is a third explanatory diagram illustrating the current path of the inverter circuit according to the embodiment when the W-phase load > U-phase load. Figure 12B is a fourth explanatory diagram illustrating the current path of the inverter circuit according to the embodiment when the W-phase load > U-phase load. [Figure 13] Figure 13 is a schematic circuit diagram showing the configuration of a conventional inverter circuit. [Figure 14] Figure 14A is a graph showing the waveforms of the output voltage, common noise voltage, and reactor current in a simulation using a conventional inverter circuit. Figure 14B is a graph obtained by the Fast Fourier Transform of the common noise voltage in a simulation using a conventional inverter circuit. Figure 14C is a graph obtained by the Fast Fourier Transform of the reactor current in a simulation using a conventional inverter circuit. [Figure 15] Figure 15A is a graph showing the waveforms of the output voltage, common noise voltage, and reactor current in a simulation using the inverter circuit according to the embodiment. Figure 15B is a graph obtained by the Fast Fourier Transform of the common noise voltage in a simulation using the inverter circuit according to the embodiment. Figure 15C is a graph obtained by the Fast Fourier Transform of the reactor current in a simulation using the inverter circuit according to the embodiment. [Figure 16] Figure 16 is a schematic circuit diagram showing a first modified example of the inverter circuit according to the embodiment. [Figure 17] Figure 17 is a schematic circuit diagram showing a second modified example of the inverter circuit according to the embodiment. [Figure 18] Figure 18 is a schematic circuit diagram showing a third modified example of the inverter circuit according to the embodiment. [Figure 19] Figure 19 is a schematic circuit diagram showing a fourth modified example of the inverter circuit according to the embodiment. [Modes for carrying out the invention]

[0024] <Examples of application> Hereinafter, an example of an embodiment of the present invention will be described based on the drawings. The present invention can be applied, for example, as a single-phase three-wire grid-connected inverter circuit (hereinafter simply referred to as an inverter circuit) 91 as shown in Figure 1. Figure 1 is a schematic diagram that schematically shows the configuration of the inverter circuit 91 according to this application example.

[0025] As shown in Figure 1, the inverter circuit 91 has DC connection terminals D1 and D2 to which DC power output from the DC power supply 70 is transformed by a DC / DC converter (not shown in Figure 1) and smoothed via a smoothing capacitor (not shown in Figure 1) is input, and U-phase terminal A1, W-phase terminal A2 and O-phase terminal A3 to which AC power is output. Note that O-phase terminal A3 is the AC side terminal corresponding to the neutral wire. The DC power input from DC connection terminals D1 and D2 is reverse rectified by the inverter circuit 91 and output as AC power via U-phase terminal A1-O-phase terminal A3, W-phase terminal A2-O-phase terminal A3, or U-phase terminal A1-W-phase terminal A2.

[0026] The inverter circuit 91 is equipped with eight switching elements Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8. By controlling the opening and closing of each switching element, it converts DC power to AC power using the PWM (Pulse Width Modulation) modulation method. In this application example, IGBTs (Insulated Gate Bipolar Transistors) are used as each switching element.

[0027] Furthermore, as shown in Figure 1, the inverter circuit 91 includes capacitors C1 and C2 in series, with one end connected to DC connection terminal D1 and the other end connected to DC connection terminal D2, and a voltage divider circuit 54 that connects to O-phase terminal A3 in the middle between capacitors C1 and C2. The inverter circuit 91 also includes three legs: U-phase leg 51 corresponding to U-phase terminal A1, W-phase leg 52 corresponding to W-phase terminal A2, and O-phase leg 53 corresponding to O-phase terminal A3.

[0028] The U-phase leg 51 is positioned on the AC side of the voltage divider circuit 54, between the positive and negative buses of the inverter circuit 91. The U-phase leg 51 consists of a switching element Q1 that constitutes the upper U-phase arm and a switching element Q3 that constitutes the lower U-phase arm, connected in series. The U-phase terminal A1 is connected between the switching elements Q1 and Q3 via a U-phase inductor Lu. The U-phase inductor Lu functions as an AC reactor.

[0029] The W-phase leg 52 is positioned on the AC side of the voltage divider circuit 54, between the positive and negative buses of the inverter circuit 91. The W-phase leg 52 consists of a switching element Q2 that constitutes the upper W-phase arm and a switching element Q4 that constitutes the lower W-phase arm, connected in series. The W-phase terminal A2 is connected between the switching elements Q2 and Q4 via a W-phase inductor Lw. The W-phase inductor Lw functions as an AC reactor.

[0030] Furthermore, the O-phase leg 53 is configured such that an upper arm set is arranged in series with a switching element Q5 forming the upper first arm of the O-phase and a switching element Q6 having a diode facing the opposite direction to the switching element Q5 and forming the upper second arm of the O-phase, and a lower arm set is arranged in series with a switching element Q7 forming the lower first arm of the O-phase and a switching element Q8 having a diode facing the opposite direction to the switching element Q7 and forming the lower second arm of the O-phase. The O-phase leg 53 has switching element Q5 connected to the middle of the U-phase leg 51 and the U-phase inductor Lu, and switching element Q8 connected to the middle of the W-phase leg 52 and the W-phase inductor Lw. In addition, the O-phase leg is connected to the middle of capacitors C1 and C2 of the voltage divider circuit 54 via an O-phase inductor Lo between the switching element Q6 of the upper arm set and the switching element Q7 of the lower arm set. In other words, the O-phase leg 53 is connected to the O-phase terminal A3 via the intermediate points of the O-phase inductor Lo, capacitor C1, and capacitor C2.

[0031] In this application example, switching elements Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 correspond to the first, third, second, fourth, fifth, sixth, seventh, and eighth switching elements according to the present invention, respectively.

[0032] When using the inverter circuit 91 in this application example, especially when performing power conversion to supply AC power to a load during standalone operation, the switching elements Q5 to Q8 perform different switching operations depending on the magnitude of the U-phase load (output power via U-phase terminal A1) and the W-phase load (output power via W-phase terminal A2), thereby outputting AC power according to the load conditions of each phase. However, in any situation, during the period when three or more of the switching elements Q1 to Q4 are OFF and current cannot flow back through the U-phase leg 51 and W-phase leg 52 (in this application example, the dead time period when all switching elements Q1 to Q4 are OFF), the magnetic energy stored in each inductor is released, and current flows back through the path including each switching element Q5 to Q8 and each inductor in the O-phase leg 53 to output AC power.

[0033] According to the inverter circuit 91 in the above-described application example, fluctuations in the voltage to ground during power conversion can be suppressed while employing a simple circuit configuration, and common noise can be effectively suppressed.

[0034] <Embodiment> Next, an example of an embodiment of the present invention will be described in more detail with reference to Figures 2 to 15. The distributed power supply system 1 according to this embodiment includes a power conditioner (PSC) 10 equipped with the inverter circuit 91 described in the above example. In the following, components already described will be denoted by the same reference numerals, and further explanation will be omitted.

[0035] (Overall system configuration) Figure 2 is a schematic diagram showing the general configuration of the distributed power system 1 according to this embodiment. The distributed power system 1 is a grid-connected system that includes three different distributed power sources: a solar cell 71, a storage battery 72, and an on-board battery 73, a so-called tri-hybrid type PCS 10 that performs power conversion for these three distributed power sources, a distribution board 20, and loads 31, and is connected to the commercial power grid (not shown) via a pole-mounted transformer 32. The loads 31 include general loads and specific loads.

[0036] PCS10 is a DC / DC converter 80a that corresponds to the solar cell 71, and a battery 72. The system includes a corresponding DC / DC converter 80b, a DC / DC converter 80c corresponding to the onboard battery 73, a smoothing capacitor C3, an inverter 11, and an operating mode switching relay 12. In the following, DC / DC converters 80a, 80b, and 80c may be referred to as DC / DC converter 80 unless it is necessary to distinguish them. Similarly, the distributed power sources of the solar cell 71, storage battery 72, and onboard battery 73 may be referred to as DC power supply 70 unless it is necessary to distinguish them.

[0037] The operating mode switching relay 12 is a relay that switches the connected circuit (power supply destination) according to the interconnected operation mode, which performs power control in conjunction with the commercial power grid, and the independent operation mode, which performs independent operation.

[0038] In this embodiment, the DC / DC converters 80b and 80c of the PCS10, as well as the inverter 11, are configured to output power in both directions. That is, the storage battery 72 and the on-board battery 73 can both output power to the load 31 or the commercial power grid (discharge) and receive power from the commercial power grid (charge), but the following explanation will assume that they are primarily power sources supplying DC power.

[0039] The distribution board 20 distributes power between the distributed power sources, including the solar cell 71, the storage battery 72, and the vehicle battery 73, as well as the commercial power grid, and the load 31. The distribution board 20 is equipped with a circuit breaker (MCCB) 21 that shuts off the circuit when an overcurrent (overvoltage) is detected, and a power transfer switch (DTMC) 22 that switches the power path between the commercial power grid and the DC power source 70.

[0040] (Regarding inverters) Next, the inverter 11 will be described based on Figure 3. As shown in Figure 3, the inverter 11 is equipped with a power conversion circuit with a configuration similar to that of the inverter circuit 91 described in the application example. The inverter 11 also includes a control unit 100 that controls the opening and closing of each of the switching elements Q1 to Q8, DC voltmeters 41a, 41b, 41c, AC voltmeters 43a, 43b, DC ammeter 42, and AC ammeters 44a, 44b, 44c.

[0041] The control unit 100 is a computer that has a storage medium for storing the control program and a processor such as a CPU (Central Processing Unit) that executes control procedures according to the control program. The control unit 100 acquires the output signals of the DC voltmeters 41a, 41b, 41c, DC ammeter 42, AC voltmeters 43a, 43b, AC ammeters 44a, 44b, 44c via a communication line and controls each component of the inverter 11 so that the output voltage or output current reaches the target value.

[0042] More specifically, the control unit 100 controls the configuration of the inverter 11, including each switching element, so that the target voltage is one of the following: output voltage Vo,uo, output voltage Vo,wo, the sum of output voltage Vo,uo and output voltage Vo,wo, the intermediate voltage between DC connection terminal D1 and capacitors C1 and C2, or the intermediate voltage between DC connection terminal D2 and capacitors C1 and C2; or the target current is one of the following: output current iu, output current iw, or output current io.

[0043] Figure 4 shows an example of the hardware configuration of the control unit 100 of the inverter 11 according to this embodiment. As shown in Figure 4, the control unit 100 is a computer whose components include a processor 101, main memory 102, auxiliary storage 103, communication interface (IF) 104, and input / output IF 105, which are interconnected by a connection bus 106. The main memory 102 and auxiliary storage 103 are recording media that the control unit 100 can read. Multiple instances of each of the above components may be provided, or some components may be omitted. stomach.

[0044] The processor 101 is a central processing unit that controls the entire control unit 100. The processor 101 is, for example, a CPU, an MPU (Micro-Processing Unit), a DSP (Digital Signal Processor), etc. The processor 101, for example, deploys a program stored in the auxiliary storage device 103 into the working area of ​​the main memory device 102 in an executable format, and provides a function that matches a predetermined purpose by controlling peripheral devices through the execution of the program. However, some or all of the functions provided by the processor 101 may be provided by an ASIC (Application Specific Integrated Circuit), a GPU (Graphics Processing Unit), etc. Similarly, some or all of the functions may be realized by an FPGA (Field-Programmable Gate Array), a dedicated LSI (large-scale integration) such as a numerical processing processor, or other hardware circuits.

[0045] The main memory 102 and the auxiliary storage device 103 constitute the memory of the control unit 100. The main memory 102 stores programs executed by the processor 101, data processed by the processor, etc. The main memory 102 includes flash memory, RAM (Random Access Memory), and ROM (Read Only Memory). The auxiliary storage device 103 is a storage medium that stores programs executed by the processor 101, etc., operation setting information, various tables, and other information. The auxiliary storage device 103 includes, for example, an HDD (Hard-disk Drive), SSD (Solid State Drive), EPROM (Erasable Programmable ROM), flash memory, USB memory, SD (Secure Digital) memory card, etc. The communication IF 104 is a communication interface with the communication network. The communication IF 104 can adopt an appropriate configuration depending on the connection method with the communication network to which it is connected.

[0046] The input / output IF105 is an interface that performs data input and output between the input and output devices of the inverter 11. Data is output to output devices such as LCDs and other display devices through the input / output IF105. Operation instructions are also received through the input / output IF105, and the processing intended by the operator is performed based on those instructions.

[0047] The control unit 100, as described above, generates PWM modulated signals for switching control of each switching element Q1 to Q8 in the power conversion circuit. Specifically, it compares a reference signal (sine wave) representing the AC output waveform with a predetermined carrier signal (triangular wave) to generate pulse waveforms for switching the switching elements belonging to the upper arm and the switching elements belonging to the lower arm on and off, respectively.

[0048] (Switching control) Next, we will explain the switching control of each switching element performed by the control unit 100. During grid-connected operation, since it is connected to a stable grid power supply, the voltage of the power output from the inverter 11 only needs to be 200V between the U-phase terminal A1 and the W-phase terminal A2. Therefore, all switching elements Q5 to Q8 of the O-phase leg 53 are turned OFF, and only the U-phase leg 51 and the W-phase leg 52 (only switching elements Q1 to Q4) need to be switched. This method of converting DC power to AC power using the so-called two-leg method is well known, so we will omit the explanation.

[0049] On the other hand, during standalone operation, the grid power supply and load 31 are disconnected, and the power output from inverter 11 is supplied directly to load 31. Therefore, it is necessary to output 100V between U-phase terminal A1 and O-phase terminal A3, and between W-phase terminal A2 and O-phase terminal A3. In this embodiment, the switching control during standalone operation involves different switching operations of the O-phase leg 53, i.e., switching elements Q5 to Q8, depending on the magnitude of the power output from the U-phase terminal A1 to the O-phase terminal A3 (U-phase load) and the power output from the W-phase terminal A2 to the O-phase terminal A3 (W-phase load). These will be explained in detail below.

[0050] (at load balance) Figure 5 is an explanatory diagram showing the relationship between the voltage command (sine wave), carrier signal (carrier wave), and pulse waves related to the ON / OFF state of each switching element in the inverter 11 of this embodiment when the U-phase load and W-phase load are balanced. Table 1 below lists the ON / OFF states of each switching element during each period T1 to T4 shown in Figure 5. Figure 6 is an explanatory diagram showing the current path of the power conversion circuit during periods T2 and T3.

[0051] [Table 1]

[0052] As shown in Figure 5, when the load is balanced, if the voltage command is in a positive cycle, the control alternately repeats the switching operations shown in periods T1 and T2. As shown in Table 1, during period T1, switching element Q1 is ON, switching element Q2 is OFF, switching element Q3 is OFF, switching element Q4 is ON, switching element Q5 is ON, switching element Q6 is OFF, switching element Q7 is ON, and switching element Q8 is OFF. Current flows sequentially from capacitors C1 and C2 through switching element Q1, U-phase inductor Lu, W-phase inductor Lw, and switching element Q4, and power is transmitted to the AC side.

[0053] Furthermore, as shown in Table 1, during period T2, all switching elements Q1 to Q4 of the U-phase leg 51 and W-phase leg 52 are OFF (so-called dead time), switching element Q5 is ON, switching element Q6 is OFF, switching element Q7 is ON, and switching element Q8 is OFF. Period T2 is the period during which the magnetic energy accumulated in the U-phase inductor Lu and W-phase inductor Lw during period T1 is released, and the current flows sequentially through the paths of U-phase inductor Lu, W-phase inductor Lw, switching element Q8 (diode), switching element Q7, switching element Q6 (diode), and switching element Q5, and power is transmitted to the AC side. Figure 6 shows the current path during period T2 with black arrows.

[0054] As shown in Figure 5, when the voltage command is a negative cycle, the control alternately repeats the switching operations shown in periods T3 and T4. As shown in Table 1, in period T3, all switching elements Q1 to Q4 of the U-phase leg 51 and W-phase leg 52 are OFF, switching element Q5 is OFF, switching element Q6 is ON, switching element Q7 is OFF, and switching element Q8 is ON. Period T3 is the period in which the magnetic energy accumulated in the U-phase inductor Lu and W-phase inductor Lw during period T4, described later, is released, and the current is in the W-phase inductor Lw, U-phase inductor Lu, switching element Q5 (diode), switching element Q6, switching element Q7 (diode), in that order. The current flows through the switching element Q8, and power is transmitted to the AC side. In Figure 6, the current path during period T3 is shown by a white arrow.

[0055] Furthermore, as shown in Table 1, during period T4, switching element Q1 is OFF, switching element Q2 is ON, switching element Q3 is ON, switching element Q4 is OFF, switching element Q5 is OFF, switching element Q6 is ON, switching element Q7 is OFF, and switching element Q8 is ON. Current flows sequentially from capacitors C1 and C2 through switching element Q2, W-phase inductor Lw, U-phase inductor Lu, and switching element Q3, and power is transmitted to the AC side.

[0056] (U phase load>W phase load) Next, we will explain switching control when the U-phase load is greater than the W-phase load. Figure 7 is an explanatory diagram showing the relationship between the voltage command, carrier signal, and pulse waves related to the ON / OFF state of each switching element when the U-phase load is greater than the W-phase load. Table 2 below lists the ON / OFF state of each switching element during each period T1 to T8 shown in Figure 7. Figures 8A and 8B are explanatory diagrams showing the current path of the power conversion circuit during periods T2 and T4, and Figures 9A and 9B are explanatory diagrams showing the current path of the power conversion circuit during periods T6 and T8.

[0057] [Table 2]

[0058] As shown in Figure 7, when the load imbalance occurs and the U-phase load is greater than the W-phase load, if the voltage command is in a positive cycle, the control sequentially repeats the switching operations shown in period T1 to T4. As shown in Table 2, during periods T1 and T3, switching element Q1 is ON, switching element Q2 is OFF, switching element Q3 is OFF, switching element Q4 is ON, switching element Q5 is ON, switching element Q6 is OFF, switching element Q7 is ON, and switching element Q8 is OFF. Then, current flows from capacitors C1 and C2 in order, through switching element Q1, U-phase inductor Lu, W-phase inductor Lw, and switching element Q4, and power is transmitted to the AC side.

[0059] Furthermore, during period T2, switching element Q1 is ON, switching element Q2 is OFF, switching element Q3 is OFF, switching element Q4 is ON, switching element Q5 is ON, switching element Q6 is OFF, switching element Q7 is ON, and switching element Q8 is ON. The current flows from C1 and C2 through switching element Q1, U-phase inductor Lu, W-phase inductor Lw, and switching element Q4; from switching element Q1 and U-phase inductor Lu, through the midpoint between capacitors C1 and C2 (hereinafter also referred to as the DC midpoint) to switching element Q1; and from U-phase inductor Lu, through the DC midpoint, O-phase inductor Lo, switching element Q7, and switching element Power is transmitted to the AC side through three paths: the path to sub-Q8, the path to the switching element Q4, and the path to the AC side. Figure 8A shows the current flow during period T2 when the U-phase load is greater than the W-phase load, indicated by a dotted line.

[0060] Furthermore, during period T4, all switching elements Q1 to Q4 of the U-phase leg 51 and W-phase leg 52 are OFF, switching element Q5 is ON, switching element Q6 is OFF, switching element Q7 is ON, and switching element Q8 is OFF. Period T4 is the period during which the magnetic energy accumulated in the U-phase inductor Lu, O-phase inductor Lo, and W-phase inductor Lw during periods T1 to T3 is released, and the current flows through the paths of U-phase inductor Lu, O-phase inductor Lo (via the DC midpoint), switching element Q6 (and its diode), switching element Q5, and O-phase inductor Lo, W-phase inductor Lw, switching element Q8 (and its diode), and switching element Q7, transmitting power to the AC side. Figure 8B shows the current flow during period T4 when the U-phase load > W-phase load with a dotted line.

[0061] On the other hand, as shown in Figure 7, when the voltage command is a negative cycle, the control sequentially repeats the switching operations shown in period T5 to T8. As shown in Table 2, during periods T5 and T7, switching element Q1 is OFF, switching element Q2 is ON, switching element Q3 is ON, switching element Q4 is OFF, switching element Q5 is OFF, switching element Q6 is ON, switching element Q7 is OFF, and switching element Q8 is ON. Then, current flows from capacitors C1 and C2 in order, through switching element Q2, W-phase inductor Lw, U-phase inductor Lu, and switching element Q3, and power is transmitted to the AC side.

[0062] Furthermore, during period T6, switching element Q1 is OFF, switching element Q2 is ON, switching element Q3 is ON, switching element Q4 is OFF, switching element Q5 is OFF, switching element Q6 is ON, switching element Q7 is ON, and switching element Q8 is ON. Then, current flows from capacitors C1 and C2 to switching element Q2, W-phase inductor Lw, U-phase inductor Lu, and switching element Q3; a path flows from switching element Q2, switching element Q8, switching element Q7, and O-phase inductor Lo through the DC midpoint to Q2; and a path flows from O-phase inductor Lo through the DC midpoint to U-phase inductor Lu and switching element Q3, and power is transmitted to the AC side through these three paths. Figure 9A shows the current flow during period T6 when U-phase load > W-phase load with dotted lines.

[0063] Furthermore, during period T8, all switching elements Q1 to Q4 of the U-phase leg 51 and W-phase leg 52 are turned OFF, switching element Q5 is OFF, switching element Q6 is ON, switching element Q7 is OFF, and switching element Q8 is ON. Period T8 is the period during which the magnetic energy accumulated in the U-phase inductor Lu, O-phase inductor Lo, and W-phase inductor Lw during periods T5 to T7 is released, and current flows through the paths of O-phase inductor Lo, U-phase inductor Lu, switching element Q5 (and its diode), switching element Q6, and W-phase inductor Lw, O-phase inductor Lo, switching element Q7 (and its diode), and switching element Q8, transmitting power to the AC side. Figure 9B shows the current flow during period T8 when the U-phase load > W-phase load with a dotted line.

[0064] (W phase load > U phase load) Next, we will explain switching control when the W-phase load is greater than the U-phase load. Figure 10 is an explanatory diagram showing the relationship between the voltage command, carrier signal, and pulse waves related to the ON / OFF state of each switching element when the W-phase load is greater than the U-phase load. Table 3 below lists the ON / OFF state of each switching element during each period T1 to T8 shown in Figure 10. Figures 11A and 11B are explanatory diagrams showing the current path of the power conversion circuit during periods T2 and T4, and Figures 12A and 12B show the current path during periods T6 and T8. This is an explanatory diagram showing the current path in a power conversion circuit.

[0065] [Table 3]

[0066] As shown in Figure 10, when the load imbalance occurs and the W-phase load is greater than the U-phase load, if the voltage command is in a positive cycle, the control unit 100 performs control that sequentially repeats the switching operations shown in periods T1 to T4. During periods T1 and T3, as shown in Table 3, switching element Q1 is ON, switching element Q2 is OFF, switching element Q3 is OFF, switching element Q4 is ON, switching element Q5 is ON, switching element Q6 is OFF, switching element Q7 is ON, and switching element Q8 is OFF. Then, current flows from capacitors C1 and C2 in order through switching element Q1, U-phase inductor Lu, W-phase inductor Lw, and switching element Q4, and power is transmitted to the AC side.

[0067] Furthermore, during period T2, switching element Q1 is ON, switching element Q2 is OFF, switching element Q3 is OFF, switching element Q4 is ON, switching element Q5 is ON, switching element Q6 is ON, switching element Q7 is ON, and switching element Q8 is OFF. Then, current flows from capacitors C1 and C2 to switching element Q1, U-phase inductor Lu, W-phase inductor Lw, and switching element Q4; a path flows from switching element Q1, switching element Q5, switching element Q6, and O-phase inductor Lo to switching element Q1 via the DC midpoint; and a path flows from the DC midpoint to the W-phase inductor Lw and switching element Q4, and power is transmitted to the AC side through these three paths. Figure 11A shows the current flow during period T2 when the W-phase load > U-phase load with dotted lines.

[0068] Furthermore, during period T4, all switching elements Q1 to Q4 of the U-phase leg 51 and W-phase leg 52 are OFF, switching element Q5 is ON, switching element Q6 is OFF, switching element Q7 is ON, and switching element Q8 is OFF. Period T4 is the period during which the magnetic energy accumulated in the U-phase inductor Lu, O-phase inductor Lo, and W-phase inductor Lw during periods T1 to T3 is released. Current flows through the paths of U-phase inductor Lu, O-phase inductor Lo, switching element Q6 (diode), and switching element Q5, and O-phase inductor Lo, W-phase inductor Lw, switching element Q8 (diode), and switching element Q7, and power is transmitted to the AC side. Figure 11B shows the current flow during period T4 when the W-phase load > U-phase load with a dotted line.

[0069] On the other hand, as shown in Figure 10, when the voltage command is a negative cycle, the control sequentially repeats the switching operations shown in period T5 to T8. As shown in Table 3, during periods T5 and T7, switching element Q1 is OFF, switching element Q2 is ON, switching element Q3 is ON, switching element Q4 is OFF, and switching element Q5 is OFF. Switching element Q6 turns ON, switching element Q7 turns OFF, and switching element Q8 turns ON. Current flows sequentially from capacitors C1 and C2 through switching element Q2, W-phase inductor Lw, U-phase inductor Lu, and switching element Q3, and power is transmitted to the AC side.

[0070] Furthermore, during period T6, switching element Q1 is OFF, switching element Q2 is ON, switching element Q3 is ON, switching element Q4 is OFF, switching element Q5 is ON, switching element Q6 is ON, switching element Q7 is OFF, and switching element Q8 is ON. Then, current flows from capacitors C1 and C2 to switching element Q2, W-phase inductor Lw, U-phase inductor Lu, and switching element Q3; from switching element Q2 and W-phase inductor Lw to switching element Q2 via the DC midpoint; and from the DC midpoint to O-phase inductor Lo, switching element Q6, switching element Q5, and switching element Q3, and power is transmitted to the AC side through these three paths. Figure 12A shows the current flow during period T6 when the W-phase load > U-phase load with dotted lines.

[0071] Furthermore, during period T8, all switching elements Q1 to Q4 of the U-phase leg 51 and W-phase leg 52 are turned OFF, switching element Q5 is OFF, switching element Q6 is ON, switching element Q7 is OFF, and switching element Q8 is ON. Period T8 is the period during which the magnetic energy accumulated in the U-phase inductor Lu, O-phase inductor Lo, and W-phase inductor Lw during periods T5 to QT7 is released. Current flows through the paths of O-phase inductor Lo, U-phase inductor Lu, switching element Q5 (and its diode), and switching element Q6, and through the paths of W-phase inductor Lw, O-phase inductor Lo, switching element Q7 (and its diode), and switching element Q8, and power is transmitted to the AC side. Figure 12B shows the current flow during period T8 when the W-phase load > U-phase load with a dotted line.

[0072] As described above, in the inverter 11 according to this embodiment, the O-phase leg 53 corresponding to the neutral wire is not provided between the positive bus and the negative bus, but rather between the U-phase leg 51 and the U-phase inductor Lu, and between the W-phase leg 52 and the W-phase inductor Lw. Furthermore, when the U-phase load and the W-phase load are unbalanced, switching control is performed to recirculate the current through the path flowing through the O-phase inductor Lo connected to the DC midpoint. The U-phase load and the W-phase load are constantly detected based on the outputs of the AC-side voltmeter and ammeter, and the control unit 100 switches the switching control method in real time according to the relative magnitudes of these loads.

[0073] (Example of experiment) A comparative simulation experiment was conducted to compare the noise during power conversion between the inverter 11 according to the present embodiment described above and a conventional inverter circuit as shown in Figure 13. The experimental conditions were as follows: DC power supply voltage of 380V, AC output voltage Vo,uo of 101V, AC output voltage Vo,wo of 101V, grid frequency of 50Hz, output power of U-phase-O-phase 3kW, W-phase-O-phase 3kW, switching frequency of 19.2kHz, and inductance of each inductor Lu, Lw, and Lo of 600μH.

[0074] Figures 14A, 14B, and 14C are graphs showing the simulation results when using a conventional inverter circuit as shown in Figure 13. Figure 14A shows the waveforms of the output voltage, common noise voltage, and reactor current, Figure 14B shows the graph obtained by the Fast Fourier Transform of the common noise voltage, and Figure 14C shows the graph obtained by the Fast Fourier Transform of the reactor current.

[0075] Figures 15A, 15B, and 15C show a simulation using the inverter circuit according to this embodiment. These are graphs showing the results of the experiment. Figure 15A shows the waveforms of the output voltage, common noise voltage, and reactor current, Figure 15B shows the graph obtained by the Fast Fourier Transform of the common noise voltage, and Figure 15C shows the graph obtained by the Fast Fourier Transform of the reactor current.

[0076] As can be seen from the comparison between Figures 14A, 14B, and 14C and Figures 15A, 15B, and 15C, the inverter 11 according to this embodiment significantly suppresses both common noise and the ripple component of the reactor current (i.e., normal noise) compared to conventional inverter circuits.

[0077] According to the inverter 11 of this embodiment described above, common noise, normal noise, switching losses, and reactor iron losses can be reduced while employing a simple circuit configuration. Furthermore, by introducing a hybrid PCS 10 equipped with such an inverter, a highly efficient distributed power supply system 1 can be realized.

[0078] <Variation> The embodiments described above are merely illustrative examples, and the present invention is not limited to the specific forms described above. The present invention can be modified and combined in various ways within the scope of its technical concept. For example, the inverter circuit 91 described above can also be modified in various ways, and such modifications will be described below.

[0079] (Variation 1) Figure 16 shows a schematic configuration of the inverter circuit 92 according to the first modified example. The inverter circuit 92 has a configuration that is generally similar to the inverter circuit 91 already described, but differs in that it is equipped with a short-circuit relay R1 that is configured to short-circuit the intermediate points between switching elements Q5 and Q6 and between switching elements Q7 and Q8. With such a short-circuit relay R1, it is possible to short-circuit the switching elements Q6 or Q7 or the diodes connected in parallel to these switching elements during switching control, thereby improving the efficiency and reducing the losses of the inverter.

[0080] (Modification 2) Figure 17 shows a schematic configuration of the inverter circuit 93 according to the second modified example. In the inverter circuit 93 according to this modified example, a short-circuit relay R2 is provided that enables short-circuiting between the intermediate points of switching elements Q6 and Q7 and the O-phase terminal A3. By using an inverter circuit 93 with such a configuration, a multi-level operation capable and highly efficient inverter can be realized.

[0081] (Variation 3) Figure 18 shows a schematic configuration of the inverter circuit 94 according to the third modified example. In this modified example, the inverter circuit 94 is provided with a short-circuit relay R3 arranged in parallel with the O-phase inductor Lo, which enables short-circuiting between the switching elements Q6 and Q7 and between the capacitors C1 and C2. With this configuration, when the inverter stops, the magnetic energy stored in the O-phase inductor Lo can be consumed by the short-circuit relay R3, thereby increasing the safety of the circuit.

[0082] (Modification 4) Figure 19 shows a schematic configuration of the inverter circuit 95 according to the fourth modified example. The inverter circuit 95 according to this modified example has a fuse F1 between the DC connection terminal D1 and the switching element Q1, a fuse F2 between the DC connection terminal D2 and the switching element Q3, and a fuse F3 between the DC midpoint and the O-phase inductor Lo. According to the configuration, if a short circuit occurs due to a failure of the switching element, the fuse will blow, allowing the inverter to be safely shut down.

[0083] <Other> In addition to the modifications to the inverter circuit configuration, various other modifications are possible. For example, while the above examples illustrate the use of IGBTs as switching elements, other switching elements such as MOSFETs (metal oxide semiconductor field effect transistors) can be used instead. Furthermore, the short-circuit relays R1, R2, and R3 in the above modifications do not necessarily have to be relays; they can be replaced with other components capable of short-circuiting the path.

[0084] Furthermore, in each of the above examples, the U-phase inductor Lu and the W-phase inductor Lw may be formed using a common core and connected in a combined manner. With such a configuration, the inductor can be miniaturized.

[0085] Furthermore, the applications of the inverter circuit according to the present invention are not particularly limited, and it can be incorporated into various devices other than PCS.

[0086] <Note 1> A single-phase three-wire inverter circuit (91, 92, 93, 94, 95) that converts DC power input to the first input terminal (D1) and the second input terminal (D2) into AC power and outputs it, A voltage divider circuit (54) is provided with a first capacitor (C1) and a second capacitor (C2) in series, one end of which is connected to the first input terminal and the other end of which is connected to the second input terminal, and which is connected to the neutral AC side terminal (A3) in the middle between the first capacitor and the second capacitor, The circuit includes a first switching element (Q1) and a second switching element (Q3) in series, with one end connected to the first input terminal and the other end connected to the second input terminal on the AC output side of the capacitor circuit, and a first leg (51) located between the first and second switching elements, connected to the first phase AC side terminal (A1) via a first inductor (Lu). The third switching element (Q2) and the fourth switching element (Q4) are provided in series, and one end of the second leg (52) is connected to the first input terminal and the other end is connected to the second input terminal on the AC output side of the capacitor circuit, and the second leg (52) is connected to the second phase AC side terminal (A2) via a second inductor (Lw) between the third and fourth switching elements. A set consisting of a fifth switching element (Q5) and a sixth switching element (Q6) connected in series, and a set consisting of a seventh switching element (Q7) and an eighth switching element (Q8) connected in series are provided in series, one end of which is connected between the midpoint of the first and second switching elements and the first inductor, and the other end of which is connected between the midpoint of the third and fourth switching elements and the second inductor, and a third leg (52) in the midpoint of the sixth and seventh switching elements that is connected to the midpoint of the first and second capacitors via a third inductor (Lo), Having, Inverter circuit.

[0087] <Note 2> At the timing when each switching element of one of the first and second legs and at least one switching element of the other leg are turned OFF, the third leg The power is recirculated through a path including each switching element and at least the first inductor and the second inductor to output AC power. The inverter circuit described in Appendix 1.

[0088] <Note 3> The device further includes a first short-circuiting means (R1) that enables short-circuiting between the fifth and sixth switching elements and between the seventh and eighth switching elements. The inverter circuit described in Appendix 1 or 2.

[0089] <Note 4> The device further includes a second short-circuiting means (R2) that enables short-circuiting between the intermediate point of the sixth switching element and the seventh switching element and the neutral AC side terminal. An inverter circuit as described in any of the appendices 1 to 3.

[0090] <Note 5> The device further includes a third short-circuiting means (R3) arranged in parallel with the third inductor, which enables short-circuiting between the intermediate points of the sixth switching element and the seventh switching element and between the intermediate points of the first capacitor and the second capacitor. An inverter circuit as described in any of the appendices 1 to 4.

[0091] <Note 6> Fuses (F1, F2, F3) are provided between the first input terminal and the first leg, between the second input terminal and the first leg, and between the intermediate point between the first capacitor and the second capacitor and the third inductor, respectively. An inverter circuit as described in any of the appendices 1 to 5.

[0092] <Note 7> The inverter circuit described in any of appendices 1 to 6, wherein the first inductor and the second inductor are realized using a common core.

[0093] <Note 8> The first inductor and the second inductor are connected in a summation manner. The inverter circuit described in Appendix 7.

[0094] <Note 9> The inverter circuits (91, 92, 93, 94, 95) described in any of the appendices 1 to 8, A control unit (100) that controls the opening and closing of each of the aforementioned switching elements and A first DC voltmeter (41a) detects a DC voltage which is the voltage between the first input terminal and the second input terminal, A second DC voltmeter (41b) detects a second DC voltage which is the voltage between the midpoint of the first capacitor and the second capacitor and the first input terminal, A third DC voltmeter (41c) detects a third DC voltage which is the voltage between the midpoint of the first capacitor and the second capacitor and the second input terminal, A first AC voltmeter (43a) detects a first AC voltage which is the voltage between the first phase AC terminal and the neutral wire AC terminal, A second AC voltmeter (43b) detects the second AC voltage, which is the voltage between the second phase AC terminal and the neutral wire AC terminal, It has, The control unit controls the switching of each switching element so that the first AC voltage, the second AC voltage, the sum of the first and second AC voltages, the second DC voltage, the third DC voltage, or the difference between the second and third DC voltages becomes a target value. Power converter (11).

[0095] <Note 10> The control unit, In cases where the power supplied to the load via the first phase and the power supplied to the load via the second phase are unbalanced, the power conversion device (11) described in Appendix 9 controls the switching of each switching element to recirculate the power corresponding to the first phase and the second phase using a path via the third inductor, in addition to the power output path via the first inductor and the second inductor.

[0096] <Note 11> The inverter circuits (91, 92, 93, 94, 95) described in any of the appendices 1 to 8, A control unit (100) that controls the opening and closing of each of the aforementioned switching elements and A DC ammeter (42) for measuring the DC current, which is the current of the DC power, A first AC ammeter (44a) detects the first AC current, which is the current between the first inductor and the first phase AC terminal, A second AC ammeter (44b) detects the second AC current, which is the current between the second inductor and the second phase AC terminal, A third AC ammeter (44c) detects the third AC current, which is the current between the third inductor and the neutral wire AC side terminal, It has, The control unit controls the switching of each of the switching elements so that the first AC current, the second AC current, or the third AC current reaches a target value. Power converter (11).

[0097] <Note 12> The control unit, The power conversion device according to Appendix 11, wherein, in the event of an imbalance between the power supplied to the load via the first phase and the power supplied to the load via the second phase, the switching control of each switching element is performed to recirculate the power corresponding to the first phase and the second phase using a path via the third inductor, in addition to the power output path via the first inductor and the second inductor.

[0098] <Note 13> It is connected to the commercial power grid and has a power converter (11) as described in any one of the appendices 9 to 12, a distributed power source (71, 72, 73), and a load (31), Distributed power systems. [Explanation of Symbols]

[0099] 1. Distributed power systems 10 PCS 11. Inverter 12. Operating mode switching relay 20... Distribution board 21. Miniature Circuit Breaker (MCCB) 22. Power selector switch (DTMC) 31...Load 32. Pole-mounted transformer 41a, 41b, 41c... DC voltmeter 42...DC ammeter 43a, 43b... AC voltmeter 44a, 44b, 44c...AC ammeter 51···U phase leg 52···W phase leg 53···O phase leg 70...DC power supply 71... Solar cells 72... Storage batteries 73...Car battery 80, 80a, 80b, 80c... DC / DC converters 91, 92, 93, 94, 95... Inverter circuits 100... Control Unit A1...U phase terminal A2...W phase terminal A3...O phase terminal C1, C2, C3... Capacitors D1, D2... DC connection terminals F1, F2, F3... Fuse Lu···U-phase inductor Lw···W phase inductor Lo···O phase inductor R1, R2, R3... Short-circuit relays Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8... Switching elements

Claims

1. A single-phase three-wire inverter circuit that converts DC power input to the first input terminal and the second input terminal into AC power and outputs it, A voltage divider circuit comprising a first capacitor and a second capacitor in series, with one end connected to the first input terminal and the other end connected to the second input terminal, and connected to the neutral AC side terminal midway between the first capacitor and the second capacitor, The first switching element and the second switching element are provided in series, with one end connected to the first input terminal and the other end connected to the second input terminal on the AC output side of the capacitor circuit, and a first leg connected to the first phase AC side terminal via a first inductor between the first and second switching elements, The third switching element and the fourth switching element are provided in series, and one end of the second leg is connected to the first input terminal and the other end is connected to the second input terminal on the AC output side of the capacitor circuit, and the second leg is connected to the second phase AC side terminal via a second inductor between the third switching element and the fourth switching element, A set of fifth and sixth switching elements connected in series, and a set of seventh and eighth switching elements connected in series are provided in series, with one end connected between the midpoint of the first and second switching elements and the first inductor, and the other end connected between the midpoint of the third and fourth switching elements and the second inductor, and a third leg in the midpoint of the sixth and seventh switching elements that connects to the midpoint of the first and second capacitors via a third inductor, Having, Inverter circuit.

2. At the timing when each switching element of one of the first and second legs and at least one switching element of the other leg are turned OFF, power is returned through a path including each switching element of the third leg and at least the first and second inductors to output AC power. The inverter circuit according to claim 1.

3. The device further includes a first short-circuiting means that enables short-circuiting between the fifth and sixth switching elements and between the seventh and eighth switching elements. The inverter circuit according to claim 1.

4. The device further includes a second short-circuiting means that enables short-circuiting between the intermediate point of the sixth switching element and the seventh switching element and the neutral AC side terminal. The inverter circuit according to claim 1.

5. The device further includes a third short-circuiting means arranged in parallel with the third inductor, which enables short-circuiting between the intermediate points of the sixth switching element and the seventh switching element and between the intermediate points of the first capacitor and the second capacitor. The inverter circuit according to claim 1.

6. A fuse is provided between the first input terminal and the first leg, between the second input terminal and the first leg, and between the intermediate point between the first capacitor and the second capacitor and the third inductor. The inverter circuit according to claim 1.

7. The inverter circuit according to claim 1, wherein the first inductor and the second inductor are realized using a common core.

8. The first inductor and the second inductor are connected in a summation manner. The inverter circuit according to claim 7.

9. The inverter circuit according to claim 2, A control unit that controls the opening and closing of each of the aforementioned switching elements A first DC voltmeter that detects the DC voltage which is the voltage between the first input terminal and the second input terminal, A second DC voltmeter for detecting a second DC voltage, which is the voltage between the midpoint of the first capacitor and the second capacitor and the first input terminal, A third DC voltmeter for detecting a third DC voltage, which is the voltage between the midpoint of the first capacitor and the second capacitor and the second input terminal, A first AC voltmeter for detecting a first AC voltage, which is the voltage between the first phase AC terminal and the neutral wire AC terminal, A second AC voltmeter for detecting the second AC voltage, which is the voltage between the second phase AC terminal and the neutral wire AC terminal, It has, The control unit controls the switching of each switching element so that the first AC voltage, the second AC voltage, the sum of the first and second AC voltages, the second DC voltage, the third DC voltage, or the difference between the second and third DC voltages becomes a target value. Power converter.

10. The control unit, When the power supplied to the load via the first phase and the power supplied to the load via the second phase are unbalanced, the switching control of each switching element is performed so that the power corresponding to the first phase and the second phase is recirculated using the path via the third inductor, in addition to the power output path via the first inductor and the second inductor. The power conversion device according to claim 9.

11. The inverter circuit according to claim 2, A control unit that controls the opening and closing of each of the aforementioned switching elements A DC ammeter for measuring the DC current, which is the current of the aforementioned DC power, A first AC ammeter for detecting the first AC current, which is the current between the first inductor and the first phase AC terminal, A second AC ammeter for detecting the second AC current, which is the current between the second inductor and the second phase AC terminal, A third AC ammeter for detecting the third AC current, which is the current between the third inductor and the neutral wire AC side terminal, It has, The control unit controls the switching of each of the switching elements so that the first AC current, the second AC current, or the third AC current reaches a target value. Power converter.

12. The control unit, When the power supplied to the load via the first phase and the power supplied to the load via the second phase are unbalanced, in addition to the power output path via the first and second inductors, a path via the third inductor is used to supply power to the first and second phases. The switching of each of the aforementioned switching elements is controlled to recirculate the corresponding power. The power conversion device according to claim 11.

13. A power converter connected to a commercial power grid, comprising a power converter according to any one of claims 9 to 12, a distributed power source, and a load, Distributed power systems.

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