Display device and method for manufacturing the same

Abstract

To improve the yield of display devices. [Solution] According to the embodiment, the display device comprises a substrate having a display area on which a plurality of subpixels are arranged; a rib layer having a pixel opening in each of the plurality of subpixels; a conductive lower part disposed above the rib layer and an upper part having an end protruding from the side surface of the lower part, a partition wall surrounding each of the plurality of subpixels; a plurality of display elements disposed on each of the plurality of subpixels and each containing an organic layer that emits light in response to the application of a voltage; a plurality of first sealing layers made of an inorganic insulating material that cover each of the plurality of display elements; and a second sealing layer made of an inorganic insulating material that covers the plurality of first sealing layers. Furthermore, the partition wall is divided into a plurality of segments by slits, and the second sealing layer is in contact with the rib layer at the slits.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a method for manufacturing the same.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies for improving the yield are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a display device and a method for manufacturing the same that can improve the yield.

Means for Solving the Problems

[0005] Generally, according to the embodiment, the display device comprises a substrate having a display area on which a plurality of subpixels are arranged; a rib layer having a pixel opening in each of the plurality of subpixels; a conductive lower part disposed above the rib layer and an upper part having an end protruding from the side surface of the lower part, a partition wall surrounding each of the plurality of subpixels; a plurality of display elements disposed in each of the plurality of subpixels and each containing an organic layer that emits light in response to the application of a voltage; a plurality of first sealing layers made of an inorganic insulating material that cover each of the plurality of display elements; and a second sealing layer made of an inorganic insulating material that covers the plurality of first sealing layers. Furthermore, the partition wall is divided into a plurality of segments by slits, and the second sealing layer is in contact with the rib layer at the slits.

[0006] From another perspective, above at least a portion of the partition wall, the adjacent ends of the first sealing layer are spaced apart from each other, and the second sealing layer is in contact with the upper part in the region between these ends.

[0007] From yet another perspective, the display device comprises a substrate having a display area on which a plurality of subpixels are arranged and a peripheral area surrounding the display area; a first partition surrounding each of the plurality of subpixels, comprising a rib layer formed in the display area and the peripheral area and having a pixel opening in each of the plurality of subpixels, a conductive lower part disposed above the rib layer and an upper part having an end protruding from the side surface of the lower part; a plurality of display elements disposed in each of the plurality of subpixels and each containing an organic layer that emits light in response to the application of a voltage; a plurality of first sealing layers made of an inorganic insulating material and covering each of the plurality of display elements; a second sealing layer made of an inorganic insulating material and covering the plurality of first sealing layers; and a dam portion disposed in the peripheral area and surrounding the display area. Furthermore, the rib layer is removed in at least a portion of the area between the edge of the substrate and the dam portion.

[0008] Furthermore, according to the embodiment, the method for manufacturing a display device includes forming a rib layer on top of a substrate, forming a first partition wall surrounding each of a plurality of subpixels, which includes a conductive lower part located above the rib layer and an upper part having an end protruding from the side surface of the lower part, forming a plurality of display elements for each of the plurality of subpixels, which include an organic layer that emits light in response to the application of a voltage, and a plurality of first sealing layers made of an inorganic insulating material that cover each of the display elements, forming a second sealing layer made of an inorganic insulating material that covers the plurality of first sealing layers, and forming a resin layer that covers a part of the second sealing layer. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 shows an example of the configuration of a display device according to the first embodiment. [Figure 2] Figure 2 is a schematic plan view showing an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic plan view showing some elements of a display device. [Figure 5] Figure 5 is a schematic cross-sectional view of the display device along the VV line in Figure 2. [Figure 6] Figure 6 is a schematic cross-sectional view of the display device along the VI-VI line in Figure 2. [Figure 7] Figure 7 is a schematic plan view of the area enclosed by frame VII in Figure 4. [Figure 8] Figure 8 is a schematic cross-sectional view of the display device along the line VIII-VIII in Figure 7. [Figure 9] Figure 9 is a schematic cross-sectional view of the display device along the IX-IX line in Figure 7. [Figure 10] Figure 10 is a schematic plan view of the motherboard according to the first embodiment. [Figure 11] Figure 11 is a schematic plan view of the panel section according to the first embodiment. [Figure 12]FIG. 12 is a flowchart showing an example of a method for manufacturing a display device according to the first embodiment. [Figure 13A] FIG. 13A is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 13B] FIG. 13B is a schematic cross-sectional view showing a process following FIG. 13A. [Figure 13C] FIG. 13C is a schematic cross-sectional view showing a process following FIG. 13B. [Figure 13D] FIG. 13D is a schematic cross-sectional view showing a process following FIG. 13C. [Figure 13E] FIG. 13E is a schematic cross-sectional view showing a process following FIG. 13D. [Figure 13F] FIG. 13F is a schematic cross-sectional view showing a process following FIG. 13E. [Figure 13G] FIG. 13G is a schematic cross-sectional view showing a process following FIG. 13F. [Figure 13H] FIG. 13H is a schematic cross-sectional view showing a process following FIG. 13G. [Figure 14] FIG. 14 is a schematic plan view of the region surrounded by frame XIV in FIG. 11. [Figure 15] FIG. 15 is a schematic cross-sectional view of the panel portion along line XV-XV in FIG. 14. [Figure 16A] FIG. 16A is a cross-sectional view showing a comparative example. [Figure 16B] FIG. 16B is another cross-sectional view showing a comparative example. [Figure 16C] FIG. 16C is yet another cross-sectional view showing a comparative example. [Figure 17A] FIG. 17A is a cross-sectional view showing the effect of the first embodiment. [Figure 17B] FIG. 17B is another cross-sectional view showing the effect of the first embodiment. [Figure 17C] FIG. 17C is yet another cross-sectional view showing the effect of the first embodiment. [Figure 18] FIG. 18 is a schematic cross-sectional view of the panel portion according to the second embodiment. [Figure 19]Figure 19 is a schematic cross-sectional view of the panel portion according to the third embodiment. [Figure 20] Figure 20 is a schematic cross-sectional view of the panel portion according to the fourth embodiment. [Figure 21] Figure 21 is a schematic cross-sectional view of the panel portion according to the fifth embodiment. [Figure 22] Figure 22 is a schematic cross-sectional view of the panel portion according to the sixth embodiment. [Figure 23] Figure 23 is a schematic cross-sectional view of the panel portion according to the seventh embodiment. [Modes for carrying out the invention]

[0010] Several embodiments will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0011] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis as the Y direction, and the direction along the Z axis as the Z direction. The Z direction is the normal direction of the plane containing the X and Y directions. Viewing various elements parallel to the Z direction is called a plan view.

[0012] Each embodiment of the display device is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable devices.

[0013] [First Embodiment] Figure 1 shows an example configuration of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.

[0014] In this embodiment, the shapes of the substrate 10 and the display area DA in plan view are circular. However, the shapes of the substrate 10 and the display area DA in plan view are not limited to circular, and may be other shapes such as rectangles, squares, or ellipses.

[0015] The display area DA comprises a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of sub-pixels SP that display different colors. In this embodiment, it is assumed that each pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. Each pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0016] The display device DSP further includes a terminal section T located in the peripheral region SA. A flexible circuit board, for example, that supplies voltage and signals for driving the display device DSP, is connected to the terminal section T.

[0017] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0018] The display area DA is arranged with multiple scan lines G that supply scan signals to the pixel circuits 1 of each sub-pixel SP, multiple signal lines S that supply video signals to the pixel circuits 1 of each sub-pixel SP, and multiple power lines PL. In Figure 1, the scan lines G and power lines PL extend in the X direction, and the signal lines S extend in the Y direction, but this is not the only example.

[0019] The gate electrode of pixel switch 2 is connected to scan line G. One of the source and drain electrodes of pixel switch 2 is connected to signal line S, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to power line PL and capacitor 4, and the other is connected to display element DE.

[0020] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0021] Figure 2 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3 that constitute a single pixel PX. In the example in Figure 2, sub-pixels SP1 and SP3 are aligned in the Y direction. Also, sub-pixels SP1 and SP3 are aligned with sub-pixel SP2 in the X direction.

[0022] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP1 and SP3 are alternately arranged in the Y direction, and columns in which multiple sub-pixels SP2 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0023] A rib layer 5 is arranged in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, pixel apertures AP1, AP2, and AP3 are all rectangular. The area of ​​pixel aperture AP1 is larger than the area of ​​pixel aperture AP3. Also, the area of ​​pixel aperture AP2 is larger than the area of ​​pixel aperture AP1. However, the shapes of pixel apertures AP1, AP2, and AP3 are not limited to this example.

[0024] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the pixel aperture AP3.

[0025] The lower electrode LE1, upper electrode UE1, and organic layer OR1 constitute the display element DE1 of the sub-pixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 constitute the display element DE2 of the sub-pixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 constitute the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0026] A conductive partition wall 6A (first partition wall) is positioned above the rib layer 5. Partition wall 6A serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. Partition wall 6A overlaps with the rib layer 5 overall and has a similar planar shape to the rib layer 5. Partition wall 6A surrounds the sub-pixels SP1, SP2, and SP3.

[0027] The partition wall 6A has multiple slits SL extending in the Y direction. In the example in Figure 2, sub-pixels SP1, SP2, and SP3 constituting one pixel PX are arranged between two slits SL in the X direction. Furthermore, the partition wall 6A has a connecting section CT that connects the portions separated by the slits SL (segments SG, described later). Note that the arrangement of the slits SL and connecting section CT is not limited to the example in Figure 2. For example, there may be continuous slits SL between both ends of the display area DA in the Y direction.

[0028] Sub-pixels SP1, SP2, and SP3 are each fitted with sealing layers SE11, SE12, and SE13 (first sealing layers). Sealing layer SE11 continuously covers the display element DE1 and the surrounding partition wall 6A. Sealing layer SE12 continuously covers the display element DE2 and the surrounding partition wall 6A. Sealing layer SE13 continuously covers the display element DE3 and the surrounding partition wall 6A.

[0029] In the example shown in Figure 2, the sealing layers SE11, SE12, and SE13 do not overlap with the slit SL. In another example, at least one of the sealing layers SE11, SE12, and SE13 may overlap with the slit SL.

[0030] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring such as the pixel circuit 1, scan line G, signal line S, and power line PL shown in Figure 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11.

[0031] The lower electrodes LE1, LE2, and LE3 are placed on the organic insulating layer 12. The rib layer 5 is placed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The periphery of the lower electrodes LE1, LE2, and LE3 is covered by the rib layer 5. Although not shown in the cross-section of Figure 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12.

[0032] The partition wall 6A includes a conductive lower portion 61 positioned on the rib layer 5 and an upper portion 62 positioned on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. That is, the partition wall 6A is overhanging in shape, with both ends of the upper portion 62 protruding beyond the sides of the lower portion 61.

[0033] In the example shown in Figure 3, the lower section 61 has a bottom layer 63 positioned on top of the rib layer 5 and an axial layer 64 positioned on top of the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the axial layer 64. In the example shown in Figure 3, both ends of the bottom layer 63 protrude from the sides of the axial layer 64.

[0034] Furthermore, in the example shown in Figure 3, the upper section 62 comprises a first top layer 65 and a second top layer 66 positioned on top of the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, it is not limited to this, and the first top layer 65 and the second top layer 66 may have equivalent widths.

[0035] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6A.

[0036] Display element DE1 includes a cap layer CP1 covering the upper electrode UE1. Display element DE2 includes a cap layer CP2 covering the upper electrode UE2. Display element DE3 includes a cap layer CP3 covering the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers to improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively.

[0037] In the following explanation, a multilayer containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as multilayer film FL1, a multilayer containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as multilayer film FL2, and a multilayer containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as multilayer film FL3.

[0038] Sub-pixels SP1, SP2, and SP3 are each fitted with sealing layers SE11, SE12, and SE13 (first sealing layers). Sealing layer SE11 continuously covers the laminated film FL1 and the surrounding partition wall 6A. Sealing layer SE12 continuously covers the laminated film FL2 and the surrounding partition wall 6A. Sealing layer SE13 continuously covers the laminated film FL3 and the surrounding partition wall 6A.

[0039] In the example shown in Figure 3, the sealing layer SE11 on the partition wall 6A between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the same partition wall 6A. Also, the sealing layer SE11 on the partition wall 6A between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the same partition wall 6A. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact above the partition wall 6A.

[0040] The sealing layers SE11, SE12, and SE13 are covered by the sealing layer SE2 (second sealing layer). Details of the sealing layer SE2 will be described later with reference to Figures 5 and 6, etc.

[0041] The sealing layer SE2 is covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE3 (third sealing layer). The sealing layer SE3 is covered by the resin layer RS2. The resin layers RS1, RS2 and the sealing layer SE3 are provided continuously over at least the entire display area DA, and a portion of them extends into the peripheral area SA.

[0042] In the example shown in Figure 3, a touch panel electrode TP for detecting user touch operations is placed on top of the sealing layer SE3. The touch panel electrode TP is made of, for example, a metal material and has a shape similar to the partition wall 6A in a plan view.

[0043] A cover member, such as a polarizing plate, protective film, or cover glass, may be further placed above the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer, such as OCA (Optical Clear Adhesive).

[0044] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2, SE3 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2, SE3 are formed of silicon nitride. The resin layers RS1, RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0045] The lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of this reflective layer, respectively. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0046] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0047] The organic layers OR1, OR2, and OR3 are composed of multiple thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked sequentially in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including multiple emissive layers.

[0048] The cap layers CP1, CP2, and CP3 have a laminated structure in which multiple transparent layers are stacked, for example. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from those of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. Note that at least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0049] The bottom layer 63 and axial layer 64 of the partition wall 6A are formed of a metallic material. For example, the metallic material for the bottom layer 63 can be molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb). For example, the metallic material for the axial layer 64 can be aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). The axial layer 64 may also be formed of an insulating material.

[0050] The first top layer 65 of the partition wall 6A is formed of, for example, a metallic material. The second top layer 66 of the partition wall 6A is formed of, for example, a conductive oxide. As the metallic material forming the first top layer 65, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy can be used. As the conductive oxide forming the second top layer 66, for example, ITO or IZO can be used. The upper part 62 may consist of three or more layers, or it may be formed as a single layer. Furthermore, the upper part 62 may include a layer formed of an insulating material.

[0051] A common voltage is supplied to the partition wall 6A. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the video signal on the signal line S through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0052] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the red wavelength range.

[0053] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0054] Figure 4 is a schematic plan view showing some elements of the display device DSP. The partition wall 6A is divided into multiple segments SG by multiple slits SL, as also shown in Figure 2. Note that in Figure 4, the slits SL and segments SG are schematically shown. For example, if slits SL are located on both sides of the pixel PX in the X direction, as shown in Figure 2, more slits SL are formed in the display area DA.

[0055] At least some of the multiple segments SG are connected by connecting sections CT that cross the slits SL, as shown in Figure 2. On the other hand, some of the multiple slits SL may not have connecting sections CT.

[0056] One end of each segment SG in the direction of extension of the slit SL (Y direction in this embodiment) is connected to a power supply line PW provided in the surrounding region SA. The power supply line PW is connected to a terminal section T. A common voltage is applied to each segment SG from the terminal section T via the power supply line PW. In the example in Figure 4, the other ends of each segment SG are separated by the slit SL and are not connected by a conductive member such as the power supply line PW.

[0057] Figure 5 is a schematic cross-sectional view of the display device DSP along the VV line in Figure 2, showing a portion of the adjacent sub-pixels SP1 and SP2 separated by a slit SL, and the partition wall 6A between them. The side of the partition wall 6A facing the slit SL is an overhang shape, with the upper part 62 protruding from the side surface of the axial layer 64. The rib layer 5 is not open in the slit SL.

[0058] In the example shown in Figure 5, both the end E11 of sealing layer SE11 and the end E12 of sealing layer SE12 are located above the partition wall 6A. That is, sealing layers SE11 and SE12 do not overlap with the slit SL. In another example, ends E11 and E12 may be located at the slit SL. In this case, a portion of the slit SL overlaps with sealing layers SE11 and SE12.

[0059] Gaps G1 and G2 are formed between the upper part 62 of the partition wall 6A and the sealing layers SE11 and SE12 above it, respectively. The slit SL is filled with a resin layer RS1. Gaps G1 and G2 may be filled with the resin layer RS1, or at least a portion of them may be void. In addition, laminated films FL1 and FL2 may be placed in at least a portion of gaps G1 and G2, respectively.

[0060] The sealing layer SE2 has a first portion P1 that covers the sealing layers SE11 and SE12, and a second portion P2 located in the slit SL. The first portion P1 covers not only the upper surface of the sealing layers SE11 and SE12, but also the ends E11 and E12. Furthermore, in the example in Figure 5, the first portion P1 also covers the area near the entrance of the gaps G1 and G2 (part of the ceiling surface of the gaps G1 and G2).

[0061] The second portion P2 is in contact with the rib layer 5 in the slit SL and is covered by the resin layer RS1. Furthermore, the second portion P2 covers the bottom layer 63, axial layer 64, first top layer 65, and second top layer 66 of the partition wall 6A exposed from the sealing layers SE11 and SE12. In the example in Figure 5, the first portion P1 and the second portion P2 are separated. In another example, the first portion P1 and the second portion P2 may be connected.

[0062] Figure 6 is a schematic cross-sectional view of a display device DSP along the VI-VI line in Figure 2, showing parts of the sub-pixels SP1 and SP2 and the partition wall 6A between them. In the example in Figure 6, the end E11 of the sealing layer SE11 and the end E12 of the sealing layer SE12 are both located above the partition wall 6A and are spaced apart in the X direction. In addition, gaps G1 and G2 are formed between the upper part 62 of the partition wall 6A and the sealing layers SE11 and SE12 above it, respectively.

[0063] The space between ends E11 and E12 is filled with resin layer RS1. The gaps G1 and G2 may be filled with resin layer RS1 as described above, or at least a portion of them may be void.

[0064] In the cross-section shown in Figure 6, the first portion P1 of the sealing layer SE2 covers the ends E11 and E12. Furthermore, the sealing layer SE2 has a third portion P3 located above the partition wall 6A. The third portion P3 is in contact with the upper part 62 (second top layer 66) in the region between the ends E11 and E12 and is covered by the resin layer RS1. In the example in Figure 6, the first portion P1 and the third portion P3 are separated. In another example, the first portion P1 and the third portion P3 may be connected.

[0065] The sealing layer SE11 has a thickness T1. The sealing layer SE2 has a thickness T2 that is smaller than the thickness T1 (T1 > T2). In one example, the thickness T2 is less than or equal to half the thickness T1. In this case, specific values ​​that can be applied are when the thickness T1 is 2.0 μm or more and the thickness T2 is 500 nm to 1.0 μm. Note that the thicknesses of sealing layers SE12 and SE13 are, for example, the same as the thickness T1 of sealing layer SE11.

[0066] Figures 5 and 6 focus on the area near the boundary between subpixels SP1 and SP2, but the same configuration can be applied to the area near the boundary between subpixels SP1 and SP3, and also to the area near the boundary between subpixels SP2 and SP3. The first portion P1 of the sealing layer SE2 also covers the top surface and edges of the sealing layer SE13.

[0067] Figure 7 is a schematic plan view of the area enclosed by frame VII in Figure 4. This plan view shows the edge E10 of the substrate 10 and some of the elements located in its vicinity.

[0068] A partition wall 6B is located in the surrounding area SA. Although simplified in Figure 7, partition wall 6B has multiple openings. Partition wall 6B is connected to partition wall 6A located in the display area DA.

[0069] Between the bulkhead 6B and end E10, dam sections DM1, DM2, DM3, DM4, and DM5 are positioned. Dam sections DM1, DM2, and DM3 form an annular structure surrounding the display area DA and bulkhead 6B. However, dam section DM3 is interrupted near terminal section T.

[0070] Dam sections DM4 and DM5 are located between terminal section T and dam section DM2. Dam section DM4 branches into dam sections DM41 and DM42 near end E10.

[0071] The terminal section T has multiple pads PD. These pads PD have an elongated shape in the Y direction and are arranged in the X direction between the dam section DM5 and the end section E10. Multiple partition walls 6C (second partition walls) are arranged near the end section E10. For example, these partition walls 6C are arranged at predetermined intervals along the end section E10.

[0072] Figure 8 is a schematic cross-sectional view of the display device DSP along the line VIII-VIII in Figure 7. Partition walls 6B and 6C have a similar structure to partition wall 6A. That is, partition walls 6B and 6C include a lower part 61 and an upper part 62. The lower part 61 includes a bottom layer 63 and an axial layer 64, and the upper part 62 includes a first top layer 65 and a second top layer 66. At the ends of partition walls 6B and 6C, the upper part 62 protrudes beyond the side surface of the lower part 61.

[0073] The circuit layer 11 shown in Figure 3 includes inorganic insulating layers 31, 32, and 33 made of inorganic insulating material, an organic insulating layer 34 made of organic insulating material, and metal layers 41, 42, and 43. The inorganic insulating layer 31 covers the upper surface of the substrate 10. The metal layer 41 is placed on top of the inorganic insulating layer 31. The inorganic insulating layer 32 covers the metal layer 41. The metal layer 42 is placed on top of the inorganic insulating layer 32. The inorganic insulating layer 33 covers the metal layer 42. The organic insulating layer 34 covers the inorganic insulating layer 33. The metal layer 43 is placed on top of the organic insulating layer 34 and is covered by the organic insulating layer 12.

[0074] The dam sections DM1, DM2, and DM3 all protrude above the substrate 10. In the example in Figure 8, the dam section DM1 is formed of organic insulating layers 12 and 34. Similarly, the dam sections DM2 and DM3 are also formed of organic insulating layers 12 and 34. In other words, in this embodiment, the dam sections DM1, DM2, and DM3 are formed of the same material as the organic insulating layers 12 and 34 and in the same layer as the organic insulating layers 12 and 34.

[0075] Below the dam sections DM1 and DM2, a power supply line PW to which a common voltage is applied is located. The power supply line PW has a first wiring W1 formed of a metal layer 42 and a second wiring W2 formed of a metal layer 43.

[0076] In the example shown in Figure 8, the first wiring W1 and the second wiring W2 are in contact at the contact portion CN0 located between the dam portions DM1 and DM2. In each of the dam portions DM1 and DM2, a portion of the second wiring W2 is located between the organic insulating layers 12 and 34.

[0077] In the surrounding region SA, a conductive relay layer RL0 connecting the partition wall 6B and the power supply line PW, and a rib layer 5 are further arranged. The relay layer RL0 is formed, for example, from the same material and using the same process as the lower electrodes LE1, LE2, and LE3 described above.

[0078] The intermediate layer RL0 is located on the display area DA side (left side in the diagram) of the dam section DM1 and covers the organic insulating layer 12. The rib layer 5 continuously covers the intermediate layer RL0 and the dam sections DM1, DM2, and DM3.

[0079] The partitions 6B and 6C are positioned on top of the rib layer 5. Partition 6B is in contact with the intermediate layer RL0 at the contact portion CN1. Specifically, the rib layer 5 has an opening at the contact portion CN1, and the lower part 61 of partition 6B (specifically the bottom layer 63) is in contact with the intermediate layer RL0 through this opening. The contact portion CN1 is located above the organic insulating layer 12.

[0080] The relay layer RL0 is in contact with the second wiring W2 of the power supply line PW at the contact portion CN2. In a plan view, the contact portion CN2 is located between the end E0 of the organic insulating layer 12 and the dam portion DM1.

[0081] A laminated film FLx is positioned on top of the partition wall 6B. The partition wall 6B and the laminated film FLx are covered by a sealing layer SE1x. The laminated film FLx is formed using the same process and materials as any of the laminated films FL1, FL2, or FL3 shown in Figure 3. The sealing layer SE1x is formed using the same process and materials as any of the sealing layers SE11, SE12, or SE13 shown in Figure 3. In this embodiment, we assume that the laminated film FLx and the sealing layer SE1x are formed using the same process and materials as the laminated film FL3 and the sealing layer SE13, respectively. That is, the laminated film FLx includes an upper electrode UE3, an organic layer OR3, and a cap layer CP3. The end Es1 of the sealing layer SE1x is located, for example, between the partition wall 6B and the dam portion DM1.

[0082] A sealing layer SE2 is also placed in the surrounding region SA. The sealing layer SE2 covers the sealing layer SE1x and also covers the rib layer 5 in the region outside the end Es1 of the sealing layer SE1x (towards the end E10). Furthermore, the sealing layer SE2 also covers the partition wall 6C.

[0083] Above the sealing layer SE2 are the resin layer RS1, sealing layer SE3, and resin layer RS2 shown in Figure 3. Furthermore, above the sealing layer SE3 are the touch panel wiring TPL connected to the touch panel electrode TP shown in Figure 3. For example, the touch panel wiring TPL is made of the same material as the touch panel electrode TP.

[0084] The resin layer RS1 covers the sealing layer SE2. The dam sections DM1, DM2, and DM3 play a role in preventing the resin layer RS1 from curing during the manufacturing of the display device DSP. In the example in Figure 8, the end portion Er1 of the resin layer RS1 is located above the dam section DM2. That is, the resin layer RS1 covers both the dam section DM1 and a portion of the dam section DM2. However, the position of the end portion Er1 is not limited to this example.

[0085] The sealing layer SE3 covers the end portion Er1 of the resin layer RS1. The sealing layer SE3 is in contact with the sealing layer SE2 in the region outside the end portion Er1 (to the right in the figure). In the example in Figure 8, a removal region RA1 is formed near the dam portion DM3 where the sealing layers SE2 and SE3 have been removed. By providing the removal region RA1, even if cracks occur in the sealing layers SE2 and SE3, the growth of these cracks toward the display region DA can be suppressed.

[0086] Figure 9 is a schematic cross-sectional view of the display device DSP along the IX-IX line in Figure 7. Dam sections DM4 and DM5 are formed by organic insulating layers 12 and 34, similar to dam sections DM1, DM2, and DM3.

[0087] In the example shown in Figure 9, the end Es2 of the sealing layer SE2 and the end Es3 of the sealing layer SE3 are aligned. These ends Es2 and Es3 are located, for example, above the dam section DM4 and are covered by the resin layer RS2. However, the positions of ends Es2 and Es3 are not limited to this example.

[0088] The end portion Er2 of the resin layer RS2 is located, for example, above the dam portion DM5. The rib layer 5 is also formed in the region outside of the end portion Er2 (towards the end portion E10). The pad PD of the terminal portion T is located between the end portion Er2 and the end portion E10.

[0089] The pad PD is formed from the same material as, for example, the touch panel electrode TP and the touch panel wiring TPL. The pad PD is connected to the relay layer RL1. Furthermore, the relay layer RL2 is connected to the relay layer RL2, and the relay layer RL2 is connected to the wiring LL. For example, the relay layer RL1 is formed from the metal layer 43 of the circuit layer 11, the relay layer RL2 is formed from the metal layer 42 of the circuit layer 11, and the wiring LL is formed from the metal layer 41 of the circuit layer 11.

[0090] Next, an example of a manufacturing method for a DSP display device will be described. When manufacturing a DSP display device, a large motherboard is created in which multiple regions (panel sections) are formed, each containing a portion corresponding to the DSP display device.

[0091] Figure 10 is a schematic plan view of the motherboard MB (display device motherboard) according to this embodiment. The motherboard MB is rectangular, as shown in the figure, but it may also have other shapes such as a circle.

[0092] The motherboard MB has multiple panel sections PP arranged in a matrix, and a marginal area BA surrounding these panel sections PP. In the example shown in Figure 10, each panel section PP is arranged in the X and Y directions with the marginal area BA in between. However, the arrangement of the multiple panel sections PP on the motherboard MB is not limited to this example. In other examples, some panel sections PP may be arranged without the marginal area BA in between.

[0093] Figure 11 is a schematic plan view of the panel section PP. The outline of the panel section PP corresponds to the cut line CL1 used to cut out each panel section PP from the motherboard MB.

[0094] The panel section PP has the display area DA and the peripheral area SA described above. The peripheral area SA in the panel section PP corresponds to the area between the display area DA and the cut line CL1.

[0095] The peripheral region SA further has a cut line CL2 which defines the outer shape of the substrate 10 of the display device DSP. During the manufacturing of the display device DSP, the panel portion PP is cut out from the motherboard MB along the cut line CL1. Furthermore, the display device DSP is cut out from the panel portion PP along the cut line CL2.

[0096] Figure 12 is a flowchart showing an example of a method for manufacturing a display device DSP. Figures 13A to 13H are schematic cross-sectional views showing the manufacturing process of a display device DSP. In Figures 13A to 13H, the focus is mainly on the display area DA, and elements below the organic insulating layer 12 are omitted.

[0097] In forming the panel portion PP, first, a circuit layer 11 including the inorganic insulating layers 31, 32, 33, the organic insulating layer 34, and the metal layers 41, 42, 43, etc., is formed on top of the substrate 10 of the mother board MB (step PR1 in Figure 12). Furthermore, an organic insulating layer 12 is formed to cover the circuit layer 11 (step PR2 in Figure 12). At this time, the dam portions DM1, DM2, DM3, and DM4 are also formed.

[0098] After step PR2, as shown in Figure 13A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR3 in Figure 12). Furthermore, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed over the entire motherboard MB (step PR4 in Figure 12). At this point, the rib layer 5 does not have pixel apertures AP1, AP2, and AP3. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0099] After the formation of the rib layer 5, a partition wall 6A is formed on top of the rib layer 5, as shown in Figure 13B (step PR5 in Figure 12). Partition walls 6B and 6C in the surrounding region SA are also formed together with partition wall 6A.

[0100] Next, as shown in Figure 13C, pixel apertures AP1, AP2, and AP3 are formed in the rib layer 5 (step PR6 in Figure 12). Note that the pixel apertures AP1, AP2, and AP3 may be formed in front of the partition walls 6A, 6B, and 6C.

[0101] After step PR6, a process for forming the display element DE1 is carried out (step PR7 in Figure 12). In forming the display element DE1, first, as shown in Figure 13D, a laminated film FL1 and a sealing layer SE11 are formed. As shown in Figure 3, the laminated film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel aperture AP1, an upper electrode UE1 that covers the organic layer OR1, and a cap layer CP1 that covers the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed, for example, by vapor deposition. The sealing layer SE11 can be formed, for example, by CVD.

[0102] The laminated film FL1 and the sealing layer SE11 are formed on the entire motherboard MB, including not only the display area DA of each panel section PP, but also the peripheral area SA and the margin area BA. The laminated film FL1 is divided by overhanging partitions 6A, 6B, and 6C. The sealing layer SE11 continuously covers each divided portion of the laminated film FL1 and the partitions 6A, 6B, and 6C.

[0103] Next, the multilayer film FL1 and the sealing layer SE11 are patterned. In this patterning, as shown in Figure 13D, a resist RT is placed on top of the sealing layer SE11. The resist RT covers the subpixel SP1 and a portion of the surrounding partition wall 6A.

[0104] Subsequently, an etching process is performed using the resist RT as a mask. As a result, as shown in Figure 13E, the portions of the multilayer film FL1 and the sealing layer SE11 that are exposed from the resist RT are removed. In other words, the portions of the multilayer film FL1 and the sealing layer SE11 that overlap with the lower electrode LE1 are left, and the other portions are removed. This forms the display element DE1 on the sub-pixel SP1. For example, in the peripheral region SA and the margin region BA, the multilayer film FL1 and the sealing layer SE11 are removed by this etching process. This etching process may include wet etching or dry etching performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, the resist RT is removed (peeled off).

[0105] After step PR7, a process for forming the display element DE2 is carried out (step PR8 in Figure 12). The display element DE2 can be formed using the same procedure as the display element DE1. That is, in forming the display element DE2, the multilayer film FL2 and the sealing layer SE12 are formed over the entire mother substrate MB. As shown in Figure 3, the multilayer film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel aperture AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2.

[0106] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed, for example, by vapor deposition. The sealing layer SE12 can be formed, for example, by CVD. By patterning such a multilayer film FL2 and sealing layer SE2, a display element DE2 is formed on the sub-pixel SP2, as shown in Figure 13F. For example, in the peripheral region SA and the blank region BA, the multilayer film FL2 and sealing layer SE12 are removed by etching during the patterning process.

[0107] After step PR8, a process for forming the display element DE3 is carried out (step PR9 in Figure 12). The display element DE3 can be formed using the same procedure as for the display elements DE1 and DE2. That is, in forming the display element DE3, the multilayer film FL3 and the sealing layer SE13 are formed over the entire mother substrate MB. As shown in Figure 3, the multilayer film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel aperture AP3, an upper electrode UE3 that covers the organic layer OR3, and a cap layer CP3 that covers the upper electrode UE3.

[0108] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed, for example, by vapor deposition. The sealing layer SE13 can be formed, for example, by CVD. By patterning such a multilayer film FL3 and sealing layer SE13, a display element DE3 is formed on the sub-pixel SP3, as shown in Figure 13G.

[0109] For example, in most of the peripheral region SA and the margin region BA, the multilayer film FL3 and the sealing layer SE13 are removed by etching during the patterning process. However, the portion of the multilayer film FL3 and the sealing layer SE13 that covers the partition wall 6B is left intact. This remaining portion corresponds to the aforementioned multilayer film FLx and sealing layer SE1x.

[0110] Note that, while this example assumes that the display elements DE1, DE2, and DE3 are formed in this order, they may be formed in any other order.

[0111] After step PR9, as shown in Figure 13H, a sealing layer SE2 covering the sealing layers SE11, SE12, and SE13 is formed, for example, by CVD (step PR10). The sealing layer SE2 is formed over the entire mother substrate MB, including the panel portion PP and the margin area BA.

[0112] Next, a resin layer RS1 is formed (step PR11 in Figure 12). The resin layer RS1 can be formed, for example, by an inkjet method. After step PR11, a sealing layer SE3 is formed, for example, by CVD (step PR12 in Figure 12).

[0113] After step PR12, etching is performed to remove the rib layer 5, sealing layer SE2, and sealing layer SE3 covering the terminal portion T (step PR13 in Figure 12). Furthermore, etching is performed to remove a wider area of ​​sealing layers SE2 and SE3, including the terminal portion T (step PR14 in Figure 12). In step PR14, the rib layer 5 is not removed. These etchings are, for example, dry etchings. The removal region RA1 shown in Figure 8 is also formed by the etching in step PR14.

[0114] After step PR14, the touch panel electrode TP, touch panel wiring TPL, and pad PD are formed (step PR15 in Figure 12). Furthermore, the resin layer RS2 is formed (step PR16 in Figure 12). The resin layer RS2 can be formed, for example, by an inkjet method.

[0115] After step PR16, the motherboard MB is cut along cut line CL1 (step PR17 in Figure 12). Furthermore, the panel portion PP is cut along cut line CL2 (step PR18 in Figure 12). This completes the display device DSP. For cutting in steps PR17 and PR18, for example, laser cutting, which irradiates with an infrared laser along cut lines CL1 and CL2, can be used. However, cutting in steps PR17 and PR18 may be carried out by other methods such as scribe cutting.

[0116] Figure 14 is a schematic plan view of the area enclosed by frame XIV in Figure 11, showing some of the elements of the panel section PP before cutting along the cut line CL2 (process PR18).

[0117] The cut line CL2 corresponds to the edge E10 of the substrate 10 after the execution of process PR18. In Figure 14, the configuration inside the cut line CL2 (upper left side in the figure) is the same as that shown in Figure 7.

[0118] Dam sections DM41, DM42, and DM5 extend outside the cut line CL2 and enclose a roughly circular area (see Figure 11) enclosed by the cut line CL2. In the example in Figure 14, numerous bulkheads 6C are also placed in the areas between the cut line CL2 and dam section DM41, between dam sections DM41 and DM42, and between dam sections DM42 and DM5. Further bulkheads 6C may be placed in the areas overlapping with dam sections DM41, DM42, and DM5, or in the area outside dam section DM5.

[0119] Figure 15 is a schematic cross-sectional view of the panel section PP along the line XV-XV in Figure 14. Dam sections DM41, DM42, and DM5 are formed by organic insulating layers 12 and 34, similar to dam sections DM1, DM2, and DM3.

[0120] Dam sections DM41, DM42, and DM5 are covered by rib layer 5, sealing layer SE2, and sealing layer SE3. The bulkhead 6C outside the cut line CL2 is located above rib layer 5 and is covered by sealing layer SE2.

[0121] In the example shown in Figure 15, the cut line CL2 overlaps with the inorganic insulating layers 31-33, the rib layer 5, the sealing layer SE2, the sealing layer SE3, and the resin layer RS2. However, the cut line CL2 does not overlap with the partition wall 6C.

[0122] Now, let's explain the effects of this embodiment. Figures 16A to 16C are cross-sectional views showing a comparative example with this embodiment. Figures 17A to 17C are cross-sectional views showing the effects of this embodiment. These figures show the structure around the slit SL, similar to Figure 5. Note that the comparative example differs from the structure of this embodiment in that it does not have a sealing layer SE2.

[0123] When forming the resin layer RS1 using an inkjet method, droplets D of the resin material are ejected onto each panel section PP, as shown in Figure 16A. Most of these droplets D adhere to the sealing layers SE11, SE12, and SE13.

[0124] As shown in Figure 16B, droplets D adhering to the sealing layers SE11, SE12, and SE13 spread out due to wetting. The edges E11 and E12 of sealing layers SE11 and SE12, and the edge of sealing layer SE13, are generally vertically cut. Therefore, as shown in the left-hand droplet D in the figure, surface tension at these edges may prevent droplets D from flowing into the slit SL.

[0125] Furthermore, gaps G1 and G2 are formed between the upper part 62 of the partition wall 6A and the sealing layers SE11 and SE12, and similar gaps are formed between the upper part 62 and the sealing layer SE13. Therefore, even if the droplet D spreads and wets the slit SL, the air bubbles in these gaps may break up the droplet D as they escape, as indicated by arrow B. In addition, the side of the partition wall 6A facing the slit SL is overhanging, and the droplet D may also be broken up by air bubbles that form in this area.

[0126] If droplet D hardens in a fragmented state, a shape defect in the resin layer RS1 may occur near the slit SL, as shown in Figure 16C. Specifically, the resin layer RS1 may not adequately fill the slit SL, resulting in a step corresponding to the slit SL. If the sealing layer SE3 is formed in this state, the sealing layer SE3 may be fragmented, potentially creating a pathway for moisture penetration. Furthermore, the touch panel electrode TP formed on top of the sealing layer SE3 may also become disconnected.

[0127] In contrast, in this embodiment, as shown in Figure 17A, a sealing layer SE2 is provided that covers the entire display area DA, including the sealing layers SE11, SE12, SE13 and the slit SL. By covering the edges E11, E12 of the sealing layers SE11, SE12 and the edge of the sealing layer SE13 with this sealing layer SE2, the steps at these edges become smoother. As a result, as shown in Figure 17B, droplets D can flow more easily into the slit SL.

[0128] As shown in Figure 17C, the droplet D is smoothed without being divided by the slit SL. As a result, it becomes possible to form a resin layer RS1 with a flat top surface, as shown in Figure 5. This suppresses the division of the sealing layer SE3 near the slit SL and the disconnection of the touch panel electrode TP.

[0129] Furthermore, if the sealing layer SE2 is formed thickly, the gaps G1 and G2 between the upper part 62 and the sealing layers SE11 and SE12, and the entrance to the gap between the upper part 62 and the sealing layer SE13 will be sealed. In addition, the space below the upper part 62 of the partition wall 6A facing the slit SL will also be filled to some extent by the sealing layer SE2. In this case, it is also possible to suppress the fragmentation of the liquid droplet D by the aforementioned air bubbles.

[0130] The above effects can be obtained not only near the slit SL, but also in locations such as those shown in Figure 6. That is, if the ends of the sealing layers SE11, SE12, and SE13 are spaced apart above the partition wall 6A, there is a possibility that the resin layer RS1 may not flow into the space between these ends, but this situation can be suppressed by providing the sealing layer SE2.

[0131] Furthermore, as shown in Figures 8 and 9, the sealing layer SE2 is in contact with the sealing layer SE3 in the surrounding region SA. This allows the resin layer RS1 to be completely surrounded by an inorganic insulating material, further suppressing the occurrence of moisture penetration pathways. In addition to those described herein, various other desirable effects can be obtained from this embodiment.

[0132] The second to sixth embodiments are disclosed below. These embodiments focus on a cross-section similar to that in Figure 15 and disclose other configurations applicable to the peripheral region SA of the panel portion PP. For configurations of the panel portion PP not mentioned in each embodiment, those of the first embodiment can be applied. Furthermore, by cutting the panel portion PP disclosed in each embodiment along the cut line CL2, a display device DSP having a configuration of the panel portion PP inside the cut line CL2 can be obtained.

[0133] [Second Embodiment] Figure 18 is a schematic cross-sectional view of the panel portion PP according to the second embodiment. In this embodiment, the dam portion DM3 is not provided. Furthermore, a removal region RA2 is provided between the dam portions DM2 and DM41, where the rib layer 5 has been removed. The removal region RA2 can be formed, for example, in the process of forming pixel apertures AP1, AP2, and AP3 in the rib layer 5 (process PR6 in Figure 12).

[0134] The removal area RA2 overlaps with the cut line CL2. The ends of the rib layer 5 located at the edge of the removal area RA2 are covered by the sealing layers SE2 and SE3. The partition walls 6C on both sides of the cut line CL2 are located in the removal area RA2. These partition walls 6C are placed on top of the inorganic insulating layer 33 and are covered by the sealing layer SE2.

[0135] By omitting the dam section DM3 as in this embodiment, the width of the surrounding region SA can be narrowed. Furthermore, because the rib layer 5 is removed at the cut line CL2, cutting the panel section PP using the laser cutting method described above becomes easier.

[0136] Furthermore, if the panel portion PP shown in Figure 18 is cut along the cut line CL2, a display device DSP will be manufactured in which the rib layer 5 is removed in a portion between the outermost dam portion DM41 and the end portion E10 of the substrate 10.

[0137] [Third Embodiment] Figure 19 is a schematic cross-sectional view of the panel portion PP according to the third embodiment. The configuration shown in this figure differs from the second embodiment (Figure 18) in that the width of the removal area RA2 is narrowed.

[0138] Specifically, the removal area RA2 is located between the partition walls 6C on both sides of the cut line CL2. As a result, these partition walls 6C are located on top of the rib layer 5, allowing them to be stably formed on the same substrate as partition walls 6A, etc.

[0139] [Fourth Embodiment] Figure 20 is a schematic cross-sectional view of the panel portion PP according to the fourth embodiment. The configuration shown in this figure differs from the third embodiment (Figure 19) in that the rib layer 5 is removed in the removal region RA1.

[0140] The removal region RA1 can be formed, for example, by etching in step PR13 in Figure 12. In this case, the edges of the rib layer 5, the sealing layer SE2, and the sealing layer SE3 align at the edge of the removal region RA1.

[0141] [Fifth Embodiment] Figure 21 is a schematic cross-sectional view of the panel portion PP according to the fifth embodiment. The configuration shown in this figure differs from the second embodiment (Figure 18) in that a removal region RA3 is further provided where the sealing layers SE2 and SE3 have been removed.

[0142] The removal area RA3 overlaps with the cut line CL2. More specifically, the removal area RA3 is located between the partition walls 6C on both sides of the cut line CL2. The removal area RA3 can be formed by etching in step PR14 in Figure 12.

[0143] As in this embodiment, when a removal area RA3 is provided, cutting the panel portion PP using the laser cutting method described above becomes even easier.

[0144] [Sixth Embodiment] Figure 22 is a schematic cross-sectional view of the panel portion PP according to the sixth embodiment. The configuration shown in this figure corresponds to the configuration of the third embodiment (Figure 19) with the addition of a removal area RA3 similar to that of the fifth embodiment (Figure 21). With such a configuration, the same effects as those of the third and fifth embodiments are achieved.

[0145] [Seventh Embodiment] Figure 23 is a schematic cross-sectional view of the panel portion PP according to the seventh embodiment. The configuration shown in this figure corresponds to the configuration of the fourth embodiment (Figure 20) with the addition of a removal area RA3 similar to that of the fifth embodiment (Figure 21). With such a configuration, the same effects as those of the fourth and fifth embodiments are achieved.

[0146] In each of the embodiments described above, the term "partition wall" includes various overhanging structures. Even if the overhanging structure has a different shape from the partition wall disclosed in each embodiment, the laterally protruding portion corresponds to the "upper part," and the recessed portion below that portion corresponds to the "lower part."

[0147] All display devices and manufacturing methods that a person skilled in the art can implement by appropriately modifying the design based on the display devices and manufacturing methods disclosed in each embodiment also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0148] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications to the above-described embodiments in which a person skilled in the art has appropriately added, deleted, or modified components, or added, omitted, or modified processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0149] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0150] DSP...Display device, DA...Display area, SA...Peripheral area, PX...Pixel, SP1, SP2, SP3...Sub-pixel, LE1, LE2, LE3...Lower electrode, OR1, OR2, OR3...Organic layer, UE1, UE2, UE3...Upper electrode, SE11, SE12, SE13, SE2, SE3...Sealing layer, RS1, RS2...Resin layer, SL...Slit, CT...Connection part, 5...Rib layer, 6A, 6B, 6C...Partition wall, 61...Lower part, 62...Upper part, 63...Bottom layer, 64...Axial layer.

Claims

1. A substrate having a display area in which multiple subpixels are arranged, A rib layer having a pixel aperture in each of the plurality of subpixels, It includes a conductive lower part positioned above the rib layer and an upper part having an end protruding from the side surface of the lower part, and a partition wall surrounding each of the plurality of subpixels, Each of the aforementioned sub-pixels is arranged and includes a plurality of display elements, each containing an organic layer that emits light in response to the application of a voltage, A plurality of first sealing layers formed of an inorganic insulating material, each covering the plurality of display elements, A second sealing layer formed of an inorganic insulating material and covering the plurality of first sealing layers, Equipped with, The partition wall is divided into multiple segments by slits, The second sealing layer is in contact with the rib layer in the slit. Display device.

2. The second sealing layer further comprises a resin layer covering the above-mentioned second sealing layer, At least a portion of the slit is filled with the resin layer. The display device according to claim 1.

3. The ends of the plurality of first sealing layers are located above the partition wall. The second sealing layer covers the ends of the plurality of first sealing layers. The display device according to claim 1.

4. The second sealing layer has a first portion that covers the plurality of first sealing layers and a second portion that contacts the rib layer in the slit. The first part and the second part are separated, The display device according to claim 1.

5. The second sealing layer is thinner than the first sealing layer. The display device according to any one of claims 1 to 4.

6. A substrate having a display area in which multiple subpixels are arranged, A rib layer having a pixel aperture in each of the plurality of subpixels, It includes a conductive lower part positioned above the rib layer and an upper part having an end protruding from the side surface of the lower part, and a partition wall surrounding each of the plurality of subpixels, Each of the aforementioned sub-pixels is arranged and includes a plurality of display elements, each containing an organic layer that emits light in response to the application of a voltage, A plurality of first sealing layers formed of an inorganic insulating material, each covering the plurality of display elements, A second sealing layer formed of an inorganic insulating material and covering the plurality of first sealing layers, Equipped with, Above at least a portion of the partition wall, the adjacent ends of the first sealing layer are spaced apart from each other, and the second sealing layer is in contact with the upper part in the region between these ends. Display device.

7. The second sealing layer further comprises a resin layer covering the above-mentioned second sealing layer, Above at least a portion of the partition wall, the space between the ends of adjacent first sealing layers is filled with the resin layer. The display device according to claim 6.

8. The second sealing layer covers the ends of the plurality of first sealing layers. The display device according to claim 6.

9. The second sealing layer has a first portion that covers the plurality of first sealing layers and a third portion that contacts the upper portion. The first part and the third part are separated, The display device according to claim 6.

10. The second sealing layer is thinner than the first sealing layer. The display device according to any one of claims 6 to 9.

11. A substrate having a display area in which multiple subpixels are arranged and a peripheral area surrounding the display area, A rib layer formed in the display area and the peripheral area, having a pixel aperture in each of the plurality of subpixels, A first partition wall surrounds each of the plurality of subpixels, including a conductive lower portion positioned above the rib layer and an upper portion having an end protruding from the side surface of the lower portion. Each of the aforementioned sub-pixels is arranged and includes a plurality of display elements, each containing an organic layer that emits light in response to the application of a voltage, A plurality of first sealing layers formed of an inorganic insulating material, each covering the plurality of display elements, A second sealing layer formed of an inorganic insulating material and covering the plurality of first sealing layers, A dam section is arranged in the aforementioned peripheral area and surrounds the aforementioned display area, Equipped with, In at least a portion of the region between the edge of the substrate and the dam portion, the rib layer is removed. Display device.

12. The second sealing layer covers the end of the rib layer. The display device according to claim 11.

13. A resin layer covering the second sealing layer in at least the display area, A third sealing layer formed of an inorganic insulating material and covering the resin layer, Furthermore, The third sealing layer covers the end of the rib layer. The display device according to claim 11.

14. The end of the second sealing layer and the end of the third sealing layer are aligned. The display device according to claim 13.

15. The second partition wall further includes a conductive lower portion located in the area where the rib layer has been removed in the peripheral region, and an upper portion having an end protruding from the side surface of the lower portion. The display device according to any one of claims 11 to 14.

16. The second sealing layer covers the second partition wall. The display device according to claim 15.

17. A rib layer is formed on top of the substrate. It includes a conductive lower portion located above the rib layer and an upper portion having an end protruding from the side surface of the lower portion, forming a first partition wall that surrounds each of the plurality of subpixels. Each of the plurality of sub-pixels is provided with a plurality of display elements, each containing an organic layer that emits light in response to the application of a voltage, and a plurality of first sealing layers made of an inorganic insulating material that cover each of the display elements. A second sealing layer made of an inorganic insulating material is formed to cover the plurality of first sealing layers. A resin layer is formed that covers a portion of the second sealing layer. A method for manufacturing a display device, including the following.

18. A portion of the second sealing layer exposed from the resin layer is removed. A method for manufacturing a display device according to claim 17, further comprising the above.

19. Before forming the rib layer, a dam portion is formed that surrounds the display area including the plurality of subpixels. After forming the rib layer, at least a portion of the rib layer located on the outside of the dam section is removed. The substrate is cut in the region where the rib layer has been removed. A method for manufacturing a display device according to claim 17, further comprising the above.

20. A second partition wall is formed, which includes a conductive lower portion located in the region where the rib layer has been removed, and an upper portion having an end protruding from the side surface of the lower portion. A method for manufacturing a display device according to claim 19, further comprising the above.

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