Display control system and control unit

Abstract

Reduces the duration of the white streaks that appear on the LCD display unit screen when the power is forcibly turned off. [Solution] The CPU 122 detects the falling edge of the vertical synchronization signal (step S1, YES for step S1), starts the timer counting operation (step S2), determines whether a predetermined time has elapsed since the falling edge of the vertical synchronization signal (step S3), determines whether the signal level of the vertical synchronization signal is high or low (step S4), and determines that the signal level of the vertical synchronization signal is low (NO for step S4), changes the signal level of the DISP signal from high to low, outputs a DISP signal with a low signal level to the LCD 130, resets the timer count value, and stops the timer counting operation (step S6).

Description

Technical Field

[0001] The present invention relates to a display control system and a control unit, and particularly to a display control system and a control unit for switching a screen of a liquid crystal display unit between a display state and a non-display state.

Background Art

[0002] Conventionally, various techniques have been provided to solve problems occurring in the display of liquid crystal display units. For example, in Patent Document 1, in a controller that also serves as a CRT and display control, since the number of latch panels for distinguishing one scanning period differs for each frame, if LCD control is performed as it is, display abnormalities occur. As a countermeasure, within one frame period, the number of latch pulses is counted for each frame, and when the number exceeds a predetermined number, the output of the excess latch pulses is restricted to make the number of latch pulses in each frame the same, thereby avoiding display abnormalities.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, when the device enters an abnormal state such as freezing and the power of the device is forcibly turned off, in a conventional display control system that controls the display of a liquid crystal display unit, white streaks may appear on the screen of the liquid crystal display unit. This will be described below.

[0005] A conventional display control system includes a power management unit to which a power switch is connected, a first board equipped with a first control unit capable of communicating with the power management unit, a FET arranged on an electric wire between the power management unit and a liquid crystal display unit, and a second board equipped with a second control unit capable of switching between a conductive state and a non-conductive state of the FET and communicating with the first control unit. Note that the voltage supply to the second control unit, which is farther away from the power management unit, stops later than that to the first control unit, which is closer to the power management unit, and the operation stops after the first control unit.

[0006] The first control unit outputs a vertical synchronizing signal (Vertical Synchronizing Signal: VSYNC) and an image data signal to the liquid crystal display unit. The second control unit outputs a screen display control signal (DISP signal) to the liquid crystal display unit, where the screen of the liquid crystal display unit becomes a display state when the signal level is high level and becomes a non-display state when the signal level is low level.

[0007] In the case of forced power-off when an abnormality such as the device freezing occurs, if the user long-presses the power switch for 5 seconds or more in the power-on state, the power management unit detects the long-press of the power switch for 5 seconds or more and forcibly shifts the device including the display control system to the power-off state.

[0008] At this time, on the first board side such as the first control unit, the output of the image data signal from the first control unit to the liquid crystal display unit stops, and the signal level of the vertical synchronizing signal from the first control unit to the liquid crystal display unit becomes low level, and the low-level vertical synchronizing signal continues.

[0009] After the output stop of the image data signal on the first board side such as the first control unit and the signal level of the vertical synchronizing signal becoming low level and the start of the continuation of the low-level vertical synchronizing signal, on the second board side such as the second control unit, the signal level of the DISP signal from the second control unit to the liquid crystal display unit transitions from high level to low level, the low-level DISP signal continues, and the voltage supply to the liquid crystal display unit stops.

[0010] From the moment the output of the image data signal stops and the signal level of the vertical synchronization signal goes low, until the moment the signal level of the DISP signal transitions from high to low, until the moment the low-level DISP signal resumes, and until the voltage supply to the liquid crystal display unit stops, the DISP signal remains at a high level and the output of the image data signal stops. As a result, white streaks appear on the screen of the liquid crystal display unit during this period.

[0011] This invention has been made in view of the above circumstances, and aims to shorten the duration of the appearance of white streaks that appear on the screen of the liquid crystal display unit when the power is forcibly turned off. [Means for solving the problem]

[0012] A display control system according to one aspect of the present invention is a display control system for controlling the display of a liquid crystal display unit, wherein the display control system comprises a power management unit to which a power switch is connected, a first board equipped with a first control unit that is supplied with voltage from the power management unit and can communicate with the power management unit, and a second board equipped with a second control unit that is supplied with voltage from the power management unit and can communicate with the first control unit, wherein the first control unit outputs a vertical synchronization signal to the liquid crystal display unit, the second control unit outputs a screen display control signal to the liquid crystal display unit such that the screen of the liquid crystal display unit is displayed when the signal level is high and the screen of the liquid crystal display unit is not displayed when the signal level is low, the first control unit further outputs the vertical synchronization signal to the liquid crystal display unit to the second control unit, and the second control unit detects the falling edge of the vertical synchronization signal and then controls the vertical synchronization signal for one low-level period T of the vertical synchronization signal. Low A single low-level period T of the vertical synchronization signal that is longer than the above. Low and one high-level period T High The combined period T Low +T High A predetermined time T that is shorter than ThWhen the vertical synchronization signal has a low signal level after a certain period has elapsed, the signal level of the screen display control signal is set to the low level, and the screen display control signal is output to the liquid crystal display unit.

[0013] The control unit according to one aspect of the present invention is mounted on a board in the control unit, mounted on another board, and supplied with voltage from a power management unit to which a power switch is connected. The control unit is mounted on the other board, supplied with voltage from the power management unit, can communicate with the power management unit, and can communicate with another control unit that outputs a vertical synchronization signal to the liquid crystal display unit. When the signal level is high, the screen of the liquid crystal display unit is in the display state, and when the signal level is low, the screen of the liquid crystal display unit is in the non-display state. The control unit outputs a screen display control signal to the liquid crystal display unit, and the vertical synchronization signal output by the other control unit to the liquid crystal display unit is input to the control unit. The control unit detects the fall of the vertical synchronization signal and then a predetermined time T longer than one low-level period T of the vertical synchronization signal and shorter than the combined period T of one low-level period T and one high-level period T of the vertical synchronization signal. When the predetermined time T has elapsed and the signal level of the vertical synchronization signal is low, the signal level of the screen display control signal is set to the low level, and the screen display control signal is output to the liquid crystal display unit. Low longer than, and a predetermined time T shorter than the combined period T of one low-level period T and one high-level period T of the vertical synchronization signal. Low and one high-level period T High of the vertical synchronization signal, and a combined period T Low +T High When the predetermined time T has elapsed and the signal level of the vertical synchronization signal is low, the signal level of the screen display control signal is set to the low level, and the screen display control signal is output to the liquid crystal display unit. Th When the vertical synchronization signal has a low signal level after a certain period has elapsed, the signal level of the screen display control signal is set to the low level, and the screen display control signal is output to the liquid crystal display unit.

Effect of the Invention

[0014] According to the display control system of the present invention, a vertical synchronization signal is input from the first control unit to the second control unit. The second control unit detects the fall of the vertical synchronization signal and then a predetermined time T ThIf the vertical synchronization signal is at a low level after a certain period has elapsed, the screen display control signal is set to a low level to disable the LCD display unit's screen and output to the LCD display unit. In this way, by using the vertical synchronization signal to control the signal level of the screen display control signal, the second control unit can shorten the time from the falling edge of the vertical synchronization signal to the low level of the screen display control signal when the vertical synchronization signal no longer rises to a high level due to a forced power off. This shortens the duration for which white lines appear on the LCD display unit's screen when the power is forcibly turned off.

[0015] According to the control unit of the present invention, a vertical synchronization signal is input to the control unit from another control unit, and the control unit detects the falling edge of the vertical synchronization signal and then performs a predetermined time T Th If the vertical sync signal is at a low level after a certain period, the screen display control signal is set to a low level to disable the LCD display unit's screen and output to the LCD display unit. In this way, by using the vertical sync signal to control the signal level of the screen display control signal, the control unit can shorten the time from the falling edge of the vertical sync signal to the low level of the screen display control signal when the vertical sync signal no longer rises to a high level due to a forced power off. This shortens the duration for which white lines appear on the LCD display unit's screen when the power is forcibly turned off. [Brief explanation of the drawing]

[0016] [Figure 1] This is a system configuration diagram of a display control system according to one embodiment of the present invention. [Figure 2] Figure 1 is a flowchart showing the processing steps performed by the CPU mounted on the panel board. [Figure 3] This figure shows the timing charts for the vertical synchronization signal, image data signal, and DISP signal in the display control system shown in Figure 1. [Figure 4] This is a system configuration diagram of the display control system in the comparative example. [Figure 5]This figure shows the sequence of screen blackouts for the LCD using the display control system of the comparative example shown in Figure 4, when the power is normally turned off. [Figure 6] This figure shows the sequence of screen blackouts for the LCD when the display control system of the comparative example in Figure 4 is forcibly powered off. [Figure 7] Figure 6 shows an example of white streaks that appear on the LCD screen during the screen-off sequence when the power is forcibly turned off. [Modes for carrying out the invention]

[0017] The following describes a display control system according to one embodiment of the present invention, with reference to the drawings.

[0018] First, the system configuration of the display control system 100 according to one embodiment of the present invention will be described with reference to Figure 1. Figure 1 is a system configuration diagram of the display control system 100 according to one embodiment of the present invention.

[0019] The display control system 100 controls the display of the LCD (Liquid Crystal Display) 130 and comprises a main board 110 equipped with a PMIC (Power Management Integrated Circuit) 111 and a CPU (Central Processing Unit) 112, and a panel board 120 equipped with an FET (Field Effect Transistor) 121 and a CPU 122.

[0020] The PMIC111 is connected to a power switch (PSW). The PMIC111 is an IC that manages power, such as converting a 24V voltage to a 3.3V voltage (3.3V1_C). When the user turns on the power using the power switch (PSW), the PMIC111 supplies a 3.3V voltage (3.3V1_C) to the CPU112, CPU122, FET121, etc. When the user turns off the power using the power switch (PSW), for example, by pressing the power switch (PSW) for less than 5 seconds (5 seconds is just an example and is not limited to this) (normal power off operation), or by pressing the power switch (PSW) for 5 seconds (5 seconds is just an example and is not limited to this) or longer (forced power off operation)), the voltage (3.3V1_C) becomes 0V, and the PMIC111 stops supplying voltage to the CPU112, CPU122, FET121, etc. Furthermore, CPU122, which is further away from PMIC111, will lose voltage later than CPU112, which is closer to PMIC111, and will therefore stop operating later than CPU112.

[0021] CPU112 is constructed, for example, by an ASIC (Application Specific Integrated Circuit), and receives voltage (3.3V 1C) from PMIC111. CPU112 can communicate with PMIC111 and can communicate with CPU122 mounted on panel board 120.

[0022] FET121 is placed in the wire between PMIC111 and LCD130 and is switched between a conductive state and a non-conductive state by CPU122. Note that FET121 is just one example of a switching circuit, and the switching circuit placed in the wire between PMIC111 and LCD130 may be a switching circuit other than an FET.

[0023] The CPU 122 is supplied with voltage (3.3V1_C) from the PMIC 111. The CPU 122 can communicate with the CPU 112 mounted on the main board 110. The CPU 122 switches the FET 121 between a conductive state and a non-conductive state. For example, the CPU 122 controls the FET 121 to be conductive when the power is turned on and to be non-conductive when the power is turned off. The voltage supplied to the LCD 130 (3.3V1_REC) is 3.3V when the FET 121 is controlled to be conductive by the CPU 122, and 0V when the FET 121 is controlled to be non-conductive by the CPU 122.

[0024] The CPU 112 outputs a vertical synchronization signal to the LCD 130 and CPU 122. The vertical synchronization signal is a signal that indicates the timing for starting the scanning of one screen (one frame). When the power is on, the CPU 112 outputs a vertical synchronization signal (VSYNC) to the LCD 130 and CPU 122 that alternates between a high level (greater than 0(V), for example, 2(V)) and a low level (0(V)). In the case of a normal power off by pressing the power switch PSW for less than 5 seconds, the CPU 112 receives an off-mode transition instruction signal from the PSW 111, which is output by the PMIC 111 when it detects that the power switch PSW has been pressed for less than 5 seconds, and sets the vertical synchronization signal to a low level, continuing to output the low-level vertical synchronization signal to the LCD 130 and CPU 122. In the case of a forced power off by pressing and holding the power switch PSW for 5 seconds or more, the CPU 112 will stop operating because voltage will no longer be supplied to it from PSW111. As a result, the vertical synchronization signal will go to a low level, and a low-level vertical synchronization signal will continue to be input to the LCD130 and CPU122.

[0025] Furthermore, the CPU 112 outputs image data signals of the images to be displayed on the LCD 130 screen, which are stored in memory (not shown), to the LCD 130. The image data signals have two signal levels: high level (greater than 0(V), for example, 2(V): image data value "1") and low level (0(V): image data value "0").

[0026] The CPU 122 outputs a screen display control signal (DISP signal) to the LCD 130. The DISP signal is used to switch the LCD 130's screen between a display state and a non-display state. When the signal level is high (greater than 0(V), for example, 2(V)), the LCD 130's screen is displayed, and when the signal level is low (0(V)), the LCD 130's screen is non-displayed. When the DISP signal is high, the LCD 130 displays an image on the screen based on the image data signal. When the DISP signal is low, the LCD 130 clears the display data so that no image is displayed on the screen, thus turning the screen non-displayed. Alternatively, when the DISP signal level is high, the LCD 130 displays an image on the LCD 130's screen by operating the drive circuits that drive each part of the LCD 130. On the other hand, when the signal level of the DISP signal is low, the LCD130 stops the drive circuits that drive each part of the LCD130, thereby preventing an image from being displayed on the LCD130 screen. The CPU122 transitions the signal level of the DISP signal from low to high during startup, etc. In the case of a normal power off by pressing the power switch PSW for less than 5 seconds, the CPU122 receives an off-mode transition instruction signal from the CPU112, which is output by the CPU112 after it receives an off-mode transition instruction signal from the PMIC111, and transitions the signal level of the DISP signal from high to low, and continues to output a DISP signal with a low signal level to the LCD130. In the case of a forced power off by pressing and holding the power switch PSW for 5 seconds or more, the CPU122 controls the signal level of the DISP signal as follows and outputs the DISP signal to the LCD130. Th This is a single low-level period T of the vertical synchronization signal. Low (See Figure 3) Longer than the single low-level period T of the vertical synchronization signal. Low (See Figure 3) and one high-level period T High (See Figure 3) The combined period T Low +T HighIt is shorter than this. Therefore, when the signal level of the vertical synchronization signal is repeatedly switching between high and low levels, a predetermined time T occurs after the signal level of the vertical synchronization signal transitions from high to low. Th At the time that has elapsed, the signal level of the vertical synchronization signal is high. On the other hand, in the case of a forced power off, the signal level of the vertical synchronization signal input to the CPU 122 will remain low, and a predetermined time T will be required after the vertical synchronization signal level transitions from high to low. Th At the point when this time has elapsed, the signal level of the vertical synchronization signal is low.

[0027] CPU122 detects the falling edge of the vertical synchronization signal and then processes the vertical synchronization signal for one low-level period T. Low (See Figure 3) Longer than the single low-level period T of the vertical synchronization signal. Low (See Figure 3) and one high-level period T High (See Figure 3) The combined period T Low +T High A predetermined time T that is shorter than Th When the time has elapsed, if the signal level of the vertical synchronization signal is low, the signal level of the DISP signal is set to low, and the DISP signal is output to the LCD130.

[0028] High-level period T High This is the low-level period T. Low Longer than a predetermined time T Th is within the above range (low-level period T) Low Longer than, period T Low +T High Within a range shorter than the above, the low-level period T Low It may also be considered to be more than twice that amount of time.

[0029] High-level period T High This is the low-level period T. Low Longer than a predetermined time T Th This is the low-level period T. Low It may also be assumed to be twice the time.

[0030] In this embodiment, the high-level period T High This is the low-level period T. Low Longer than (T High >T Low ), Low-level period T Low When = 2 (μs), a predetermined time T Th This is the low-level period T. Low Twice the time (T Low Let's assume that ×2 = 4 (μs).

[0031] The LCD130 displays the screen when the DISP signal level is high, and displays an image on the screen based on the image data signal while maintaining vertical synchronization with the vertical synchronization signal. On the other hand, the LCD130 turns off the screen when the DISP signal level is low. The frame rate of the LCD130 is 60Hz or 120Hz, and the high-level period of the vertical synchronization signal T High and low-level period T Low The combined period T High +T Low In the former case, it is approximately 0.017 ms, and in the latter case, it is approximately 0.008 ms.

[0032] Next, we will explain the sequence for turning off the LCD 130 screen during normal power-off by the display control system 100, whose system configuration is shown in Figure 1 (the sequence for switching the LCD 130 screen from the displayed state to the hidden state).

[0033] When the power is on, PMIC111 detects that the power switch PSW has been pressed for less than 5 seconds and outputs an off-mode transition instruction signal to CPU112. When CPU112 receives the off-mode transition instruction signal from PMIC111, it outputs the off-mode transition instruction signal to CPU122. When CPU112 receives the off-mode transition instruction signal from PMIC111, it stops outputting the image data signal to LCD130. As a result, the signal level of the image data signal from CPU112 to LCD130 remains low, with no image data. When CPU122 receives the off-mode transition instruction signal from CPU112, it transitions the signal level of the DISP signal from high to low, and continues to output the low-level DISP signal to LCD130. CPU112 sets the signal level of the vertical synchronization signal to low, and continues to output the low-level vertical synchronization signal to LCD130. CPU122 controls FET121 to a non-conductive state. As a result, the voltage (3.3V1_REC) becomes 0 (V), and no voltage is supplied to the LCD130. In the normal power-off sequence for the LCD130 screen, the DISP signal is maintained at a low level before the vertical sync signal is maintained at a low level, so no white streaks appear on the LCD130 screen.

[0034] Next, the processing performed by the CPU 122 in Figure 1 will be explained with reference to Figure 2. Figure 2 is a flowchart showing the processing procedure of the CPU 122 in Figure 1. However, the flowchart shown in Figure 2 shows the processing procedure of the CPU 122 after the user presses the power switch PSW while the power is off and each part of the device equipped with the display control system 100 is started up. When the signal level of the vertical synchronization signal is repeatedly high and low, a predetermined time T occurs after the signal level of the vertical synchronization signal transitions from high to low. Th At the point when T has elapsed, the signal level of the vertical synchronization signal is high. On the other hand, in the case of a forced power off, the signal level of the vertical synchronization signal input to CPU122 will remain low for a predetermined time T ThAt the point when the time has elapsed, the signal level of the vertical synchronization signal is low. The CPU 122 executes the processing procedure shown in the flowchart of Figure 2 by reading a program containing the processing procedure shown in the flowchart of Figure 2, which is stored in memory (not shown), from that memory and executing it. The processing procedure shown in the flowchart of Figure 2 may also be implemented in hardware.

[0035] The CPU 122 determines whether or not it has detected a falling edge of the vertical synchronization signal from a high level to a low level (step S1). If the CPU 122 determines that it has not detected a falling edge of the vertical synchronization signal (S1:NO), the process in step S1 is repeated.

[0036] On the other hand, if the CPU 122 determines that it has detected the falling edge of the vertical synchronization signal (S1:YES), the CPU 122 starts the counting operation of its built-in timer (step S2). The timer counts up, for example, with the reciprocal of the clock frequency as one count time. Note that the timer may be one other than the one built into the CPU 122.

[0037] CPU122, based on the timer count value, determines a predetermined time T from the falling edge of the vertical synchronization signal. Th It is determined whether the time has elapsed (step S3). The CPU 122 determines whether the time T has elapsed since the falling edge of the vertical synchronization signal. Th If it is determined that time T has not elapsed (S3:NO), the process in step S3 is repeated. However, if a predetermined time T is not met, Th As stated above, for example, the time obtained by multiplying the timer's 1-count time by the timer's count value is the elapsed time from the falling edge of the vertical synchronization signal.

[0038] CPU122 starts from the falling edge of the vertical synchronization signal for a predetermined time T Th If it is determined that the time has elapsed (S3:YES), the CPU 122 determines whether the signal level of the vertical synchronization signal is high or not (step S4).

[0039] If the CPU 122 determines that the signal level of the vertical synchronization signal is high (S4: YES), the CPU 122 resets the count value of the built-in timer and stops the timer's counting operation (step S5).

[0040] If CPU122 determines that the signal level of the vertical synchronization signal is not high (S4:NO), that is, if the signal level of the vertical synchronization signal is low, CPU122 changes the signal level of the DISP signal from high to low, resets the count value of the built-in timer, and stops the timer's counting operation (step S6). After that, the power to CPU122 is turned off.

[0041] Next, the processing of the display control system 100 in Figure 1 will be explained with reference to Figure 3. Figure 3 is a timing chart of the vertical synchronization signal, image data signal, and DISP signal in the display control system 100 in Figure 1.

[0042] In the dotted lines A1 and A2, where the power is on, the CPUs 112 and 122 of the display control system 100 perform the following processing.

[0043] CPU 112 outputs a vertical synchronization signal whose signal level alternates between high and low, and outputs an image data signal with image data. CPU 122 detects the falling edge of the vertical synchronization signal (step S1, YES in step S1) and starts the counting operation of its built-in timer (step S2). CPU 122 starts counting for a predetermined time T from the falling edge of the vertical synchronization signal. Th The CPU 122 determines whether the time has elapsed (step S3), and if it determines that the time has elapsed (YES in step S3), it determines whether the signal level of the vertical synchronization signal is high or low (step S4). The CPU 122 determines that the signal level of the vertical synchronization signal is high or low (YES in step S4), resets the count value of the built-in timer, and stops the timer's counting operation (step S5).

[0044] At the dotted line A3 where a forced power off occurs, the CPUs 112 and 122 of the display control system 100 perform the following processing.

[0045] Due to the forced power off, the signal level of the vertical synchronization signal input to CPU122 remains at a low level for a predetermined time T. Th At the point when the vertical synchronization signal has elapsed, the signal level of the vertical synchronization signal is low. Also, the image data signal becomes an image data signal without image data. The CPU 122 detects the falling edge of the vertical synchronization signal (step S1, YES for step S1) and starts the counting operation of the built-in timer (step S2). The CPU 122 starts the counting operation of the built-in timer from the falling edge of the vertical synchronization signal for a predetermined time T Th The CPU 122 determines whether the time has elapsed (step S3), and if it determines that the time has elapsed (YES in step S3), it determines whether the signal level of the vertical synchronization signal is high or low (step S4). The CPU 122 determines that the signal level of the vertical synchronization signal is low (NO in step S4), and the CPU 122 transitions the signal level of the DISP signal from high to low, outputs the low-level DISP signal to the LCD 130, resets the count value of the built-in timer, and stops the timer's counting operation (step S6).

[0046] The display control system 100C, which is compared with the display control system 100 of this embodiment, will be described below with reference to Figures 4 to 7.

[0047] Figure 4 is a system configuration diagram of the comparative example display control system 100C. The display control system 100C controls the display of the LCD 130 and comprises a main board 110C equipped with a PMIC 111 connected to a power switch PSW and a CPU 112C, and a panel board 120C equipped with an FET 121 and a CPU 122C.

[0048] The comparative example PMIC111 operates in the same manner as the PMIC111 of this embodiment. Similarly, the comparative example LCD130 operates in the same manner as the LCD130 of this embodiment.

[0049] CPU112C receives voltage (3.3V1_C) from PMIC111. CPU112C can communicate with PMIC111 and can communicate with CPU122C mounted on panel board 120C.

[0050] The CPU122C is supplied with voltage (3.3V1_C) from the PMIC111. The CPU122C can communicate with the CPU112C mounted on the main board 110C. The CPU122C switches the FET121, which is located in the wire between the PMIC111 and the LCD130, between a conductive state and a non-conductive state. The voltage supplied to the LCD130 (3.3V1_REC) becomes 3.3V when the FET121 is controlled to be conductive by the CPU122C, and becomes 0V when the FET121 is controlled to be non-conductive by the CPU122C.

[0051] The CPU112C outputs vertical synchronization signals and image data signals to the LCD130. When the power is on, the CPU112C outputs a vertical synchronization signal to the LCD130 that alternates between high and low levels as a signal level. In the case of a normal power off by pressing the power switch PSW for less than 5 seconds, the CPU112C receives an off-mode transition instruction signal from PSW111, lowers the vertical synchronization signal to a low level, and continues to output a low-level vertical synchronization signal to the LCD130. In the case of a forced power off by pressing and holding the power switch PSW for 5 seconds or more, the CPU112C stops operating because voltage is no longer supplied to it from PSW111. As a result, the vertical synchronization signal becomes low, and a low-level vertical synchronization signal is continuously input to the LCD130.

[0052] The CPU122C outputs a display control signal (DISP signal) to the LCD130. The CPU122C transitions the signal level of the DISP signal from low to high during startup, etc. In the case of a normal power off by pressing the power switch PSW for less than 5 seconds, the CPU122C receives an off-mode transition instruction signal from the CPU112C and transitions the DISP signal from high to low, continuously outputting a low-level DISP signal to the LCD130. In the case of a forced power off by pressing and holding the power switch PSW for 5 seconds or more, the operation of the CPU122C stops because voltage is no longer supplied to the CPU122C, causing the DISP signal to become low, and a low-level DISP signal is continuously input to the LCD130.

[0053] Unlike the display control system 100 of this embodiment, the comparative example display control system 100C is not configured such that the vertical synchronization signal output by the CPU 112C is input to the CPU 122C.

[0054] Next, we will explain the screen-off sequence of the LCD 130 during normal power-off using the comparative example display control system 100C, whose system configuration is shown in Figure 4 (the sequence for switching the LCD 130 screen from the displayed state to the hidden state), with reference to Figure 5. Figure 5 is a diagram illustrating the screen-off sequence of the LCD 130 during normal power-off using the comparative example display control system shown in Figure 4.

[0055] In a normal power-off state, the PMIC111 detects when the power switch PSW is pressed for less than 5 seconds while the power is on and outputs an off-mode transition instruction signal to the CPU112C. When the CPU112C receives the off-mode transition instruction signal from the PMIC111, it outputs an off-mode transition instruction signal to the CPU122C.

[0056] The screen-off sequence for LCD130 at this time is as shown in Figure 5, and the processes are carried out in the following order: (1), (2), (3), (4).

[0057] (1) When the CPU112C receives an off-mode transition instruction signal from the PMIC111, it stops outputting image data signals to the LCD130. As a result, the signal level of the image data signal from the CPU112C to the LCD130 remains low, indicating no image data. (2) The CPU122C transitions the signal level of the DISP signal from a high level to a low level, and continues to output the DISP signal with a low signal level to the LCD130. (3) The CPU112C lowers the signal level of the vertical synchronization signal and continues to output the low-level vertical synchronization signal to the LCD130. (4) The CPU 122 controls the FET 121 to a non-conductive state. As a result, the voltage (3.3V1_REC) becomes 0 (V), and no voltage is supplied to the LCD 130.

[0058] In the normal power-off sequence for the LCD130 screen described above, the DISP signal is maintained at a low level before the vertical sync signal is maintained at a low level, so no white streaks appear on the LCD130 screen.

[0059] Next, we will explain the sequence of screen blackout for the LCD 130 when the display control system 100C of the comparative example, whose system configuration is shown in Figure 4, is forcibly powered off in the event of an abnormality such as the device freezing, with reference to Figure 6. Figure 6 is a diagram illustrating the sequence of screen blackout for the LCD 130 when the display control system of the comparative example in Figure 4 is forcibly powered off.

[0060] In the case of a forced power off, the PMIC111 detects that the power switch PSW has been pressed for 5 seconds or more. However, unlike in the case of a normal power off, the PMIC111 does not output the above-mentioned off-mode transition instruction signal to the CPU112C, nor does the CPU122C receive the off-mode transition instruction signal from the CPU112C. For this reason, the screen off sequence of the LCD130 in the case of a forced power off is different from the screen off sequence of the LCD130 shown in Figure 5 in the case of a normal power off, and is the screen off sequence of the LCD130 shown in Figure 6 below, in the order of (1) and (2) below. In addition, the display control system 100C of the comparative example differs from the display control system 100 of this embodiment in that the vertical synchronization signal output by the CPU112C is not input to the CPU122C. For this reason, the CPU122C cannot execute the processing procedure shown in the flowchart of Figure 2.

[0061] (1) On the main board 110 side, such as the CPU112C, the output of image data signals from the CPU112C to the LCD130 stops, and the signal level of the vertical synchronization signal from the CPU112C to the LCD130 becomes low, and the low-level vertical synchronization signal continues.

[0062] (2) On the panel board 120 side, such as the CPU 122C, the signal level of the DISP signal from the CPU 122C to the LCD 130 transitions from a high level to a low level, and the low-level DISP signal continues while voltage is no longer supplied to the LCD 130.

[0063] In the LCD130 screen blackout sequence during the forced power-off described above, from the moment the image data signal output stops and the vertical synchronization signal goes low and the low-level vertical synchronization signal begins to continue, until the DISP signal level transitions from high to low and the low-level DISP signal begins to continue, and the voltage supply to the LCD130 stops (for example, 0.1 seconds), the DISP signal remains high and the image data signal output stops. As a result, during this period, white streaks appear on the LCD130 screen, as shown in Figure 7 as an example.

[0064] According to the embodiment described above, the CPU 122 receives a vertical synchronization signal from the CPU 112, and the CPU 122 detects the falling edge of the vertical synchronization signal and then performs a predetermined time T Th If the vertical sync signal is at a low level when the time has elapsed, the DISP signal is set to a low level to turn off the LCD130 screen and output to the LCD130. In this way, by using the vertical sync signal to control the signal level of the DISP signal, the CPU122 can shorten the time from the falling edge of the vertical sync signal to the low level of the DISP signal when the vertical sync signal no longer rises to a high level due to a forced power off. This shortens the duration for which white lines appear on the LCD130 screen when the power is forcibly turned off.

[0065] Furthermore, by adding one port to the CPU122 without adding any new configuration units, it is possible to shorten the duration for which white lines appear on the LCD130 screen during a forced power off by adding another unit during a forced power off.

[0066] Also, a predetermined time T Th to T Low By setting it to ×2 or more, the determination process in step S4 (determining whether the signal level of the vertical synchronization signal is high) when the vertical synchronization signal is repeatedly switching between low and high levels can be reliably performed at the timing of the high level following the low level where the falling edge was detected, even if there is a time lag in the transition timing from low level to high level of the vertical synchronization signal by the CPU 112.

[0067] Also, a predetermined time T Th to T Low By multiplying by 2, the duration for which white lines appear on the LCD130 screen when the power is forcibly turned off can be significantly reduced.

[0068] It should be noted that the present invention is not limited to the configurations of the above embodiments, and various modifications are possible. Furthermore, the configurations and processes shown in the above embodiments using Figures 1 to 3 are merely one embodiment of the present invention, and the present invention is not intended to be limited to these configurations and processes. [Explanation of symbols]

[0069] 100 Display Control System 110 Mainboard 111 PMIC (power management IC) 112 CPU 120 Panel Board 121 FET 122 CPU 130 LCD

Claims

1. In a display control system that controls the display of a liquid crystal display unit, The aforementioned display control system is A power management unit to which a power switch is connected, and a first board equipped with a first control unit that receives voltage from the power management unit and is capable of communicating with the power management unit, A second board is equipped with a second control unit that receives voltage from the power management unit and is capable of communicating with the first control unit, Equipped with, The first control unit is, The vertical synchronization signal is output to the LCD display unit. The second control unit outputs a screen display control signal to the liquid crystal display unit such that when the signal level is high, the screen of the liquid crystal display unit is displayed, and when the signal level is low, the screen of the liquid crystal display unit is turned off. The first control unit further outputs the vertical synchronization signal to be output to the liquid crystal display unit to the second control unit. The second control unit is, After detecting the falling edge of the vertical synchronization signal, one low-level period T of the vertical synchronization signal occurs. Ｌｏｗ A single low-level period T of the vertical synchronization signal that is longer than the above. Ｌｏｗ and one high-level period T Ｈｉｇｈ The combined period T Ｌｏｗ +T Ｈｉｇｈ A predetermined time T that is shorter than Ｔｈ When the time has elapsed, if the signal level of the vertical synchronization signal is low, the signal level of the screen display control signal is set to low, and the screen display control signal is output to the liquid crystal display unit. Display control system.

2. The aforementioned high-level period T Ｈｉｇｈ The low-level period T Ｌｏｗ Longer than, the predetermined time T Ｔｈ is a time that is at least twice the low-level period T Ｌｏｗ ​ The display control system according to claim 1.

3. The predetermined time T Ｔｈ This is the low-level period T. Ｌｏｗ It is twice the time. The display control system according to claim 2.

4. In the control unit, The control unit is It is mounted on the board, Voltage is supplied from a power management unit mounted on a separate board, to which a power switch is connected. It is mounted on the aforementioned separate board, receives voltage from the power management unit, is capable of communicating with the power management unit, and is capable of communicating with another control unit that outputs a vertical synchronization signal to the liquid crystal display unit. A screen display control signal is output to the liquid crystal display unit such that when the signal level is high, the screen of the liquid crystal display unit is displayed, and when the signal level is low, the screen of the liquid crystal display unit is turned off. The control unit receives the vertical synchronization signal that the other control unit outputs to the liquid crystal display unit. The control unit is After detecting the falling edge of the vertical synchronization signal, one low-level period T of the vertical synchronization signal occurs. Ｌｏｗ A single low-level period T of the vertical synchronization signal that is longer than the above. Ｌｏｗ and one high-level period T Ｈｉｇｈ The combined period T Ｌｏｗ +T Ｈｉｇｈ A predetermined time T that is shorter than Ｔｈ When the time has elapsed, if the signal level of the vertical synchronization signal is low, the signal level of the screen display control signal is set to low, and the screen display control signal is output to the liquid crystal display unit. Control unit.

Images