Error correction method and error correction circuit

Abstract

This invention provides an error correction method and error correction circuit for digital coherent optical transmission systems that suppress increases in circuit size and power consumption, even when the code length is large. [Solution] The error correction method of the present invention is a method that performs error correction multiple times, and in some error corrections, only the latter half of the code is targeted for correction. For the bits in the latter half of the code, error correction is performed using the LLR (log-likelihood ratio) input from the preceding circuit, and for the bits in the first half of the code, error correction is performed using the fixed maximum value that the LLR can take.

Description

Technical Field

[0001] The present invention relates to an error correction method and an error correction circuit for a digital coherent optical transmission system.

Background Art

[0002] Error correction is a technique in which, in order to correct bit errors occurring in a transmission line, an error correction code (parity bit) is added to a code (information bit) transmitted on the transmission side and then transmitted, and the received error correction code (parity bit) is used on the reception side to correct the error of the received code (information bit). For further increasing the capacity and speed of optical communication, long-distance transmission of signals exceeding 100 Gbps is required, and the use of the digital coherent optical transmission method is expected. In the transmission of signals exceeding 100 Gbps, the influence of transmission line noise becomes large, so advanced error correction is required. In digital coherent optical transmission, in addition to the conventional hard decision, high error correction capabilities are realized by soft decision and iterative decoding (see Patent Document 1).

[0003] When performing error correction processing on the reception side, LLR (Log-Likelihood Ratio) is used as soft decision information that is input to the error correction decoding circuit. This LLR is a value derived from the coordinate deviation of the received symbol, and is obtained from the ratio of the probability that the transmission signal is 0 and the probability that it is 1. The absolute value of the LLR indicates the certainty of the 1 / 0 determination result of the received code.

[0004] In conventional error correction techniques, since the holding of LLR for the code length is required for error correction processing, there is a problem that the circuit scale and power consumption increase in error correction processing with a large code length.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] The present invention was made to solve the above problems, and aims to provide an error correction method and an error correction circuit that can reduce power consumption in error correction processing with a large code length. [Means for solving the problem]

[0007] The error correction method of the present invention is characterized in that, in the error correction process of a digital coherent optical transmission system, multiple error corrections are performed, and in some error corrections, only the latter half of the code is targeted for correction. Furthermore, one example configuration of the error correction method of the present invention includes a first step of calculating the LLR for each bit of the code to be error corrected, and a second step of performing error correction processing using the LLR, updating the LLR based on the error correction determination result, and outputting it to the subsequent circuit, wherein in a part of the second step which is performed multiple times, error correction is performed on the latter half of the code using the LLR input from the preceding circuit, and error correction is performed on the first half of the code using a fixed maximum value that the LLR can take. Furthermore, one example configuration of the error correction method of the present invention is characterized in that, after processing the first step, the processing of the second step is performed multiple times, and the second step includes the step of performing error correction using the LLR input from the preceding circuit only for the latter half of the bits if the desired error correction performance can be obtained, and performing error correction on the first half of the bits using the fixed maximum value that the LLR can take if the desired error correction performance cannot be obtained, and performing error correction using the LLR input from the preceding circuit for all bits if the desired error correction performance cannot be obtained.

[0008] Furthermore, the error correction circuit of the present invention is characterized in that, in the error correction process of a digital coherent optical transmission system, it performs multiple error corrections, and in some error corrections, only the latter half of the code is targeted for correction. Furthermore, one example of the error correction circuit of the present invention is characterized by further comprising a soft decision circuit that calculates the LLR for each bit of the code from the coordinate shift of the received symbol and outputs it to a subsequent circuit. Furthermore, one example of the error correction circuit of the present invention comprises a plurality of soft-decision decoding circuits that perform error correction processing using the LLR and update the LLR based on the result, wherein, when the desired error correction performance can be obtained, the soft-decision decoding circuit performs error correction only on the latter half of the codeword consisting of multiple bits using the LLR input from the preceding circuit, and performs error correction on the first half of the codeword using the fixed highest value that the LLR can take, and when the desired error correction performance cannot be obtained, it performs error correction on all bits using the LLR output from the preceding circuit.

[0009] Furthermore, one example of the error correction circuit of the present invention is characterized in that, among the multiple stages of the soft-decision decoding circuit, error correction is performed only in the final stage soft-decision decoding circuit, with the LLR of the first half bits set to the maximum value, while in the other soft-decision decoding circuits, error correction is performed for all bits using the LLR output from the preceding circuit. Furthermore, one example of the error correction circuit of the present invention is characterized in that, in all of the multiple stages of the soft-decision decoding circuit, error correction is performed with the LLR of the first half bits set to the maximum value, and error correction of the second half bits is performed using the LLR output from the preceding circuit. Furthermore, one example of the error correction circuit of the present invention is characterized in that, in some of the multiple stages of the soft-decision decoding circuit, error correction is performed with the LLR of the first half bits set to the maximum value, error correction of the second half bits is performed using the LLR output from the preceding circuit, and in the other soft-decision decoding circuits, error correction is performed for all bits using the LLR output from the preceding circuit. [Effects of the Invention]

[0010] According to the present invention, in the error correction process of a digital coherent optical transmission system, by performing multiple error corrections and correcting only the latter half of the code in some error corrections, it is possible to suppress increases in circuit size and power consumption. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a block diagram showing the configuration of the transmitting device of a digital coherent optical transmission system according to an embodiment of the present invention. [Figure 2] Figure 2 is a block diagram showing the configuration of the receiving device of a digital coherent optical transmission system according to an embodiment of the present invention. [Figure 3] Figure 3 is a block diagram showing the configuration of a soft judgment circuit and an error correction decoding circuit according to an embodiment of the present invention. [Figure 4] Figure 4 is a flowchart illustrating the operation of the soft judgment circuit and error correction decoding circuit according to an embodiment of the present invention. [Figure 5] Figure 5 illustrates the overall code arrangement and the placement of each code in oFEC. [Figure 6] Figure 6 illustrates the sign overlap in oFEC. [Figure 7] Figure 7 illustrates the sign overlap in oFEC. [Modes for carrying out the invention]

[0012] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Figure 1 is a block diagram showing the configuration of a transmitting device in a digital coherent optical transmission system according to an embodiment of the present invention. Figure 2 is a block diagram showing the configuration of a receiving device in a digital coherent optical transmission system according to an embodiment of the present invention. The transmitting device 1 encodes and modulates the transmission data to generate a transmission signal. The transmission signal is received by the receiving device via a wired or wireless transmission path. The receiving device demodulates and decodes the received signal to generate received data.

[0013] The transmission device 1 includes an error correction encoding circuit 10, a symbol mapping circuit 11, a modulation circuit 12, and a DA conversion circuit 13. The error correction encoding circuit 10 generates encoded data by performing, for example, BCH (Bose-Chaudhuri-Hocquenghem) encoding or LDPC (Low Density Parity Check) encoding on the transmission data.

[0014] The symbol mapping circuit 11 performs carrier modulation by assigning the encoded data output from the error correction encoding circuit 10 to symbol points such as QPSK (Quadrature Phase Shift Keying) or 16QAM (Quadrature Amplitude Modulation). The modulation circuit 12 generates a modulated signal by performing, for example, OFDM (Orthogonal Frequency Division Multiplexing) modulation on the data carrier-modulated by the symbol mapping circuit 11.

[0015] The DA conversion circuit 13 converts the modulated signal from a digital signal to an analog signal to generate a transmission signal. The transmission signal is converted into an optical signal by an optical transmission module (not shown) and sent out through an optical fiber transmission line.

[0016] The receiving device 2 includes an AD conversion circuit 20, a demodulation circuit 21, a symbol demapping circuit 22, a soft decision circuit 23, and an error correction decoding circuit 24.

[0017] An optical receiving module (not shown) of the receiving device 2 converts the optical signal received from the optical fiber transmission line into an analog received signal. The AD conversion circuit 20 converts the analog received signal into a digital signal. The demodulation circuit 21 performs a demodulation process corresponding to the OFDM modulation or the like performed on the transmission device 1 side on the signal output from the AD conversion circuit 20 and outputs the demodulated received signal to the symbol demapping circuit 22.

[0018] The symbol demapping circuit 22 outputs a bit sequence corresponding to the ideal signal point closest to the received signal (received symbol) based on hard judgment from the received signal output from the demodulation circuit 21. The soft decision circuit 23 calculates and outputs the LLR (log-likelihood ratio) for each bit based on the coordinate shift of the received symbol. The error correction decoding circuit 24 performs error correction on the bit sequence output from the soft decision circuit 23 based on the bitwise LLR (log-likelihood ratio) generated by the soft decision circuit 23.

[0019] Figure 3 is a block diagram showing the configuration of the soft decision circuit 23 and the error correction decoding circuit 24 of this embodiment. The error correction decoding circuit 24 consists of a plurality of cascaded soft decision decoding circuits (SD-DEC: Soft Decision Decoder) 240-1 to 240-k (where k is an integer of 2 or more).

[0020] The soft-decision decoding circuits 240-1 to 240-k include error correction units 241-1 to 241-k that perform error correction processing based on the LLR calculated or updated in the preceding circuit. Furthermore, the soft-decision decoding circuits 240-1 to 240-(k-1) include LLR update units 242-1 to 242-(k-1) that update the LLR (log-likelihood ratio) based on the results of the error correction processing.

[0021] The configuration shown in Figure 3 is an example of a configuration that includes a soft decision circuit 23 and k stages of soft decision decoding circuits 240-1 to 240-k. The number of stages of the soft decision decoding circuits 240-1 to 240-k is not limited, and any number of soft decision decoding circuits can be provided depending on the required error tolerance. Although not shown in Figure 3, a hard decision decoding unit (HD-DEC) may be provided after the soft decision decoding circuit 240-k.

[0022] Figure 4 is a flowchart illustrating the operation of the soft decision circuit 23 and the error correction decoding circuit 24 in this embodiment. The soft decision circuit 23 calculates the LLR (log-likelihood ratio), which indicates the bitwise probability of the data (symbols) output from the symbol demapping circuit 22 (Figure 4, step S100). A method for calculating the LLR (log-likelihood ratio) is disclosed, for example, in Patent Document 1.

[0023] The first stage soft-decision decoding circuit 240-1 uses the LLR (log-likelihood ratio) supplied from the soft-decision circuit 23 to perform error correction processing on the bit sequence output from the soft-decision circuit 23 and update the LLR (Figure 4, steps S101, S102). The soft-decision decoding circuit 240-1 outputs the error-corrected bit sequence and the updated LLR.

[0024] The second stage soft-decision decoding circuit 240-2 uses the LLR (log-likelihood ratio) supplied from the soft-decision decoding circuit 240-1 to perform error correction processing on the bit sequence output from the soft-decision decoding circuit 240-1 and update the LLR (Figure 4, steps S103, S104). The soft-decision decoding circuit 240-2 outputs the error-corrected bit sequence and the updated LLR.

[0025] The third stage soft-decision decoding circuit 240-3 uses the LLR (log-likelihood ratio) supplied from the soft-decision decoding circuit 240-2 to perform error correction processing on the bit sequence output from the soft-decision decoding circuit 240-2 and update the LLR (Figure 4, steps S105, S106). The soft-decision decoding circuit 240-3 outputs the error-corrected bit sequence and the updated LLR.

[0026] The (k-1)th stage soft-decision decoding circuit 240-(k-1) uses the LLR (log-likelihood ratio) supplied from the soft-decision decoding circuit 240-(k-2) to perform error correction processing on the bit sequence output from the soft-decision decoding circuit 240-(k-2) and update the LLR (Figure 4, steps S107, S108). The soft-decision decoding circuit 240-(k-1) outputs the error-corrected bit sequence and the updated LLR.

[0027] The k-th stage soft-decision decoding circuit 240-k uses the LLR (log-likelihood ratio) supplied from the soft-decision decoding circuit 240-(k-1) to perform error correction on the bit sequence output from the soft-decision decoding circuit 240-(k-1) (Figure 4, step S109). The soft-decision decoding circuit 240-k outputs the bit sequence after error correction. In some of the 2nd to kth soft-decision decoding circuits 240-2 to 240-k, error correction is performed by maximizing the LLR of the first half of the bits.

[0028] Figure 5 shows the overall code array and the placement of each code in oFEC. Each code consists of 256 bits (16 bits x 16), and all 256 bits constituting a single code undergo error correction simultaneously. Of the 256 bits that make up a single code, the first 128 bits are arranged in vertical columns of 16 bits each within a 16x16 block. The 16x16 blocks in which the first 128 bits are arranged are shifted by 16 columns every 16 rows. Of the 256 bits that make up a single code, the latter 128 bits are arranged in horizontal rows of 16 bits each within a 16x16 block. The 16x16 blocks in which the latter 128 bits are arranged are shifted by 16 columns on the same row. For example, the first half (bits 0-127) of the code (20,0) is located in column 0 (c=0) within a 16x16 block where (R,C) = (1,0)(3,1)(5,2)(7,3)(9,4)(11,5)(13,6)(15,7). The latter half of the code (20,0) (bits 128-255) is located in row 0 (r=0) of the 16x16 block where (R,C)=(20,0)~(20,7). Similarly, the first half of the code (20,15) (bits 0-127) is located in column 15 (c=15) of the 16x16 block where (R,C)=(1,1)(3,1)(5,2)(7,3)(9,4)(11,5)(13,6)(15,7). The latter half of the code (20,15) (bits 128-255) is located in row 15 (r=15) of the 16x16 block where (R,C)=(20,0)~(20,7).

[0029] The following provides a detailed explanation. Error correction capability improves by repeatedly performing error correction processing. Figures 6 and 7 illustrate the overlap of codes in oFEC. In Figures 6 and 7, 200a and 200b represent code A, 201a and 201b represent code P, 202a and 202b represent code Q, and 203a and 203b represent code Z. Of these, codes arranged vertically, such as 200a, 201a, 202a, and 203a, are referred to as "vertically long 16 bits" in this book, and codes arranged horizontally, such as 200b, 201b, 202b, and 203b, are referred to as "horizontally long 16 bits."

[0030] In Figures 6 and 7, the first 128 bits of the eight "vertically elongated 16 bits" of code Z within the 16x16 blocks (R,C) = (20,0), (22,1), (24,2), ..., (34,7) have already undergone the first error correction as other codes at the time of error correction processing for code Z, and will undergo error correction a second time as code Z. For example, when error correction processing is performed for code Z, the 256 bits within (20,0) have already undergone error correction processing once by codes A to P. Because the bits to be corrected by the "horizontally elongated 16 bits" of codes A to P and the "vertically elongated 16 bits" of code Z overlap, the "vertically elongated 16 bits" of code Z undergo error correction twice. On the other hand, when error correction processing is performed for code Z, the eight "horizontally elongated 16 bits" of code Z within (39,0) to (39,7) undergo error correction for the first time. Thus, at a given point in time, the latter 128 bits will have more residual errors than the first 128 bits because they undergo fewer error corrections.

[0031] This embodiment utilizes such characteristics. For example, in the soft-decision decoding circuit 240-3, if the LLR (log-likelihood ratio) is calculated only for the latter 128 bits of the 256 bits to be error corrected, and a fixed maximum value that the LLR can take is output for the first 128 bits, then the calculation and storage circuit for the LLR is required for the latter 128 bits, but the calculation and storage circuit for the LLR is not required for the first 128 bits, thus reducing the circuit size and power consumption.

[0032] For example, if the third stage soft-decision decoding circuit 240-3 processes data using the maximum LLR (log-likelihood ratio) of the first 128 bits, the soft-decision decoding circuit 240-3 will perform the same processing as the soft-decision decoding circuits 240-1 and 240-2 on data in an array as explained in Figure 7. However, because the LLR (log-likelihood ratio) of the first 128 bits is at its highest value, the error correction decision will result in "no error correction," and the error correction process will not be performed.

[0033] As described above, this embodiment utilizes the difference in residual error rates among code locations that occur after multiple error corrections to efficiently correct only the code locations with high residual error rates. As a result, this embodiment can suppress the increase in circuit size and power consumption that accompanies an increase in the number of error correction iterations.

[0034] In this embodiment, we have used a 256-bit code of Open FEC (oFEC) for explanation. However, any error correction method that generates a difference in residual error rate due to code overlap can be applied to reduce power consumption and circuit size by utilizing the difference in residual error rate. For more information on oFEC, see the document "Open ROADM MSA 3.01 W-Port Digital Specification", June 25, 2019. <https: / / view.officeapps.live.com / op / view.aspx?src=https%3A%2F%2F0201.nccdn.net%2F1_2%2F000%2F000%2F141%2Fb6c%2FOpenROADM_MSA3.01-W-Port-Digital-Specification.docx&wdOrigin=BROWSELINK> It is disclosed in "[ ]".

[0035] Error correction processing is performed sequentially on the bit array of oFEC as shown in Figure 5, in the order in which the rows increase. 256 bits of the same code are processed simultaneously. The code processing order is from top to bottom in Figure 5. When this embodiment is applied to oFEC, some of the soft-decision decoding circuits 240-X perform error correction on the first 128 bits of the 256 bits to be corrected, using a fixed maximum value (LLR=1) for the LLR (log-likelihood ratio), and perform error correction on the latter 128 bits based on the LLR (log-likelihood ratio) from the preceding circuit.

[0036] In this embodiment, for the sake of simplicity, a configuration with k stages of soft-decision decoding circuitry is assumed. In an actual circuit, the optimal number of error corrections is determined by considering the balance between power consumption and error correction performance. The number of stages in which the soft-decision decoding circuitry that maximizes the LLR (log-likelihood ratio), which gives the present invention its characteristic configuration, is placed should also be determined by considering the balance between power consumption and error correction performance.

[0037] Each of the transmitting device 1 and receiving device 2 described in this embodiment can be configured with hardware logic such as an ASIC (application-specific integrated circuit) or an FPGA (field-programmable gate array). Alternatively, at least a portion of each of the transmitting device 1 and receiving device 2 may be implemented by a computer. In this case, the CPU of each device executes the processing described in this embodiment according to a program stored in memory. [Explanation of Symbols]

[0038] 1...Transmitter, 2...Receiver, 10...Error correction coding circuit, 11...Symbol mapping circuit, 12...Modulation circuit, 13...DA conversion circuit, 20...AD conversion circuit, 21...Demodulation circuit, 22...Symbol demapping circuit, 23...Soft decision circuit, 24...Error correction decoding circuit, 240-1~240-k...Soft decision decoding circuit, 241-1~241-k...Error correction unit, 242-1~242-(k-1)...LLR update unit.

Claims

1. An error correction method for a digital coherent optical transmission system, characterized by performing multiple error corrections, and in some error corrections, only the latter half of the code is targeted for correction.

2. In the error correction method described in claim 1, The first step is to calculate the bitwise LLR of the code to be error corrected, The process includes a second step of performing error correction using the aforementioned LLR, updating the LLR based on the error correction determination result, and outputting it to the subsequent circuit. An error correction method characterized in that, in a part of the second step which is performed multiple times, the latter half of the code bits are corrected using the LLR input from the preceding circuit, and the first half of the code bits are corrected using a fixed maximum value that the LLR can take.

3. In the error correction method described in claim 2, After processing in the first step, the processing in the second step is performed multiple times. The second step is characterized by including the step of performing error correction using the LLR input from the preceding circuit only for the latter half of the bits if the desired error correction performance can be obtained, and performing error correction on the first half of the bits using the fixed maximum value that the LLR can take, and performing error correction using the LLR input from the preceding circuit for all bits if the desired error correction performance cannot be obtained.

4. An error correction circuit for a digital coherent optical transmission system, characterized by performing multiple error corrections, and in some error corrections, only the latter half of the code being corrected.

5. In the error correction circuit according to claim 4, An error correction circuit further comprising a soft decision circuit that calculates the LLR for each bit of the code from the coordinate shift of the received symbol and outputs it to a subsequent circuit.

6. In the error correction circuit described in claim 5, The system includes multiple soft-decision decoding circuits that perform error correction processing using the aforementioned LLR and update the LLR based on the results. The soft-decision decoding circuit is characterized in that, when the desired error correction performance can be obtained, it performs error correction on only the latter half of a codeword consisting of multiple bits using the LLR input from the preceding circuit, and performs error correction on the first half of the codeword using the fixed highest value that the LLR can take, and when the desired error correction performance cannot be obtained, it performs error correction on all bits using the LLR output from the preceding circuit.

7. In the error correction circuit according to claim 6, An error correction circuit characterized in that, among the multiple stages of the soft-decision decoding circuit, error correction is performed only in the final stage soft-decision decoding circuit, with the LLR of the first half bits set to the maximum value, while in the other soft-decision decoding circuits, error correction is performed for all bits using the LLR output from the preceding circuit.

8. In the error correction circuit according to claim 6, An error correction circuit characterized in that, in all of the multiple stages of the soft-decision decoding circuit, error correction is performed with the LLR of the first half bits set to the maximum value, and error correction of the second half bits is performed using the LLR output from the preceding circuit.

9. In the error correction circuit according to claim 6, An error correction circuit characterized in that, in some of the multiple stages of the soft-decision decoding circuit, error correction is performed with the LLR of the first half bits set to the maximum value, and error correction of the second half bits is performed using the LLR output from the preceding circuit, and in the other soft-decision decoding circuits, error correction is performed for all bits using the LLR output from the preceding circuit.

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