Integrated LDPC and RAID Decryption Method

Abstract

The present invention provides a data storage device that handles errors resulting from physical defects. [Solution] The error correction code (ECC) system of the data storage device utilizes an integrated decoding scheme to correct errors in a codeword when the decoding process using a first decoding scheme fails, and uses information derived from a second decoding scheme to generate soft bit information or reliability information associated with the failed portion of the codeword. The soft bit information derived from the second decoding scheme is provided to the first decoding scheme when the first decoding scheme attempts to correct or decode the failed codeword.

Description

Technical Field

[0001] Data storage devices typically include error correction capabilities to correct errors that occur when data is read from the data storage device. For example, when data is written to a data storage device, the data is encoded by an error correction code (ECC) low-density parity-check (LDPC) encoder to generate redundant information. The redundant information is known as parity bits. The parity bits and the data are stored as an ECC codeword.

[0002] When an ECC codeword is read from the data storage device, a decoder such as an LDPC decoder decodes the codeword and corrects any possible errors. Generally, an LDPC decoder is used to correct random errors that occur on the data storage device.

[0003] However, an LDPC decoder cannot handle large errors that occur as a result of memory defects and / or failures. Therefore, a data storage device can also incorporate an independent disk redundant array (RAID) storage scheme aimed at handling errors resulting from physical defects. For example, a RAID storage scheme distributes data along with first parity information and second parity information in stripes that cross multiple different solid-state drives (SSDs) or cross multiple different memory dies within a single SSD. The parity information enables the recovery of data within the stripe if one of the SSDs or one of the memory dies fails.

[0004] In some examples, LDPC decoding and RAID decoding are combined to increase the chances that an error can be corrected. For example, if multiple pages fail the decoding operation, a RAID-based decoding scheme is implemented for that page, followed by an LDPC decoding scheme. This process is repeated for each failed page.

[0005] However, there may be situations where errors in the data exceed the correction capabilities of the LDPC and RAID decoders, but the bit error rate (BER) of the data is not high enough to indicate that the entire codeword is invalid or that the memory die has failed.

[0006] Therefore, it would be beneficial to utilize RAID parity information in the LDPC decoding method in order to enable the LDPC decoding method to correct data with a high BER. [Overview of the project]

[0007] This disclosure describes an error-correcting code (ECC) system for a data storage device. The ECC system utilizes an integrated decoding scheme to correct errors in a codeword (or flash memory unit (FMU)) when at least one codeword or FMU fails the initial decoding process. For example, when a codeword fails the initial decoding process using a first decoding scheme (e.g., an LDPC decoding scheme), information derived from or otherwise associated with a second decoding scheme (e.g., a RAID decoding scheme) is used to generate soft bit information or reliability information associated with the failed portion of the codeword. The soft bit information derived from the second decoding scheme is provided to the first decoding scheme, which attempts to decode the previously failed codeword. Thus, the information derived from or associated with the second decoding scheme can be used to correct random errors that cannot be corrected using the first decoding scheme, or when there are no memory defects but the number of memory defects is less (or more) than the correction capability of the second decoding scheme.

[0008] Accordingly, an example of the present disclosure describes a method that includes determining that a codeword has failed in a first decoding process using a first decoding scheme.

[0009] Based at least in part on determining that the codeword failed in a first decoding process using a first decoding scheme, first parity information and second parity information associated with the portion of the codeword are identified. In one example, the first and second parity information are associated with a second decoding scheme. The reliability of the portion of the codeword is adjusted at least in part on the first and second parity information. The reliability of the portion of the codeword is then provided to the first decoding scheme for the second decoding process.

[0010] Another example describes a data storage device having a controller and an error correction code (ECC) system. In one example, the ECC system identifies codewords with a number of errors exceeding the correction capability of a first decoding scheme. The ECC system also identifies first and second parity information associated with the codewords. In one example, the first and second parity information are associated with a second decoding scheme. The ECC system calculates the reliability of a portion of the codeword. In one example, the reliability of a portion of the codeword is at least partially based on the first and second parity information. The ECC system also provides the reliability of a portion of the codeword to the first decoding scheme.

[0011] Further examples describe data storage devices including control means and error correction means. The error correction means are operable to identify a plurality of codewords having a number of errors that exceeds the correction capability of a first decoding scheme. The error correction means are also operable to determine that the number of the plurality of codewords exceeds the correction capability of a second decoding scheme. In response to the determination, the error correction means uses the second decoding scheme to generate a list of potential codewords using at least a portion of the striped codewords associated with the first codeword among the plurality of codewords. The error correction means also determines the reliability of each potential codeword in the list of codewords and provides at least one potential codeword in the list of codewords to the first decoding scheme.

[0012] This summary is provided in a simplified form to introduce the selection of concepts further described below in modes for carrying out the invention. This summary is not intended to identify the main or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. [Brief explanation of the drawing]

[0013] Non-exclusive and non-exclusive examples are illustrated with reference to the following diagram. [Figure 1] This is a block diagram of a system including a host device and data storage device, as an example. [Figure 2A] This example illustrates how a memory device contains multiple memory blocks. [Figure 2B] This example illustrates how a memory block can contain one or more pages. [Figure 2C] An example illustrates how a memory block contains numerous bit lines and word lines. [Figure 3] An example data structure for storing multiple codewords, multiple stripe codewords, and parity information is shown. [Figure 4A] This example demonstrates how different parts of a striped codeword corresponding to a failed codeword are erased and how potential codewords are determined. [Figure 4B] Another example illustrates how different parts of the striped codeword corresponding to a failed codeword are erased and how potential codewords are determined. [Figure 5] This example demonstrates how to use a unified decoding scheme to decode a failed codeword. [Figure 6] This example demonstrates how to use a unified decoding scheme to decode multiple failed codewords. [Figure 7] This is a perspective view of a storage device including a three-dimensional (3D) stacked non-volatile memory as an example. [Figure 8]This is a block diagram of a storage device as an example.

[0014] Detailed explanation In the following detailed description, references are made to the accompanying drawings, which form part of this specification, and which illustrate specific embodiments or examples. These embodiments may be combined, used in other embodiments, or modified structurally without departing from the disclosure. Accordingly, the following detailed description should not be construed as restrictive, and the scope of this disclosure is defined by the accompanying claims and their equivalents.

[0015] A data storage device includes error correction capabilities to correct errors that occur when data is read from the data storage device. For example, when data is written to a data storage device, the data is encoded by an error-correcting code (ECC) encoder (e.g., an LDPC encoder) to generate a parity bit. The parity bit is combined with the data and stored as an ECC codeword.

[0016] When an ECC codeword is read from a data storage device, a decoder (e.g., an LDPC decoder) decodes the codeword and corrects any errors that may exist. Generally, LDPC decoders are used to correct random errors that occur on the data storage device. For example, an LDPC decoder corrects errors up to a certain bit error rate (BER).

[0017] In some cases, data storage devices also incorporate RAID encoding / decoding schemes. In a RAID encoding / decoding scheme, data is distributed in stripes (e.g., elements XORed together) across multiple different solid-state drives (SSDs) or across multiple memory dies within a single SSD, along with first and second parity information. The parity information allows for the recovery of data within the stripe in the event of failure of one of the SSDs or one of the memory dies.

[0018] Typically, a RAID scheme can correct a fixed number (e.g., two) of failures within a stripe. However, there can be situations where the errors in the codeword exceed the correction capabilities of the LDPC decoder and / or the RAID decoder. For example, a stripe may have three or more failures and thus may not be decodable by the RAID decoder.

[0019] However, when the bit error rate (BER) of the failed codeword does not exceed an error threshold (e.g., a 50% error rate that renders a memory die inoperable) but exceeds the error threshold of the LDPC decoder, integrated LDPC and RAID decoding schemes such as those described herein are used to correct the errors.

[0020] Specifically, this application describes an ECC system for a data storage device. The ECC system utilizes an integrated decoding scheme to correct errors in a codeword (or flash memory unit (FMU)) when at least one codeword fails an initial decoding process that uses a first decoding scheme. For example, when a codeword fails an initial decoding process that utilizes a first decoding scheme (e.g., an LDPC type decoding scheme), information derived from or otherwise associated with a second decoding scheme (e.g., a RAID decoding scheme) is used to recover the information. Thus, information derived from or associated with the second decoding scheme can be used to correct random errors that cannot be corrected using the first decoding scheme or when the number of memory defects is less than or more than (but there are no memory defects) the correction capabilities of the second decoding scheme.

[0021] For example, when a codeword or FMU fails an initial decoding process that uses a first decoding scheme, parity information associated with the second decoding scheme is used to generate or determine soft bit information. The soft bit information is provided to the first decoding scheme for subsequent decoding attempts on the failed codeword.

[0022] As described above, many technical benefits can be realized, including but not limited to improving the decoding capability of the first decoding method by using information derived from the second decoding method, which improves the reliability of the data storage device and extends the effective lifespan of the data storage device.

[0023] These advantages, along with other examples, will be shown and explained in more detail with respect to Figures 1 to 8.

[0024] Figure 1 is a block diagram of a system 100 including a host device 105 and a data storage device 110 in one example. In this example, the host device 105 includes a processor 115 and memory 120 (e.g., main memory). The memory 120 includes, or is associated with, an operating system 125, a kernel 130, and / or applications 135.

[0025] The processor 115 can execute various instructions, such as instructions from the operating system 125 and / or application 135. The processor 115 includes circuits such as microcontrollers, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), hardwired logic, analog circuits, and / or various combinations thereof. In one example, the processor 115 includes a system-on-a-chip (SoC).

[0026] In one example, memory 120 is used by the processor 115 or by the host device 105 to store data that is otherwise executed. The data stored in memory 120 includes instructions provided by the data storage device 110 via the communication interface 140. The data stored in memory 120 also includes data used to execute instructions from the operating system 125 and / or one or more applications 135. Memory 120 may be a single memory or may include multiple memories, such as one or more non-volatile memories, one or more volatile memories, or a combination thereof.

[0027] In one example, the operating system 125 creates a virtual address space for application 135 and / or other processes run by processor 115. The virtual address space maps to locations in memory 120. The operating system 125 also includes, or is associated with, a kernel 130. The kernel 130 manages various resources of the host device 105 (e.g., memory allocation) and includes instructions for handling read and write requests, etc.

[0028] The communication interface 140 connects the host device 105 and the data storage device 110 in a communicative manner. The communication interface 140 may be Serial Advanced Technology Attachment (SATA), PCI express (PCIe) bus, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Ethernet, Fibre Channel, or Wi-Fi. Therefore, the host device 105 and the data storage device 110 do not need to be located in the same physical location and can communicate via a network such as a local area network (LAN) or a wide area network (WAN) such as the Internet. In addition, the host device 105 can interface with the data storage device 110 using a logical interface specification such as NVMe (Non-Volatile Memory express) or AHCI (Advanced Host Controller Interface).

[0029] The data storage device 110 includes a controller 150 and a memory device 155. In one example, the controller 150 is communicatively coupled to the memory device 155. The memory device 155 includes one or more memory dies (e.g., a first memory die 165 and a second memory die 170). Although memory dies are specifically mentioned, the memory device 155 may include any non-volatile memory device, storage device, storage element or storage medium, including NAND flash memory cells and / or NOR flash memory cells.

[0030] The memory cells can take the form of solid-state (e.g., flash) memory cells and can be programmable once, several times, or multiple times. Furthermore, the memory cells may be single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), penta-level cells (PLC), and / or any other memory technology may be used. In one example, the memory cells are arranged in a two-dimensional configuration. In another example, the memory cells are arranged in a three-dimensional configuration.

[0031] In one example, the data storage device 110 is attached to or embedded within the host device 105. In another example, the data storage device 110 is implemented as an external or portable device that can be communicatively or selectively coupled to and detached from the host device 105. In yet another example, the data storage device 110 is a component of a network-accessible data storage system, a network-connected storage system, a cloud data storage system, etc. (e.g., a solid-state drive (SSD)).

[0032] As described above, the memory device 155 of the data storage device 110 includes a first memory die 165 and a second memory die 170. Although two memory dies are shown, the memory device 155 may include any number of memory dies (for example, one memory die, two memory dies, eight memory dies, or any other number of memory dies).

[0033] The memory device 155 also includes support circuitry. In one example, the support circuitry includes a read / write circuit 160. The read / write circuit 160 supports the operation of the memory dies of the memory device 155. Although the read / write circuit 160 is shown as a single component, it may be divided into separate components, such as a read circuit and a write circuit. The read / write circuit 160 may be located outside the memory dies of the memory device 155. In another example, one or more of the memory dies may include a corresponding read / write circuit 160 that can operate to read data from and / or write data to memory elements within an individual memory die, independently of other read and / or write operations on any of the other memory dies.

[0034] In one example, one or more of the first memory die 165 and the second memory die 170 contain one or more memory blocks. In one example, each memory block contains one or more memory cells. A block of memory cells is the smallest number of memory cells that can be physically erased together. In one example, to improve parallelism, each block may operate or be organized into a larger block or metablock. For example, one block from different memory dies may be logically linked to each other to form a metablock.

[0035] For example, referring to Figure 2A, Figure 2A shows how the memory device 200 includes a number of memory blocks in one example. For example, the memory device 200 (e.g., memory element, memory die, non-volatile memory device) includes four planes or subarrays (e.g., a first plane 205, a second plane 210, a third plane 215, and a fourth plane 220). In one example, the planes are integrated on a single memory die. In another example, the planes are located on two different memory dies (e.g., two planes on each memory die). In yet another example, the planes are located on four separate memory dies. Although four planes are shown and described, the memory device 200 may have any number of planes and / or memory dies.

[0036] In one example, each plane is divided into memory blocks that constitute memory cells. As shown in Figure 2A, the rectangles represent memory blocks such as memory block 225, memory block 230, memory block 235, and memory block 240. Each plane of the memory device 200 may contain tens or hundreds of memory blocks. In one example, each memory block is a unit of erasure and is sometimes called an erase block. For example, memory blocks 225, 230, 235, and 240 contain the minimum number of memory cells that are erased together.

[0037] In addition, various memory blocks are logically linked or grouped together (for example, using a table in controller 150 (Figure 1), or a table accessible by controller 150 (Figure 1)) to form a metablock. The metablock is written to, read from, and / or erased as a single unit. For example, memory blocks 225, 230, 235, and 240 form a first metablock, and memory blocks 245, 250, 255, and 260 form a second metablock. The memory blocks used to form a metablock do not need to be limited to the same relative positions within their respective planes.

[0038] In one example, each memory block is divided into pages of memory cells for operational purposes. Referring to Figure 2B, for example, Figure 2B illustrates how a memory block contains one or more pages in one example. For instance, the memory cells of memory blocks 225, 230, 235, and 240 are divided into N distinct pages (indicated as P0 to PN). While a specific number of pages is shown in Figure 2B, a memory block can have any number of pages of memory cells within each memory block.

[0039] In one example, a page is a unit of data programming within a memory block. Each page contains the smallest amount of data that can be programmed at once. The smallest unit of data that can be read at once may be less than a page. For example, each page can be further divided into segments or units, each segment containing the smallest number of memory cells that can be written at once as a basic programming operation. The data stored in a segment or unit of memory cells is referred to herein as a flash memory unit (FMU). An FMU can be a page, an ECC page, a codeword, or otherwise may contain the amount of data that can be written at once during a basic programming operation and / or the amount of data that can be encoded and / or decoded by an ECC system (e.g., ECC system 180 (Figure 1)) during a single encoding and / or decoding operation.

[0040] Metapage 270 is shown in Figure 2B as being formed from one physical page from memory blocks 225, 230, 235, and 240. In the illustrated example, metapage 270 contains page P1 in each of the four memory blocks. However, the pages of metapage 270 do not need to have the same relative position within each of the memory blocks. Metapage 270 may be the largest unit of programming within a memory block.

[0041] The memory blocks disclosed in Figures 2A and 2B are referred to herein as physical memory blocks because they relate to a group of physical memory cells as described above. As used herein, a logical memory block is a virtual unit of address space defined to have the same size as a physical memory block. Each logical memory block includes a range of logical memory block addresses (LBAs) associated with data received from a host. The LBAs are then mapped to one or more physical memory blocks in the data storage device 110 where the data is physically stored.

[0042] As mentioned above, each memory block can contain any number of memory cells. The design, size, and organization of a memory block may depend on the desired architecture, design, and application for each memory die. For example, a memory block may contain a contiguous set of memory cells sharing multiple word lines and bit lines.

[0043] Figure 2C illustrates, in one example, how a memory block contains multiple bit lines 275 and word lines 280. For example, as shown in Figure 2C, memory block 225 contains bit lines BL0 to BLN (collectively, bit lines 275), where N is the total number of bit lines. Furthermore, memory block 225 also contains word lines WL0 to WLN (collectively, word lines 280), where N is the total number of word lines. In one example, multiple memory blocks can share the same bit lines.

[0044] The word line 280 can function as a single-level cell (SLC) word line, a multi-level cell (MLC) word line, a tri-level cell (TLC) word line, a quad-level cell (QLC) word line, a penta-level cell (PLC) word line, and so on. In addition, each memory cell may be programmable to a state that exhibits one or more values ​​(e.g., a threshold voltage in a flash configuration or a resistance state in a resistive memory configuration).

[0045] In the example shown in Figure 2C, four memory cells are connected in series to form a NAND string. Although four memory cells are shown, any number of memory cells (e.g., 16, 32, 64, 128, 256, or any other number of memory cells) may be used. One terminal of the NAND string is connected to the corresponding bit line via a drain-selection gate (connected to the drain line SGD), and the other terminal of the NAND string is connected to the source line via a source-selection gate (connected to the source line SGS). Furthermore, although eight bit lines are shown in Figure 2C, any number of bit lines can be used.

[0046] Referring back to Figure 1, as previously mentioned, the data storage device 110 also includes a controller 150. Although a single controller 150 is shown and described, the data storage device 110 can include multiple controllers. In such an example, a first controller performs a first operation or set of operations, and a second controller performs a second operation or set of operations. In one example, the first set of operations and the second set of operations are performed on the same memory die. In another example, the first set of operations is performed on a first memory die or a first set of memory dies, and the second set of operations is performed on a second memory die or a second set of memory dies.

[0047] The controller 150 is communicatively coupled to the memory device 155 via a bus, interface, or other communication circuit. In one example, the communication circuit includes one or more channels that enable the controller 150 to communicate with the first memory die 165 and / or the second memory die 170 of the memory device 155. In another example, the communication circuit includes multiple separate channels that enable the controller 150 to communicate independently of the first memory die 165 and / or in parallel with the second memory die 170 of the memory device 155.

[0048] The controller 150 receives data and / or commands from the host device 105. The controller 150 also transmits data to the host device 105. For example, the controller 150 transmits data to and / or receives data from the host device 105 via the communication interface 140. The controller 150 also transmits data and / or commands to and / or receives data from the memory device 155.

[0049] The controller 150 sends data and corresponding write commands to the memory device 155 to cause the memory device 155 to store the data at a specified address in the memory device 155. In one example, the write command specifies a physical address of the memory device 155. The controller 150 also sends data and / or commands associated with one or more background scan operations, garbage collection operations, and / or wear leveling operations.

[0050] The controller 150 also sends one or more read commands to the memory device 155. For example, a read command specifies the physical address of a portion of the memory device 155 where the data is stored. The controller 150 also tracks the number of program / erase cycles or other programming operations performed on or by the memory device and / or the memory die of the memory device 155.

[0051] The controller 150 also includes, or is associated with, the ECC system 180. In one example, the ECC system 180 is a packaged functional hardware unit designed for use with other components / systems. In another example, the ECC system 180 is a portion of program code (e.g., software or firmware) executable by a processor or processing circuit. In yet another example, the ECC system 180 is a self-contained hardware and / or software component that interfaces with other components and / or systems. Although the ECC system 180 is shown as part of the controller 150, the ECC system 180 may be separate from the controller 150.

[0052] In one example, the ECC system 180 receives data to be stored in the memory device 155 and generates a codeword. For example, the ECC system 180 includes an encoder that encodes the received data using a first encoding scheme. In one example, the first encoding scheme is an ECC encoding scheme such as a Reed-Solomon encoder, a Bose Chaudhuri Hocquenghem (BCH) encoder, a low-density parity-check (LDPC) encoder, a turbocode encoder, an encoder configured to encode one or more other ECC encoding schemes, or any combination thereof.

[0053] For example, when data is received from the host device 105, the ECC system 180 encodes the data into one or more codewords. The codewords are then stored in the memory device 155 (or another location). For example, when data is received, the data is divided into N data words. The first part of the data corresponds to the first data word, and the Nth data word corresponds to the last data word of the data. The ECC system 180 encodes the first data word to generate the first codeword (including the data and associated parity bits), encodes the second data word to generate the second codeword, and so on, for all N data words.

[0054] In addition, the ECC system 180 includes an encoder that encodes data according to a second encoding scheme. For example, the second encoding scheme is a RAID (e.g., RAID 6) or XOR encoding scheme that generates striped parity data or striped codewords. For example, when codewords corresponding to N data words are generated (e.g., resulting in N codewords), the ECC system 180 uses the second encoding scheme to generate striped codewords corresponding to multiple sequences of multiple bits from each of the N codewords. For example, the ECC system 180 is configured to generate first parity data corresponding to the first striped codeword by encoding a first part (e.g., 8 bits) of each of the N codewords. The ECC system 180 generates a second striped codeword by encoding a second part of each of the N codewords. This process is repeated for each part of each codeword.

[0055] In one example, the parity information of a striped codeword is represented as P parity information and Q parity information. P parity information and Q parity information are calculated using the following formulas.

[0056]

number

[0057] As shown in the formula above, P parity information is

[0058]

number

[0059] When codewords and striped codewords are generated (or are being generated), the codewords, striped codewords, and parity information are stored in a data structure. For example, referring to Figure 3, Figure 3 shows an example of a data structure 300 that stores multiple codewords, multiple striped codewords, and parity information 360. As shown in Figure 3, the data structure 300 contains multiple codewords. For example, the data structure 300 contains N codewords, including codeword 0 310, codeword 1 320, codeword 2 330, codeword 3 340, and codeword N 350. Although five codewords are shown and described, the data structure 300 can contain any number of codewords.

[0060] As previously explained, data structure 300 also contains one or more striped codewords (represented by dashed rectangles). For example, data structure 300 contains a first striped codeword 370, a second striped codeword 380, and an M striped codeword 390, where M is any number greater than 1.

[0061] In one example, the first striped codeword 370 includes the first part of codeword 0 310, the first part of codeword 1 320, the first part of codeword 2 330, the first part of codeword 3 340, and the first part of codeword N 350. The first part of the codeword is encoded using a striped coding scheme (e.g., Reed-Solomon coding scheme) for a single symbol (e.g., an 8-bit chunk) to generate parity information 360 (e.g., P parity information and Q parity information) corresponding to the first striped codeword 370.

[0062] Similarly, the second striped codeword 380 includes the second portion of codeword 0 310, the second portion of codeword 1 320, the second portion of codeword 2 330, the second portion of codeword 3 340, and the second portion of codeword N 350. The parity information 360 associated with the second striped codeword is also generated as described above.

[0063] Referring back to Figure 1, the ECC system 180 also includes a first decoder that decodes data or codewords using a first decoding scheme 185, and a second decoder that decodes data or codewords using a second decoding scheme 190. In one example, the first decoding scheme 185 is an LDPC decoding scheme, and the second decoding scheme 190 is a RAID (e.g., RAID 6) or XOR decoding scheme. In another example, the first decoding scheme is a RAID decoding scheme, and the second decoding scheme is an LDPC decoding scheme. While specific decoding schemes are mentioned, other encoding and / or decoding schemes may be used. In one example, the first decoding scheme 185 is used to decode generated codewords, and the second decoding scheme 190 is used to decode striped codewords.

[0064] In one example, when a codeword is decoded, the ECC system 180 may determine that the codeword contains various errors. In some examples, the number of errors detected or identified in the codeword may exceed the correction capabilities of the first decoding scheme 185 and / or the second decoding scheme 190. However, the errors do not reach a level that invalidates the entire codeword. In such examples, an integrated decoding scheme is used to correct the errors. In one example, the integrated decoding scheme utilizes the first decoding scheme 185 and the second decoding scheme 190 to correct the various errors detected by the ECC system 180.

[0065] For example, the second decoding scheme 190 is used to generate confidence information (also called soft bit information or soft information) about different parts of the striped codeword associated with the failed codeword. The confidence information is then provided to the first decoding scheme 185 during subsequent attempts to correct the failed codeword.

[0066] In one example, each codeword resides on a separate page of the memory device 155. Thus, each codeword can be decoded independently of other codewords. For example, referring again to Figure 3, codeword 0310 includes a parity bit used by the ECC system (e.g., ECC system 180 (Figure 1)) to correct bit errors to the extent of the correction capability of the first decoding scheme (e.g., first decoding scheme 185 (Figure 1)). Similarly, codeword 1320 includes a parity bit used by the ECC system to correct bit errors identified in codeword 1320.

[0067] However, if one or more of the codewords contain bit errors that exceed the correction capabilities of the first decoding scheme but do not reach a level that invalidates the entire codeword, the ECC system uses parity information 360 associated with a second decoding scheme (e.g., a second decoding scheme 190 (Figure 1) or a RAID 6 decoding scheme) to generate soft bit information that can be used to correct the failed codeword.

[0068] For example, if one or more codewords in data structure 300 fail to decode using the first decoding scheme, the ECC system reads the remaining codewords from data structure 300 and attempts to decode them. In one example, the ECC system decodes the remaining codewords belonging to a particular stripe. The ECC system then decodes the failed codeword and / or various parities ( For example, this would involve generating P parity information and / or Q parity information.

[0069] If the number of failed codewords in data structure 300 is less than or equal to the correction capability of a second decoding scheme (e.g., second decoding scheme 190 (Figure 1)), the second decoding scheme may be used to generate soft bit information or reliability information associated with each stripe codeword. In another example, the decoding schemes described herein may also be used when the number of failed codewords in data structure exceeds the correction capability of the second decoding scheme, provided that the number of errors in the failed codewords and / or the BER do not exceed an error threshold that would invalidate the memory die. The soft bit information is used to correct one or more of the failed codewords in an iterative manner, as described in more detail herein.

[0070] In another example, when a codeword in data structure 300 fails to decode using the first decoding scheme, the ECC system performs iterative decoding using both the first and second decoding schemes. For example, the ECC system exchanges information between the first and second decoding schemes to generate soft information or a confidence score associated with the failed portion of the codeword. For example, parity information associated with the second decoding scheme (e.g., P parity information and / or Q parity information) is used to determine the confidence or log-likelihood ratio (LLR) (e.g., the probability that a particular bit is "1" or "0") of a particular bit or portion within the failed codeword.

[0071] For example, an ECC system receives or determines P-parity information for a specific bit or page of a failed codeword (or portion of a codeword) and reliability information associated with the codeword. The ECC system then compares the P-parity information for the specific bit or page with the hard bit information associated with that specific bit and / or page of the failed codeword. If the P-parity information and the hard bit information match, the LLR (or reliability) associated with that specific bit or portion of the codeword (e.g., the portion of the striped codeword associated with the failed codeword) is increased. However, if the hard bit information associated with that specific bit of the codeword does not match the P-parity information, the reliability of that specific bit or portion of the codeword is decreased.

[0072] In another example, the LLR or reliability score for a particular bit and / or page associated with a failed codeword is at least partially based on the P parity information associated with that bit, the Q parity information associated with that bit, and the original hard and soft bit information of that bit sensed from the memory device. For example, for each bit index i in a failed codeword or a portion of a failed codeword, the soft and hard bit information of bit i is sensed from memory. This can be expressed by the following formula: HB i +SB i (Sensed from memory)

[0073] The P parity information associated with bit i and the Q parity information associated with bit i are also reproduced or determined. In one example, the P parity information associated with bit i and the Q parity information associated with bit i are generated by the following equations (these equations are the inverse equations of the equations mentioned above for generating the P parity information and Q parity information).

[0074]

number

[0075] Once the P parity and Q parity information for a specific bit i is determined, the value for P and the value for Q are compared. In cases where the P and Q values ​​do not match for a specific bit i, the original LLR or reliability of that bit i remains unchanged.

[0076] However, in examples where the P and Q values ​​for a particular bit i match or are the same, the values ​​for P and / or Q are compared against the hard bit value for that particular bit i. If the values ​​for P and / or Q match the hard bit value for that particular bit i, the original LLR or reliability of that particular bit i is increased. In one example, the magnitude of the LLR is at least partially based on the soft bit of that particular bit i as perceived by the memory device, and the sign of the LLR is at least partially based on the hard bit of that particular bit i.

[0077] In another example, the P and Q values ​​of a particular bit i may match or be the same, but the P and / or Q values ​​may not match the hard bit value of that particular bit i. In such an example, the original LLR or reliability of that particular bit i is reduced.

[0078] The decision regarding whether the LLR of a particular bit i should be increased or decreased is determined by the BER. i The BER that forms the basis of a particular bit i is expressed by the following formula:

[0079]

number

[0080] When the LLR is determined for a particular bit i, the newly updated LLR can be used by a first decoding scheme to decode a particular codeword. For example, the newly updated LLR for a particular bit i is provided to the first encoding scheme during subsequent decoding attempts of a failed codeword. This process is repeated iteratively between the failed codeword and the striped codeword until the codeword is corrected or a timeout condition occurs.

[0081] For example, the ECC system 180 can correct up to two failed codewords using the decoding techniques described above. For instance, each codeword may be coded using a first coding scheme (e.g., LDPC coding), and each striped codeword may be coded using a second coding scheme (e.g., Reed-Solomon coding). As previously described, the first decoding scheme 185 may include the LDPC decoding scheme, and the second decoding scheme 190 may include the Reed-Solomon erase-correction scheme. Although the LDPC and Reed-Solomon schemes are described, each codeword may be coded / decoded using a different coding / decoding scheme (e.g., BCH scheme), and each striped codeword may be coded / decoded using a different striped coding / decoding scheme (e.g., another BCH scheme).

[0082] For example, if a codeword fails to decode using the first decoding scheme 185, the symbol of the striped codeword associated with the failed codeword is erased. The correct value of the symbol can then be determined using the erase-decode algorithm.

[0083] For example, referring again to Figure 3, if codewords 0 310 and 1 320 fail to decode using the first decoding method, the second decoding method determines a portion of the first striped codeword 370 associated with codeword 0 310 and a portion of the first striped codeword 370 associated with codeword 1 320. This process is repeated for each striped codeword in the data structure 300.

[0084] However, there may be situations where more than two codewords fail to decode. For example, codewords 0 310, 1 320, 2 330, 3 340, and N350 may all have failed in the decoding process using the first decoding scheme 185. In this example, the codewords failed due to random errors exceeding the correction capability of the first decoding scheme 185, but not due to a memory defect that corrupted the entire codeword. For example, the BER of a codeword can be between 1% and 10%. While a specific range of BER has been mentioned, any BER can be used. However, in some examples, the BER is 50% or less (though this is not required).

[0085] In the following example, the ECC system 180 utilizes a Reed-Solomon decoding scheme (or erase-decoding scheme) that uses symbols (e.g., 8-bit symbols) to group data. The erase-decoding algorithm is also configured to deterministically correct up to t symbol erases during the decoding stage. In this example, t=2.

[0086] As explained earlier, in this example there are five codewords that failed to decode: codeword 0 310, codeword 1 320, codeword 2 330, codeword 3 340, and codeword N350. Therefore,

[0087]

number

[0088] For example, referring to Figure 4A, Figure 4A shows, in one example, how different parts of a striped codeword corresponding to a failed codeword are erased and how a potential codeword is determined. In this example, data structure 400 contains N codewords - codeword 0 410, codeword 1 420, codeword 2 430, codeword 3 440, and codeword N 450. In one example, data structure 400 is similar to data structure 300 shown and explained with respect to Figure 3. Although five codewords are shown and explained, data structure 400 can contain any number of codewords. Data structure 400 also contains one or more striped codewords (represented by dashed rectangles). For example, data structure 400 contains a first striped codeword 460, a second striped codeword 470, and an M striped codeword 480. In one example, M is any number greater than 1.

[0089] The first striped codeword 460 includes the first part 405 of codeword 0 410, the first part 415 of codeword 1 420, the first part 425 of codeword 2 430, the first part 435 of codeword 3 440, and the first part 445 of codeword N 450. In one example, each of the first parts of a striped codeword is encoded using a striped coding scheme (e.g., Reed-Solomon) for 8-bit chunks to generate a symbol. In one example, each of the other striped codewords includes a similar part of each codeword. For example, the second striped codeword 470 includes the second part of codeword 0 410, the second part of codeword 1 420, the second part of codeword 2 430, the second part of codeword 3 440, and the second part of codeword N 450.

[0090] To generate a first potential codeword for the codeword list 490, the first and second parts of the first striped codeword 460 are erased. Then, a decoding operation using a second decoding scheme (e.g., Reed-Solomon decoding scheme) is used to decode and / or correct the first striped codeword 460. This process is then repeated for each pair of parts within the first striped codeword 460.

[0091] For example, in the first iteration, the first portion 405 of codeword 0 410 associated with the first stripe codeword 460 and the first portion 415 of codeword 1 420 associated with the first stripe codeword 460 are erased. Then, the second decoding scheme is applied to the first portion 425 of codeword 2 430, the first portion 435 of codeword 3 440, and the first portion 445 of codeword N 450 to generate the first potential codeword. The first potential codeword is stored in the codeword list 490.

[0092] In the second iteration (shown in Figure 4B), the first portion 405 of codeword 0 410 associated with the first stripe codeword 460 and the first portion 415 of codeword 2 430 associated with the first stripe codeword 460 are erased. The second decoding scheme is then applied to the first portion 425 of codeword 1 420, the first portion 435 of codeword 3 440, and the first portion 445 of codeword N 450 to generate a second potential codeword. The second potential codeword is stored in the codeword list 490. This process is repeated for each pair of portions of the first stripe codeword 460. In one example, this process generates soft bit information associated with each portion.

[0093] The process described above continues for each of the other striped codewords in data structure 400. For example, the process described above continues for the second striped codeword 470 and the M-striped codeword 480. In one example, when all the striped codewords have been traversed, each of the failed codewords in data structure 400 can be decoded using the generated soft information.

[0094] One example involves two methods for generating soft information based on a list of 490 codewords: the maximum likelihood method and the maximum posterior method. Each of these is described in more detail below.

[0095] In the maximum likelihood method, the list of codewords 490 is at the symbol level for each symbol. For example, the list of codewords 490 is sorted so that the symbols with the "worst" (or largest) amount of data to be erased (e.g., symbols associated with the codeword with the highest BER) are at the top of the list. As a result, the chances of the remaining failed data being decoded in a subsequent decoding operation (e.g., an LDPC decoding operation) are increased using the determined soft bit information.

[0096] For example, to save latency, the ECC system 180 selects and corrects codewords that are more prone to errors when compared to other codewords. As a result, the remaining codewords may be easier to decode using additional soft bit information.

[0097] For example, the symbol value for each part of the striped codeword is compared to the original channel HB+SB LLR. The closest value is selected for each symbol (e.g., using Euclidean distance). Another iteration of decoding (e.g., LDPC decoding) is initiated using a second codeword from the codeword list 490. In the second iteration, soft bit information and / or updated LLR associated with the symbols and / or parts of the codeword may be used.

[0098] In the maximum posterior method, all codewords can be used together. For example, when the codeword list 490 is created (as described above), all codewords that take "1" for a particular bit are called C1, and all codewords that take "0" for a particular bit are called C0. Next, the ECC system 180 determines the probability of receiving these bits. The probability is used to determine the LLR for each bit and / or codeword. In one example, the LLR is determined using the following formula:

[0099]

number

[0100] Once the LLR is determined, decoding using the first decoding scheme 185 is initiated using the updated LLR. For example, LLRs associated with various striped codewords may be used to decode various failed codewords. This process can be performed iteratively and / or repeatedly. For example, decoding using the first decoding scheme 185 is initiated, followed by the second decoding scheme 190, and then back to the first decoding scheme.

[0101] Figure 5 illustrates a method 500 for using a unified decoding scheme to decode a failed codeword, as an example. In this example, method 500 is performed by an ECC system, such as the ECC system 180 shown and described with respect to Figure 1.

[0102] In one example, method 500 is initiated during the decoding operation. For example, a codeword may be decoded using a first decoding scheme (e.g., an LDPC decoding scheme). In this example, a codeword being decoded using the first decoding scheme has failed in the decoding process and is identified as a failed codeword (510). In one example, the codeword fails based on various random errors such that the codeword's BER exceeds the correction capability of the first decoding scheme.

[0103] When a codeword is identified as a failed codeword, the ECC system initiates iterative decoding using the first and second decoding schemes (520). For example, the ECC system generates confidence information or soft bit information for each part or bit of the codeword that failed the decoding process. In one example, the confidence information for the soft bit information is generated using the second decoding scheme.

[0104] For example, for each part or bit of a failed codeword, the ECC system generates a representation of the failed codeword (530). For example, the ECC determines hard bit information and soft bit information associated with the bit. In one example, the hard bit information and soft bit information are sensed from the channel and / or memory device.

[0105] In another example, the ECC system also receives and / or determines, as described above, the P parity information for a specific bit or page of the failed codeword (or portion of a codeword), and the Q parity information associated with that specific bit or page of the failed codeword.

[0106] Once the P parity information and Q parity information for a particular bit are determined, the ECC system compares the value for P with the value for Q (540). The ECC system then determines whether the parity information or values ​​match (550). If the ECC system determines that the P value and Q value do not match, the original LLR or reliability of the particular bit remains unchanged, and the process is repeated for the next bit or portion of the codeword.

[0107] However, if the ECC system determines that the P and Q values ​​match or are the same (550), the ECC system compares the P and / or Q values ​​to the hard bit value of the particular bit (560). Based on the comparison, the ECC system increases or decreases the LLR of the particular bit.

[0108] For example, if the values ​​of P and / or Q match the hard bit value of a particular bit, the ECC system increases the original LLR or absolute reliability of the particular bit (590). However, if the ECC system determines that the values ​​of P and / or Q do not match the hard bit value of the particular bit, the ECC system decreases the absolute LLR of the particular bit (580). Method 500 can then be repeated. When the LLR is determined for a particular bit, the newly updated LLR may be used by the first decoding scheme to decode a particular codeword, and method 500 can be repeated.

[0109] Figure 6 illustrates a method 600 for decoding multiple failed codewords using an integrated decoding scheme, as an example. In this example, method 600 is performed by an ECC system, such as the ECC system 180 shown and described with respect to Figure 1. In the example illustrated and described with respect to Figure 6, multiple codewords fail in the decoding process using the first decoding scheme. In addition, the codewords fail due to random errors that exceed the correction capability of the first decoding scheme, but not due to memory defects that corrupt the entire codeword. Furthermore, the number of failed codewords exceeds the number of codewords that can be corrected using the second decoding scheme.

[0110] For example, method 600 is initiated during a decoding operation in which the ECC system determines that the number of failed codewords exceeds the correction capability of the second decoding scheme (610). For example, the second decoding scheme may support decoding of n codewords, where n is greater than 1. However, during a first decoding operation using the first decoding scheme, the ECC system may determine that m codewords have failed to decode, where m is greater than n.

[0111] In such an example, the ECC system generates a list of potential codewords (620). In one example, the list of potential codewords is:

[0112]

number

[0113] To generate a list of potential codewords, various parts of each stripe codeword are erased. Then, potential codewords are generated using a decoding operation that employs a second decoding scheme (e.g., Reed-Solomon decoding scheme). For example, the first and second parts of the first stripe codeword are erased. Then, the first stripe codeword is generated, decoded, and / or corrected using a decoding operation that employs the second decoding scheme. This process is then repeated for each pair of parts within the first stripe codeword. In one example, this process generates soft bit information associated with each part.

[0114] Next, for each potential codeword in the list of potential codewords, soft information or LLR information is calculated (630). For example, as previously described, there are two methods for generating soft information based on a list of codewords: the maximum likelihood method and the maximum posterior method.

[0115] When the LLR for each potential codeword in the list of potential codewords has been determined, the failed codeword (or multiple failed codewords) can be decoded using the newly determined LLR (640).

[0116] Figures 7 and 8 illustrate exemplary storage devices that may be used with, or otherwise implement, various features described herein. For example, the storage devices shown and described with respect to Figures 7 and 8 may include various systems and components similar to those shown and described with respect to Figure 1. For example, the controller 822 shown and described with respect to Figure 8 may be similar to the controller 150 in Figure 1. Similarly, the memory die 808 may be similar to the first memory die 165 and / or the second memory die 170 in Figure 1.

[0117] Figure 7 is a perspective view of a storage device 700 including a three-dimensional (3D) stacked non-volatile memory according to an example. In this example, the storage device 700 includes a substrate 710. Blocks of memory cells are included on or above the substrate 710. The blocks include a first block (BLK0 720) and a second block (BLK1 730). Each block consists of memory cells (e.g., non-volatile memory elements). The substrate 710 also includes a peripheral region 740 having support circuits used by the first and second blocks.

[0118] The substrate 710 also supports the circuitry beneath the blocks, along with one or more lower metal layers patterned into conductive paths to carry signals from the circuitry. In one example, the blocks are formed in the intermediate region 750 of the memory device 700. The memory device also includes an upper region 760. The upper region 760 includes one or more upper metal layers patterned into conductive paths to carry signals from the circuitry. Each block of the memory cell includes a stacked region of the memory cell. In one example, alternating levels of the stack represent word lines. Two blocks are shown, but additional blocks may be used and extend in the x and / or y directions.

[0119] In one example, the plane length of the substrate 710 in the x-direction represents the direction in which the signal path for word lines or control gate lines extends (e.g., the direction of the word line or drain-end selection gate (SGD) line), and the plane width of the substrate 710 in the y-direction represents the direction in which the signal path for bit lines extends (e.g., the direction of the bit line). The z-direction represents the height of the memory device 700.

[0120] Figure 8 is a functional block diagram of a memory device 800 according to an embodiment. In one embodiment, the memory device 800 is similar to the 3D stacked non-volatile memory device 700 shown and described with respect to Figure 7. In one embodiment, the components shown in Figure 8 are electrical circuits. In one embodiment, the memory device 800 includes one or more memory dies 805. Each memory die 805 includes a three-dimensional memory structure 810 of memory cells (e.g., a 3D array of memory cells), a control circuit 815, and a read / write circuit 820. In another embodiment, a two-dimensional array of memory cells can be used. The memory structure 810 is addressable by word lines using a first decoder 825 (e.g., a row decoder) and by bit lines using a second decoder 830 (e.g., a column decoder). The read / write circuit 820 may also include a plurality of sense blocks 835, including SB1, SB2, ..., SBp (e.g., sense circuits), which enable pages of memory cells to be read or programmed in parallel. The sense blocks 835 may include bit line drivers.

[0121] In one example, the controller 840 is contained within the same storage device 800 as one or more memory dies 805. In another example, the controller 840 is formed on a die bonded to the memory dies 805, in which case each memory die 805 may have its own controller 840. In yet another example, the controller die controls all of the memory dies 805. Although a single controller 840 is shown, the storage device 800 may contain multiple controllers, each controller responsible for a different operation as described herein.

[0122] Commands and data are transferred between the host 845 and the controller 840 using the data bus 850. Furthermore, commands and data are transferred between the controller 840 and one or more memory dies 805 via line 855. In one example, the memory die 805 includes a set of input and / or output (I / O) pins connected to line 855.

[0123] The memory structure 810 also includes one or more arrays of memory cells. The memory cells are arranged in a three-dimensional or two-dimensional array. The memory structure 810 includes any type of non-volatile memory formed on one or more physical levels of arrays of memory cells having active regions located above a silicon substrate. The memory structure 810 may also be in a non-volatile memory device having circuits associated with the operation of the memory cells, and the associated circuits may be on or within the substrate.

[0124] The control circuit 815 works together with the read / write circuit 820 to perform memory operations (e.g., erase, program, read, etc.) on the memory structure 810. The control circuit 815 may also include registers, ROM fuses, and other devices for storing default values ​​such as base voltage and other parameters.

[0125] The control circuit 815 also includes a state machine 860, an on-chip address decoder 865, and a power control module. The state machine 860 provides chip-level control of various memory operations, such as selecting memory blocks for programming. The state machine 860 is programmable by software. In another example, the state machine 860 is implemented entirely in hardware (e.g., electrical circuitry) without the use of software.

[0126] The on-chip address decoder 865 provides an address interface between the addresses used by the host 845 and / or the controller 840 and the hardware addresses used by the first decoder 825 and the second decoder 830. The power control module 870 controls the power and voltage supplied to the word lines and bit lines during memory operation. The power control module 870 may include a word line layer in a 3D configuration, selection transistors (e.g., SGS transistors and SGD transistors), and drivers for the source lines. The power control module 870 may include one or more charge pumps for generating voltage.

[0127] The control circuit 815, state machine 860, on-chip address decoder 865, first decoder 825, second decoder 830, power control module 870, sense block 835, read / write circuit 820, and / or controller 840 may be considered as one or more control circuits and / or management circuits that perform some or all of the operations described herein.

[0128] In one example, the controller 840 is an electrical circuit that may be on-chip or off-chip. Furthermore, the controller 840 may include one or more processors 880, a ROM 885, a RAM 890, a memory interface 895, and a host interface 897, all of which can be interconnected. In one example, one or more processors 880 are an example of a control circuit. In other examples, state machines or other custom circuits designed to perform one or more functions may be used. Devices such as the ROM 885 and RAM 890 may contain code, such as an instruction set. One or more of the processors 880 may be operable to execute an instruction set to provide some or all of the functions described herein.

[0129] Alternatively or additionally, one or more of the processors 880 may access code from memory devices within the memory structure 810, such as reserved areas of memory cells connected to one or more word lines. A memory interface 895 communicating with one or more of the ROM 885, RAM 890, and processors 880 may be an electrical circuit providing an electrical interface between the controller 840 and the memory die 805. For example, the memory interface 895 may modify the format or timing of signals, provide buffers, isolate from surges, latch I / O, and so on.

[0130] One or more processors 880 may issue commands to the control circuit 815 or any other component of the memory die 805 using the memory interface 895. The ROM 885, RAM 890, and host interface 897 communicating with one or more processors 880 may be electrical circuits providing an electrical interface between the controller 840 and the host 845. For example, the host interface 897 may modify the format or timing of signals, provide buffers, isolate from surges, latch I / O, etc. Commands and data from the host 845 are received by the controller 840 via the host interface 897. Data sent to the host 845 can be transmitted using the data bus 850.

[0131] Multiple memory elements within the memory structure 810 may be configured to be connected in series or so that each element is individually accessible. As a non-limiting example, a flash memory device with a NAND configuration (e.g., NAND flash memory) typically includes memory elements connected in series. A NAND string is an example of a set of memory cells and selection gate transistors connected in series.

[0132] A NAND flash memory array may be configured such that the array includes multiple NAND strings. In one example, a NAND string contains multiple memory cells sharing a single bit line and is accessed as a group. Alternatively, the memory elements may be configured such that each memory element is individually accessible (e.g., a NOR memory array). The NAND and NOR memory configurations are examples, and memory cells may have other configurations.

[0133] Memory cells may be arranged in an ordered array, such as multiple rows and / or columns, at the level of a single memory device. However, memory elements may be arranged in an irregular or non-orthogonal configuration, or in a structure that is not considered an array.

[0134] In one example, a 3D memory structure may be arranged vertically as a stack of multiple 2D memory devices. In another non-limiting example, a 3D memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main plane of the substrate, such as in the y-direction), each having multiple memory cells. The vertical columns may be arranged as a two-dimensional array of memory cells, with memory cells on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a 3D memory array.

[0135] In another example, in a 3D NAND memory array, memory elements may be coupled to each other to form vertical NAND strings that traverse multiple horizontal memory device levels. Other 3D configurations can be envisioned where some NAND strings contain memory elements within a single memory level, and others contain memory elements that span multiple memory levels. 3D memory arrays can also be designed in NOR and ReRAM configurations.

[0136] Accordingly, examples of the present disclosure describe a method comprising determining that a codeword has failed in a first decoding process using a first decoding scheme, identifying first and second parity information associated with a portion of a codeword, at least based on the determination that the codeword has failed in a first decoding process using a first decoding scheme, wherein the first and second parity information is associated with a second decoding scheme, adjusting the reliability of the portion of the codeword at least based on the first and second parity information, and providing the reliability of the portion of the codeword to the first decoding scheme for a second decoding process. In one example, the first decoding scheme is a low-density parity-check (LDPC) decoding scheme. In one example, the second decoding scheme is an independent-die redundant array (RAID) decoding scheme. In one example, the first parity information is at least based on an XOR operation performed on different portions of a striped codeword associated with the codeword. In one example, the second parity information is at least partially based on multiplying a different portion of the striped codeword associated with the codeword by the codebook associated with the second decoding scheme. In one example, the reliability of a portion of the codeword is adjusted when the first parity information matches the second parity information. In one example, the method also includes increasing the reliability of a portion of the codeword based at least partially on the determination that the first and second parity information matches the hard bit information associated with the codeword. In one example, the method also includes decreasing the reliability of a portion of the codeword based at least partially on the determination that the first and second parity information does not match the hard bit information associated with the codeword.

[0137] The embodiment also describes a data storage device including a controller and an error correction code (ECC) system associated with the controller, which identifies codewords having a number of errors exceeding the correction capability of a first decoding scheme, identifies first parity information and second parity information associated with the codewords, the first parity information and second parity information are associated with a second decoding scheme, and which is capable of calculating the reliability of a portion of a codeword based at least in part on the first parity information and second parity information, and providing the reliability of the portion of a codeword to the first decoding scheme. In one example, the first parity information is at least in part based on an XOR operation performed on different portions of a striped codeword associated with the codeword. In one example, the second parity information is at least in part based on multiplying different portions of a striped codeword associated with the codeword by a codebook associated with the second decoding scheme. In one example, calculating the reliability of a portion of a codeword includes adjusting the reliability of the portion of a codeword when the first parity information matches the second parity information. In one example, calculating the reliability of a portion of a codeword further comprises increasing the reliability of the portion of the codeword based at least in part on the determination that the first and second parity information matches the hard bit information associated with the codeword. In another example, calculating the reliability of a portion of a codeword further comprises decreasing the reliability of the portion of the codeword based at least in part on the determination that the first and second parity information does not match the hard bit information associated with the codeword.

[0138] The example also describes a data storage device comprising a control means and an error correction means associated with the control means, which is capable of identifying a plurality of codewords having a number of errors that exceeds the correction capability of a first decoding scheme, determining that the number of the plurality of codewords exceeds the correction capability of a second decoding scheme, generating a list of potential codewords using at least a portion of the striped codewords associated with the first codeword among the plurality of codewords using the second decoding scheme, determining the reliability of each potential codeword in the list of codewords, and providing at least one potential codeword in the list of codewords to the first decoding scheme. In one example, the first decoding scheme is a low-density parity-check (LDPC) decoding scheme, and the second decoding scheme is an independent-die redundant array (RAID) decoding scheme. In one example, the list of potential codewords is ordered at least in part on a determined probability that each potential codeword in the list of potential codewords contains an error. In one example, the potential codewords in the list of potential codewords are ordered at least in part on the amount of errors. In one example, the error correction means may further operate to compare at least a portion of at least one potential codeword with reliability information associated with a first codeword. In another example, the error correction means may further operate to determine the combined reliability of each of the potential codewords in the list of potential codewords.

[0139] Those skilled in the art will recognize that the technology described herein is not limited to a single specific memory structure, but rather encompasses many related memory structures within the spirit and scope of the technology described herein and as understood by those skilled in the art.

[0140] The descriptions and examples of one or more embodiments provided in this disclosure are not intended in any way to limit or restrict the scope of this disclosure. The embodiments, examples, and details provided in this disclosure are considered sufficient to convey ownership and enable others to create and use the best form of the claimed disclosure.

[0141] The claimed disclosure should not be construed as being limited to any aspects, examples, or details provided herein. Various features (both structural and methodological), whether shown and described together or separately, are intended to be selectively rearranged, included, or omitted to produce embodiments having a particular set of features. While descriptions and examples of this disclosure have been provided, those skilled in the art can envision variations, modifications, and alternative embodiments that fall within the spirit of a broader aspect of the general inventive concept embodied herein, without departing from the broader scope of the claimed disclosure.

[0142] Aspects of the present disclosure are described above with reference to schematic flowcharts and / or schematic block diagrams of methods, apparatus, systems, and computer program products according to embodiments of the present disclosure. It will be understood that each block in the schematic flowcharts and / or schematic block diagrams, and combinations of blocks within the schematic flowcharts and / or schematic block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a computer processor or other programmable data processing device so that instructions executed through the processor or other programmable data processing device create means for performing functions and / or operations specified in one or more blocks in the schematic flowcharts and / or schematic block diagrams.

[0143] References to elements in this specification using designations such as "first," "second," etc., generally do not limit the number or order of those elements. Rather, these designations can be used as a way to distinguish two or more elements or instances of elements. Thus, references to first and second elements do not mean that only two elements may be used, or that the first element precedes the second element. Furthermore, unless otherwise specified, a set of elements may include one or more elements.

[0144] Terms used in the description or claims in the form of “at least one of A, B, or C” or “A, B, C, or any combination thereof” mean “A, B, or C, or any combination of these elements.” For example, this term may include A, or B, or C, or A and B, or A and C, or A and B and C, or 2A, or 2B, or 2C, or 2A and B, etc. As a further example, “at least one of A, B, or C” is intended to include A, B, C, AB, AC, BC, and ABC, as well as multiples of the same member. Similarly, “at least one of A, B, and C” is intended to include A, B, C, AB, AC, BC, and ABC, as well as multiples of the same member.

[0145] Similarly, as used herein, the phrase “and / or” referring to a list of linked items refers to any combination of items. For example, “A and / or B” is intended to include A only, B only, or A and B together. As another example, “A, B, and / or C” is intended to include A only, B only, C only, A and B together, A and C together, B and C together, or A, B and C together.

Claims

1. It is a method, The codeword determines that the first decoding process using the first decoding scheme has failed, Identifying first parity information and second parity information associated with a portion of a codeword, at least in part on determining that the codeword failed in the first decoding process using the first decoding scheme, wherein the first parity information and the second parity information are associated with the second decoding scheme. Adjusting the reliability of the portion of the codeword based at least partially on the first parity information and the second parity information, A method comprising providing the reliability of the portion of the codeword to the first decoding scheme for a second decoding process.

2. The method according to claim 1, wherein the first decoding method is a low-density parity check (LDPC) decoding method.

3. The method according to claim 1, wherein the second decoding method is a redundant array (RAID) decoding method of independent dies.

4. The method according to claim 1, wherein the first parity information is at least partially based on an XOR operation performed on different portions of a striped codeword associated with the codeword.

5. The method according to claim 1, wherein the second parity information is at least partially based on multiplying a different portion of a striped codeword associated with the codeword by a codebook associated with the second decoding scheme.

6. The method according to claim 1, wherein the reliability of the portion of the codeword is adjusted when the first parity information matches the second parity information.

7. The method according to claim 6, further comprising increasing the reliability of the portion of the codeword based at least in part on a determination that the first parity information and the second parity information match hard bit information associated with the codeword.

8. The method according to claim 6, further comprising reducing the reliability of the portion of the codeword based at least in part on the determination that the first parity information and the second parity information do not match the hard bit information associated with the codeword.

9. A data storage device, Controller and An error correction code (ECC) system associated with the controller, Identify codewords having a number of errors that exceeds the correction capability of the first decoding scheme, Identify the first parity information and the second parity information associated with the codeword, and the first parity information and the second parity information are associated with the second decoding scheme. The reliability of a portion of the codeword is calculated based at least partially on the first parity information and the second parity information, and A data storage device comprising: an error correction code (ECC) system operable to provide the reliability of the portion of the codeword to the first decoding scheme.

10. The data storage device according to claim 9, wherein the first parity information is at least partially based on an XOR operation performed on different portions of a striped codeword associated with the codeword.

11. The data storage device according to claim 9, wherein the second parity information is at least partially based on multiplying a different portion of a striped codeword associated with the codeword by a codebook associated with the second decoding scheme.

12. The data storage device according to claim 9, wherein calculating the reliability of the portion of the codeword includes adjusting the reliability of the portion of the codeword if the first parity information matches the second parity information.

13. The data storage device according to claim 12, wherein calculating the reliability of the portion of the codeword further includes increasing the reliability of the portion of the codeword, at least in part on the determination that the first parity information and the second parity information match the hard bit information associated with the codeword.

14. The data storage device according to claim 12, wherein calculating the reliability of the portion of the codeword further comprises reducing the reliability of the portion of the codeword, at least in part, based on the determination that the first parity information and the second parity information do not match the hard bit information associated with the codeword.

15. A data storage device, Control means and Error correction means associated with the control means, Identifying multiple codewords having a number of errors that exceeds the correction capability of the first decoding method, It is determined that the number of the aforementioned codewords exceeds the correction capability of the second decoding method, Using the second decoding method described above, a list of potential codewords is generated using at least a portion of the stripe codewords associated with the first codeword among the plurality of codewords. Determine the reliability of each potential codeword in the aforementioned list of codewords, and A data storage device comprising error correction means operable to provide at least one potential codeword from the list of codewords to the first decoding scheme.

16. The data storage device according to claim 15, wherein the first decoding method is a low-density parity check (LDPC) decoding method, and the second decoding method is an independent die redundant array (RAID) decoding method.

17. The data storage device according to claim 15, wherein the list of potential codewords is ordered at least in part on a determined probability that each potential codeword in the list of potential codewords contains an error.

18. The data storage device according to claim 15, wherein the potential codewords in the list of potential codewords are ordered at least in part on the amount of error.

19. The data storage device according to claim 15, wherein the error correction means is further operable to compare at least a portion of the at least one potential codeword with reliability information associated with the first codeword.

20. The data storage device according to claim 15, wherein the error correction means is further operable to determine the combined reliability of each of the potential codewords in the list of potential codewords.

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