Delay measurement method and communication system

Abstract

Perform high-precision delay measurement. [Solution] Communication device 1 inserts a DM identifier into the first frame signal and starts measuring the delay time. It extracts the DM identifier and the measurement result of the processing time from the second frame signal received from communication device 2. It calculates the delay time of the communication path between communication devices 1 and 2 by subtracting the measurement result of the processing time from the measurement result of the delay time from the insertion of the DM identifier to the detection of the DM identifier contained in the second frame signal. Communication device 2 starts measuring the processing time at the same time as detecting the DM identifier contained in the received first frame signal. It inserts the extracted DM identifier into the second frame signal to be transmitted to communication device 1, and also inserts a value indicating the measurement result of the processing time from the detection of the DM identifier contained in the first frame signal to the insertion of the DM identifier into the second frame signal.

Description

Technical Field

[0001] The present invention relates to a delay measurement method, a communication system, and a communication device.

Background Art

[0002] The standard ODU (Optical channel Data Unit) DM (Delay Measurement) function defined in ITU-T (International Telecommunication Union-Telecommunication Standardization Sector) G.709 is a function for measuring the delay amount of a communication path in frame units (see Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3).

[0003] FIG. 19 is a diagram for explaining a conventional DM function. The communication device 1000 inserts a DM identifier into Row 2 and Col 3 of the overhead (hereinafter, OH) for controlling the ODU frame 2000, and increments a counter for delay measurement for each frame. The insertion of the DM identifier is performed by bit-inverting any bit of the 7 bits of Row 2 and Col 3 of the OH.

[0004] The communication device 1001 extracts the DM identifier from the OH of the ODU frame 2000 transmitted from the communication device 1000. The communication device 1001 inserts the extracted DM identifier into Row 2 and Col 3 of the OH of the ODU frame 2001 to be sent to the communication device 1000. The extraction and insertion of the DM identifier are performed by extracting Row 2 and Col 3 of the OH of the ODU frame 2000 and inserting them into Row 2 and Col 3 of the OH of the ODU frame 2001.

[0005] Communication device 1000 extracts Row2 and Col3 of the OH of ODU frame 2001 transmitted from communication device 1001. Communication device 1000 terminates DM when it receives the same values ​​for Row2 and Col3 inserted into the OH of ODU frame 2000 for three consecutive frames. Communication device 1000 obtains the measurement result of the number of frames from the time of DM identifier insertion to the end of DM from a counter, and subtracts the protection time (3 frames) from the measurement result to determine the delay amount of the communication path between communication device 1000 and 1001.

[0006] Conventional DM functions had the problem that the unit of delay measurement was frames, resulting in a coarse granularity of delay measurement (for example, 1.2 μs for ODU4). Furthermore, at the communication device 1001, which is the loopback point of the DM signal, a delay occurs due to the loopback processing, separate from the delay amount of the communication path, leading to errors in the delay measurement results. Additionally, because the DM function is not defined as a standard for the FlexO (Flexible OTN) frame format, delay measurement could not be performed in applications where ODU OH, such as OIF 400ZR / 800ZR, does not exist.

[0007] Furthermore, conventional DM functions had the drawback of not being able to measure the delay time for both the frame transmission process and the frame reception process within the device. [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] "JT-G709 Interfaces for the Optical Transport Network (OTN)", Information and Communication Technology Committee, March 1, 2011.<https: / / www.ttc.or.jp / application / files / 4615 / 5425 / 1895 / JT-G709v2.1.pdf> [Non-Patent Document 2] “Characteristics of optical transport network hierarchy equipment functional blocks”, ITU-T Recommendation G.798, 2010 [Non-Patent Document 3] “Flexible OTN common elements”, ITU-T Recommendation G.709.1, 2024 [Overview of the Initiative] [Problems that the invention aims to solve]

[0009] The present invention was made to solve the above problems, and aims to provide a delay measurement method, a communication system, and a communication device that can perform delay measurement with high accuracy even for frame formats in which the DM function is not defined by standard.

[0010] Furthermore, the present invention aims to provide a delay measurement method and a communication device that can measure the delay time of the frame transmission process and the frame reception process within the device. [Means for solving the problem]

[0011] The delay measurement method of the present invention comprises: a first step in which a first communication device inserts a DM identifier into a first frame signal to be transmitted to a second communication device connected to it via a network; a second step in which the first communication device starts measuring the delay time simultaneously with the insertion of the DM identifier; a third step in which the first communication device transmits the first frame signal to the second communication device; a fourth step in which the second communication device receives the first frame signal; a fifth step in which the second communication device extracts a DM identifier from the first frame signal; a sixth step in which the second communication device starts measuring the processing time simultaneously with the detection of the DM identifier contained in the first frame signal; and the second communication device inserts the DM identifier extracted in the fifth step into a second frame signal to be transmitted to the first communication device. The method is characterized by including a seventh step of inserting a value indicating the measurement result of the processing time from the detection of the DM identifier included in the first frame signal to the insertion of the DM identifier into the second frame signal, an eighth step of the second communication device transmitting the second frame signal to the first communication device, a ninth step of the first communication device receiving the second frame signal, a tenth step of extracting the DM identifier and the measurement result of the processing time of the second communication device from the second frame signal, and an eleventh step of calculating a value obtained by subtracting the measurement result of the processing time from the measurement result of the delay time from the insertion of the DM identifier into the first frame signal to the detection of the DM identifier included in the second frame signal as the delay time of the communication path between the first communication device and the second communication device.

[0012] Furthermore, one example configuration of the delay measurement method of the present invention is a 12th step in which the first communication device sets a value to be added to the median value of the first FIFO buffer inserted on the path of the first frame signal within its own device when in delay amount notification mode; a 13th step in which the first communication device adjusts the delay amount of the first FIFO buffer based on the value to be added to the median value when in delay amount notification mode; and the second communication device adjusts the delay amount of the second FIFO buffer within its own device based on the value to be added to the median value notified by the first communication device when in delay amount notification mode. The present invention further includes a 14th step of adjusting the delay amount of a second FIFO buffer inserted on the path of a frame signal, wherein the first step includes inserting the DM identifier into the first frame signal in DM mode and inserting a value to be added to the median into the first frame signal in delay amount notification mode, and the fifth step includes extracting the DM identifier from the first frame signal in DM mode and extracting a value to be added to the median from the first frame signal in delay amount notification mode.

[0013] Furthermore, the delay measurement method of the present invention is characterized by including the step of measuring the delay time of a second signal transmitted from the starting end of the parallel signal path, which is located parallel to the starting end of the first signal path, to the ending end of the parallel signal path, which is located parallel to the ending end of the first signal path, in a parallel signal path formed in parallel with the path of a first signal transmitted and received between a first communication device and a second communication device on the opposite side, as the delay time of the path of the first signal. Furthermore, one example configuration of the delay measurement method of the present invention is characterized by further including the steps of setting a value to be added to the median value of FIFO buffers inserted on the path of the first signal and on the parallel signal path, respectively, and adjusting the delay amount of the FIFO buffer based on the value to be added to the median value.

[0014] Furthermore, the communication system of the present invention comprises a first communication device and a second communication device connected to the first communication device via a network, wherein the first communication device includes a first insertion unit configured to insert a DM identifier into a first frame signal to be transmitted to the second communication device, a first transmission unit configured to transmit the first frame signal to the second communication device, a first counter configured to start measuring a delay time simultaneously with the insertion of the DM identifier, a first receiving unit configured to receive a second frame signal transmitted from the second communication device, a first extraction unit configured to extract a DM identifier and a measurement result of the processing time of the second communication device from the second frame signal, and a value obtained by subtracting the measurement result of the processing time from the measurement result of the delay time from the insertion of the DM identifier into the first frame signal to the detection of the DM identifier contained in the second frame signal, The first communication device comprises a delay time calculation unit configured to calculate the delay time of the communication path between the first communication device and the second communication device, the second communication device comprising a second receiving unit configured to receive the first frame signal, a second extraction unit configured to extract a DM identifier from the first frame signal, a second counter configured to start measuring the processing time simultaneously with the detection of the DM identifier contained in the first frame signal, a second insertion unit configured to insert the DM identifier extracted by the second extraction unit into the second frame signal to be transmitted to the first communication device, and to insert a value indicating the measurement result of the processing time from the detection of the DM identifier contained in the first frame signal to the insertion of the DM identifier into the second frame signal, and a second transmitting unit configured to transmit the second frame signal to the first communication device.

[0015] Furthermore, in one configuration example of the communication system of the present invention, the first communication device further comprises a first FIFO buffer inserted on the path of the first frame signal, a delay setting unit configured to set a value to be added to the median value of the first FIFO buffer in delay amount notification mode, and a first delay adjustment unit configured to adjust the delay amount of the first FIFO buffer based on the value to be added to the median value in delay amount notification mode, wherein the first insertion unit of the first communication device inserts the DM identifier into the first frame signal in DM mode, and in delay amount notification mode the first The second communication device is characterized in that it inserts a value to be added to the median value into the frame signal, the second extraction unit of the second communication device extracts the DM identifier from the first frame signal in DM mode, and extracts a value to be added to the median value from the first frame signal in delay amount notification mode, and the second communication device further comprises a second FIFO buffer inserted on the path of the second frame signal, and a second delay adjustment unit configured to adjust the delay amount of the second FIFO buffer based on the value to be added to the median value extracted by the second extraction unit in delay amount notification mode.

[0016] Furthermore, in one configuration example of the communication system of the present invention, the first and second FIFO buffers are asynchronous FIFO buffers with different write and read clocks, and the first and second delay adjustment units adjust the frequency of the read clock by PLL control so that the processing delay amount of the first and second frame signals remains constant, based on the usage amount of the first and second FIFO buffers and the value to be added to the median value. Furthermore, in one configuration example of the communication system of the present invention, the first and second FIFO buffers are synchronous FIFO buffers that share a write clock and a read clock, and the first and second delay adjustment units adjust the read pointers of the first and second FIFO buffers based on the write pointers of the first and second FIFO buffers and the value to be added to the median value so that the processing delay amount of the first and second frame signals becomes constant. Furthermore, in one configuration example of the communication system of the present invention, the first and second FIFO buffers are asynchronous FIFO buffers with different write and read clocks, and the first and second delay adjustment units use a basic read clock with a frequency higher than the design value of the read clock frequency of the first and second FIFO buffers, and output the result of masking the high period of the basic read clock as the read clock of the first and second FIFO buffers, based on the usage amount of the first and second FIFO buffers and the value to be added to the median value, so that the processing delay amount of the first and second frame signals remains constant.

[0017] Furthermore, the communication device of the present invention is characterized by comprising a parallel signal path formed in parallel with the path of a first signal transmitted and received between it and a communication device on the opposite side, and a delay time measurement unit that measures the delay time of a second signal transmitted from the starting end of the parallel signal path, which is located parallel to the starting end of the first signal path, to the end of the parallel signal path, which is located parallel to the end of the first signal path, as the delay time of the first signal path. Furthermore, one example of the configuration of the communication device of the present invention is characterized by further comprising: a first FIFO buffer inserted on the path of the first signal; a second FIFO buffer inserted on the parallel signal path; a delay setting unit configured to set a value to be added to the median value of the first and second FIFO buffers; and a delay adjustment unit configured to adjust the delay amount of the first and second FIFO buffers based on the value to be added to the median value. [Effects of the Invention]

[0018] According to the present invention, the first communication device inserts a DM identifier into the first frame signal and starts measuring the delay time. It extracts the DM identifier and the measurement result of the processing time of the second communication device from the received second frame signal. It calculates the delay time of the communication path between the first and second communication devices by subtracting the measurement result of the processing time from the measurement result of the delay time from the insertion of the DM identifier to the detection of the DM identifier contained in the second frame signal. The second communication device starts measuring the processing time simultaneously with the detection of the DM identifier contained in the first frame signal. It inserts the extracted DM identifier into the second frame signal to be transmitted to the first communication device, and also inserts a value indicating the measurement result of the processing time from the detection of the DM identifier contained in the first frame signal to the insertion of the DM identifier into the second frame signal. As a result, in the present invention, the unit of delay measurement can be set to the signal processing clock period unit, and delay measurement can be performed with higher accuracy than conventional delay measurement methods. Furthermore, in the present invention, delay measurement can be performed for frame formats in which the DM function is not defined by standard. Furthermore, in this invention, the error in delay measurement can be reduced by subtracting the measurement result of the processing time of the second communication device from the measurement result of the delay time from the insertion of the DM identifier to the detection of the DM identifier contained in the second frame signal.

[0019] Furthermore, the present invention allows for the measurement of the delay times of the transmission and reception processes of the first signal within the same communication device by measuring the delay time of the second signal transmitted from the start of the parallel signal path, which is located parallel to the start of the first signal path, to the end of the parallel signal path, which is located parallel to the end of the first signal path, as the delay time of the first signal path. In addition, the present invention allows for delay measurement to be performed in units of signal processing clock cycles, enabling more accurate delay measurement than conventional delay measurement methods. Moreover, the present invention allows for delay measurement for frame formats for which the DM function is not defined as a standard. [Brief explanation of the drawing]

[0020] [Figure 1] Figure 1 is a block diagram showing the configuration of a communication system according to a first embodiment of the present invention. [Figure 2] Figure 2 is a flowchart for explaining the operation at the time of DM of the communication device on the transmission side according to the first embodiment of the present invention. [Figure 3] Figure 3 is a flowchart for explaining the operation at the time of DM of the communication device on the loopback side according to the first embodiment of the present invention. [Figure 4] Figure 4 is a timing chart for explaining the operation at the time of DM of the communication device on the transmission side according to the first embodiment of the present invention. [Figure 5] Figure 5 is a timing chart for explaining the operation at the time of DM of the communication device on the loopback side according to the first embodiment of the present invention. [Figure 6] Figure 6 is a block diagram showing the configuration of a communication system according to a second embodiment of the present invention. [Figure 7] Figure 7 is a flowchart for explaining the operation at the time of DM of the communication device on the transmission side according to the second embodiment of the present invention. [Figure 8] Figure 8 is a flowchart for explaining the operation at the time of DM of the communication device on the loopback side according to the second embodiment of the present invention. [Figure 9] Figure 9 is a block diagram showing the configuration of a FIFO buffer and a delay adjustment unit according to the second embodiment of the present invention. [Figure 10] Figure 10 is a block diagram showing the configuration of a FIFO buffer and a delay adjustment unit according to the third embodiment of the present invention. [Figure 11] Figure 11 is a block diagram showing the configuration of a FIFO buffer and a delay adjustment unit according to the fourth embodiment of the present invention. [Figure 12] Figure 12 is a waveform diagram showing an example of mask control by a mask control unit according to the fourth embodiment of the present invention. [Figure 13] Figure 13 is a block diagram showing the configuration of a communication device according to the fifth embodiment of the present invention. [Figure 14]Figure 14 is a flowchart illustrating the operation of the transmitting side during DM (Direct Debit) of a communication device according to a fifth embodiment of the present invention. [Figure 15] Figure 15 is a flowchart illustrating the operation of the receiving side during DM (Direct Debit) in a communication device according to a fifth embodiment of the present invention. [Figure 16] Figure 16 is a block diagram showing the configuration of a communication device according to the sixth embodiment of the present invention. [Figure 17] Figure 17 is a flowchart illustrating the operation of the transmitting side during DM (Direct Debit) of a communication device according to the sixth embodiment of the present invention. [Figure 18] Figure 18 is a flowchart illustrating the operation of the receiving side during DM (Direct Debit) in a communication device according to the sixth embodiment of the present invention. [Figure 19] Figure 19 is a diagram illustrating the conventional DM function. [Modes for carrying out the invention]

[0021] [First Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Figure 1 is a block diagram showing the configuration of a communication system according to a first embodiment of the present invention. The communication system consists of a communication device 1, a communication device 2, and an optical network 3 connecting the communication device 1 and the communication device 2.

[0022] The communication device 1 includes a mapping processing unit 10 that stores the Ethernet (registered trademark) client to be transmitted to the communication device 2 in the payload of the FlexO frame, an OH insertion unit 11 that inserts a DM identifier into the OH of the FlexO frame signal generated by the mapping processing unit 10, a counter 12 that starts counting a clock for measuring delay time simultaneously with the insertion of the DM identifier, a D / A conversion unit 13 that converts the output of the OH insertion unit 11 from a digital signal to an analog signal, and an optical transmission unit 14 that converts the output of the D / A conversion unit 13 into an optical signal and sends it to the optical network 3.

[0023] Furthermore, the communication device 1 includes an optical receiving unit 15 that converts an optical signal received from the communication device 2 via the optical network 3 into an electrical signal, an A / D conversion unit 16 that converts the output of the optical receiving unit 15 from an analog signal to a digital signal, an OH extraction unit 17 that extracts OH from the FlexO frame signal output of the A / D conversion unit 16, a demapping processing unit 18 that extracts the Ethernet client from the payload of the FlexO frame signal, and a delay time calculation unit 19 that calculates the delay time of the communication path between the communication device 1 and the communication device 2.

[0024] The communication device 2 includes an optical receiving unit 20 that converts an optical signal received from the communication device 1 via the optical network 3 into an electrical signal, an A / D conversion unit 21 that converts the output of the optical receiving unit 20 from an analog signal to a digital signal, an OH extraction unit 22 that extracts a DM identifier from the OH of the FlexO frame signal output of the A / D conversion unit 21, a counter 23 that starts counting a clock for measuring processing time at the same time as the extraction of the DM identifier, and a demapping processing unit 24 that extracts the Ethernet client from the payload of the FlexO frame signal.

[0025] Furthermore, the communication device 2 includes a mapping processing unit 25 that stores the Ethernet client to be transmitted to the communication device 1 in the payload of the FlexO frame, an OH insertion unit 26 that inserts the DM identifier extracted by the OH extraction unit 22 into the OH of the FlexO frame signal generated by the mapping processing unit 25, and also inserts the measurement result of the counter 23 from the extraction to the insertion of the DM identifier, a D / A conversion unit 27 that converts the output of the OH insertion unit 11 from a digital signal to an analog signal, and an optical transmission unit 28 that converts the output of the D / A conversion unit 27 into an optical signal and sends it to the optical network 3.

[0026] Figure 2(A) is a flowchart explaining the transmission operation of communication device 1 during direct current (DM), Figure 2(B) is a flowchart explaining the reception operation of communication device 1 during DM, Figure 3(A) is a flowchart explaining the reception operation of communication device 2 during DM, and Figure 3(B) is a flowchart explaining the transmission operation of communication device 2 during DM. Figure 4 is a timing chart explaining the operation of communication device 1 during DM, and Figure 5 is a timing chart explaining the operation of communication device 2 during DM.

[0027] As shown in Figures 4 and 5, a FlexO frame consists of an AM (Alignment Marker) field, an EOH (Extended Overhead) field, a BOH (Basic Overhead) field, and a payload. One frame has 128 bits in the row direction and 5140 bits in the column direction.

[0028] The mapping processing unit 10 of the communication device 1 generates a FlexO frame signal and stores the Ethernet client to be transmitted to the communication device 2 in the payload of the FlexO frame signal (Figure 2(A) step S100). As shown in Figure 4(A), the OH insertion unit 11 of the communication device 1 inserts a DM identifier into the BOH of the FlexO frame signal 200 generated by the mapping processing unit 10 at the start of DM (Figure 2(A) step S101). The insertion of the DM identifier is performed by bit-flipping the 1st to 7th bits of col29 of the BOH from "0" to "1". It is also possible to bit-flip the bits from "1" to "0". In practice, the DM identifier is always inserted by the OH insertion unit 11. The difference between DM mode and other modes is whether or not the DM identifier is bit-flipped. DM mode and delay amount notification mode are determined using the 8th bit of col29 (i.e., the bit not used in DM). The OH insertion unit 11 also stores "0" in all of col30~31 of the BOH.

[0029] When the OH insertion unit 11 first inserts the DM identifier into the BOH of the FlexO frame signal 200 (YES in step S102 of Figure 2(A)), it causes the counter 12 to start counting the clock for delay time measurement, as shown in Figure 4(C) (step S103 of Figure 2(A)).

[0030] The D / A conversion unit 13 of the communication device 1 converts the FlexO frame signal 200 output from the OH insertion unit 11 into an analog signal (Figure 2(A) step S104). The optical transmission unit 14 of the communication device 1 converts the output of the D / A conversion unit 13 into an optical signal and sends it to the optical network 3 (Figure 2(A) step S105).

[0031] The optical receiving unit 20 of the communication device 2 converts the optical signal received from the communication device 1 via the optical network 3 into an electrical signal (Figure 3(A) step S300). The A / D conversion unit 21 of the communication device 2 converts the output of the optical receiving unit 20 into a digital signal (Figure 3(A) step S301).

[0032] As shown in Figure 5(A), the OH extraction unit 22 of the communication device 2 extracts the value of col29 of the BOH of the FlexO frame signal 200 output from the A / D conversion unit 21 (Figure 3(A) step S302). When the OH extraction unit 22 detects the DM identifier for the first time, i.e., when the 1st to 7th bits of the extracted col29 are bit-inverted to "1", the OH extraction unit 22 causes the counter 23 to start counting the clock for measuring the processing time, as shown in Figure 5(C) (Figure 3(A) step S304).

[0033] The demapping processing unit 24 of the communication device 2 extracts the Ethernet client from the payload of the received FlexO frame signal 200 (Figure 3(A) step S305). Meanwhile, the mapping processing unit 25 of the communication device 2 generates a FlexO frame signal and stores the Ethernet client to be transmitted to the communication device 1 in the payload of the FlexO frame signal (Figure 3(B) step S400).

[0034] As shown in Figure 5(B), the OH insertion unit 26 of the communication device 2 stores the value of col29 extracted by the OH extraction unit 22 in col29 of the BOH of the FlexO frame signal 201 generated by the mapping processing unit 25 (Figure 3(B) step S401). Furthermore, the OH insertion unit 26 stores the count value of the counter 23 from the detection of the DM identifier by the OH extraction unit 22 to the insertion of the DM identifier by the OH insertion unit 26 in col30~31 of the BOH of the FlexO frame signal 201 (Figure 3(B) step S402). In the examples of Figures 5(B) and 5(C), the count value 5130 is stored.

[0035] The D / A conversion unit 27 of the communication device 2 converts the FlexO frame signal 201 output from the OH insertion unit 26 into an analog signal (Figure 3(B) step S403). The optical transmission unit 28 of the communication device 2 converts the output of the D / A conversion unit 27 into an optical signal and sends it to the optical network 3 (Figure 3(B), step S404).

[0036] Next, the optical receiving unit 15 of the communication device 1 converts the optical signal received from the communication device 2 via the optical network 3 into an electrical signal (Figure 2(B) step S200). The A / D conversion unit 16 of the communication device 2 converts the output of the optical receiving unit 15 into a digital signal (Figure 2(B) step S201).

[0037] As shown in Figure 4(B), the OH extraction unit 17 of the communication device 1 extracts the values ​​of col29 and col30~31 of the BOH of the FlexO frame signal 201 output from the A / D conversion unit 16 (Figure 2(B) step S202).

[0038] The delay time calculation unit 19 of the communication device 1 terminates DM when the value of col29 of the BOH extracted by the OH extraction unit 17 matches the value stored in col29 of the BOH of the FlexO frame signal 200 by the OH insertion unit 11, that is, when it detects a DM identifier (YES in step S203 of Figure 2(B)).

[0039] The delay time calculation unit 19 obtains the count value of the counter 12 from the initial insertion of the DM identifier by the OH insertion unit 11 to the detection of the DM identifier. The delay time calculation unit 19 then calculates the delay time between communication device 1 and communication device 2 by subtracting the processing time corresponding to the values ​​of col30~31 of the BOH extracted by the OH extraction unit 17 from the delay time corresponding to the obtained count value (Figure 2(B) step S204).

[0040] The demapping processing unit 18 of the communication device 1 extracts the Ethernet client from the payload of the received FlexO frame signal 201 (Figure 2(B) step S205).

[0041] As described above, in this embodiment, the unit of delay measurement can be set to the signal processing clock period, enabling delay measurement with higher accuracy than conventional delay measurement methods. Furthermore, this embodiment does not depend on the frame structure, and only requires the allocation of 3 bytes of OH for DM processing, so delay measurement can be performed for FlexO frame formats where the DM function is not defined by default. It can also be applied to other frame formats such as OTUCN, not just FlexO. Moreover, in this embodiment, the amount of processing delay generated in communication device 2 is measured in signal processing clock periods and notified to communication device 1, allowing communication device 1 to subtract the processing time of communication device 2 from the measured delay time. As a result, the error in delay measurement can be reduced in this embodiment.

[0042] In this embodiment, the protection stage n is set to 0, but protection stage processing may be performed. That is, the delay time calculation unit 19 of the communication device 1 may terminate DM when the value of col29 of the BOH extracted by the OH extraction unit 17 and the value stored in col29 of the BOH of the FlexO frame signal 200 by the OH insertion unit 11 match consecutively for the protection stage n number of times (for example, 3 frames) (YES in step S203). In this case, the delay time calculation unit 19 obtains the count value of the counter 12 from the first insertion of the DM identifier by the OH insertion unit 11 until the end of DM. The delay time calculation unit 19 then calculates the delay time of the communication path between the communication device 1 and the communication device 2 by subtracting the processing time corresponding to the values ​​of col30~31 of the BOH extracted by the OH extraction unit 17 and the protection time corresponding to the protection stage n (time corresponding to 3 frames) from the delay time corresponding to the obtained count value (step S204).

[0043] [Second Example] Next, a second embodiment of the present invention will be described. Communication devices may be provided with a FIFO (First In, First Out) buffer for clock swapping when the operating clocks inside the communication device are different. In this embodiment, the delay amount of the FIFO buffer is adjusted to make the processing delay amount of the frame signal constant.

[0044] Figure 6 is a block diagram showing the configuration of the communication system according to this embodiment. The communication system of this embodiment consists of a communication device 1a, a communication device 2a, and an optical network 3 connecting the communication device 1a and the communication device 2a.

[0045] Communication device 1a is the same as communication device 1 of the first embodiment, with a FIFO buffer 30 added between the output of the mapping processing unit 10 and the input of the OH insertion unit 11, and a FIFO buffer 31 added between the output of the OH insertion unit 11 and the input of the D / A conversion unit 13. Furthermore, a FIFO buffer 32 is added between the output of the A / D conversion unit 16 and the input of the OH extraction unit 17, a FIFO buffer 33 is added between the output of the OH extraction unit 17 and the input of the demapping processing unit 18, and a delay setting unit 34 and delay adjustment units 35, 36 are also added.

[0046] Communication device 2a is the same as communication device 2 of the second embodiment, with a FIFO buffer 40 added between the output of the A / D conversion unit 21 and the input of the OH extraction unit 22, and a FIFO buffer 41 added between the output of the OH extraction unit 22 and the input of the demapping processing unit 24. Furthermore, a FIFO buffer 42 is added between the output of the mapping processing unit 25 and the input of the OH insertion unit 26, a FIFO buffer 43 is added between the output of the OH insertion unit 26 and the input of the D / A conversion unit 27, and delay adjustment units 44 and 45 are also added.

[0047] Figure 7(A) is a flowchart explaining the transmission operation of communication device 1a during direct current (DM), Figure 7(B) is a flowchart explaining the reception operation of communication device 1a during DM, Figure 8(A) is a flowchart explaining the reception operation of communication device 2a during DM, and Figure 8(B) is a flowchart explaining the transmission operation of communication device 2a during DM.

[0048] The process in step S100 of Figure 7(A) is the same as in the first embodiment. The delay setting unit 34 of the communication device 1a calculates a value to be added to the median value of the FIFO buffer when in delay amount notification mode and notifies the OH insertion unit 11 and delay adjustment units 35, 36 of the communication device 1a (Figure 7(A) step S106). The median value of the FIFO buffer is the delay time from the input to the FIFO buffer to the read from the FIFO buffer. The value to be added to the median value of the FIFO buffer is (Dref-Dm) / 2, where Dref is the nominal delay amount and Dm is the DM measurement value. The nominal delay amount Dref is the reference value of the delay time of the communication path between communication device 1a and communication device 2a, and is a predetermined design value. The DM measurement value Dm is the delay time corresponding to the count value of the counter 12 acquired in step S204 by the delay time calculation unit 19 immediately before step S106. Therefore, in order to calculate the value to be added to the median of the FIFO buffer, it is a requirement that the delay time calculation by the delay time calculation unit 19 (DM mode) has been completed at least once.

[0049] When in delay amount notification mode, the delay adjustment units 35 and 36 of the communication device 1a adjust the delay amounts of the FIFO buffers 31 and 32, respectively, based on the values ​​notified by the delay setting unit 34 (Figure 7(A) step S107).

[0050] Figure 9 is a block diagram showing an example configuration of the FIFO buffer 31 and the delay adjustment unit 35. The delay adjustment unit 35 consists of a usage calculation unit 350 that calculates the usage amount of the FIFO buffer 31, a variable frequency divider 351 that divides the write clock of the FIFO buffer 31, a frequency divider 352 that divides the read clock of the FIFO buffer 31, an exclusive OR circuit (XOR) 353 that performs an exclusive OR operation between the outputs of the frequency divider 351 and the output of the frequency divider 352, a low-pass filter (LPF) 354 that low-pass filters the output of the XOR 353, and a voltage-controlled oscillator (VCO) 355 that outputs a clock with a frequency corresponding to the output of the LPF 354 as the read clock of the FIFO buffer 31. The write clock of the FIFO buffer 31 and the read clock of the FIFO buffer 32 are the same as the clock used for measuring the delay time of the counter 12.

[0051] The usage calculation unit 350 calculates the usage amount of the FIFO buffer 31 by adding the value notified by the delay setting unit 34 to the known median value of the FIFO buffer 31, and then subtracting the delay time from the input of the FIFO buffer 31 to the storage position of the first data in the FIFO buffer 31. The frequency divider 352 divides the Read Clock of the FIFO buffer 31 by a fixed frequency division ratio.

[0052] On the other hand, the variable frequency divider 351 divides the write clock of the FIFO buffer 31 by a variable division ratio. The variable frequency divider 351 divides the write clock of the FIFO buffer 31 by a variable division ratio so that the delay time from the input of the FIFO buffer 31 to the storage position of the first data matches the value notified by the delay setting unit 34 (so that the calculation result of the usage calculation unit 350 becomes 0). The variable frequency divider 351 lowers the frequency of the write divided clock when the usage of the FIFO buffer 31 is small, and raises the frequency of the write divided clock when the usage of the FIFO buffer 31 is large.

[0053] As a result, when the usage of the FIFO buffer 31 is low, the output of the LPF354 becomes low, and the frequency of the Read clock output from the VCO355 becomes low. Conversely, when the usage of the FIFO buffer 31 is high, the output of the LPF354 becomes high, and the frequency of the Read clock output from the VCO355 becomes high.

[0054] The configuration of the FIFO buffer 32 and the delay adjustment unit 36 ​​is the same as that shown in Figure 9. In this way, the processing delay amount of the frame signal (the main signal processing delay amount of the DSP) can be kept constant.

[0055] The OH insertion unit 11 of the communication device 1a inserts a DM identifier into the BOH of the FlexO frame signal 200 generated by the mapping processing unit 10 in DM mode, similar to the first embodiment (Figure 7(A) step S101). As described above, the DM identifier is actually always inserted by the OH insertion unit 11. The difference between DM mode or delay amount notification mode and other modes is whether or not the DM identifier is bit-inverted.

[0056] Furthermore, the OH insertion unit 11 inserts a delay amount notification identifier into the 8th bit of col29 of the BOH of the FlexO frame signal 200 when in delay amount notification mode, and stores the values ​​notified by the delay setting unit 34 in col30~31 of the BOH (Figure 7(A), step S108). The insertion of the delay amount notification identifier is performed by bit-flipping the 8th bit of col29 of the BOH from "0" to "1". When the least significant bit (8th bit) of col29 is "0", it represents DM mode, and when it is "1", it represents delay amount notification mode. In Figure 7(A), for the sake of simplicity, the processing of steps S101 and S108 is shown as being performed simultaneously, but in reality, DM mode and delay amount notification are mutually exclusive, and are performed in an order such as DM → delay amount notification → DM → delay amount notification → ..... When the least significant bit of col29 = 0, it represents DM mode, and when the least significant bit = 1, it represents delay amount notification mode. The processing in steps S102 to S105 in Figure 7(A) is the same as in the first embodiment. Needless to say, the processing in step S103 is not executed in the delay amount notification mode.

[0057] The processing in steps S300 and S301 in Figure 8(A) is the same as in the first embodiment. The OH extraction unit 22 of the communication device 2a extracts the values ​​of col29 and col30~31 of the BOH of the FlexO frame signal 200 output from the A / D conversion unit 21 (step S302a in Figure 8(A)). The processing in steps S303 and S304 in Figure 8(A) is the same as in the first embodiment. It goes without saying that the processing in step S304 is not performed in the delay amount notification mode.

[0058] The OH extraction unit 22 detects the delay amount notification identifier by bit-inverting the first bit of the extracted col29, and determines that the delay amount has been notified from the communication device 1a when the values ​​of the extracted col30 to 31 match consecutively for the number of protection stages n (e.g., 3 frames) (YES in step S306 of Figure 8(A)).

[0059] The OH extraction unit 22 notifies the delay adjustment units 44 and 45 of the communication device 2a of the value to be added to the median value of the FIFO buffer, which is extracted from cols 30 to 31. The delay adjustment units 44 and 45 adjust the delay amounts of the FIFO buffers 40 and 43, respectively, based on the value notified by the OH extraction unit 22 (Figure 8(A), step S307). The configuration of the delay adjustment units 44 and 45 is the same as that of the delay adjustment units 35 and 36. The write clock of the FIFO buffers 40 and 43 is the same as the clock used for measuring the processing time of the counter 23. In this way, the processing delay amount of the frame signal (the main signal processing delay amount of the DSP) can be kept constant. Needless to say, the process in step S307 is not executed in DM mode.

[0060] The process in step S305 of Figure 8(A), and the receiving operation of communication device 1a (Figure 7(B)) and the transmitting operation of communication device 2a (Figure 8(B)) are the same as in the first embodiment. Needless to say, in delay amount notification mode, the process in step S204 of Figure 7(B) and the process in step S402 of Figure 8(B) are not executed.

[0061] [Third embodiment] Figure 10 is a block diagram showing the configuration of the FIFO buffer 31 and delay adjustment unit 35 according to a third embodiment of the present invention. This embodiment is another example of the FIFO buffer and delay adjustment unit of the second embodiment. In this embodiment as well, the configuration of the communication system is the same as in the second embodiment, so it will be described using the reference numerals in Figure 6.

[0062] In this embodiment, the write and read clocks for FIFO buffers 31 and 32 are a common clock, and are the same as the clock used to measure the delay time of counter 12. The write and read clocks for FIFO buffers 40 and 43 are a common clock, and are the same as the clock used to measure the processing time of counter 23.

[0063] The delay adjustment unit 35 in this embodiment consists of a Read pointer output unit 356 that outputs a value obtained by subtracting from the Write pointer of the FIFO buffer 31 a value obtained by adding a value notified by the delay setting unit 34 to the known median value of the FIFO buffer 31, as the Read pointer of the FIFO buffer 31.

[0064] The configuration of FIFO buffers 32, 40, and 43 is the same as that of FIFO buffer 31 in Figure 10. The configuration of delay adjustment units 36, 44, and 45 is the same as that of delay adjustment unit 35 in Figure 10. On the communication device 2a side, the Read pointer output units 356 that constitute the delay adjustment units 44 and 45 should output the Read pointers of FIFO buffers 40 and 43 by subtracting from the Write pointers of FIFO buffers 40 and 43 the value obtained by adding the value notified by the OH extraction unit 22 to the known median value of FIFO buffers 40 and 43, respectively.

[0065] Thus, in this embodiment, the processing delay amount of the frame signal (the main signal processing delay amount of the DSP) can be kept constant, similar to the second embodiment. However, the second embodiment is a hitless configuration using a PLL (Phase Locked Loop) control method in which the main signal passing through FIFO buffers 31, 32, 40, and 43 is not interrupted. In contrast, in this embodiment, the Read pointer jumps according to the value to be added to the median value, so an interruption occurs in the main signal.

[0066] [Fourth embodiment] Figure 11 is a block diagram showing the configuration of a FIFO buffer 31 and a delay adjustment unit 35 according to a fourth embodiment of the present invention. This embodiment is another example of the FIFO buffer and delay adjustment unit of the second embodiment. In this embodiment as well, the configuration of the communication system is the same as in the second embodiment, so it will be described using the reference numerals in Figure 6.

[0067] The delay adjustment unit 35 of this embodiment consists of a usage calculation unit 357 that calculates the usage amount of the FIFO buffer 31, a determination unit 358 that compares the calculation result of the usage calculation unit 357 with a value notified by the delay setting unit 34, a read clock generation unit 359 that generates a basic read clock with a duty cycle of 50%, a storage unit 360 that stores a predetermined denominator value of the mask rate of the basic read clock, a storage unit 361 that stores a predetermined numerator value of the mask rate for slowing down the read clock, a storage unit 362 that stores a predetermined numerator value of the mask rate for speeding up the read clock, a selector 363 that selects either the value of the storage unit 361 or the storage unit 362 according to the determination result of the determination unit 358, and a mask control unit 364 that outputs the result of masking the high period of the basic read clock with a mask rate determined by the denominator value stored in the storage unit 360 and the numerator value output from the selector 363 as the read clock of the FIFO buffer 31.

[0068] The Read Clock generation unit 359 generates a basic Read Clock with a frequency slightly higher than the reference value (design value) of the Read Clock frequency. The usage calculation unit 357 calculates the usage amount of the FIFO buffer 31 by subtracting the known median value of the FIFO buffer 31 from the delay time from writing to reading from the FIFO buffer 31.

[0069] The memory unit 361 stores in advance a value for the numerator of the mask ratio that is slightly smaller than the reference value of the numerator, which is such that the average frequency of the Read clock output from the mask control unit 364 becomes the reference value of the Read clock frequency. The memory unit 362 stores in advance a value for the numerator that is slightly larger than the reference value of the numerator. The determination unit 358 compares the calculation result of the usage calculation unit 357 with the value notified by the delay setting unit 34.

[0070] If the determination unit 358 determines that the value notified by the delay setting unit 34 is less than the usage amount of the FIFO buffer 31, selector 363 selects and outputs the numerator value stored in the storage unit 362. If the determination unit 358 determines that the value notified by the delay setting unit 34 is more than the usage amount of the FIFO buffer 31, selector 363 selects and outputs the numerator value stored in the storage unit 361. If the determination unit 358 determines that the usage amount of the FIFO buffer 31 and the value notified by the delay setting unit 34 match, selector 363 maintains the previous selection.

[0071] The mask control unit 364 outputs the result of masking the high period of the basic read clock with a mask rate determined by the denominator value stored in the memory unit 360 and the numerator value output from the selector 363, as the read clock for the FIFO buffer 31. An example of mask control by the mask control unit 364 is shown in Figure 12. In the example in Figure 12, the mask rate is set to 50% for clarity. 300 is the basic read clock with a duty cycle of 50%, and 301 is the read clock after mask control output from the mask control unit 364 to the FIFO buffer 31.

[0072] In a real-world example, the frequency of the basic Read clock is, for example, 103MHz, the reference value of the Read clock frequency is, for example, 100MHz, the reference value of the numerator of the mask rate is, for example, 100000000, the value of the denominator stored in memory unit 360 is, for example, 103000000, the value of the numerator stored in memory unit 361 is, for example, 99990000, and the value of the numerator stored in memory unit 362 is, for example, 100010000.

[0073] In this way, by lowering the Read clock frequency when the FIFO buffer 31 is not being used, and increasing the Read clock frequency when the FIFO buffer 31 is being used, the processing delay amount of the frame signal (the main signal processing delay amount of the DSP) can be kept constant.

[0074] The configuration of FIFO buffers 32, 40, and 43 is the same as that of FIFO buffer 31 in Figure 11. The configuration of delay adjustment units 36, 44, and 45 is the same as that of delay adjustment unit 35 in Figure 11. In the case of the communication device 2a, the determination unit 358 of the delay adjustment units 44 and 45 should compare the calculation result of the usage calculation unit 357 with the value notified from the OH extraction unit 22.

[0075] [Fifth Example] In the first to fourth embodiments, it is possible to measure the delay time of the communication path between communication devices 1,1a and 2,2a, but it is not possible to measure the delay times of the transmission process and the reception process within the same communication device. This embodiment aims to solve this problem.

[0076] Figure 13 is a block diagram showing the configuration of a communication device according to this embodiment. The communication device 5 of this embodiment includes a mapping processing unit 50 that stores an Ethernet client to be transmitted to a communication device on the opposite side (not shown) in the payload of a FlexO frame, a processing unit 51 that performs encoding, symbol mapping, waveform shaping, pre-equalization, and other processing on the output of the mapping processing unit 50, a D / A conversion unit 52 that converts the output of the processing unit 51 from a digital signal to an analog signal, an optical transmission unit 53 that converts the output of the D / A conversion unit 52 into an optical signal and sends it to an optical network, a mapping processing unit 54 that performs the same processing as the mapping processing unit 50 on a second signal propagated by a parallel signal path formed in parallel with the signal path input to the mapping processing unit 50, a processing unit 55 that performs the same processing as the processing unit 51 on the output of the mapping processing unit 54, and a delay time measurement unit 56 that measures the delay time from the input of the mapping processing unit 54 to the processing unit 55.

[0077] Furthermore, the communication device 5 includes an optical receiving unit 58 that converts an optical signal received from the opposing communication device via an optical network into an electrical signal, an A / D conversion unit 59 that converts the output of the optical receiving unit 58 from an analog signal into a digital signal, a processing unit 60 that performs processing such as wavelength dispersion compensation, equalization, error correction, symbol demapping, and signal synchronization on the output of the A / D conversion unit 59, a demapping processing unit 61 that extracts the Ethernet client from the payload of the FlexO frame signal, a processing unit 62 that performs the same processing as the processing unit 60 on a second signal propagated by a parallel signal path formed in parallel with the signal path input to the processing unit 60, a demapping processing unit 63 that performs the same processing as the demapping processing unit 61 on the output of the processing unit 62, and a delay time measurement unit 64 that measures the delay time from the processing unit 62 to the output of the demapping processing unit 63.

[0078] In the first to fourth embodiments, for the sake of simplicity, the description of the processing unit located between the OH insertion units 11 and 26 and the D / A conversion units 13 and 27 (corresponding to processing unit 51 in Figure 13) has been omitted. Similarly, the description of the processing unit located between the A / D conversion units 16 and 21 and the OH extraction units 17 and 22 (corresponding to processing unit 60 in Figure 13) has been omitted.

[0079] Figure 14 is a flowchart illustrating the operation of the transmitting side of communication device 5 during direct current (DM), and Figure 15 is a flowchart illustrating the operation of the receiving side of communication device 5 during DM. The mapping processing unit 50 of the communication device 5 generates a FlexO frame signal and stores the Ethernet client to be transmitted to the opposing communication device in the payload of the FlexO frame signal (Figure 14, step S500). The processing unit 51 of the communication device 5 performs digital signal processing such as encoding, symbol mapping, waveform shaping, and pre-equalization on the output of the mapping processing unit 50 (Figure 14, step S501).

[0080] The D / A conversion unit 52 of the communication device 5 converts the output of the processing unit 51 into an analog signal (Figure 14, step S502). The optical transmission unit 53 of the communication device 5 converts the output of the D / A conversion unit 52 into an optical signal and sends it to the optical network (Figure 14, step S503).

[0081] Within the communication device 5, a parallel signal path for the transmitting side is formed in parallel with the main signal path for the transmitting side, from the input terminal of the mapping processing unit 50 to the output terminal of the processing unit 51. At the beginning of the parallel signal path, which is located parallel to the input terminal of the mapping processing unit 50, is the input terminal of a dummy mapping processing unit 54 for delay time measurement. At the end of the parallel signal path, which is located parallel to the output terminal of the processing unit 51, is the output terminal of a dummy processing unit 55 for delay time measurement. The circuit is arranged so that the delay time from the input terminal of the mapping processing unit 54 to a predetermined measurement point in the processing unit 55 (a point where bit inversion for DM can be detected) is the same as the delay time from the input terminal of the mapping processing unit 50 to a predetermined intermediate point in the processing unit 51 (a point where bit inversion for DM can be detected).

[0082] At the start of DM, the mapping processing unit 54 inverts one bit of the input parallel signal (Figure 14, step S504). Simultaneously with the bit inversion by the mapping processing unit 54, the delay time measurement unit 56 starts counting the clock for delay time measurement (Figure 14, step S505).

[0083] When the delay time measurement unit 56 detects a bit inversion of the parallel signal at a predetermined measurement point in the processing unit 55 (YES in step S506 of Figure 14), it acquires a count value from the bit inversion by the mapping processing unit 54 to the detection of the bit inversion at the measurement point of the processing unit 55, and calculates a delay time corresponding to the acquired count value as the delay time of the main signal path on the transmitting side from the input terminal of the mapping processing unit 50 to a predetermined intermediate point in the processing unit 51 (step S507 of Figure 14).

[0084] Meanwhile, the optical receiving unit 58 of the communication device 5 converts the optical signal received from the opposing communication device via the optical network into an electrical signal (Figure 15, step S600). The A / D conversion unit 59 of the communication device 5 converts the output of the optical receiving unit 58 into a digital signal (Figure 15, step S601).

[0085] The processing unit 60 of the communication device 5 performs digital signal processing on the output of the A / D conversion unit 59, including wavelength dispersion compensation, equalization, error correction, symbol demapping, and signal synchronization (Figure 15, step S602). The demapping processing unit 61 of the communication device 5 extracts the Ethernet client from the payload of the FlexO frame output from the processing unit 60 (Figure 15, step S603).

[0086] Within the communication device 5, a parallel signal path for the receiving side is formed in parallel with the main signal path for the receiving side, from the input terminal of the processing unit 60 to the output terminal of the demapping processing unit 61. At the start of the parallel signal path, which is located parallel to the input terminal of the processing unit 60, is the input terminal of a dummy processing unit 62 for delay time measurement. At the end of the parallel signal path, which is located parallel to the output terminal of the demapping processing unit 61, is the output terminal of a dummy demapping processing unit 63 for delay time measurement. The circuit is arranged so that the delay time from a predetermined measurement start point in the processing unit 62 (a point where bit inversion for DM is possible) to the output terminal of the demapping processing unit 63 is the same as the delay time from a predetermined intermediate point in the processing unit 60 (a point where bit inversion for DM is possible) to the output terminal of the demapping processing unit 61.

[0087] At the start of DM, the processing unit 62 inverts one bit of the parallel signal input to the internal measurement start point (Figure 15, step S604). Simultaneously with the bit inversion by the processing unit 62, the delay time measurement unit 64 starts counting the clock for delay time measurement (Figure 15, step S605).

[0088] When the delay time measurement unit 64 detects a bit inversion of the parallel signal at the output of the demapping processing unit 63 (YES in step S606 of Figure 15), it acquires a count value from the bit inversion by the processing unit 62 to the detection of the bit inversion at the output of the demapping processing unit 63, and calculates a delay time corresponding to the acquired count value as the delay time of the main signal path on the transmitting side from a predetermined intermediate point in the processing unit 60 to the output terminal of the demapping processing unit 61 (step S607 of Figure 15).

[0089] Thus, in this embodiment, the delay times of both the transmission and reception processes of the main signal within the same communication device can be measured. Furthermore, in this embodiment, the unit of delay measurement can be the signal processing clock period, enabling more accurate delay measurement than conventional delay measurement methods. In addition, this embodiment can perform delay measurement for FlexO frame formats where the DM function is not defined by default. Moreover, it can be applied not only to FlexO but also to other frame formats such as OTUCN. However, in this embodiment, if processing such as scrambling, symbol mapping, or interleaving is performed in processing units 51 and 55, it becomes impossible to detect bit inversion, so the delay time that can be measured is the delay time from the input terminal of the mapping processing unit 50 to the midpoint of processing unit 51. Similarly, since bit inversion for DM cannot be performed until processing such as symbol demapping is completed in processing units 60 and 62, the delay time that can be measured is the delay time from the midpoint of processing unit 60 to the output terminal of the demapping processing unit 61. Another example will be described later.

[0090] [Sixth Embodiment] In the fifth embodiment, as in the second to fourth embodiments, it is possible to adjust the delay amount of the FIFO buffer. Figure 16 is a block diagram showing the configuration of the communication device according to this embodiment.

[0091] The communication device 5a of this embodiment is the same as the communication device 5 of the fifth embodiment, but with the addition of a FIFO buffer 66 on the main signal path on the transmitting side between the output of the mapping processing unit 50 and the input of the processing unit 51, and a FIFO buffer 67 on the parallel signal path on the transmitting side between the output of the mapping processing unit 54 and the input of the processing unit 55. Furthermore, a FIFO buffer 68 is added on the main signal path on the receiving side between the output of the processing unit 60 and the input of the demapping processing unit 61, and a FIFO buffer 69 is added on the parallel signal path on the receiving side between the output of the processing unit 62 and the input of the demapping processing unit 63. In addition, delay setting units 70, 72 and delay adjustment units 71, 73 are added.

[0092] Figure 17 is a flowchart illustrating the operation of the transmitting side of communication device 5a during direct current (DM), and Figure 18 is a flowchart illustrating the operation of the receiving side of communication device 5a during DM. The process in steps S500 to S503 in Figure 17 is the same as in the fifth embodiment.

[0093] The delay setting unit 70 of the communication device 5a calculates a value to be added to the median value of the transmitting FIFO buffers 66 and 67 and notifies the delay adjustment unit 71 of the communication device 5a (Figure 17, step S508). The median value of the FIFO buffers 66 and 67 is the delay time from the input to the reading of the FIFO buffers 66 and 67. The value to be added to the median value of the FIFO buffers 66 and 67 is (Dtxref - Dmtx) / 2, where Dtxref is the nominal delay amount of the transmitting side and Dmtx is the DM measurement value of the transmitting side. The nominal delay amount Dtxref is the reference value of the delay time of the main signal path of the transmitting side and is a predetermined design value. The DM measurement value Dmtx is the delay time calculated by the delay time measurement unit 56 in step S507 immediately before step S508. Therefore, in order to calculate the value to be added to the median of the FIFO buffers 66 and 67, it is a requirement that the delay time calculation by the delay time measurement unit 56 has been completed at least once.

[0094] The delay adjustment unit 71 of the communication device 5a adjusts the delay amount of the FIFO buffers 66 and 67 based on the value notified by the delay setting unit 70 (step S510 in Figure 17). Any of the configurations of the FIFO buffers 66 and 67 and the delay adjustment unit 71 from the second to fourth embodiments may be used. The processing in steps S504 to S507 in Figure 17 is the same as in the fifth embodiment.

[0095] The processing in steps S600 to S603 in Figure 18 is the same as in the fifth embodiment. The delay setting unit 72 of the communication device 5a calculates a value to be added to the median value of the receiving side's FIFO buffers 68 and 69 and notifies the delay adjustment unit 73 of the communication device 5a (step S608 in Figure 18). The median value of the FIFO buffers 68 and 69 is the delay time from the input to the FIFO buffers 68 and 69 to the read from the FIFO buffers 68 and 69. The value to be added to the median value of the FIFO buffers 68 and 69 is (Drxref - Dmrx) / 2, where Drxref is the nominal delay amount of the receiving side and Dmrx is the DM measurement value of the receiving side. The nominal delay amount Drxref is the reference value of the delay time of the main signal path of the receiving side and is a predetermined design value. The DM measurement value Dmrx is the delay time calculated in step S607 by the delay time measurement unit 64 immediately before step S608. Therefore, in order to calculate the value to be added to the median of the FIFO buffers 68 and 69, it is a requirement that the delay time calculation by the delay time measurement unit 64 has been completed at least once.

[0096] The delay adjustment unit 73 of the communication device 5a adjusts the delay amount of the FIFO buffers 68 and 69 based on the value notified by the delay setting unit 72 (step S610 in Figure 18). Any of the configurations of the FIFO buffers 68 and 69 and the delay adjustment unit 73 can be used from the second to fourth embodiments. The processing in steps S604 to S608 in Figure 18 is the same as in the fifth embodiment. Thus, in this embodiment, the processing delay amount of the frame signal (the main signal processing delay amount of the DSP) can be kept constant.

[0097] In the fifth and sixth embodiments, the parallel signal path is provided with a circuit that performs the same processing as the main signal. However, as explained in the fifth embodiment, the delay time that can be measured is the delay time from the input terminal of the mapping processing unit 50 to the intermediate point of the processing unit 51, and the delay time from the intermediate point of the processing unit 60 to the output terminal of the demapping processing unit 61. Therefore, a parallel signal path may be provided that performs processing that propagates the signal with the same delay as the main signal. That is, even if the main signal has multiple bits per clock cycle (for example, 128 bits), the parallel signal may be a signal that notifies only 1 bit of delay information. This makes it possible to measure the delay time from the input terminal of the mapping processing unit 50 to the output terminal of the processing unit 51, and the delay time from the input terminal of the processing unit 60 to the output terminal of the demapping processing unit 61. If the parallel signal is 1 bit, it is sufficient to provide only the parallel signal path, and it is not necessary to provide dummy mapping processing units 54, 55, 62 and demapping processing unit 63.

[0098] The mapping processing units 10, 24, 25, 50, 54, the demapping processing units 18, 24, 61, 63, the OH insertion units 11, 26, the counters 12, 23, the OH extraction units 17, 22, the delay time calculation unit 19, the FIFO buffers 30-33, 40-43, 66-69, the delay setting units 34, 70, 72, the delay adjustment units 35, 36, 44, 45, 71, 73, the processing units 51, 55, 60, 62, and the delay time measurement units 56, 64 described in the first to sixth embodiments can be implemented, for example, by a DSP (Digital Signal Processor). Alternatively, some of these configurations may be implemented by software processing on a computer equipped with a CPU (Central Processing Unit), a storage device, and an interface. [Explanation of symbols]

[0099] 1,1a,2,2a,5,5a…Communication device, 3…Optical network, 10,25,50,54…Mapping processing unit, 18,24,61,63…Demapping processing unit, 11,26,54…OH insertion unit, 12,23…Counter, 13,27,52…D / A conversion unit, 14,28,53…Optical transmission unit, 15,20,58…Optical reception unit, 16,21,59…A / D conversion unit, 17,22…OH extraction unit, 19…Delay time calculation unit, 30~33,40~43,66~69…FIFO buffer, 3 4, 70, 72... Delay setting unit; 35, 36, 44, 45, 71, 73... Delay adjustment unit; 51, 55, 60, 62... Processing unit; 56, 64... Delay time measurement unit; 350, 357... Usage amount calculation unit; 351... Variable frequency divider; 352... Frequency divider; 353... Exclusive OR circuit; 354... Low-pass filter; 355... Voltage-controlled oscillator; 356... Read pointer output unit; 358... Determination unit; 359... Read clock generation unit; 360~362... Memory unit; 363... Selector; 364... Mask control unit.

Claims

1. The first step is for the first communication device to insert a DM identifier into a first frame signal to be transmitted to a second communication device connected to it via a network, The first communication device starts measuring the delay time simultaneously with the insertion of the DM identifier in a second step, A third step in which the first communication device transmits the first frame signal to the second communication device, The second communication device receives the first frame signal in a fourth step, The second communication device performs a fifth step of extracting a DM identifier from the first frame signal, The second communication device starts measuring the processing time simultaneously with detecting the DM identifier included in the first frame signal, A seventh step in which the second communication device inserts the DM identifier extracted in the fifth step into the second frame signal to be transmitted to the first communication device, and also inserts a value indicating the measurement result of the processing time from the detection of the DM identifier contained in the first frame signal to the insertion of the DM identifier into the second frame signal, The eighth step is for the second communication device to transmit the second frame signal to the first communication device, The first communication device receives the second frame signal in a ninth step, A tenth step of extracting a DM identifier and the measurement result of the processing time of the second communication device from the second frame signal, A delay measurement method characterized by including an eleventh step of calculating a value obtained by subtracting the measurement result of the processing time from the measurement result of the delay time from the insertion of a DM identifier into the first frame signal to the detection of a DM identifier contained in the second frame signal, as the delay time of the communication path between the first communication device and the second communication device.

2. In the delay measurement method according to claim 1, The first communication device, in delay amount notification mode, sets a value to be added to the median value of the first FIFO buffer inserted on the path of the first frame signal within the device, A thirteenth step in which the first communication device adjusts the delay amount of the first FIFO buffer based on a value to be added to the median value when in delay amount notification mode, The second communication device further includes a 14th step in which, in delay amount notification mode, the second communication device adjusts the delay amount of the second FIFO buffer inserted into the path of the second frame signal within its own device based on a value to be added to the median value notified by the first communication device, The first step includes inserting the DM identifier into the first frame signal when in DM mode, and inserting a value to be added to the median value into the first frame signal when in delay amount notification mode. The fifth step is a delay measurement method characterized by including the step of extracting the DM identifier from the first frame signal when in DM mode, and extracting a value to be added to the median value from the first frame signal when in delay amount notification mode.

3. A delay measurement method characterized by including the step of measuring the delay time of a second signal transmitted from the starting end of the parallel signal path, which is located parallel to the starting end of the first signal path, to the ending end of the parallel signal path, which is located parallel to the ending end of the first signal path, in a parallel signal path formed in parallel with the path of a first signal transmitted and received between a first communication device and a second communication device on the opposite side, as the delay time of the path of the first signal.

4. In the delay measurement method according to claim 3, The steps include setting a value to be added to the median value of the FIFO buffers inserted on the path of the first signal and on the parallel signal path, respectively, A delay measurement method further comprising the step of adjusting the delay amount of the FIFO buffer based on a value to be added to the median value.

5. The system comprises a first communication device and a second communication device connected to the first communication device via a network. The first communication device is A first insertion unit configured to insert a DM identifier into a first frame signal to be transmitted to the second communication device, A first transmitting unit configured to transmit the first frame signal to the second communication device, A first counter configured to start measuring the delay time simultaneously with the insertion of the DM identifier, A first receiving unit configured to receive a second frame signal transmitted from the second communication device, A first extraction unit configured to extract a DM identifier and the measurement result of the processing time of the second communication device from the second frame signal, The system includes a delay time calculation unit configured to calculate the delay time between the first communication device and the second communication device by subtracting the measurement result of the processing time from the measurement result of the delay time from the insertion of the DM identifier into the first frame signal to the detection of the DM identifier contained in the second frame signal, The second communication device is A second receiving unit configured to receive the first frame signal, A second extraction unit configured to extract a DM identifier from the first frame signal, A second counter configured to start measuring the processing time simultaneously with the detection of the DM identifier included in the first frame signal, A second insertion unit is configured to insert the DM identifier extracted by the second extraction unit into the second frame signal to be transmitted to the first communication device, and to insert a value indicating the measurement result of the processing time from the detection of the DM identifier contained in the first frame signal to the insertion of the DM identifier into the second frame signal, A communication system characterized by comprising a second transmitting unit configured to transmit the second frame signal to the first communication device.

6. In the communication system described in claim 5, The first communication device is A first FIFO buffer inserted on the path of the first frame signal, A delay setting unit configured to set a value to be added to the median value of the first FIFO buffer when in delay amount notification mode, The system further includes a first delay adjustment unit configured to adjust the delay amount of the first FIFO buffer based on a value to be added to the median value when in delay amount notification mode, The first insertion unit of the first communication device inserts the DM identifier into the first frame signal when in DM mode, and inserts a value to be added to the median value into the first frame signal when in delay amount notification mode. The second extraction unit of the second communication device extracts the DM identifier from the first frame signal in DM mode, and extracts a value to be added to the median value from the first frame signal in delay amount notification mode. The second communication device is A second FIFO buffer inserted on the path of the second frame signal, A communication system further comprising a second delay adjustment unit configured to adjust the delay amount of the second FIFO buffer based on a value to be added to the median value extracted by the second extraction unit when in delay amount notification mode.

7. In the communication system according to claim 6, The first and second FIFO buffers are asynchronous FIFO buffers with different write and read clocks. A communication system characterized in that the first and second delay adjustment units adjust the frequency of the Read clock by PLL control so that the processing delay amount of the first and second frame signals remains constant, based on the usage amount of the first and second FIFO buffers and the value to be added to the median value.

8. In the communication system according to claim 6, The first and second FIFO buffers are synchronous FIFO buffers that share a write clock and a read clock. A communication system characterized in that the first and second delay adjustment units adjust the Read pointers of the first and second FIFO buffers so that the processing delay amount of the first and second frame signals remains constant, based on the Write pointers of the first and second FIFO buffers and the value to be added to the median value.

9. In the communication system according to claim 6, The first and second FIFO buffers are asynchronous FIFO buffers with different write and read clocks. A communication system characterized in that the first and second delay adjustment units use a basic read clock with a frequency higher than the design value of the read clock frequency of the first and second FIFO buffers, and output the result of masking the high period of the basic read clock as the read clock of the first and second FIFO buffers, based on the usage amount of the first and second FIFO buffers and the value to be added to the median, so that the processing delay amount of the first and second frame signals becomes constant.

10. A parallel signal path formed in parallel with the path of the first signal transmitted and received between the opposing communication device and the other party, A communication device comprising: a delay time measuring unit that measures the delay time of a second signal transmitted from the starting end of the parallel signal path, which is located parallel to the starting end of the first signal path, to the end of the parallel signal path, which is located parallel to the end of the first signal path, as the delay time of the first signal path.

11. In the communication device according to claim 10, A first FIFO buffer inserted on the path of the first signal, A second FIFO buffer inserted on the aforementioned parallel signal path, A delay setting unit configured to set a value to be added to the median value of the first and second FIFO buffers, A communication device further comprising a delay adjustment unit configured to adjust the delay amounts of the first and second FIFO buffers based on a value to be added to the median value.

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