Electric motor control unit

Abstract

When the drive current flowing through multiple winding sets of an electric motor is controlled by multiple control units, the timing difference between the control units is suppressed. [Solution] The timer units 50a and 50b generate a timer value that increases at a constant speed and a periodic timer value that increases from a minimum to a maximum value at a constant speed and immediately returns to the minimum value when it reaches the maximum value. The master control unit 41a outputs a synchronization signal for resetting the periodic timer value of the slave control unit 41b, based on the periodic timer value of the master control unit 41a. The slave control unit 41b stores the timer value and the periodic timer value at the timing of the synchronization signal, calculates a clock difference based on the difference between the timer values ​​at multiple different timings, calculates the phase difference between the periodic timer values ​​of the master control unit 41a and the slave control unit 41b based on the stored periodic timer value, and corrects the maximum value of the periodic timer value based on the clock difference and the phase difference.

Description

Technical Field

[0001] The present invention relates to a control device for an electric motor.

Background Art

[0002] The electric motor control device described in Patent Document 1 below includes a plurality of arithmetic control devices that respectively generate drive control commands for an electric motor having a plurality of winding sets, and a plurality of drive circuits that respectively drive power switching elements that turn on and off the power supplied to the plurality of winding sets based on the drive control commands.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In driving an electric motor having a plurality of winding sets, when controlling the currents flowing through the plurality of winding sets by a plurality of control units, if the periods and phases of the clocks of the respective control units are different, the timing of changing the current command value, the output timing of the duty command based on the current command value, and the acquisition timing of the sensor signals (motor current value, rotational speed, etc.) used for motor control will be different for each control unit (for each winding set). As a result, there is a risk of torque fluctuations and generation of operating noise in the electric motor. An object of the present invention is to suppress a deviation in control timing between a plurality of control units when controlling the currents flowing through a plurality of winding sets in driving an electric motor having a plurality of winding sets.

Means for Solving the Problems

[0005] According to one aspect of the present invention, a control device is provided for controlling the drive of an electric motor having a plurality of winding sets. The control device comprises a plurality of drive circuits corresponding to each of the plurality of winding sets, and a plurality of control units that calculate control signals for controlling each of the plurality of drive circuits. Each of the plurality of control units comprises a timer unit that generates a timer value and a periodic timer value for determining the timing of control signal generation, and a signal generation unit that generates a control signal for controlling the drive circuit corresponding to the control unit at a timing based on the periodic timer value generated by the timer unit.

[0006] The timer unit generates a count value that increases at a constant rate as the timer value, and also generates a count value that increases at a constant rate from a minimum to a maximum value, and immediately returns to the minimum value when it reaches the maximum value as the periodic timer value. The master control unit, which is one of the multiple control units, outputs a synchronization signal to reset the periodic timer value corresponding to the slave control unit, which is one of the other control units, based on the periodic timer value corresponding to the master control unit.

[0007] The slave control unit stores the timer value and periodic timer value corresponding to the slave control unit at the timing indicated by the synchronization signal. Based on the difference between the timer values ​​stored at multiple different timings, it calculates the clock difference between the master control unit and the slave control unit. Based on the stored periodic timer value, it calculates the phase shift between the periodic timer values ​​corresponding to the master control unit and the slave control unit, respectively, and corrects the maximum value of the periodic timer value corresponding to the slave control unit based on the clock difference and phase shift. [Effects of the Invention]

[0008] According to the present invention, when driving an electric motor equipped with multiple winding sets, and when multiple control units control the current flowing through each of the multiple winding sets, it is possible to suppress the timing difference in the control between each control unit. [Brief explanation of the drawing]

[0009] [Figure 1] This is a configuration diagram showing an overview of an example of an electric power steering system according to an embodiment. [Figure 2] This block diagram shows an example of the functional configuration of an electronic control unit (ECU) as shown in Figure 1. [Figure 3] Figure 2 is a block diagram showing an example of the functional configuration of the control unit. [Figure 4] (a) to (d) are timing charts of examples of system timer values, count-up / down signals, PWM (Pulse Width Modulation) carrier signals, and OS timer values, respectively. [Figure 5] (a) to (d) are timing charts showing examples of the system timer value of the master control unit, the synchronization request signal, the OS timer value of the slave control unit, and the system timer value of the slave control unit, respectively. [Figure 6] This figure shows an example of a map that defines the relationship between candidate phase shift values ​​and phase shift. [Figure 7] (a) to (f) are explanatory diagrams illustrating the case where the period of the system timer value of the slave control unit is extended and corrected. [Figure 8] (a) to (f) are explanatory diagrams illustrating the case where the period of the system timer value of the slave control unit is shortened for correction. [Figure 9] (a) to (c) are timing charts for the first example of the on / off timing of the switching elements of the inverter circuit when the period of the system timer value is shortened. [Figure 10] (a) to (c) are timing charts for a second example of the on / off timing of the switching elements of the inverter circuit when correcting the period of the system timer value. [Figure 11] (a) to (c) are timing charts for the first example of the on / off timing of the switching elements of the inverter circuit when extending and correcting the period of the system timer value. [Figure 12] (a) to (c) are timing charts for a third example of the on / off timing of the switching elements of the inverter circuit when correcting the period of the system timer value.

Best Mode for Carrying Out the Invention

[0010] Embodiments of the present invention will be described in detail while referring to the drawings. Note that the embodiments of the present invention shown below exemplify devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the configuration, arrangement, etc. of the components as the following. The technical idea of the present invention can be variously modified within the technical scope defined by the claims described in the claims.

[0011] (Configuration) FIG. 1 is a configuration diagram showing an outline of an example of an electric power steering device according to an embodiment. A steering shaft (steering shaft, handle shaft) 2 of a steering wheel (steering handle) 1 is connected to steering wheels 8L and 8R via a reduction gear (worm gear) 3 constituting a reduction mechanism, universal joints 4a and 4b, a pinion rack mechanism 5, tie rods 6a and 6b, and further via hub units 7a and 7b.

[0012] The pinion rack mechanism 5 has a pinion 5a connected to a pinion shaft to which a steering force is transmitted from the universal joint 4b, and a rack 5b meshing with the pinion 5a, and converts the rotational motion transmitted to the pinion 5a into a straight motion in the vehicle width direction by the rack 5b. A torque sensor 10 for detecting the steering torque of the steering wheel 1 is provided on the steering shaft 2. The torque sensor 10 may have a redundant configuration by a plurality of torque only sensors (TOS: Torque Only Sensor) as will be described later. For example, the torque sensor 10 supplies detection values Tqd1 and Tqd2 of the steering torque by two TOSs to the ECU 30. Further, a steering angle sensor 14 for detecting the steering angle θh of the steering wheel 1 is provided on the steering shaft 2.

[0013] Also, an electric motor 20 that assists the steering force of the steering wheel 1 is connected to the steering shaft 2 via a reduction gear 3. The ECU 30 that controls the electric power steering (EPS) device is supplied with electric power from the battery 13 and receives an ignition key signal via the ignition (IGN) key 11. The electric motor 20 is a polyphase AC motor having multiple winding (coil) sets wound around in the same motor housing to rotate a common rotor by the multiple winding (coil) sets, and is driven by vector control by the ECU 30. In the present embodiment, the case where the electric motor 20 includes two winding sets is illustrated, but the present invention is not limited thereto and may be a motor having three or more winding sets.

[0014] The ECU 30 calculates a current command value of an assist control command based on the steering torques Tqd1 and Tqd2 detected by the torque sensor 10, the vehicle speed Vh detected by the vehicle speed sensor 12, and the steering angle θh detected by the steering angle sensor 14, and controls the current supplied to the electric motor 20 by a voltage command value Vref obtained by compensating the current command value. The ECU 30 is an example of the "control device" described in the claims.

[0015] Note that the steering angle sensor 14 is not essential, and the steering angle θh may be calculated by adding the torsional angle of the torsion bar of the torque sensor 10 to the rotation angle obtained from a rotation angle sensor that detects the rotation angle of the rotation shaft of the electric motor 20. Also, instead of the steering angle θh, the steering angles of the steered wheels 8L and 8R may be used. For example, the steering angle may be detected by detecting the displacement amount of the rack 5b.

[0016] The ECU 30 may include, for example, a computer including a processor and peripheral components such as a storage device. The processor may be, for example, a CPU (Central Processing Unit) or a MPU (Micro-Processing Unit). The storage device may include semiconductor storage devices, magnetic storage devices, and optical storage devices. The storage device may also include registers, cache memory, and memory such as ROM (Read Only Memory) and RAM (Random Access Memory) used as main memory. The functions of the ECU30 described below are realized, for example, by the ECU30's processor executing a computer program stored in a memory device.

[0017] The ECU30 may also be formed by dedicated hardware for performing the information processing described below. For example, the ECU30 may include functional logic circuits configured within a general-purpose semiconductor integrated circuit. For example, the ECU30 may have a programmable logic device (PLD) such as a field-programmable gate array (FPGA).

[0018] Figure 2 is a block diagram showing an example of the functional configuration of the ECU 30. The ECU 30 has a redundant configuration in which separate components are provided to control the drive current flowing through the first winding set of the electric motor 20 and the drive current flowing through the second winding set, respectively. The ECU 30 includes a power management circuit 40a, a control unit 41a, a drive circuit 42a, a drive voltage detection unit 43a, a drive current detection unit 44a, a rotation angle detection unit 45a, and a temperature detection unit 46a as components for controlling the drive current (i.e., the drive current of the first winding unit) that flows through the first winding unit of the electric motor 20. The control unit 41a is an example of the "master control unit" described in the claims, and may be referred to as the "master control unit" in the following description.

[0019] The power management circuit 40a generates the power supply voltage for the drive circuit 42a from the power supplied from the battery 13, and supplies the generated power supply voltage to the drive circuit 42a in accordance with the ignition key signal from the IGN key 11. The master control unit 41a acquires the vehicle speed Vh detected by the vehicle speed sensor 12 and the steering angle θh detected by the steering angle sensor 14 via a CAN (Controller Area Network) (not shown), and calculates the current command value A1 for the first winding set that generates steering assist torque for the electric motor 20 based on the steering torque Tqd1 of the steering wheel detected by the torque sensor 10's TOS 10a, the vehicle speed Vh, and the steering angle θh.

[0020] The master control unit 41a generates a PWM signal Spwm1 to control the drive circuit 42a by current feedback control and PWM control based on the detected value Id1 of the drive current of the first winding set detected by the drive current detection unit 44a and the current command value A1.

[0021] The drive circuit 42a drives the electric motor 20 by supplying a drive current to the first winding set of the electric motor 20 based on the PWM signal Spwm1 generated by the master control unit 41a. For example, the drive circuit 42a may be an inverter circuit that supplies drive current to each phase of a multiphase AC motor. The PWM signal Spwm1 is applied to the control terminal (e.g., gate terminal) of a switching element (e.g., FET) of the inverter circuit, and by controlling the switching element on and off, the drive current flowing through the first winding set of the electric motor 20 is controlled by PWM.

[0022] The drive voltage detection unit 43a monitors the drive voltage, which is the power supply voltage of the drive circuit 42a, and outputs its detected value Vd1. The drive current detection unit 44a detects the drive current flowing through the first winding set of the electric motor 20 and outputs its detected value Id1. The rotation angle detection unit 45a detects the rotation angle of the rotation shaft of the electric motor 20 and outputs its detected value θd1. The temperature detection unit 46a detects the temperature of the ECU 30 and the electric motor 20 and outputs its detected value Tpd1. These detected values ​​Vd1, Id1, θd1, and Tpd1 are input to the master control unit 41a.

[0023] As described later, the drive voltage Vd1 and temperature Tpd1 information are used to limit the current command value A1. The rotation angle θd1 of the electric motor 20 is used for calculating the current command value A1, for vector control of the electric motor 20, and for 3-phase / 2-phase conversion to convert the drive current Id1 to a dq-axis signal. The drive current Id1 converted to a dq-axis current is used for current feedback control.

[0024] Furthermore, the master control unit 41a generates a timer value by counting the clock signal of the oscillator circuit built into the master control unit 41a, and determines the start timing of processing within the master control unit 41a based on the generated timer value. In addition, based on the generated timer value, it generates timing signals that specify the timing for acquiring detection signals from the drive current detection unit 44a, the rotation angle detection unit 45a, and the temperature detection unit 46a. The dashed arrows in Figures 2 and 3 indicate the timing signals generated by the master control unit 41a and the slave control unit 41b, which will be described later.

[0025] On the other hand, as components for controlling the drive current flowing to the second winding assembly of the electric motor 20 (i.e., the drive current of the second winding assembly), the ECU 30 includes a power management circuit 40b, a control unit 41b, a drive circuit 42b, a drive voltage detection unit 43b, a drive current detection unit 44b, a rotation angle detection unit 45b, and a temperature detection unit 46b. The control unit 41b is an example of the "slave control unit" described in the claims, and may be referred to as the "slave control unit" in the following description.

[0026] The master control unit 41a and the slave control unit 41b are connected by a first communication line 47 and a second communication line 48, and the master control unit 41a and the slave control unit 41b can exchange signals and data with each other via the first communication line 47 and the second communication line 48. For example, the first communication line 47 may be a network line compliant with CAN FD (CAN with Flexible Data Rate). Also, for example, the second communication line 48 may be an I / O port connection.

[0027] In this embodiment, the case in which the electric motor 20 has two sets of windings is illustrated, but if the electric motor 20 has three or more sets of windings, it may be equipped with a power management circuit 40c... for controlling the drive current of the third and subsequent sets of windings, a control unit 41c..., a drive circuit 42c..., a drive voltage detection unit 43c..., a drive current detection unit 44c..., a rotation angle detection unit 45c..., a temperature detection unit 46c.... The operation of the control unit 41c... for controlling the drive current of the third and subsequent sets of windings is the same as the operation of the control unit 41b, and the control unit 41c... is also an example of the "slave control unit" described in the claims.

[0028] The power management circuit 40b generates the power supply voltage for the drive circuit 42b from the power supplied from the battery 13, and supplies the generated power supply voltage to the drive circuit 42b in accordance with the ignition key signal from the IGN key 11. If the ECU 30 is functioning correctly, the slave control unit 41b receives the current command value A1 calculated by the master control unit 41a via the first communication line 47.

[0029] The slave control unit 41b generates a PWM signal Spwm2 to control the drive circuit 42b by performing current feedback control and PWM control based on the detected value Id2 of the drive current of the second winding set detected by the drive current detection unit 44b and the current command value A1. On the other hand, if the ECU 30 is not functioning correctly (for example, when the master control unit 41a, TOS 10a, or the first communication line 47 fails), the slave control unit 41b calculates a current command value A2 for the second winding set that generates steering assist torque for the electric motor 20, based on the steering torque Tqd2 detected by the torque sensor 10's TOS 10b, the vehicle speed Vh, and the steering angle θh. The slave control unit 41b may always calculate the current command value A2 regardless of whether the master side fails or the first communication line 47 fails. The slave control unit 41b may select either the current command value A1 or the current command value A2 after determining the failure status and the availability of the current command value A1.

[0030] The slave control unit 41b generates a PWM signal Spwm2 to control the drive circuit 42b by current feedback control and PWM control based on the detected value Id2 of the drive current of the second winding set detected by the drive current detection unit 44b and the current command value A2. The drive circuit 42b drives the electric motor 20 by supplying a drive current to the second winding set of the electric motor 20 based on the PWM signal Spwm2 generated by the slave control unit 41b.

[0031] For example, the drive circuit 42b may be an inverter circuit that supplies drive current to each phase of a multiphase AC motor. The PWM signal Spwm2 is applied to the control terminal of the switching element of the inverter circuit, and by controlling the switching element on and off, the drive current flowing to the second winding set of the electric motor 20 is controlled by PWM.

[0032] The drive voltage detection unit 43b monitors the drive voltage, which is the power supply voltage of the drive circuit 42b, and outputs its detected value Vd2. The drive current detection unit 44b detects the drive current flowing through the second winding set of the electric motor 20 and outputs its detected value Id2. The rotation angle detection unit 45b detects the rotation angle of the rotation shaft of the electric motor 20 and outputs its detected value θd2. The temperature detection unit 46b detects the temperature of the ECU 30 and the electric motor 20 and outputs its detected value Tpd2. These detected values ​​Vd2, Id2, θd2, and Tpd2 are input to the slave control unit 41b.

[0033] As described later, the drive voltage Vd2 and temperature Tpd2 information are used to limit the current command values ​​A1 and A2. The rotation angle θd2 of the electric motor 20 is used for calculating the current command value A2, for vector control of the electric motor 20, and for 3-phase / 2-phase conversion to convert the drive current Id2 into a dq-axis signal. The drive current Id2 converted to a dq-axis current is used for current feedback control.

[0034] Furthermore, the slave control unit 41b generates a timer value by counting the clock signal of the oscillator circuit built into the slave control unit 41b, and determines the start timing of processing within the slave control unit 41b based on the generated timer value. It also generates a timing signal that specifies the timing for acquiring detection signals from the drive current detection unit 44b, the rotation angle detection unit 45b, and the temperature detection unit 46b, based on the generated timer value.

[0035] Figure 3 is a block diagram showing an example of the functional configuration of the master control unit 41a and the slave control unit 41b. The master control unit 41a includes a timer unit 50a, an assist command value calculation unit 51a, a limiting unit 52a, a current control / PWM control unit 53a, and a synchronization processing unit 54a. The assist command value calculation unit 51a, the limiting unit 52a, and the current control / PWM control unit 53a are examples of the "signal generation unit" described in the claims. The timer unit 50a calculates a system timer value Ts1, which is used to determine the start timing of processing in the master control unit 41a and the timing of acquiring detection signals from the drive current detection unit 44a, the rotation angle detection unit 45a, and the temperature detection unit 46a.

[0036] Figure 4(a) is a timing chart of an example of the system timer value Ts1. The system timer value Ts1 is a periodic timer with a period T1, and the timer unit 50a generates the system timer value Ts1 as a count value obtained by counting the clock signal generated by an oscillator circuit (not shown) built into the timer unit 50a. The timer unit 50a counts one period of the clock signal and increases the value of the system timer value Ts1 from the minimum value Tmin to the maximum value Tmax at a constant rate (constant rate of change over time).

[0037] When the system timer value Ts1 reaches its maximum value Tmax, the timer unit 50a resets the system timer value Ts1 to its minimum value Tmin before the next clock signal period arrives. As a result, the timer unit 50a generates a system timer value Ts1 that increases from the minimum value Tmin to the maximum value Tmax at a constant rate corresponding to the frequency of the clock signal, and immediately returns to the minimum value Tmin when it reaches the maximum value Tmax. The system timer value Ts1 is an example of the "periodic timer value" described in the claims. For example, the timer unit 50a may generate a system timer value Ts1 with a period T1 = 250 [μs] by counting a 200 [MHz] clock signal 50,000 times from a minimum value Tmin = "0" to a maximum value Tmax = "50,000".

[0038] The timer unit 50a generates a timing signal that specifies the start timing of processing in the master control unit 41a based on the system timer value Ts1. For example, the timer unit 50a generates timing signals that specify the timing for the AD converter of the assist command value calculation unit 51a to sample the steering torque Tqd1 output from TOS10a, and the timing for updating the current command value A1, based on the system timer value Ts1.

[0039] For example, the timer unit 50a generates a timing signal that specifies the control timing for current control by the current control / PWM control unit 53a based on the system timer value Ts1. For example, the timer unit 50a generates a timing signal that specifies the timing for the current control / PWM control unit 53a to generate a duty cycle command value corresponding to the current command value A1, and a count-up / down signal Cud used in the generation of the PWM carrier signal Sc in the current control / PWM control unit 53a, based on the system timer value Ts1.

[0040] Figures 4(b) and 4(c) are timing charts for an example of a count-up / down signal Cud and a PWM carrier signal Sc, respectively. The timer unit 50a divides one period T1 of the system timer value Ts1 into N periods (where N is an integer greater than or equal to 2, and in the example in Figure 4, N=5) and generates a count-up-down signal Cud that increases or decreases the value of the PWM carrier signal Sc.

[0041] For example, the timer unit 50a may determine the falling edge timing at which the first period of the N-period count-up-down signal Cud, obtained by dividing one period T1 of the system timer value Ts1, begins (i.e., the falling edge timing at which the fifth period ends), by the timing ts at which the system timer value Ts1 is reset to its minimum value Tmin. Furthermore, the timer unit 50a may determine the falling timing for the start of the second to fifth cycles and the rising timing in the middle of the first to fifth cycles based on the timing at which the system timer value Ts1 reaches a predetermined value.

[0042] For example, if the minimum value Tmin and maximum value Tmax of the system timer value Ts1 are "0" and "50000", respectively, the timing when the system timer value Ts1 reaches "10000", "20000", "30000", and "40000" can be obtained as the falling edge timing when the 2nd to 5th cycles begin.

[0043] Additionally, the timing at which the system timer value Ts1 reaches "5000", "15000", "25000", "35000", and "45000" may be acquired as the rising edge timing in the middle of the 1st to 5th cycles. The current control / PWM control unit 53a generates a triangular wave PWM carrier signal Sc as shown in Figure 4(c) by increasing the value of the PWM carrier signal Sc at a constant rate during the period when the value of the count-up-down signal Cud is "H", and decreasing the value of the PWM carrier signal Sc at a constant rate during the period when the value of the count-up-down signal Cud is "L".

[0044] In Figure 4(c), an example of a PWM carrier signal Sc that peaks (maximum value) when the system timer value Ts1 reaches its minimum value Tmin is shown. However, the PWM carrier signal Sc may also be a triangular wave that troughs (minimum value) when the system timer value Ts1 reaches its minimum value Tmin. The timer unit 50a generates a timing signal that specifies the timing for acquiring detection signals from the drive current detection unit 44a, the rotation angle detection unit 45a, and the temperature detection unit 46a, based on the system timer value Ts1.

[0045] Furthermore, the timer unit 50a generates an OS timer value To1 as a count value obtained by counting the clock signal generated by an oscillator circuit (not shown) built into the timer unit 50a. The OS timer value To1 is an example of the "timer value" described in the claims.

[0046] Figure 4(d) is a timing chart of an example of the OS timer value To1. The OS timer value To1 is a count value that increases at a constant rate according to the frequency of the clock signal. In practice, since the memory capacity of the OS timer value To1 is finite (e.g., 32 bits), the OS timer value To1 becomes a periodic timer that resets to "0" when the next clock signal period arrives after reaching an upper limit according to the memory capacity. One period of the OS timer value To1 is set to be much longer than one period T1 of the system timer value Ts1.

[0047] Refer to Figure 3. The assist command value calculation unit 51a acquires the vehicle speed Vh detected by the vehicle speed sensor 12 and the steering angle θh detected by the steering angle sensor 14 via a CAN (Controller Area Network) (not shown). It also acquires the steering torque Tqd1 of the steering wheel detected by the torque sensor 10's TOS 10a and the rotation angle θd1 of the rotation shaft of the electric motor 20 detected by the rotation angle detection unit 45a.

[0048] The assist command value calculation unit 51a calculates the current command value A1 of the first winding set that generates steering assist torque in the electric motor 20 based on the steering torque Tqd1, the vehicle speed Vh, the steering angle θh, and the rotation angle θd1. The assist command value calculation unit 51a outputs the calculated current command value A1 to the limiting unit 52a and also transmits it to the slave control unit 41b via the first communication line 47.

[0049] The assist command value calculation unit 51a updates the current command value A1 at the timing specified by the timing signal generated based on the system timer value Ts1. Note that the update period of the current command value A1 does not need to be the same as the period T1 of the system timer value Ts1, and may be longer than the period T1 of the system timer value Ts1 (a natural number multiple of T1). For example, the update period of the current command value A1 may be 1 [ms].

[0050] The limiting unit 52a limits the current command value A1 based on the drive voltage Vd1 detected by the drive voltage detection unit 43a and the temperature Tpd1 of the ECU 30 and electric motor 20 detected by the temperature detection unit 46a, and calculates the limited current command value A1L. The current control / PWM control unit 53a converts the drive current Id1 of the first winding set of the electric motor 20, detected by the drive current detection unit 44a, into a dq axis current based on the rotation angle θd1 of the rotation axis of the electric motor 20 detected by the rotation angle detection unit 45a.

[0051] The current control / PWM control unit 53a calculates the duty cycle command value for PWM control of the drive current of the first winding set by current feedback control that brings the current deviation between the drive current Id1, which has been converted to the dq axis current, and the limited current command value A1L closer to zero. The current control / PWM control unit 53a calculates the duty cycle command value at the timing specified by the timing signal generated by the timer unit 50a.

[0052] The current control / PWM control unit 53a generates a PWM carrier signal Sc based on the count-up / down signal Cud generated by the timer unit 50a. The current control / PWM control unit 53a generates a PWM signal Spwm1 that controls the drive circuit 42a based on the duty cycle command value and the PWM carrier signal Sc, and outputs it to the drive circuit 42a. The synchronization processing unit 54a will be described later.

[0053] On the other hand, the slave control unit 41b includes a timer unit 50b, an assist command value calculation unit 51b, a limiting unit 52b, a current control / PWM control unit 53b, and a synchronization processing unit 54b. The assist command value calculation unit 51b, the limiting unit 52b, and the current control / PWM control unit 53b are examples of the "signal generation unit" described in the claims. The timer unit 50b generates system timer value Ts2 and OS timer value To2, similar to system timer value Ts1 and OS timer value To1, by operating in the same manner as the timer unit 50a of the master control unit 41a described above. System timer value Ts2 and OS timer value To2 are examples of "timer values" of the "periodic timer value" described in the claims.

[0054] The timer unit 50b generates a timing signal that specifies the start timing of processing in the slave control unit 41b based on the system timer value Ts2. For example, the assist command value calculation unit 51b generates timing signals that specify the timing for sampling the steering torque Tqd2, the timing for updating the current command value A2, and timing signals that specify the control timing for current control by the current control / PWM control unit 53b (duty cycle command value generation timing signal and count-up / down signal Cud). Furthermore, the timer unit 50b generates a timing signal that specifies the timing for acquiring detection signals from the drive current detection unit 44b, the rotation angle detection unit 45b, and the temperature detection unit 46b, based on the system timer value Ts2.

[0055] The assist command value calculation unit 51b acquires the vehicle speed Vh detected by the vehicle speed sensor 12 and the steering angle θh detected by the steering angle sensor 14 via CAN (not shown). It also acquires the steering torque Tqd2 of the steering wheel detected by the torque sensor 10's TOS 10b and the rotation angle θd2 of the rotation shaft of the electric motor 20 detected by the rotation angle detection unit 45b.

[0056] The assist command value calculation unit 51b calculates the current command value A2 of the second winding set that generates steering assist torque in the electric motor 20 based on the steering torque Tqd2, the vehicle speed Vh, the steering angle θh, and the rotation angle θd2. The assist command value calculation unit 51b outputs the calculated current command value A2 to the limiting unit 52b.

[0057] The assist command value calculation unit 51b updates the current command value A2 at the timing specified by the timing signal generated based on the system timer value Ts2. Note that the update period of the current command value A2 does not need to be the same as the period T2 of the system timer value Ts2, and may be longer than the period T2 of the system timer value Ts2. For example, the update period of the current command value A2 may be 1 [ms].

[0058] If the current command value A1 is available, the limiting unit 52b limits the current command value A1 received from the master control unit 41a based on the drive voltage Vd2 detected by the drive voltage detection unit 43b and the temperature Tpd2 of the ECU 30 and electric motor 20 detected by the temperature detection unit 46b, and calculates the limited current command value A2L. If the current command value A1 is not available, the limiting unit 52b limits the current command value A2 based on the drive voltage Vd2 and temperature Tpd2, and calculates the limited current command value A2L. If the current command value A1 is not available, for example, if the master control unit 41a, TOS 10a, or first communication line 47 fails.

[0059] The current control / PWM control unit 53b converts the drive current Id2 of the second winding set of the electric motor 20, detected by the drive current detection unit 44b, into a dq axis current based on the rotation angle θd2 of the rotation shaft of the electric motor 20 detected by the rotation angle detection unit 45b. The current control / PWM control unit 53b calculates the duty cycle command value for PWM control of the drive current of the second winding set by current feedback control that brings the current deviation between the drive current Id2, which has been converted to the dq axis current, and the limited current command value A2L closer to zero. The current control / PWM control unit 53b calculates the duty cycle command value at the timing specified by the timing signal generated by the timer unit 50b.

[0060] The current control / PWM control unit 53b generates a PWM carrier signal Sc based on the count-up / down signal Cud generated by the timer unit 50b. The current control / PWM control unit 53b generates a PWM signal Spwm2 that controls the drive circuit 42b based on the duty cycle command value and the PWM carrier signal Sc, and outputs it to the drive circuit 42b. The synchronization processing unit 54b will be described later.

[0061] Next, the synchronization processing unit 54a of the master control unit 41a and the synchronization processing unit 54b of the slave control unit 41b will be described. The timer unit 50a of the master control unit 41a and the timer unit 50b of the slave control unit 41b each generate system timer values ​​Ts1 and Ts2 based on the clock signals of separate oscillator circuits. Therefore, if the clock signal of the master control unit 41a and the clock signal of the slave control unit 41b are different, a difference will occur between the system timer value Ts1 and the system timer value Ts2.

[0062] As a result, the timing at which the current command value A1 is reflected and the timing at which the duty cycle command value is generated will differ between the master control unit 41a and the slave control unit 41b. In addition, the timing at which the detection signals of each detection unit 44a to 46a are acquired will differ from the timing at which the detection signals of each detection unit 44b to 46b are acquired. As a result, there is a risk of torque fluctuations and operating noise in the electric motor 10.

[0063] Therefore, the synchronization processing units 54a and 54b and the timer unit 50b of the slave control unit 41b perform a system timer synchronization process to eliminate (or reduce) the deviation of the system timer value Ts2 with respect to the system timer value Ts1. In the system timer synchronization process, the synchronization processing unit 54a of the master control unit 41a generates a synchronization request signal Ss based on the system timer value Ts1 and outputs it to the synchronization processing unit 54b of the slave control unit 41b via the second communication line 48. The synchronization request signal Ss is an example of the "synchronization signal" described in the claims.

[0064] Figures 5(a) and 5(b) are time charts of an example of the system timer value Ts1 and synchronization request signal Ss of the master control unit 41a, respectively. For example, the synchronization request signal Ss may be an I / O signal that turns on and off at the timings t(k-1), t(k), t(k+1)... when the system timer value Ts1 is reset from the maximum value Tmax to the minimum value Tmin. The synchronization processing unit 54b stores the system timer value Ts2 and the OS timer value To2 at the timing when the synchronization request signal Ss changes from on to off or from off to on. For example, the synchronization processing unit 54b may activate DMA (Direct Memory Access) both when it detects the rising edge and the falling edge of the synchronization request signal Ss in Figure 5(b) and execute an interrupt process to store the system timer value Ts2 and the OS timer value To2.

[0065] Hereinafter, the change of the synchronization request signal Ss from on to off or off to on may simply be referred to as "the synchronization request signal Ss changes." The timing of the change in the synchronization request signal Ss is an example of the "timing indicated by the synchronization signal" as described in the claims. The synchronization request signal Ss is not limited to the signal shown in Figure 5(b); any signal indicating the timing at which the system timer value Ts1 is reset from its maximum value Tmax to its minimum value Tmin is sufficient. For example, the synchronization request signal Ss may be a narrow on / off signal or pulse signal that rises at the timing when the system timer value Ts1 is reset from its maximum value Tmax to its minimum value Tmin. In this case, the timing at which the synchronization request signal Ss changes from off to on becomes the "timing indicated by the synchronization signal".

[0066] The synchronization processing unit 54b calculates a clock difference α, which is a value corresponding to the difference in the period of the clock signal between the master control unit 41a and the slave control unit 41b, based on the difference in the OS timer value To2 stored at multiple different timings. Figure 5(c) is a timing chart of an example of the OS timer value To2 of the slave control unit 41b.

[0067] For example, the synchronization processing unit 54b may calculate the difference ΔT(k) = T(k) - T(k-1) between the value T(k) of the OS timer value To2 stored in the current interrupt processing and the value T(k-1) of the OS timer value To2 stored in the previous interrupt processing, and then calculate the difference by subtracting the default value of the maximum value Tmax of the system timer value Ts2 (hereinafter referred to as "basic maximum value Tmax0") from the difference ΔT(k), and use the clock difference α = ΔT - Tmax0. As the basic maximum value Tmax0, the maximum value Tmax used by the timer unit 50a of the master control unit 41a to generate the system timer value Ts1 may be used.

[0068] If the clock signal of the slave control unit 41b is faster than the clock signal of the master control unit 41a (i.e., the rate of increase of OS timer value To2 and system timer value Ts2 is faster than the rate of increase of OS timer value To1 and system timer value Ts1), the clock difference α has a positive value, and if the opposite is true, the clock difference α has a negative value.

[0069] The synchronization processing unit 54b may store the value T(ki) of the OS timer value To2 at the timing of a constant period T1 (e.g., on / off period) indicated by the synchronization request signal Ss (i=0,1,2,...N:N is a positive integer), calculate multiple changes in the OS timer value To2 during the constant period ΔT(kj)=T(kj)-T(kj-1) (j=0,1,2,...N-1), and calculate the average value of the multiple changes (e.g., moving average or weighted average) as ΔTwav. The synchronization processing unit 54b may also calculate the difference obtained by subtracting the basic maximum value Tmax0 from the average value ΔTwav as the clock difference α=ΔTwav-Tmax0. Here, the period T1 indicated by the synchronization request signal Ss may change in the real time axis due to the influence of temperature, etc., on the clock signal of the oscillation circuit of the master control unit 41a. The constant period T1 mentioned above does not indicate that the period is constant in the real time axis, but rather that the period set in software is constant.

[0070] For example, if the calculated ΔT is not within a predetermined tolerance range, the synchronization processing unit 54b may invalidate the OS timer value To2 that was stored this time. Then, the execution of the system timer synchronization process (a series of processes up to correcting the maximum value of the system timer) may be canceled this time. After the next interrupt processing, it may be decided again whether or not to execute the synchronization process. This eliminates malfunctions of the synchronization process due to noise mixed into the synchronization request signal Ss. The predetermined tolerance range may be, for example, 250 ± 2 [μs]. That is, the tolerance range of the clock difference α may be ± 2 [μs].

[0071] Furthermore, the synchronization processing unit 54b calculates the phase difference β between the system timer value Ts1 of the master control unit 41a and the system timer value Ts2 of the slave control unit 41b based on the system timer value Ts2 stored at the timing when the synchronization request signal Ss changes. Figure 5(d) is a timing chart of an example where the system timer value Ts2 corresponds to the OS timer value To2.

[0072] As shown in Figure 5(d), if the synchronization request signal Ss changes after the system timer value Ts2 has been reset from the maximum value Tmax to the minimum value Tmin, the synchronization processing unit 54b may calculate the value Ts(k) of the system timer value Ts2 stored at the time the synchronization request signal Ss changes as the phase shift β. For example, the synchronization processing unit 54b may calculate the value Ts(k) as a phase shift β when the value Ts(k) of the system timer value Ts2 is less than or equal to half of the basic maximum value Tmax0 (Tmax0 / 2). In this case, the phase shift β has a positive value.

[0073] Conversely, if the synchronization request signal Ss changes before the system timer value Ts2 is reset from the maximum value Tmax to the minimum value Tmin, the phase shift β = Ts(k) - Tmax0 can be calculated by subtracting the fundamental maximum value Tmax0 from the value Ts(k) of the system timer value Ts2 stored at the time the synchronization request signal Ss changes. For example, the synchronization processing unit 54b may calculate the difference (Ts(k)-Tmax0) as the phase shift β when the system timer value Ts2 value Ts(k) is greater than Tmax0 / 2. In this case, the phase shift β has a negative value.

[0074] Alternatively, for example, the synchronization processing unit 54b may calculate a candidate phase shift value β1 based on the value Ts(k) of the system timer value Ts2 stored at the timing when the synchronization request signal Ss changes, and determine the phase shift β based on a table or map that defines the relationship between the candidate phase shift value β1 and the phase shift β, and the calculated candidate phase shift value β1.

[0075] For example, the synchronization processing unit 54b may calculate the value Ts(k) as a candidate phase shift value β1 when the value Ts(k) is less than or equal to Tmax0 / 2, and may calculate the value Ts(k)-Tmax0 as a candidate phase shift value β1 when the value Ts(k) is greater than Tmax0 / 2. Figure 6 shows an example of a map defining the relationship between the candidate phase shift value β1 and the phase shift β. The synchronization processing unit 54b determines the phase shift β based on the map shown in Figure 6 and the calculated candidate phase shift value β1.

[0076] In a table or map defining the relationship between a candidate phase shift value β1 and a phase shift β, the absolute value |β| of the phase shift β may be set to a value smaller than the absolute value |β1| of the candidate phase shift value β1 corresponding to this phase shift β. For example, in the map in Figure 6, the phase shift β is set to -125 in the range where the candidate phase shift value β1 is -201 or less; as the candidate phase shift value β1 increases from -200 to -51, the phase shift β increases linearly from -124 to -25; as the candidate phase shift value β1 increases from -50 to -4, the phase shift β increases linearly from -24 to -1; and in the range where the candidate phase shift value β1 is between -3 and 3, the phase shift β is set to 0.

[0077] Furthermore, when the candidate phase shift value β1 increases from 4 to 50, the phase shift β increases linearly from 1 to 24. When the candidate phase shift value β1 increases from 51 to 200, the phase shift β increases linearly from 25 to 124. In the range where the candidate phase shift value β1 is 201 or greater, the phase shift β is set to 125. Alternatively, instead of using a table or map that defines the relationship between the candidate phase shift value β1 and the phase shift β, one can calculate the phase shift β = C × β1 by multiplying the candidate phase shift value β1 by a coefficient C less than 1.

[0078] The synchronization processing unit 54b outputs the calculated clock difference α and phase shift β to the timer unit 50b of the slave control unit 41b. The timer unit 50b corrects the maximum value Tmax of the system timer value Ts2 based on the clock difference α and the phase shift β. For example, the timer unit 50b may set the maximum value Tmax of the system timer value Ts2 as Tmax = Tmax0 + (α + β) by adding the sum of the clock difference α and the phase shift β (α + β) to the basic maximum value Tmax0.

[0079] As a result, if the clock signal of the slave control unit 41b is faster than the clock signal of the master control unit 41a (i.e., clock difference α > 0), and the period T2 of the system timer value Ts2 is shorter than the period T1 of the system timer value Ts1, the maximum value Tmax is corrected to increase. As a result, the timing at which the system timer value Ts2 is reset from the maximum value Tmax to the minimum value Tmin is delayed, so the maximum value Tmax is corrected so that the period T2 of the system timer value Ts2 is extended.

[0080] Conversely, if the clock signal of the slave control unit 41b is slower than the clock signal of the master control unit 41a (i.e., clock difference α < 0), and the period T2 of the system timer value Ts2 is longer than the period T1 of the system timer value Ts1, the maximum value Tmax is corrected to decrease. As a result, the timing at which the system timer value Ts2 is reset from the maximum value Tmax to the minimum value Tmin is brought forward, so the maximum value Tmax is corrected to shorten the period T2 of the system timer value Ts2.

[0081] Furthermore, if there is a phase difference between system timer values ​​Ts1 and Ts2, and the timing of the reset of system timer value Ts2 is earlier than the timing of the reset of system timer value Ts1 from its maximum value Tmax to its minimum value Tmin (i.e., when the phase difference β > 0), then the maximum value Tmax is corrected to increase. As a result, the period T2 of system timer value Ts2 is extended, so the maximum value Tmax is corrected to delay the timing of the reset of system timer value Ts2.

[0082] Conversely, if the system timer value Ts2 is reset later than the system timer value Ts1 is reset from its maximum value Tmax to its maximum value Tmin (i.e., when the phase shift β < 0), the maximum value Tmax is corrected to decrease. As a result, the period T2 of the system timer value Ts2 is shortened, and the maximum value Tmax is corrected so that the system timer value Ts2 is reset earlier. Through the above operations and functions, the synchronization processing units 54a and 54b and the timer unit 50b can eliminate (or reduce) the deviation of the system timer value Ts2 with respect to the system timer value Ts1.

[0083] Next, we will explain the change in the PWM carrier signal Sc associated with the correction of the system timer value Ts2. Figures 7(a) to 7(c) show the system timer value Ts2, the count-up / down signal Cud, and the PWM carrier signal Sc when the maximum value Tmax of the system timer value Ts2 is not corrected (i.e., the maximum value Tmax is equal to the basic maximum value Tmax0) and the system timer value Ts2 is not extended or shortened (i.e., α+β=0) for comparison. Figures 8(a) to 8(c) are similar.

[0084] As described above, the timer unit 50b divides one period T2 of the system timer value Ts2 into N periods (N=5 in the example in Figure 7) to generate a count-up signal Cud. In the following explanation, among the N count-up-down signals Cud obtained by dividing one period T2 of the system timer value Ts2 into N parts, the count-up-down signals Cud for the 1st period, 2nd period, ..., Nth period may be referred to as the 1st, 2nd, ..., Nth count-up-down signals, respectively.

[0085] Furthermore, the portion of the PWM carrier signal Sc in one period T2 of the system timer value Ts2 that is increased or decreased by the 1st, 2nd, ... Nth count-up-down signals is sometimes referred to as the 1st, 2nd, ... Nth PWM carrier signal, respectively. For example, if the period T2 of the system timer value Ts2 is 250 [μs], and the PWM carrier signal Sc increases and decreases 5 times during period T2, then the first PWM carrier signal is the PWM carrier signal Sc for the first 50 [μs] period from the point when the system timer value Ts2 reaches its minimum value Tmin.

[0086] Furthermore, the second PWM carrier signal is the PWM carrier signal Sc for the second 50 [μs] period, the third PWM carrier signal is the PWM carrier signal Sc for the third 50 [μs] period, the fourth PWM carrier signal is the PWM carrier signal Sc for the fourth 50 [μs] period, and the fifth PWM carrier signal is the PWM carrier signal Sc for the last 50 [μs] period.

[0087] Figures 7(d) to 7(f) show the system timer value Ts2, the count-up / down signal Cud, and the PWM carrier signal Sc when the period T2 of the system timer value Ts2 is extended (i.e., when α+β>0). When the period T2 of the system timer value Ts2 is extended, the timer unit 50b does not change the first to (N-1)th count-up-down signals and PWM carrier signals, but changes the last (i.e., the Nth) count-up-down signal and PWM carrier signal as shown in Figures 7(e) and 7(f).

[0088] The timer unit 50b delays the falling edge timing of the Nth count-up-down signal until the timing at which the system timer value Ts2 is reset from its maximum value Tmax to its minimum value Tmin. As a result, even if the PWM carrier signal Sc reaches its upper limit, the value of the count-up-down signal Cud remains "H", so the current control / PWM control unit 53a continues to count up the PWM carrier signal Sc. However, since the current control / PWM control unit 53a limits the upper limit of the PWM carrier signal Sc, the PWM carrier signal Sc is fixed at its upper limit until the falling edge timing of the count-up-down signal Sc, as shown in section A.

[0089] Figures 8(d) to 8(f) show the system timer value Ts2, the count-up / down signal Cud, and the PWM carrier signal Sc when the period T2 of the system timer value Ts2 is shortened (i.e., when α+β<0). When the period T2 of the system timer value Ts2 is shortened, the timer unit 50b does not change the first to (N-1)th count-up-down signals and PWM carrier signals, but changes the last (i.e., the Nth) count-up-down signal and PWM carrier signal as shown in Figures 8(e) and 8(f).

[0090] The timer unit 50b advances the falling edge timing of the Nth count-up-down signal until the system timer value Ts2 is reset from its maximum value Tmax to its minimum value Tmin. When the count-up / down signal Cud changes from "H" to "L", the timer unit 50b sets the value of the PWM carrier signal Sc to its upper limit, as shown in section B of the arrow, and starts counting down the PWM carrier signal Sc from that upper limit.

[0091] Note that excessively extending or shortening the period T2 of the system timer value Ts2 will significantly distort the PWM waveform. Also, the PWM signal duty cycle command value for the next period of the system timer value Ts2 is set at a predetermined point in time within the duration of the last PWM carrier signal of the previous period. For example, if one period T2 is 250 [μs], it is set at (250 - γ) [μs] after the system timer value Ts2 is reset to its minimum value Tmin (for example, γ = 5.5 [μs]).

[0092] Therefore, if the period T2 of the system timer value Ts2 becomes shorter than (250-γ)[μs], it results in abnormal operation where the duty cycle command value cannot be set in time. Therefore, in order to prevent excessive deformation or abnormal operation of the PWM waveform, the timer unit 50b may apply a limiting process to the sum of the clock difference α and the phase shift β (α+β) to obtain a limited sum, and correct the maximum value Tmax of the system timer value Ts2 based on the limited sum.

[0093] For example, if the sum (α+β) is greater than the limit (-VL) and less than the limit VL, the sum (α+β) may be added to the basic maximum value Tmax0 to set the maximum value Tmax. If the sum (α+β) is less than or equal to the limit (-VL) or greater than or equal to the limit VL, the limit (-VL) or limit VL may be added to the basic maximum value Tmax0, respectively, to set the maximum value Tmax. For example, the limit VL may be set so that the upper limit of the extension or shortening time is 1 [μs] or less. Also, the limit may be set to a different value depending on whether the time is being extended or shortened.

[0094] Next, we will explain the changes in the on-timing and off-timing of the switching elements of the inverter circuit of the drive circuit 42b due to the correction of the system timer value Ts2. The inverter circuit has multiple switching arms formed by the series connection of an upper switching element and a lower switching element, and these multiple switching arms are connected in parallel.

[0095] If the upper and lower switching elements are turned on simultaneously, a through-current will flow and damage the switching elements. Therefore, a predetermined dead time is provided during the period from when one of the upper or lower switching elements switches from on to off to when the other switches from off to on, during which both switching elements are simultaneously turned off.

[0096] When the system timer value Ts2 is corrected, the PWM carrier signal Sc changes as shown in Figures 7(f) and 8(f), and consequently, the switching timing of the switching elements changes. Therefore, the current control / PWM control unit 53b determines the switching timing so as to ensure a predetermined dead time even when the switching timing of the switching elements changes due to the correction of the system timer value Ts2.

[0097] Figures 9(a) to 9(c) show the timing charts for the first example of the PWM carrier signal Sc, the PWM signal that switches the upper switching element, and the PWM signal that switches the lower switching element, respectively, when the period T2 of the system timer value Ts2 is corrected to be shortened.

[0098] In Figures 9(a), 10(a), and 11(a), the dashed line shows the PWM carrier signal Sc before correction by the summation value (α+β) or the limited summation value, and the solid line shows the PWM carrier signal Sc after correction by the summation value (α+β) or the limited summation value. For simplicity of explanation, Figures 9(a), 10(a), and 11(a) show examples where the system timer value Ts2 is corrected by the summation value (α+β), but when correcting with the limited summation value, replace "summation value (α+β)" with "limited summation value" in the following explanation. The dashed line indicates the current duty cycle command value, where DDL represents the dead time of the lower switching element and DDH represents the dead time of the upper switching element. For example, the dead times DDL and DDH may each be 0.5 [μs].

[0099] The upper dashed line ThL of the duty cycle command value (single dashed line) indicates the threshold value of the PWM carrier signal Sc that switches the lower switching element, taking dead time into consideration. The current control / PWM control unit 53b switches the lower switching element from off to on at timing TLon, when the PWM carrier signal Sc exceeds the threshold ThL from a state where it is less than the threshold ThL. The current control / PWM control unit 53b also switches the lower switching element from on to off at timings TLoff0 and TLoff1, when the PWM carrier signal Sc falls below the threshold ThL from a state where it is greater than the threshold ThL. Due to the shortening correction of the period T2 of the system timer value Ts2, the timing of switching the lower switching element to off is advanced from TLoff0 before correction to TLoff1 after correction.

[0100] The double-dotted line ThH below the duty cycle command value (single-dotted line) indicates the threshold value of the PWM carrier signal Sc that switches the upper switching element, taking dead time into consideration. The current control / PWM control unit 53b switches the upper switching element from on to off at timing THoff, when the PWM carrier signal Sc exceeds the threshold value ThH from a state where it is less than ThH. The current control / PWM control unit 53b also switches the upper switching element from off to on at timings THon0 and THon1, when the PWM carrier signal Sc falls below the threshold value ThH from a state where it is greater than ThH. Due to the shortening correction of the period T2 of the system timer value Ts2, the timing of switching the upper switching element to on is advanced from THon0 before correction to THon1 after correction.

[0101] In the example shown in Figure 9(a), the value obtained by subtracting the duty cycle value D2, which corresponds to the sum of the values ​​(α+β), from 100% is greater than the value obtained by adding the duty cycle value D1, which corresponds to the dead time DDL of the lower switching element, to the duty cycle command value. In other words, the duty cycle command value is smaller than the value obtained by subtracting the sum of the duty cycle value D1, which corresponds to the dead time DDL, and the duty cycle value D2, which corresponds to the sum of the values ​​(α+β), from 100% (100%-D1-D2).

[0102] The duty cycle D1, which corresponds to the dead time DDL, is defined as the product of the dead time DDL and the rate of change (i.e., slope) R of the PWM carrier signal Sc (R × DDL). For example, if the period of the PWM carrier signal Sc is 50 [μs], then R is 100% / 25 [μs]. The duty cycle D2, which corresponds to the sum (α+β), is the time Ts2 required for the system timer value Ts2 to increase from the minimum value Tmin to the base maximum value Tmax0. * The product obtained by dividing by the fundamental maximum value Tmax0 and multiplying the result by the sum of the values ​​(α+β) is (Ts2 * The product of (Ts²) × (α+β) / Tmax0) and the time rate of change R of the PWM carrier signal Sc. * It is defined as ×(α+β)×R / Tmax0).

[0103] In the case of Figure 9, even if the period T2 of the system timer value Ts2 is shortened, the timing TLon for switching the lower switching element from off to on is not advanced. Therefore, the current control / PWM control unit 53b can ensure a predetermined dead time (DDL+DDH) without having to advance the timing THoff for switching the upper switching element from on to off.

[0104] Figures 10(a) to 10(c) show timing charts for a second example of the PWM carrier signal Sc, the PWM signal that switches the upper switching element, and the PWM signal that switches the lower switching element, respectively, when the period T2 of the system timer value Ts2 is corrected to be shortened.

[0105] In the case of Figure 10(a), the value obtained by adding the duty cycle value D1, which corresponds to the dead time DDL of the lower switching element, to the duty cycle command value is greater than the value obtained by subtracting the duty cycle value D2, which corresponds to the sum (α+β), from 100%. In other words, the duty cycle command value is greater than the value obtained by subtracting the sum of the duty cycle value D1, which corresponds to the dead time DDL, and the duty cycle value D2, which corresponds to the sum (α+β), from 100% (100%-D1-D2).

[0106] In this case, the timing at which the PWM carrier signal Sc exceeds the threshold ThL is brought forward, so the timing at which the lower switching element switches from off to on is brought forward from TLon0 before correction to TLon1 after correction. For this reason, the current control / PWM control unit 53b brings forward the timing at which the upper switching element switches from on to off, from THoff0 before correction to THoff1 after correction, in order to ensure a predetermined dead time (DDL+DDH).

[0107] For example, the current control / PWM control unit 53b may set the timing of switching the lower switching element from off to on to an earlier timing (TLon0-TLon1), by setting the corrected THoff1 = THoff0 - TLon0 + TLon1, which is an earlier timing than the pre-correction THoff0.

[0108] Figures 11(a) to 11(c) are timing charts of an example of the PWM carrier signal Sc, the PWM signal that switches the upper switching element, and the PWM signal that switches the lower switching element, respectively, when the period T2 of the system timer value Ts2 is extended and corrected. In this case, the current control / PWM control unit 53b delays the timing of switching the lower switching element to the off position from TLoff0 before correction to TLoff1 after correction. It also delays the timing of switching the upper switching element to the on position from THo0 before correction to THo1 after correction.

[0109] The above explanation assumed that the PWM carrier signal supplied to the inverter circuit was at its maximum value when the period timer value reached its maximum value and was reset. Next, we will explain the case where the PWM carrier signal supplied to the inverter circuit is at its minimum value when the period timer value reached its maximum value and was reset.

[0110] Figure 12 shows an example of a process that advances the timing of switching the lower switching element from on to off when the timing of switching the upper switching element from off to on is advanced. When the duty command value is smaller than the sum of the duty value D3, which corresponds to the dead time DDH for the upper switching element, and the duty value D2, which corresponds to the sum of (α+β), the timing of switching the lower switching element from on to off is advanced to ensure a predetermined dead time (DDL+DDH).

[0111] (Effects of the embodiment) (1) A control device for controlling the drive of an electric motor having multiple winding sets comprises multiple drive circuits corresponding to each of the multiple winding sets, and multiple control units that calculate control signals for controlling each of the multiple drive circuits. Each of the multiple control units comprises a timer unit that generates a timer value and a periodic timer value for determining the timing of control signal generation, and a signal generation unit that generates a control signal for controlling the drive circuit corresponding to the control unit at a timing based on the periodic timer value generated by the timer unit.

[0112] The timer unit generates a count value that increases at a constant rate as the timer value, and also generates a count value that increases at a constant rate from a minimum to a maximum value, and immediately returns to the minimum value when it reaches the maximum value as the periodic timer value. The master control unit, which is one of the multiple control units, outputs a synchronization signal to reset the periodic timer value corresponding to the slave control unit, which is one of the other control units, based on the periodic timer value corresponding to the master control unit.

[0113] The slave control unit stores the timer value and periodic timer value corresponding to the slave control unit at the timing indicated by the synchronization signal. Based on the difference between the timer values ​​stored at multiple different timings, it calculates the clock difference between the master control unit and the slave control unit. Based on the stored periodic timer value, it calculates the phase shift between the periodic timer values ​​corresponding to the master control unit and the slave control unit, respectively, and corrects the maximum value of the periodic timer value corresponding to the slave control unit based on the clock difference and phase shift.

[0114] This suppresses the occurrence of discrepancies in the periodic timer values ​​that determine the timing of the control signals between the master control unit and the slave control unit. As a result, when driving an electric motor with multiple winding sets, and when multiple control units control the current flowing through multiple winding sets, it is possible to suppress discrepancies in the control timing between each control unit.

[0115] (2) The slave control unit may apply a limiting process to the sum of the clock difference and the phase shift to obtain a limited sum, and correct the maximum value of the period timer value based on the limited sum. This prevents excessive deformation of the PWM carrier signal and the occurrence of abnormal operation due to excessive correction of the period timer value.

[0116] (3) The slave control unit may store the timer value at a fixed period timing indicated by the synchronization signal, calculate multiple changes in the timer value during that period, and calculate the clock difference based on the average value of the multiple changes. This prevents excessive deformation of the PWM carrier signal and abnormal operation caused by excessive correction of the period timer value.

[0117] (4) The slave control unit may calculate a candidate phase shift value based on the stored period timer value and determine the phase shift based on a table or map that defines the relationship between the candidate phase shift value and the phase shift. For example, in the table or map, the absolute value of the phase shift may be set to a value smaller than the absolute value of the candidate phase shift value corresponding to that phase shift. This prevents excessive distortion of the PWM carrier signal and abnormal operation caused by excessive correction of the period timer value.

[0118] (5) The drive circuit is an inverter circuit comprising an upper switching element and a lower switching element. When the period timer value reaches its maximum value and is reset, the PWM carrier signal supplied to the inverter circuit is set to its maximum. In this case, the slave control unit may adjust the maximum value of the period timer value based on the limit-added value to decrease it, and if the duty command value for driving the motor is greater than the value obtained by subtracting from 100% the sum of the duty value corresponding to the dead time of the lower switching element and the duty value corresponding to the limit-added value, the slave control unit may advance the off timing of the upper switching element so that a predetermined dead time is generated between the off timing of the upper switching element and the on timing of the lower switching element. When the period timer value reaches its maximum value and is reset, if the PWM carrier signal supplied to the inverter circuit is set to the minimum, the slave control unit may, if the maximum value of the period timer value is reduced based on the limit-added value, and the duty cycle command value for driving the motor is smaller than the sum of the duty cycle value corresponding to the dead time of the upper switching element and the duty cycle value corresponding to the limit-added value, advance the off-timing of the lower switching element so that a predetermined dead time is generated between the on-timing of the upper switching element and the off-timing of the lower switching element. This ensures that an appropriate dead time is secured when the period of the period timer value in the slave control unit is corrected to be shorter.

[0119] (6) If the difference in the calculated timer value is not within a predetermined tolerance range, the slave control unit invalidates the stored timer value and does not need to correct the maximum value of the periodic timer value. This eliminates malfunctions of the synchronization process caused by noise mixed into the synchronization signal. [Explanation of Symbols]

[0120] 1…Steering wheel, 2…Steering shaft, 3…Reduction gear, 4a, 4b…Universal joint, 5…Pinion rack mechanism, 5a…Pinion gear (pinion), 5b…Rack bar (rack), 6a, 6b…Tie rod, 7a, 7b…Hub unit, 8L, 8R…Steering wheel, 10…Torque sensor, 11…Ignition key, 12…Vehicle speed sensor, 13…Battery, 14…Steering angle sensor, 20…Electric motor, 40a, 40b…Power management circuit, 41a 41b...Control unit (master control unit, slave control unit), 42a, 42b...Drive circuit, 43a, 43b...Drive voltage detection unit, 44a, 44b...Drive current detection unit, 45a, 45b...Rotation angle detection unit, 46a, 46b...Temperature detection unit, 47...First communication line, 48...Second communication line, 50a, 50b...Timer unit, 51a, 51b...Assist command value calculation unit, 52a, 52b...Limiting unit, 53a, 53b...Current control / PWM control unit, 54a, 54b...Synchronization processing unit

Claims

1. A control device for controlling the drive of an electric motor having multiple winding sets, Each of the aforementioned multiple winding sets is accompanied by a plurality of drive circuits, Multiple control units that each calculate control signals for controlling the multiple drive circuits, Equipped with, Each of the aforementioned plurality of control units is: A timer unit that generates a timer value and a periodic timer value for determining the timing of generating the aforementioned control signal, A signal generation unit generates a control signal that controls the drive circuit corresponding to the control unit at a timing based on the periodic timer value generated by the timer unit, Equipped with, The timer unit generates a count value that increases at a constant speed as the timer value, and generates a count value that increases from a minimum value to a maximum value at the constant speed and immediately returns to the minimum value when it reaches the maximum value as the periodic timer value. The master control unit, which is one of the plurality of control units, outputs a synchronization signal for resetting the period timer value corresponding to the slave control unit, which is one of the other control units, based on the period timer value corresponding to the master control unit. The slave control unit, The timer value and the period timer value corresponding to the slave control unit are stored at the timing indicated by the synchronization signal. Based on the difference between the timer values ​​stored at multiple different timings, the clock difference between the master control unit and the slave control unit is calculated. Based on the stored periodic timer value, the master control unit and the slave control unit calculate the phase difference between the corresponding periodic timer values. The maximum value of the periodic timer corresponding to the slave control unit is corrected based on the clock difference and the phase shift. A control device characterized by the following features.

2. The control device according to claim 1, characterized in that the slave control unit applies a limiting process to the sum of the clock difference and the phase shift to obtain a limited sum, and corrects the maximum value of the period timer value based on the limited sum.

3. The control device according to claim 1, characterized in that the slave control unit stores the timer value at a fixed period timing indicated by the synchronization signal, calculates multiple amounts of change in the timer value during the fixed period, and calculates the clock difference based on the average value of the multiple amounts of change.

4. The control device according to claim 1, characterized in that the slave control unit calculates a candidate phase shift value based on the stored period timer value and determines the phase shift based on a table or map that defines the relationship between the candidate phase shift value and the phase shift.

5. The control device according to claim 4, characterized in that, in the table or map, the absolute value of the phase shift is set to a value smaller than the absolute value of the candidate phase shift value corresponding to the phase shift.

6. The aforementioned drive circuit is an inverter circuit comprising an upper switching element and a lower switching element. In the case where the PWM carrier signal supplied to the inverter circuit is set to its maximum when the period timer value reaches the maximum value and is reset, The control device according to claim 2, wherein the slave control unit reduces the maximum value of the period timer value based on the limited addition value, and if the duty command value for driving the motor is greater than the value obtained by subtracting from 100% the sum of the duty value corresponding to the dead time of the lower switching element and the duty value corresponding to the limited addition value, the control device advances the off timing of the upper switching element so that a predetermined dead time is generated between the off timing of the upper switching element and the on timing of the lower switching element.

7. The aforementioned drive circuit is an inverter circuit comprising an upper switching element and a lower switching element. When the period timer value reaches the maximum value and is reset, the PWM carrier signal supplied to the inverter circuit is set to the minimum value, The control device according to claim 2, wherein the slave control unit reduces the maximum value of the period timer value based on the limited added value, and if the duty command value for driving the motor is smaller than the sum of the duty value corresponding to the dead time of the upper switching element and the duty value corresponding to the limited added value, the control device advances the off timing of the lower switching element so that a predetermined dead time is generated between the on timing of the upper switching element and the off timing of the lower switching element.

8. The control device according to claims 1 to 7, characterized in that, at the current timing indicated by the synchronization signal, if the difference between the timer value stored this time and the timer value stored at a different timing is not within a predetermined allowable range, the slave control unit invalidates the timer value stored this time and does not perform a series of processes related to correcting the maximum value of the periodic timer value corresponding to the slave control unit.

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