Impedance measurement system including a single pin and its phase offset compensation

Abstract

An impedance measurement system is provided. [Solution] The impedance measurement system includes a signal generator with memory. The signal generator is configured to generate a digital test signal and at least one digital demodulated signal based on the memory. The digital test signal has a first frequency, and at least one digital demodulated signal has a first frequency. The impedance measurement system also includes a single pin. The single pin is configured to supply an analog test signal based on the digital test signal to the device under test (DUT) and to measure an analog input signal in response to supplying the analog test signal to the DUT. The impedance measurement system also includes a demodulator. The demodulator is configured to acquire a first filtered digital signal and at least one digital demodulated signal based on the input signal and generate at least one demodulated digital signal indicating impedance.

Description

[Technical Field]

[0001] [Cross-reference of related applications] This application claims priority based on UK Patent Application No. 2416584.7, filed November 11, 2024, and on US Patent Application No. 18 / 999,603, filed December 23, 2024. The contents of these applications are incorporated into this application in their entirety by reference.

[0002] This disclosure relates to an impedance measurement system including a single pin, and to phase offset compensation for an impedance measurement system including a single pin, and more particularly to an impedance measurement system including a single pin that includes a phase offset compensator configured to introduce an address offset to compensate for an unknown phase offset. [Background technology]

[0003] To measure or calculate the impedance of an external device under test (DUT), the system may generate measurements representing the amplitude and phase (or real and imaginary parts) of that impedance. To reduce the number of signal pins, it is desirable to supply a "test signal" to the DUT and to have only one connection per DUT for measuring the results.

[0004] The system may determine the impedance of the DUT by applying a voltage to the DUT and measuring the amplitude and phase of the current passing through the DUT. Alternatively, the amplitude and phase of a voltage signal may be determined by applying a current to the DUT and measuring the voltage across it.

[0005] To enable measurement of the real and imaginary parts of a signal affected by a DUT with complex impedance, the test signal must be a time-varying signal, such as a signal pulse or a sinusoidal signal.

[0006] Typically, a sine wave is used. This is because a sine wave has both amplitude and phase (i.e., a real part "Re" and an imaginary part "Im").

[0007] Known systems typically implement an I / Q demodulator to derive Re and Im. The amplitude and phase of the current are measured by demodulating the signal measured across the DUT (either the current flowing through the DUT or the voltage across the DUT) using an I / Q demodulator. This measurement is performed by multiplying the measured signal by a sinusoidal and cosine signal of the same frequency. The output of the I / Q demodulator (after filtering) is the common-mode and quadrature signal in DC. The output is a complex number containing real and imaginary components. The amplitude is

[0008]

number

[0009] The phase is obtained by and

[0010]

number

[0011] It can be calculated using this method.

[0012] Known systems have limited sensitivity and are therefore susceptible to noise and parasitic components, resulting in reduced accuracy and reliability of measurement results.

[0013] Furthermore, internal signal delays, such as those caused by frequency-dependent signal processing (similar to filter characteristics) of analog amplifiers used in impedance measurement systems, or propagation delays in digital processing, can cause phase shifts unrelated to the DUT. For example, delays can occur due to mixed-signal devices such as analog-to-digital converters placed within the signal processing path. Therefore, the output of an I / Q demodulator may have a phase offset unrelated to the DUT. [Overview of the project] [Problems that the invention aims to solve]

[0014] The purpose of this disclosure is to provide an impedance measurement system that includes a single pin for measuring the impedance of an external DUT, thereby improving sensitivity, reducing susceptibility to noise, and improving measurement accuracy. Furthermore, it is desirable to develop a system that can compensate for phase offset, which improves accuracy. [Means for solving the problem]

[0015] According to a first aspect of this disclosure, an impedance measurement system is provided. The impedance measurement system includes a signal generator. The signal generator includes a memory and is configured to generate a digital test signal and at least one digital demodulated signal based on the memory. The digital test signal has a first frequency. The at least one digital demodulated signal has a first frequency. The impedance measurement system also includes a single pin. The single pin is configured to supply an analog test signal based on the digital test signal to a device under test (DUT) and to measure an analog input signal in response to supplying the analog test signal to the DUT. The impedance measurement system also includes a demodulator. The demodulator is configured to acquire a first filtered digital signal and at least one digital demodulated signal based on an input signal and generate at least one demodulated digital signal indicating impedance.

[0016] According to a second aspect of the present disclosure, an impedance measurement system including a single pin is provided. The impedance measurement system including a single pin includes an oversampling analog-to-digital converter, a digital demodulator coupled to the analog-to-digital converter, and a memory configured to generate a test signal and one or more demodulated signals. The test signal and the one or more demodulated signals are synchronized with each other. Thereby, the impedance measurement system including a single pin can simultaneously perform phase measurement and amplitude measurement of an impedance signal.

[0017] According to a third aspect of the present disclosure, an impedance measurement system including a single pin is provided. The impedance measurement system including a single pin includes an oversampling analog-to-digital converter, a digital demodulator coupled to the analog-to-digital converter, a memory configured to generate a test signal and one or more demodulated signals, and a phase offset compensator. The phase offset compensator is configured to introduce an address offset into one or more demodulated signals and / or the test signal. Thereby, an unknown phase offset between the test signal and the one or more demodulated signals is compensated. Note that the impedance measurement system including a single pin according to the third aspect may include providing and / or using the features described in the second aspect, and may further incorporate other features described herein.

Brief Description of the Drawings

[0018] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. [Figure 1] It is a diagram showing an impedance measurement system according to the prior art. [Figure 2] It is a diagram showing an exemplary embodiment of an impedance measurement system including a single pin according to the present disclosure. [Figure 3] It is a diagram showing in more detail a further exemplary embodiment of an impedance measurement system including a single pin according to the present disclosure. [Figure 4] This figure shows an exemplary embodiment of a single-pin impedance measurement system according to the present disclosure, configured to compensate for phase offset. [Figure 5] This figure shows an exemplary embodiment of a steering device using an impedance measurement system including a single pin, as disclosed herein. [Figure 6] This table compares the performance of the impedance measurement system including a single pin, as disclosed in this disclosure, with that of prior art. [Figure 7] This figure shows another embodiment of an impedance measurement system including a single pin, as disclosed herein. [Modes for carrying out the invention]

[0019] Figure 1 is a circuit diagram of a conventional impedance measurement system 100. System 100 includes a digital-to-analog converter (TX-DAC) 110 that generates a sine wave. The TX-DAC 110 is coupled to a filter 120. The TX-DAC 110 and filter 120 are configured to generate a sine wave signal at pin 130 connected to the DUT.

[0020] System 100 further includes a voltage buffer amplifier (I / V buffer) 140. The I / V buffer 140 is coupled to a bandpass filter 150. The I / V buffer 140 is configured to measure the current flowing through the DUT. This current signal is then filtered by the bandpass filter 150 and sent to an I / Q demodulation block 160. The I / Q demodulation block 160 is configured to generate an I / Q demodulated signal by multiplying the sinusoidal signal input (f), measured at pin 130, by a SIN signal and a COS signal. This generates two signals: input (f) × SIN(f) and input (f) × COS(f). These represent the real and imaginary parts of the sinusoidal signal input (f). By measuring the real and imaginary parts of the sinusoidal signal, the amplitude and phase of the signal can be calculated. These two signals (real and imaginary signals) are then sent to a multiplexer (MUX) 170 configured to interleave the signals in time. Finally, the time-interleaved signal is input to the analog-to-digital converter (ADC) 180.

[0021] The conventional system 100 has several drawbacks. Firstly, the I / Q demodulation process is susceptible to the matching of the SIN and COS signals. Any analog component in system 100 can affect the matching due to variations in processing. Secondly, the I / Q demodulation process is susceptible to variations in phase shift (i.e., delay) and the sine wave signal from DAC 110. Variations in the amplitude of the SIN and COS signals of the analog component affect the output of the I / Q demodulation block 160. Thirdly, the real and imaginary signals are sent to the ADC 180 via MUX 170, which interleaves the signals in time. This doubles the acquisition time, and to reduce impedance measurement errors, the signal must be kept at a constant level between the two acquisition times (only slight signal changes are acceptable). Finally, the bandpass filter 150, positioned before the I / Q demodulation block 160, requires stable bandpass characteristics in the analog domain. Furthermore, if the frequency of the signal supplied to filter 150 changes, corresponding changes are required to the bandpass filter. All these drawbacks limit the sensitivity of system 100. Therefore, attempting to measure small changes in impedance using system 100 complicates the configuration and increases costs.

[0022] The purpose of this disclosure is to overcome the aforementioned shortcomings of the prior art.

[0023] Figure 2 shows an exemplary embodiment of the impedance measurement system 200 including a single pin according to the present disclosure. The impedance measurement system 200 may be connected to an external system (not shown) to acquire a clock signal having a system frequency fs. For example, the system frequency f s It may also be 32MHz.

[0024] System 200 includes a signal generator 201. The signal generator 201 includes a memory 202. The signal generator 201 is configured to generate a test signal 203 based on the contents of the memory 202.

[0025] Memory 202 contains a lookup table (LUT). The LUT stores a predetermined set of values ​​for generating the digital test signal 203 at each memory address.

[0026] In the exemplary embodiment shown in Figure 2, the test signal 203 is a digital signal and is therefore also called the digital test signal 203. In other embodiments, the signal generator 201 may incorporate a digital-to-analog converter. In this case, the output of the signal generator 201 after the test signal has been generated is an analog signal. The digital test signal 203 has a first frequency.

[0027] In the exemplary embodiment shown in Figure 2, the impedance measurement system 200 further includes a digital-to-analog converter (DAC) 209 coupled to a signal generator 201. The DAC 209 acquires a digital test signal 203 and generates at least one analog test signal 206. The at least one analog test signal 206 may be called an excitation signal. In some embodiments, the DAC 209 uses a system frequency f s It may operate at a second frequency smaller than the system frequency f, for example, 4 MHz. In some embodiments, the sampling frequency of the DAC209 is equal to the second frequency. This allows the sampling rate of the DAC209 to be equal to the system frequency f s It will become smaller than that.

[0028] In some embodiments, the frequency of at least one analog test signal 207 is the system frequency f s It is synchronized with the system frequency f. In some embodiments, the frequency of at least one analog test signal 206 is the system frequency f. s The value is set by multiplying the fraction of by a prime number. In some embodiments, the frequency of at least one analog test signal 206 is set by a prime number and the system frequency f sIt may also be based on the product of . The prime numbers may be, for example, 7, 11, 13, 17, 19, etc. In some embodiments, the frequency of at least one analog test signal 206 may be based on the length of the acquisition period of the DAC 206. In some embodiments, the frequency of at least one analog test signal 206 may be determined by the following formula.

[0029]

number

[0030] Here, f ex represents the frequency of the analog test signal 206, i.e., the excitation signal, N represents a prime number, and K represents the length of the acquisition period of DAC209 in terms of the number of system clock cycles.

[0031] As an example to facilitate understanding of this disclosure, the acquisition period is 4096 system clock cycles, and the system frequency f s Table 1 shows the frequencies of the analog test signal 206 for various prime numbers when the frequency is 30.72 MHz.

[0032] [Table 1]

[0033] Advantageously, reducing the sampling rate of the DAC209 allows for a reduction in the number of samples within the LUT, thus enabling a smaller LUT. As a result, memory size and power consumption are also reduced, leading to a more efficient system.

[0034] The impedance measurement system 200 is configured to supply at least one analog test signal 206 to the DUT205 via a single pin 220. This allows the impedance of the DUT205 to be measured.

[0035] The signal generator 201 is further configured to generate at least one digital demodulated signal 204 based on the contents of the memory 202. The at least one digital demodulated signal 204 may have the same frequency as the digital test signal 203. In some embodiments, the at least one digital demodulated signal 204 may be synchronized with the digital test signal 203.

[0036] Memory 202 contains a lookup table (LUT), which stores a predetermined set of values ​​at each memory address for generating at least one digital demodulated signal 204. In other words, the LUT contains multiple samples corresponding to the amplitude values ​​of the digital demodulated signal.

[0037] At least one demodulated signal may include a first sine wave signal and a second sine wave signal (not shown). The second sine wave signal is generated by phase-shifting the first sine wave signal by 90 degrees.

[0038] The impedance measurement system 200 further includes a single pin 220 for supplying an analog test signal (SIG) 206 based on a digital test signal 203 to the DUT 205. In some embodiments, there are no other connections or couplings between the DUT 205 and the impedance measurement system 200. In some embodiments, a ground plane may be coupled to both the DUT 205 and the impedance measurement system 200.

[0039] The impedance measurement system 200 is configured to supply or provide at least one analog test signal 206 to the DUT 205 and to measure the influence of the DUT on at least one analog test signal 206 via pin 220 and input processing stage 211. The input processing stage 211 is coupled to pin 220 and is configured to acquire an analog input signal 207 and generate a first filtered digital signal 208 based on the analog input signal 207.

[0040] The impedance measurement system 200 further includes a demodulator 270. The demodulator 270 is configured to acquire a first filtered digital signal 208 and at least one digital demodulated signal 204 based on an analog input signal 207 to generate at least one demodulated digital signal representing the impedance of the DUT 205.

[0041] Figure 3 shows an exemplary embodiment of the impedance measurement system 200'' including a single pin according to the present disclosure. System 200'' details further implementation examples of System 200. For example, System 200'' includes details of further implementation examples of input processing stage 211 and demodulator 270.

[0042] System 200'' includes a memory LUT configured to generate a digital-based signal DSIG (also known as digital test signal 203). DSIG provides a test signal input to the system and may be an AC signal. In this embodiment, DSIG may be a sinusoidal signal. The frequency of the DSIG signal may be adjustable based on system parameters. DSIG can be considered a modulated signal.

[0043] The memory LUT may further generate a first signal S1, which may be a sine wave signal, and a second signal S2, which may be a cosine wave signal. Signals S1 and S2 may also be AC ​​signals. In the exemplary embodiment of Figure 2, these are sine wave signals, but in other embodiments, they may be other types of signals, such as pulse signals. Signals S1 and S2 can be considered demodulated signals. Either signal S1, S2, or a combination of S1 and S2 can be considered a digital demodulated signal 204. In some embodiments, DSIG and the signals S1 and S2 may be synchronized.

[0044] System 200 further includes a digital-to-analog converter (DAC) corresponding to DAC209 in Figure 2. The DAC receives a base signal DSIG and converts it to an analog signal. The DAC is coupled to one or more filters and buffers 210. The combination of the DAC and one or more filters and buffers 210 generates one or more time-varying signals. These time-varying signals may also be called test signals SIG and SIG'. The time-varying signals SIG and SIG' obtained from pin 220 represent the DUT. Either signal SIG or SIG', or a combination thereof, may also be referred to in this disclosure as analog input signal 207.

[0045] The system 200 may also include a multiplexer 230 configured to combine one or more time-varying signals SIG, SIG' into a single signal. In some embodiments, the multiplexer 230 is part of the input processing stage 211. In some embodiments, the analog input signal 207 may be a single signal. In such embodiments, the system 200 does not include the multiplexer 230. This single signal then passes through the amplifier 240.

[0046] The amplifier 240 is configured to supply the amplified analog input signal 207 to the oversampling ADC 250. In some embodiments, the amplifier 240 may be considered as part of the input processing stage 211.

[0047] The system 200 includes an analog-to-digital converter (ADC) 250. The ADC 250 is configured to convert the signal received from the amplifier 240 into a digital signal. The digital signal may be referred to as the digital input signal 251. The ADC 250 is further configured to oversample the signal when performing the conversion. In some embodiments, the ADC 250 is part of the input processing stage 211.

[0048] A filter 260 is coupled to the ADC 250. The filter 260 may be, for example, a comb filter. The filter 260 is configured to filter the digital input signal 251 to produce a first filtered digital signal 208. In some embodiments, the filter 260 is part of an input processing stage 211.

[0049] The filtered digital signal then passes through a demodulator 270. The demodulator may be, for example, an I / Q demodulator 271. In the exemplary embodiment of Figure 3, the input of the I / Q demodulator 271 is coupled to the output of the filter 260. However, in other embodiments without the filter 260, the I / Q demodulator 271 may be directly coupled to the output of the ADC 250. In the exemplary embodiment of Figure 3, the demodulator is configured to multiply the filtered digital signal by a first signal to generate a real part signal, and by multiplying it by a second signal to generate an imaginary part signal. In other words, the I / Q demodulator is configured to multiply the first filtered digital signal 208 by a first sine wave signal 204a to generate a real part component signal 271a representing the real part of the analog input signal 207, and to multiply the first filtered digital signal 208 by a second sine wave signal to generate an imaginary part component signal 271b representing the imaginary part of the analog input signal 207. These signals pass through an integrator 280 coupled to the output of the I / Q demodulator. The real and imaginary signals are then used to calculate the amplitude and phase of the DUT. Thus, at least one demodulated digital signal representing the impedance of the DUT 205 is based on the real component signal 271a and / or the imaginary component signal 271b.

[0050] In some embodiments, the integrator 280 may have a frequency response having a notch at the frequency of at least one harmonic of at least one demodulated digital signal. This allows the integrator to filter the real component signal 271a and the imaginary component signal 271b to generate at least one demodulated digital signal.

[0051] In some embodiments, the memory may be, for example, a look-up table. A look-up table is a hardware table for storing data. Data from the look-up table may be directly used in the DAC 209 to generate a test signal such as, for example, the digital test signal 203, or may be used to generate the first signal S1 and the second signal S2, that is, the digital demodulation signal 204. In other embodiments, based on the understanding of those skilled in the art, the memory may be other forms of hardware tables.

[0052] Since demodulation is performed in the digital domain, the alignment between the first signal S1 and the second signal S2 is ensured by the configuration. This technique is known in the art. However, in the system 200, since the multiplication of the first signal S1 and the second signal S2 is performed simultaneously on the same signal, only one acquisition per result can be used. This improves the performance of the system as compared to the prior art system of FIG. 1 which requires two samples (i.e., one for I and one for Q) to process both I data and Q data.

[0053] The ADC 250 is an oversampling type ADC and in this exemplary embodiment, is, for example, a 1-bit, second-order sigma-delta type ADC. In the exemplary embodiment of FIG. 3, the ADC 250 operates at the system frequency f s but in other embodiments, may operate at a frequency lower than the system frequency f s . In alternative embodiments, based on the understanding of those skilled in the art, other types of oversampling type ADCs may be used. Since the system 200 uses the oversampling type ADC 250, a band-pass filter is no longer required before the ADC conversion. Instead, only a small anti-aliasing low-pass filter is required by the oversampling approach.

[0054] The test signals used for I / Q demodulation, the first signal S1 and the second signal S2, are based on the same digital signal DSIG generated by the memory LUT. Therefore, the phase difference is constant and does not depend on analog matching between the three signals.

[0055] The frequency of the test signal is synchronized with the first signal S1 and the second signal S2 (demodulated signal), and the number of signal periods is set to be a prime number with respect to the sampling signal. As a result, all harmonic components of the demodulated signal are completely removed by the integrator 280. In this exemplary embodiment, the integrator 280 forms a comb filter with notches for all harmonic components. Therefore, a high-precision analog filter is not required before the ADC 250. In addition, the demodulated signal requires a small number of samples per period, which reduces the load on the memory LUT. Although the number of samples increases the number of harmonic components, the system 200 is configured to be less affected by harmonic components due to the comb filter.

[0056] Similarly, when generating test signals using a DAC, the sampling rate of the DAC can be reduced. This reduces the number of samples in the memory LUT, resulting in a reduction in the area and power consumption of the system 200. The system 200 according to this disclosure is less susceptible to harmonic interference.

[0057] The digital-based signal DSIG is sometimes also called a modulated signal or digital test signal. The first signal S1 and the second signal S2 are sometimes collectively called a demodulated signal or digital demodulated signal.

[0058] The modulated signal DSIG and demodulated signals S1 and S2 provided by the LUT may be in phase. However, as the modulated signal DSIG passes through the system 200 from the LUT to the demodulator 270, multiple processing delays occur, resulting in a phase offset between the modulated signal and the demodulated signal.

[0059] Several methods are known in the art for correcting or canceling phase offsets, depending on the cause of the phase offset. For example, if the phase offset is known, it can be canceled out in external I / Q processing. However, since the phase offset is not always known, errors may still occur. Alternatively, the phase offset may be caused by digital processing. In this case, the phase offset (latency) is due to multiple z -1 Because it is determined by the stage, further z -1 By adding a stage, the total phase shift can be compensated for by making it 360 degrees. However, this method results in increased response time and repetition rate.

[0060] When phase offset occurs in analog signal processing, a filter with a sufficiently wide bandwidth is needed so that the phase shift becomes negligible. For example, the error of the result should be less than 0.02%. However, this method widens the signal bandwidth, making the signal highly susceptible to noise. On the other hand, if the phase offset is due to variations in analog characteristics (e.g., process variations or temperature fluctuations), the phase offset can be canceled by implementing bandwidth trimming of the time constant. However, such a solution is complex and leads to a larger system and longer development time. Alternatively, it is possible to adjust the phase offset by trimming the delay between the phase of the test signal and the phases of the SIN and COS signals (demodulated signals). However, the amplitude of the test signal and / or demodulated signal must be kept constant, which requires a variable full-pass filter. Such filters are expensive to implement and occupy a large area within the system.

[0061] Therefore, there is a need for a new method to compensate for the phase offset of the input signal (i.e., the signal input from the DAC to the demodulator) caused by other factors such as signal processing delays in cable harnesses and measurement circuits, which can overcome the shortcomings of conventional technologies.

[0062] In this disclosure, this phase offset is compensated by introducing offset compensation to the demodulated signals S1, S2 or the digital test signal 203. Therefore, in some embodiments, the signal generator 201 is configured to adjust the phase of at least one digital demodulated signal 204 and / or the digital test signal 203. This allows for correction of the phase offset between the first filtered digital signal 208 and at least one digital demodulated signal 204.

[0063] Figure 4 shows an exemplary embodiment of phase offset compensation for a single-pin impedance measurement system 200'' according to the present disclosure. System 200'' in Figure 4 is identical to system 200' in Figure 3, except that some components have been omitted for ease of understanding. Components common to both Figure 3 and Figure 4 are denoted by the same reference numerals and have the same meaning and function as those in Figure 3.

[0064] In Figure 4, the LUT is shown as two separate elements: one for the modulated signal DSIG and the other for the demodulated signals S1 and S2. This is for ease of understanding. In the embodiment of Figure 4, phase offset compensation is applied only to the demodulated signals S1 and S2. Therefore, in Figure 4, the LUT is shown divided as described above.

[0065] Phase offset compensation is achieved by adding an address offset to a portion of the LUT that generates the demodulated signals S1 and S2.

[0066] Demodulation 270 in system 200'' is performed in the digital domain. The modulated and demodulated signals are based on a memory LUT. The LUT stores the first signal (or second signal). The output of the LUT is connected to the DAC. The DAC generates a test signal, also called an analog test signal. The output of the LUT is also connected to the demodulator 270. The values ​​of the modulated signal DSIG and the demodulated signals S1 and S2 are read cyclically from the memory LUT. Phase offset compensation is achieved by adding an "address offset" to the LUT addresses of the demodulated signals (S1 and S2). Thus, this "address offset" directly corresponds to the phase offset of each signal generated by the signal generator 201. In this way, the signal generator 201 can adjust the phase of at least one digital demodulated signal 204 and / or digital test signal 203 by adding an address offset to a portion of the LUT that generates at least one digital demodulated signal 204 and / or digital test signal 203.

[0067] For example, if the LUT contains N samples corresponding to the amplitude values ​​of the demodulated signals S1 and S2, the "address counter" folds back and cycles at the end, thereby generating continuous demodulated signals S1 and S2. If the LUT for the modulated signal DSIG and the LUTs for the demodulated signals S1 and S2 start from address "0", the phase between the modulated signal DSIG and the first signal S1 is 0 degrees. Also, since the second signal S2 is generated by shifting the phase of signal S1 by 90 degrees, the phase between the modulated signal DSIG and the second signal S2 at address "0" is 90 degrees. In other words, by using subsequent or preceding addresses within the LUT, a signal corresponding to a 90-degree phase offset can be obtained. The address offset defines the magnitude of the additional phase offset added between the modulated signal DSIG and the demodulated signals S1 and S2.

[0068] Address offsets can be generated in several different ways. Some generation methods are described below, but this is not an exhaustive list of all methods for generating address offsets. Other methods may also be applicable, based on the understanding of those skilled in the art.

[0069] The address offset may be provided by an external system, such as an external microcontroller unit, and can be updated at any time while using the impedance measurement system 200, which includes a single pin.

[0070] Alternatively, the impedance measurement system 200 may be configured to determine the address offset internally during the calibration phase. During the calibration phase, the impedance measurement system 200, including a single pin, needs to be connected to a DUT consisting only of capacitive loads. When this condition is met, the expected phase difference between voltage and current is defined as 90 degrees. Demodulated I / Q data is then processed, and the address offset is modified while processing is performed during the calibration phase. This adjusts the measured phase difference between voltage and current, as indicated by the output of the demodulator 270, to be equal to 90 degrees. This can be done using, for example, a simple counter or an algorithm such as, for example, the CORDIC algorithm. When the demodulator's I output is minimized, the corresponding address offset becomes the value required to compensate for the phase offset in signal processing.

[0071] As described above, phase offset may occur due to variations resulting from the analog characteristics of system 200 (e.g., processing variability or temperature fluctuations). In some embodiments, the impedance measurement systems 200, 200' and / or 200'' may include a temperature sensor (not shown) communicatively coupled to a signal generator 201. In such embodiments, memory 202 may include a set of predetermined address offset values ​​corresponding to each temperature value. Thus, the signal generator can acquire temperature measurements and generate a digital test signal 203 and / or a digital demodulated signal 204 based on the values ​​stored in the LUT for the corresponding temperature values.

[0072] As mentioned above, address offset can also be applied to the LUT for the modulated signal rather than the demodulated signal. However, applying the address offset to the demodulated signal is more reliable from the standpoint of secondary effects. This is because it is not affected by the analog settling time, even if the signal starts from a different phase. Therefore, it is preferable to apply the address offset to the demodulated signal.

[0073] The phase offset compensation described above can be used in conjunction with an impedance measurement system including a single pin, which will be described in more detail below.

[0074] Figure 5 shows an exemplary embodiment of a steering device 400 to which the impedance measuring system 200'' according to this disclosure can be applied. System 200'' has the same architecture as system 200 in Figure 2, but may optionally have the architecture of system 200' in Figure 3 or system 200'' in Figure 4. The steering device 400 includes one or more sensors 410. The steering device 400 may be, for example, a steering wheel for an automobile. In other embodiments, based on the understanding of those skilled in the art, the steering device 400 may also be incorporated into other types of vehicles.

[0075] In an exemplary embodiment of the steering device 400, one or more sensors are one or more conductive foils (not shown). As described later, a single pin of the impedance measuring system is coupled to one or more sensors 410 incorporated into the vehicle's steering wheel 400. Here, the impedance measuring system is configured to activate one or more sensors to detect contact between the operator and the steering wheel. A sinusoidal signal generated by the integrated circuit 420 is applied to each of the conductive foils. The system is configured to measure the current and phase shift across the conductive coil in order to measure the impedance.

[0076] During operation, the pressure applied by the operator's hand increases the ground capacitance to the conductive foil, resulting in the addition of resistance Z to the sensor 410. One example of an application involves sensors positioned at different locations on the steering device 400. This allows the operator to input various commands through hand gestures and hand position while maintaining contact with the steering device 400. Examples of control functions include cruise control settings and infotainment functions.

[0077] In an exemplary embodiment of the steering device 400 including the impedance measurement system 200''', the following configuration can be used: The system 200''' and ADC 250 have a system frequency f, for example, 32 megahertz. s The ADC250 is a 1-bit ADC implemented as an oversampling sigma-delta type. The ADC250 has a system frequency f s It operates as follows: The output of the ADC250 is decimated by a decimation filter to provide a sampling rate of 1 megahertz (1:32). In such an embodiment, 128 decimated samples are integrated (cumulative) after demodulation.

[0078] In this exemplary embodiment, the DAC operates at a system frequency f sIt may operate at one-eighth of that frequency. For example, if the system frequency is 32 megahertz, the DAC operates at 4 megahertz. The DAC in this exemplary embodiment is configured to generate test signals up to approximately 150 kilohertz. The exemplary system 200'' uses five memories (lookup tables in this embodiment). Thus, five different frequencies can be selected. The oversampling approach can relax the requirements for the low-pass filter 240 for the DAC output. The low-pass filter 240, placed before the ADC 250, can be implemented in a relatively simple configuration because it only needs to remove very small spurious stones by oversampling by approximately 200 times. Because the bandwidth can be set relatively high, the effects of delay variations that would occur when using a low-frequency filter are reduced.

[0079] In this exemplary embodiment, the frequency of the test signal is synchronized with the system clock frequency. The frequency of the test signal is set as the divided system clock multiplied by a prime number. For example, if one acquisition period is 4096 system clock cycles, the frequency of the test signal (the value stored in memory) is fs / 4096 × prime number. The prime number may be any of the following: 7, 11, 13, 17, 19, etc.

[0080] The exemplary impedance measurement system 200'' described above has a 16-bit resolution even without signal averaging and achieves a fast acquisition time (<200 μs).

[0081] Figure 6 shows Table 500 comparing the performance of an exemplary system 200'' with a prior art system. Column 510 shows several items compared for both systems, column 520 shows data for the exemplary system 200'' of this disclosure, and column 530 shows data for the prior art system.

[0082] As can be seen from the table, the exemplary system 200'' of this disclosure has 16 times higher sensitivity at comparable chip cost (chip size) and comparable power consumption. Furthermore, the exemplary system 200 has 4.5 times faster acquisition time compared to the prior art system. In addition, the exemplary system 200''' has 16 bits of resolution even without additional averaging (averaging for noise reduction is possible), whereas the prior art system has 10 bits of resolution without averaging.

[0083] It should be noted that the single-pin impedance measurement system described herein may be used to measure impedance in a vehicle steering system and to implement a gesture-based human-machine interface system. However, the single-pin impedance measurement system may also be implemented in other types of devices or architectures requiring impedance measurement, as understood by those skilled in the art.

[0084] Figure 7 shows another exemplary embodiment of the impedance measurement system 200A including a single pin according to the present disclosure. System 200A includes memory LUT_A configured to generate a digital-based signal DSIGA. DSIGA provides a test signal input to the system and may be an AC signal. In this embodiment, DSIGA may be a sinusoidal signal. The frequency of the DSIGA signal may be adjustable based on system parameters. DSIGA can be considered a modulated signal. Signal S1A may be a sine signal, and a second signal S2A may be a cosine signal. Signals S1A and S2A may be AC ​​signals. In this embodiment, they may be sinusoidal signals. Signals S1A and S2A can be considered demodulated signals. In some embodiments, signals DSIGA, S1A, and S2A may be synchronized. As described above, in some embodiments, a phase delay may be added to signals S1A and S2A to compensate for signal processing delays unrelated to DUT_A. For example, there is a signal processing delay introduced by the analog-to-digital converter (ADC) 250A. System 200A further includes a digital-to-analog converter (DAC_A). DAC_A receives a base signal DSIGA and converts it to an analog signal. DAC_A is coupled to one or more filters and buffers 210A. The combination of DAC_A and one or more filters and buffers 210A generates one or more time-varying signals. These time-varying signals may also be called test signals SIGA and SIGA'. The time-varying signals SIGA and SIGA' obtained at pin 220A represent DUT_A.

[0085] The system 200A may also include a multiplexer 230A configured to combine one or more time-varying signals SIGA, SIGA' into a single signal. This single signal then passes through amplifier 240A.

[0086] System 200A includes an analog-to-digital converter (ADC) 250A. The ADC 250 is configured to convert the signal received from amplifier 240A into a digital signal. The ADC 250A is further configured to oversample the signal when performing the conversion. A filter 260A is coupled to the ADC 250A. Filter 260A may be, for example, a comb filter. The filtered digital signal then passes through demodulator 270A. The demodulator may be, for example, an I / Q demodulator. The demodulator is configured to multiply the filtered digital signal by a first signal to generate a real part signal, and by multiplying it by a second signal to generate an imaginary part signal. These signals pass through integrator 280A. The real and imaginary part signals are then used to calculate the amplitude and phase of DUT_A.

[0087] In some embodiments, the memory may be, for example, a lookup table. The lookup table is a hardware table that stores data. The data from the lookup table may be used directly in DAC_A to generate a test signal, or it may be used to generate a first signal S1A and a second signal S2A. In other embodiments, as will be understood by those skilled in the art, the memory may be another form of hardware table.

[0088] Since demodulation is performed in the digital domain, the matching between the first signal S1A and the second signal S2A is ensured by the configuration. This technique is known in the art. However, in system 200A, since the multiplication of the first signal S1A and the second signal S2A is performed simultaneously on the same signal, only one acquisition can be used for each result.

[0089] The ADC250A is an oversampling ADC, and in this exemplary embodiment, it is a sigma-delta ADC (1-bit, 2nd-order sigma-delta). In alternative embodiments, other types of oversampling ADCs may be used, based on the understanding of those skilled in the art. Because System 200A uses the oversampling ADC250A, a bandpass filter is no longer required before the ADC conversion. Instead, the oversampling approach requires only a small anti-aliasing low-pass filter.

[0090] The test signals used for I / Q demodulation, the first signal S1A and the second signal S2A, are based on the same digital signal DSIGA generated by memory LUT_A. Therefore, the phase difference is constant and does not depend on analog matching between the three signals.

[0091] The frequency of the test signal is synchronized with the first signal S1A and the second signal S2A (demodulated signal), and the number of signal periods is set to be a prime number with respect to the sampling signal. As a result, all harmonic components of the demodulated signal are completely removed by the integrator 280A. In this exemplary embodiment, the integrator 280A forms a comb filter with notches for all harmonic components. Therefore, a high-precision analog filter is not required before the ADC250A. In addition, the demodulated signal requires a small number of samples per period, which reduces the load on memory LUT_A. Although the number of samples increases the number of harmonic components, the system 200A is configured to be less affected by harmonic components due to the comb filter.

[0092] Similarly, when generating test signals using DAC_A, the sampling rate of DAC_A can be reduced. This reduces the number of samples in memory LUT_A, resulting in a reduction in the area and power consumption of system 200A.

[0093] The system 200A of this disclosure has reduced sensitivity to harmonic components.

[0094] Those skilled in the art will understand that modifications of the disclosed configurations are possible without departing from the scope of this disclosure. Accordingly, the descriptions of the specific embodiments above are for illustrative purposes only and not intended to limit. It will be apparent to those skilled in the art that minor modifications are possible without substantially altering the operation.

Claims

1. An impedance measurement system, A signal generator comprising a memory and configured to generate a digital test signal and at least one digital demodulated signal based on the memory, wherein the digital test signal has a first frequency and at least one of the digital demodulated signals has the first frequency, A single pin configured to supply an analog test signal based on the digital test signal to a device under test (DUT), and to measure an analog input signal in response to supplying the analog test signal to the DUT, A demodulator configured to acquire a first filtered digital signal based on the analog input signal and at least one of the digital demodulated signals to generate at least one demodulated digital signal indicating impedance, An impedance measurement system, including...

2. The impedance measurement system according to claim 1, wherein at least one of the digital demodulated signals includes a first sinusoidal signal and a second sinusoidal signal, the second sinusoidal signal being generated by phase-shifting the first sinusoidal signal by 90 degrees.

3. The impedance measurement system according to claim 1, further comprising an input processing stage, the input processing stage being coupled to the single pin and the demodulator, and configured to acquire the analog input signal and generate the first filtered digital signal based on the analog input signal.

4. The impedance measurement system according to claim 3, wherein the input processing stage includes an oversampling ADC configured to generate a digital input signal based on the analog input signal.

5. The oversampling type ADC has a system frequency f ｓ The impedance measurement system according to claim 4, wherein the ADC is a 1-bit sigma-delta type ADC that operates in the specified manner.

6. The impedance measurement system according to claim 4, wherein the input processing stage includes a filter configured to filter the digital input signal in order to generate the first filtered digital signal.

7. The impedance measurement system according to claim 4, wherein the input processing stage includes an amplifier, and the amplifier is configured to supply the amplified analog input signal to the oversampling ADC.

8. The demodulator includes an I / Q demodulator coupled to the output of the oversampling ADC, The aforementioned I / Q demodulator is The first filtered digital signal is multiplied with the first sinusoidal signal to generate a real part signal representing the real part of the analog input signal. The system is configured to multiply the first filtered digital signal by the second sinusoidal signal to generate an imaginary component signal representing the imaginary component of the analog input signal. At least one of the demodulated digital signals is based on the real component signal and / or the imaginary component signal. The impedance measurement system according to claim 4.

9. The system further includes an integrator coupled to the output of the I / Q demodulator, The integrator includes a frequency response having a notch at the frequency of at least one harmonic of at least one of the demodulated digital signals, The integrator is configured to filter the real and imaginary components of the signal in order to generate at least one demodulated digital signal. The impedance measurement system according to claim 8.

10. The impedance measurement system according to claim 1, further comprising a digital-to-analog converter (DAC), the DAC being coupled to the signal generator and configured to acquire the digital test signal and generate at least one of the analog test signals.

11. The DAC has a system frequency f ｓ The impedance measurement system according to claim 10, having a sampling rate smaller than [a certain value].

12. The frequency of at least one of the analog test signals is the system frequency f ｓ The impedance measurement system according to claim 11, which is set by a value obtained by multiplying a fraction by a prime number.

13. The impedance measurement system according to claim 12, wherein the DAC is coupled to one or more filters and / or one or more buffers configured to acquire an output from the DAC and generate at least one of the analog test signals.

14. The impedance measurement system according to claim 1, wherein the memory includes a lookup table (LUT) in which a predetermined set of values ​​for generating the digital test signal and at least one of the digital demodulation signals is stored at each memory address.

15. The impedance measurement system according to claim 14, wherein the signal generator is configured to adjust the phase of at least one of the digital demodulated signals and / or the digital test signal, thereby correcting the phase offset between the first filtered digital signal and at least one of the digital demodulated signals.

16. The impedance measurement system according to claim 15, wherein the signal generator adjusts the phase of at least one digital demodulated signal and / or the digital test signal by adding an address offset to a portion of the LUT that generates at least one digital demodulated signal and / or the digital test signal.

17. The impedance measurement system according to claim 16, wherein the signal generator is configured to obtain the address offset from an external system to the impedance measurement system.

18. The impedance measurement system according to claim 16, configured to determine the address offset during a calibration phase, the calibration phase comprising coupling the single pin to a DUT consisting solely of a capacitive load.

19. The impedance measurement system according to claim 16, wherein the memory includes a set of predetermined address offset values ​​corresponding to each temperature value.

20. The impedance measuring system according to claim 1, wherein the single pin is coupled to one or more sensors incorporated in a vehicle steering wheel, and the impedance measuring system is configured to activate one or more of the sensors to detect contact between an operator and the vehicle steering wheel.

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