Test and measurement apparatus, data pattern generation method based thereon, and oscilloscope

Abstract

To enable both signal measurement and data pattern generation in a single device. [Solution] The test measurement device 10 includes a display 36, transmitters 16 and 18, receivers 12 and 14, one or more channels configured to send and receive signals, a data pattern generator 42, and a high-speed serial trigger (HSST) circuit 26. The high-speed serial trigger circuit 26 operates at 1 gigabit per second or more and is connected to one or more receivers to receive data patterns from the data pattern generator 42 and effectively utilize the high-speed serial trigger circuit 26.

Description

Technical Field

[0001] The present disclosure relates to a test and measurement device, and more particularly to a test and measurement device such as an oscilloscope having a built-in advanced data pattern generator function.

Background Art

[0002] An arbitrary waveform generator (AWG) is a type of test and measurement device that provides signals used in testing a device under test (DUT). Usually, users use these in addition to test and measurement devices such as oscilloscopes.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Some test and measurement devices such as oscilloscopes have an integrated or built-in arbitrary function generator (AFG). The AFG can generate functions, but it is usually performed in the analog domain. Currently, there is no option to loop back high-speed serial data to the analog channels of the device.

[0005] Using the same equipment for data pattern generation as for testing and measuring the DUT significantly reduces the complexity of the test environment. [Means for solving the problem]

[0006] Embodiments of the technology disclosed herein generally include an advanced data pattern generator function integrated into a test and measurement device for signal analysis (e.g., an oscilloscope). The output signal of this advanced data pattern generator function can be used externally from the device or internally distributed to the channel front end for direct acquisition. For example, according to some embodiments of the disclosure, an oscilloscope with a built-in high-speed serial data pattern generator function can loop back high-speed serial data to the oscilloscope's analog channels. This allows the user to easily exercise the oscilloscope's high-speed trigger function and other functions. Furthermore, according to some embodiments, the ability to create or load waveforms of various protocols based on scrambling and encoding mechanisms is also obtained.

[0007] Embodiments of the technology disclosed herein are not necessarily limited to being implemented in an oscilloscope. These built-in advanced functions can also be exercised using test equipment or a device under test (DUT). This does not necessarily have to be an oscilloscope. One embodiment is an oscilloscope with advanced data pattern generator functionality, with or without a high-speed serial trigger circuit. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an embodiment of a test and measurement device equipped with advanced data pattern generator capabilities. [Figure 2] Figure 2 shows an embodiment of a user interface that allows the user to select a scrambler and encoder to generate the corresponding waveform. [Figure 3] Figure 3 shows a flowchart of an embodiment of a method for generating advanced data pattern waveforms. [Modes for carrying out the invention]

[0009] Figure 1 shows an embodiment of a test and measurement device 10 equipped with an advanced data pattern generator function. The advanced data pattern generator (ADPG) function allows for verification of the functionality of high-speed serial triggers and other devices. The ADPG can be used to verify high-speed serial triggers (HSSTs) at any stage of quality control for any device or product. Users can generate customizable waveforms, such as inserting error bits or reading waveforms of interest from memory. The ADPG can generate high-speed waveforms based on the available bandwidth of the device, exceeding 25 gigabits per second (Gbps) in some embodiments. The ADPG allows users to effectively utilize any device, other test equipment, or device under test (DUT). Because the ADPG resides within other devices such as an oscilloscope, a separate device, such as a separate waveform generator, is not required.

[0010] In this application, "high speed" refers to a speed of 1 gigabit per second (Gbps) or higher.

[0011] In Figure 1, the device 10 has one or more transmitters and one or more receivers, which may consist of one or more transceivers that combine both functions. In the following description, the transmitters and receivers are described as being associated with channels 1 and 2 of the device, but it should be understood that the device may contain many more transmitters, receivers, and channels. The use of the numbers 1 and 2 distinguishes two different channels, but does not mean that there are only two channels. In the embodiment of Figure 1, the device has receiver 12 connected to channel 1 of the device and receiver 14 connected to a second channel (channel 2). The device also has one or more transmitters, such as transmitter 16 on channel 1 and transmitter 18 on channel 2. The input channels connected to receivers 12 and 14 may include some form of chip, such as an interface (I / F) circuit or application-specific integrated circuit (ASIC) for receiving input signals (20 for receiver 12 and 22 for receiver 14). The receiver multiplexer (RxMUX) 24 controls which channel's received data is coupled to the high-speed serial trigger (HSST) circuit 26. Transmitters 16 and 18 may have built-in pre-emphasis functions to compensate for signal loss in the circuits driving the signals.

[0012] Receivers 12 and 14 function as deserializers, converting high-speed serial data into low-speed parallel data. In most cases, receivers like 12 and 14 function as clock data recovery (CDR) modules. For example, the receivers can be composed of Intel H-tiles, but this is not intended to limit them to any particular high-speed circuit, nor does it suggest such a limitation. The HSST circuit 26 receives low-speed parallel data from the RxMUX 24, including data from the selected high-speed receiver. The HSST circuit 26 is a primary flexible serial trigger logic / state machine, typically built into the device, allowing the user to trigger the device for desired patterns, errors, sequences, etc. The output of the HSST 26 typically triggers the device's master trigger circuit 28, but may also be a stimulus signal to the ADPG state machine 30.

[0013] On the transmission side, the ADPG receives input from an ADPG user interface 38 displayed on a display 36. The display 36 may consist of a touchscreen or have adjacent user control devices, and a combination of these constitutes the user interface. The user interacts with the device 10 through the display / user interface 36 and provides generated data patterns by selection, input, or other means. These may include executable code or software running on one or more processors (such as 34). This information is passed to one or more processors, which then create or access (if stored) the generated patterns and transmit the patterns to the waveform generator 33. The waveform generator 33 may consist of a number of components not shown in this application. These may include, but are not limited to, oscillators, waveform generation / shaping circuits, modulation circuits (modulators), signal adjustment stages, etc.

[0014] The waveform generator 33 transmits waveform data through interface 32, such as a PCIe (Peripheral Component Interface express) interface. The state machine 30 may respond to various stimulus signals. The state machine 30 may control which pattern to play, or control the process of switching sequentially between various patterns in memory (stepping). It may receive patterns received through receivers 12 and 14, change the patterns, or change the patterns coming through interface 32.

[0015] Block 40 includes a PRBS (pseudo-random binary sequence) generator 42 and a block RAM 44. In one embodiment, an FPGA (Field Programmable Gate Array) may include components from interface 32 to the receiver and transmitter in block 11. This is merely one example, and other configurations are possible. The output of block 40 is sent to the encoder / scrambler 45, which will be described in detail below with respect to the user interface in Figure 2.

[0016] In one embodiment, the transmitter multiplexer (TxMUX) 46 does not function as a multiplexer. Rather than selecting a channel to receive the output signal, the TxMUX transmits the same output signal to both an internal channel and an external connector interface. In another embodiment, the TxMUX 46 can also select a channel to receive the generated data pattern. In one embodiment, a transmitter connected to channel 2 outputs a signal outside the device 10 through an external connector interface 48. The interface 48 is external in that it transmits the data pattern outside the device 10, but the interface 48 is not external to the device. The interface 48 may be part of the device 10. Providing the data pattern outside the device enables a wide variety of applications, such as applying the data pattern to a device under test 52. The external connector interface 48 may consist of any of several types of interfaces, such as an RF (radio frequency) interface or an SMA (SubMiniature Type A) interface.

[0017] In another embodiment, the TxMUX46 may choose to output the data pattern via path 50, and then internally redistribute the data pattern to one or more of the device's channel input I / F 20 and 22 to send it to receivers 12 and 14 without using external cables of the device 10. The ability to distribute the output data pattern to the device's input channels allows for the utilization, testing, and demonstration of the device's high-speed serial data triggering capabilities.

[0018] To allow the user to select the pattern they wish to generate, the ADPG user interface (U / I) 38 may provide the user with a list of possible scramblers and encoders (details shown in Figure 2). For high-speed protocols, the user generally needs to consider two blocks, a scrambler 60 and an encoder 62, when generating known waveforms for the HSST data path and setting any triggers of interest. Figure 2 shows various protocols such as NRZ and 8b10b, and their associated scrambler and encoder schemes. PCIe12 shown in this interface refers to the first and second generations of PCIe, while PCIe345 refers to the third, fourth, and fifth generations of PCIe. USBG1 and USBG2 refer to the first and second generations of USB3.

[0019] Based on the type of waveform of interest, the user can select an option from the S and E drop-down menus 60 and 62, as shown in Figure 2. For improved visibility, the user interface may include the polynomials and encoding schemes required for each protocol to generate the waveform. Note that these options are only illustrative examples of the available options. These options may further include PAM (Pulse Amplitude Modulation) supporting PCIe 6 and USB (Universal Serial Bus) version 4.

[0020] The user configures the system via U / I 38. The customer provides high-level or low-level descriptions through U / I 38, and the waveform generator 33 receives these inputs and generates a waveform. The waveform generator 33 modifies the inputs as necessary to generate a waveform and then transmits the waveform to the block RAM 44. The waveform may be generated by the waveform generator 33 in FIG. 1 or may be "generated" by accessing a predefined waveform in the memory represented by the block RAM 44. As an example of low-level control, the user may manually input a bit pattern, including error bits and anomalies that the user wishes to include. When the user inputs a pattern of 0s and 1s, the state machine 30 uses this memory portion in the block RAM 44 to bypass the encoder / scrambler 45 and transmit the user's pattern unchanged.

[0021] As an example of high-level control, the user can simply select a pattern with a PCIe-compliant pattern or a similar common label on a repeating loop. Since the waveform generator 33 knows what the compliant pattern is, it obtains the raw compliant pattern, passes it to the encoder / scrambler 45 to generate the data, and stores it in the block RAM 44. Since this data is already encoded / scrambled, the state machine resends the raw data stored in the block RAM 44.

[0022] As another example of high-level control, the user may desire, for example, an infinitely continuous scrambled PCIe packet. The pattern length is too long to be pre-calculated and placed in the block RAM 44 in advance. The waveform generator 33 simply loads a plurality of 0s into the block RAM 44, and the encoder / scrambler 45 continuously scrambles these 0 payloads so that they can be transmitted indefinitely.

[0023] The data pattern generated as a waveform is changeable. Conditions under which the data pattern may be changed include, but are not limited to, a second user input after a user input for selecting or entering the data pattern, a trigger generated in the HSST circuit, a specific state of the device such as after each acquisition (waveform data acquisition) if the device is an oscilloscope, etc. Other changes may also occur.

[0024] Figure 3 shows a flowchart of a process for generating a waveform from a user input. The process starts at step 70, where the device displays an ADPG user interface. The user makes a selection, and the device receives the selection at step 72. At step 74, the device generates a waveform corresponding to the pattern defined by the user. The generation of the pattern may use a scrambler, an encoder, both, or neither. If neither the scrambler nor the encoding is used, the data simply passes through the encoder / scrambler 45 (just pass through). Referring to Figure 1, the device loads the waveform into the memory represented by the block RAM 44, and it is read out when the transmission path is selected. As described above, the generation of the waveform also includes accessing past waveforms from the memory. In one embodiment, at step 76, in this process, the device may determine to transmit the signal to both an internal path and an external path, and in that case, it is performed at step 78 as described above. In another embodiment, the device may either select the internal path at step 82 or select the external interface at step 80.

[0025] In one embodiment, the receiver 12 or 14 functions as a deserialzier, and this function uses one receiver. When the transmitter and the receiver are part of the same transceiver, the transmitter channel associated with the receiver used is not used. The ability to utilize the unused transmitter channels for internal distribution of high-speed signals does not increase the hardware requirements of the device.

[0026] The above explanation demonstrates that advanced data pattern generator (ADPG) functionality can be incorporated into existing equipment, eliminating the need for additional equipment such as that required when using an arbitrary waveform generator.

[0027] An external path that distributes the signal to an external interface allows the user to pass the transmitted test signal through any conceivable channel that degrades the signal, such as long-distance coaxial cable, PCB loss traces, and crosstalk injection, and then return the signal to the input channel to further exercise the functionality of the HSST. Much of the analog degradation limit that the receiver can tolerate is set by the receiver itself. The receiver and HSST logic allow the device to trigger on signals applied in a non-ideal area (either customer or ADPG signals), i.e., degraded signals. In this embodiment, the ADPG may not play a very important role because the user is usually interested in their own signal. The ADPG adds a stimulus signal that would conventionally need to be generated by another device. This signal is used to drive the user's DUT and perform some function on its data. Its output signal can also be acquired and analyzed using an oscilloscope and HSST combination.

[0028] Embodiments of the disclosed technology can operate on a specially programmed general-purpose computer, including specially created hardware, firmware, digital signal processors, or processors that operate according to programmed instructions. The terms “controller” or “processor” in this application mean microprocessors, microcomputers, ASICs, and dedicated hardware controllers, etc. Embodiments of the disclosed technology can be implemented by one or more computers (including monitoring modules) or other devices, using computer-readable data such as program modules and computer-executable instructions. Generally, program modules include routines, programs, objects, components, data structures, etc., which, when executed by a processor in a computer or other device, perform specific tasks or implement specific abstract data type expressions. Computer-executable instructions may be stored on computer-readable storage media such as hard disks, optical disks, removable storage media, solid-state memory, and RAM. As will be understood by those skilled in the art, the functions of the program modules may be combined or distributed as needed in various embodiments. Furthermore, these functions can be embodied in whole or in part in firmware or hardware equivalents such as integrated circuits or field-programmable gate arrays (FPGAs). One or more aspects of the disclosed technology can be more effectively implemented using specific data structures, such data structures are considered to be within the scope of computer-executable instructions and computer-usable data described herein.

[0029] The disclosed embodiments may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored in one or more computer-readable media that can be read and executed by one or more processors. Such instructions may be referred to as computer program products. The computer-readable media described herein means any medium accessible by a computing device. For example, but not limited to, computer-readable media may include computer storage media and communication media.

[0030] Computer storage media means any medium that can be used to store computer-readable information. Examples of computer storage media include, but are not limited to, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory and other memory technologies, compact disc read-only memory (CD-ROM), DVD (Digital Video Disc) and other optical disc storage devices, magnetic cassettes, magnetic tapes, magnetic disk storage devices and other magnetic storage devices, and any other volatile or non-volatile removable or non-removable media implemented by any technology. Computer storage media exclude signals themselves and temporary forms of signal transmission.

[0031] A communication medium means any medium that can be used to transmit computer-readable information. Examples of communication mediums, though not limited to them, include coaxial cables, fiber optic cables, air, or any other medium suitable for transmitting electrical, optical, radio frequency (RF), infrared, sound, or other types of signals. Examples

[0032] The following examples are provided that are useful for understanding the technology disclosed herein. These embodiments may include one or more of the examples described below, or any combination thereof.

[0033] Embodiment 1 is a test measurement apparatus comprising a display, one or more transmitters, one or more receivers, one or more channels configured to transmit and receive signals, a data pattern generator, and a high-speed serial trigger (HSST) circuit operating at 1 gigabit per second or more, wherein the high-speed serial trigger circuit is connected to the one or more receivers and receives data patterns from the data pattern generator to exercise (effectively utilize) the high-speed serial trigger circuit.

[0034] Example 2 is the test measurement apparatus of Example 1, wherein one output of the one or more transmitters is connected to the input channel of the test measurement apparatus.

[0035] Example 3 is a test and measurement apparatus according to either Example 1 or 2, wherein one output of the one or more transmitters is connected to the external connector interface of the test and measurement apparatus.

[0036] Example 4 is a test and measurement apparatus according to any of Examples 1 to 3, further comprising one or more processors, wherein the data pattern generator consists of a program executed by the one or more processors that causes the one or more processors to perform the process of generating the data pattern.

[0037] Example 5 is the test measurement apparatus of Example 4, wherein one or more processors are further configured to execute a program that causes one or more processors to perform the process of displaying a user interface on the display.

[0038] Example 6 is the test measurement apparatus of Example 5, wherein a program that causes one or more processors to perform the process of displaying the user interface includes a program that causes one or more processors to perform the process of receiving user input specifying the pattern to be generated.

[0039] Example 7 is the test measurement apparatus of Example 6, wherein the user input includes any of the following: a training pattern, a stored pattern, a manually entered pattern, or a modified pattern.

[0040] Example 8 is the test measurement apparatus of Example 6, wherein the generated data pattern can be modified by one or more of the following: user input through the user interface, trigger events from the HSST circuit, and changes in the state of the test measurement apparatus.

[0041] Example 9 is a test and measurement apparatus according to any of Examples 1 to 8, further comprising a scrambler and an encoder.

[0042] Example 10 is the test measurement apparatus of Example 9, wherein the generated data pattern is generated based on the scrambler, the encoder, or both the scrambler and the encoder.

[0043] Example 11 is a method for generating a data pattern from a test measurement device, comprising: a process of displaying a user interface that provides options for a user to define a data pattern; a process of receiving a user-defined data pattern through the user interface; a process of generating a waveform from the user-defined data pattern; and a process of selectively distributing the waveform to at least one of the input channels of the test measurement device and the external interface of the test measurement device.

[0044] Example 12 is the method of Example 11, wherein the process for generating the waveform includes the process for generating a new waveform from the user-defined data pattern.

[0045] Example 13 is a method of either Example 11 or 12, wherein the process for generating the waveform includes a process for accessing memory and obtaining data corresponding to the user-defined data pattern.

[0046] Example 14 is a method of any of Examples 11 to 13, further comprising the process of selecting the distribution path of the waveform through the user interface described above.

[0047] Example 15 is a method of any of Examples 11 to 14, wherein the process for generating the waveform includes a process for generating a waveform at a speed of 1 gigabit per second or more.

[0048] Example 16 is a method according to any of Examples 11 to 15, wherein the process for generating the waveform includes a process for modifying the waveform based on one or more second user inputs received through the user interface.

[0049] Example 17 is a method according to any of Examples 11 to 16, wherein the process for generating the waveform includes any of the following: a process using a scrambler, a process using an encoder, a process using both the scrambler and the encoder, or a process that does not use either the scrambler or the encoder.

[0050] Embodiment 18 is an oscilloscope comprising a display, one or more transmitters, one or more receivers, one or more channels configured to transmit and receive signals, a data pattern generator for generating waveforms from user-defined data patterns, and a path selector for selectively distributing the waveforms to at least one of the input channels of the oscilloscope and the external connector interface of the oscilloscope.

[0051] Example 19 is the oscilloscope of Example 18, wherein the data pattern generator operates at 1 gigabit per second or more.

[0052] Example 20 is an oscilloscope according to either Example 18 or 19, further comprising one or more processors, wherein the data pattern generator consists of a program executed by the one or more processors that causes the one or more processors to perform the process of generating the data pattern.

[0053] Example 21 is an oscilloscope of Example 20, wherein one or more processors are further configured to execute a program that causes one or more processors to perform the process of displaying a user interface on the display.

[0054] Example 22 is an oscilloscope of Example 21, wherein a program that causes one or more processors to perform the process of displaying the user interface includes a program that causes one or more processors to perform the process of receiving user input specifying the data pattern to be generated.

[0055] Example 23 is the oscilloscope of Example 22, wherein the user input includes one of the following: a training pattern, a stored pattern, a manually entered pattern, or a modified pattern.

[0056] Example 24 is the oscilloscope of Example 22, wherein the generated data pattern can be modified by one or more of the following: user input through the user interface and / or changes in the state of the oscilloscope.

[0057] Example 25 is the oscilloscope of Example 18, further comprising a scrambler and an encoder.

[0058] Example 26 is the oscilloscope of Example 25, wherein the data pattern is generated based on the scrambler, the encoder, or both the scrambler and the encoder.

[0059] All functions disclosed in the specification, claims, abstract and drawings, and all steps in any method or process disclosed, may be combined in any combination, except where at least some of such functions or steps are mutually exclusive. Each of the functions disclosed in the specification, abstract, claims and drawings may be replaced by an alternative function that serves the same, equivalent or similar purpose, unless otherwise specified.

[0060] In addition, the description of this application refers to certain features. It should be understood that the disclosures herein include all possible combinations of these particular features. Where a particular feature is disclosed in relation to a particular embodiment, that feature may also be available in relation to other embodiments, to the extent possible.

[0061] Furthermore, when this application refers to a method having two or more defined steps or processes, these defined steps or processes may be performed in any order or simultaneously, as long as the circumstances do not rule out such possibilities.

[0062] For the sake of explanation, specific embodiments of the present invention have been illustrated and described, but it should be understood that various modifications are possible without deviating from the gist and scope of the present invention. Therefore, the present invention should not be limited to anything other than the appended claims. [Explanation of Symbols]

[0063] 10 Test and measurement device 12 receivers 14 Receivers 16 Transmitters 18 Transmitters 20 Interface (I / F) circuits or chips 22 Interface (I / F) circuits or chips 24 RxMUX 26. High-Speed ​​Serial Trigger (HSST) Circuit 28 Master Trigger 33 Waveform Generator 34 one or more processors 36 displays 38. Advanced Data Pattern Generator (ADPG) User Interface 42 PRBS Generators 44-block RAM 45 Encoders / Scramblers 46 TxMUX 48 External Connectors and Interfaces 52 Device under test

Claims

1. A test and measurement device, The display and One or more transmitters, One or more receivers, One or more channels configured to transmit and receive signals, Data pattern generator, High-speed serial trigger (HSST) circuit operating at over 1 gigabit per second and A test and measurement device comprising the above, wherein the high-speed serial trigger circuit is connected to one or more receivers and receives data patterns from the data pattern generator and utilizes the high-speed serial trigger circuit.

2. The test and measurement apparatus according to claim 1, wherein one output of one or more of the above transmitters is connected to the input channel or external connector interface of the test and measurement apparatus.

3. One or more of the above processors The process of displaying the user interface on the above display, The process of receiving user input to specify the pattern to be generated through the above user interface, and The test and measurement apparatus according to claim 1, configured to execute a program that causes one or more processors to perform the above-mentioned task.

4. The test measurement apparatus according to claim 3, wherein the user input includes any of the following: a training pattern, a stored pattern, a manually entered pattern, or a modified pattern.

5. The test and measurement apparatus according to claim 3, wherein the generated data pattern can be modified by one or more of the following: user input through the user interface, a trigger event from the HSST circuit, and a change in the state of the test and measurement apparatus.

6. The test and measurement apparatus according to claim 1, wherein the generated data pattern is generated based on a scrambler, an encoder, or both the scrambler and the encoder.

7. A method for generating data patterns from a test measurement device, The process of displaying a user interface that provides the user with options to define data patterns, The process of receiving user-defined data patterns through the above user interface, The process of generating a waveform from the above user-defined data pattern, A process for selectively distributing the above waveform to at least one of the input channels and external interfaces of the test and measurement device. A method for generating data patterns from a test and measurement device equipped with [a specific feature / function].

8. A method for generating a data pattern from a test measurement apparatus according to claim 7, further comprising a process for selecting the distribution path of the waveform through the user interface described above.

9. A method for generating a data pattern from a test measurement apparatus according to claim 7, wherein the process for generating the above waveform includes any of the following: a process using a scrambler, a process using an encoder, a process using both the above scrambler and the above encoder, or a process that does not use either the above scrambler or the above encoder.

10. It is an oscilloscope, The display and One or more transmitters, One or more receivers, One or more channels configured to transmit and receive signals, A data pattern generator that generates waveforms from user-defined data patterns, A path selector that selectively distributes the waveform to at least one of the input channels of the oscilloscope and the external connector interface of the oscilloscope. An oscilloscope equipped with [a specific feature].

11. One or more of the above processors, The process of displaying the user interface on the above display, The process involves receiving user input specifying the data pattern to be generated through the user interface described above. The oscilloscope according to claim 10, configured to execute a program that causes one or more processors to perform the above-mentioned task.

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