Motherboard for display devices

Abstract

To provide a motherboard for display devices that can improve yield. [Solution] According to the embodiment, the mother board for a display device comprises a display area for displaying an image, a margin area outside a cut line for cutting out the display area, a display element disposed in the display area, a first partition wall disposed in the margin area and including a plurality of first segments and a plurality of second segments, and a first sealing layer formed of an inorganic insulating material, disposed above the display element and the first segments, and not disposed above the second segments. The second segments have a planar shape different from that of the first segments.

Description

Technical Field

[0001] Embodiments of the present invention relate to a mother substrate for a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies for improving the yield are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

[0006] According to another embodiment, the mother board for a display device includes a display area for displaying an image, a margin area outside a cut line for cutting out the display area, an inorganic insulating layer disposed in the display area and the margin area, a display element disposed in the display area, a first partition wall disposed above the inorganic insulating layer in the margin area and including a plurality of first segments and a plurality of second segments, a first sealing layer made of an inorganic insulating material and disposed above the display element and the first segments but not above the second segments, and a resin layer disposed on the first sealing layer in the margin area.

[0007] In yet another embodiment, the mother board for a display device comprises a display area for displaying an image, a margin area outside a cut line for cutting out the display area, a display element disposed in the display area, a first partition wall disposed in the margin area and including a plurality of first segments, a plurality of second segments, and a plurality of third segments, and a first sealing layer formed of an inorganic insulating material and disposed above the display element and the first segment. The first segment, the second segment, and the third segment have different planar shapes from each other.

[0008] In yet another embodiment, the mother board for a display device comprises: a display area for displaying an image; a margin area outside a cut line for cutting out the display area; an inorganic insulating layer disposed in the display area and the margin area; a display element disposed in the display area; a first partition wall disposed above the inorganic insulating layer in the margin area and including a plurality of first segments, a plurality of second segments, and a plurality of third segments located between the plurality of first segments and the plurality of second segments; a first sealing layer made of an inorganic insulating material and disposed above the display element, the first segments, and the second segments; and a resin layer disposed above the first segments and the third segments in the margin area but not above the second segments. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 shows an example of the configuration of a display device according to the first embodiment. [Figure 2] Figure 2 is a schematic plan view showing an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display panel along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic plan view of the motherboard according to the first embodiment. [Figure 5] Figure 5 is a schematic plan view of a portion of the motherboard. [Figure 6] Figure 6 is a schematic plan view showing the island-like area and its vicinity. [Figure 7] Figure 7 is a schematic enlarged view showing section VII in Figure 6. [Figure 8] Figure 8 is a schematic cross-sectional view along the line VIII-VIII in Figure 7. [Figure 9] Figure 9 is a flowchart showing an example of a method for manufacturing a display device. [Figure 10A] Figure 10A is a schematic cross-sectional view showing the manufacturing process of a display device. [Figure 10B]Figure 10B is a schematic cross-sectional view showing the process following Figure 10A. [Figure 10C] Figure 10C is a schematic cross-sectional view showing the process following Figure 10B. [Figure 10D] Figure 10D is a schematic cross-sectional view showing the process following Figure 10C. [Figure 10E] Figure 10E is a schematic cross-sectional view showing the process following Figure 10D. [Figure 10F] Figure 10F is a schematic cross-sectional view showing the process following Figure 10E. [Figure 10G] Figure 10G is a schematic cross-sectional view showing the process following Figure 10F. [Figure 10H] Figure 10H is a schematic cross-sectional view showing the process following Figure 10G. [Figure 10I] Figure 10I is a schematic cross-sectional view showing the process following Figure 10H. [Figure 10J] Figure 10J is a schematic cross-sectional view showing the process following Figure 10I. [Figure 11A] Figure 11A is a schematic cross-sectional view showing the structure of the margin area in the manufacturing process of the display device. [Figure 11B] Figure 11B is a schematic cross-sectional view showing the process following Figure 11A. [Figure 11C] Figure 11C is a schematic cross-sectional view showing the process following Figure 11B. [Figure 11D] Figure 11D is a schematic cross-sectional view showing the process following Figure 11C. [Figure 12] Figure 12 is a schematic enlarged view showing the display device according to the second embodiment. [Figure 13] Figure 13 is a schematic cross-sectional view taken along line XIII-XIII in Figure 12. [Figure 14] Figure 14 is a schematic enlarged view showing the display device according to the third embodiment. [Figure 15] Figure 15 is a schematic cross-sectional view taken along line XV-XV in Figure 14.

Mode for Carrying Out the Invention

[0010] The embodiments will be described below with reference to the drawings. Note that the disclosure is merely an example, and modifications that can be easily conceived by those skilled in the art while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment in order to clarify the explanation; however, these are merely examples and do not limit the interpretation of the present invention. In this specification and in each drawing, components that perform the same or similar functions as those described above in previously shown drawings are given the same reference numerals, and redundant detailed explanations may be omitted as appropriate. The drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis will be referred to as the first direction X, the direction along the Y axis as the second direction Y, and the direction along the Z axis as the third direction Z. Viewing the various elements parallel to the third direction Z is called a plan view. Each embodiment of the display device is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] [First Embodiment] Figure 1 shows an example configuration of a display device DSP according to this embodiment. The display device DSP includes a display panel PNL including an insulating substrate 10. The display panel PNL has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.

[0012] In this embodiment, the shapes of the substrate 10 and the display area DA in plan view are circular. Here, the circular shape is not limited to a perfect circle, but includes shapes such as a circle with a part missing, an ellipse, or an oblong shape. Furthermore, the shapes of the substrate 10 and the display area DA in plan view are not limited to a circle, but may be other shapes such as a rectangle, square, or ellipse.

[0013] In the example shown in Figure 1, an annular dam structure DS is positioned in the surrounding region SA. The dam structure DS encloses the display region DA. The shape of the dam structure DS in plan view is, for example, circular, but is not limited to this example. The dam structure DS can be formed, for example, by an organic insulating layer 12 (see Figure 3), which will be described later.

[0014] The display area DA comprises a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. Each pixel PX includes a plurality of sub-pixels SP that display different colors. In this embodiment, it is assumed that each pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. For example, the first color is blue, the second color is green, and the third color is red, but this is not an example. Each pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0015] The display device DSP further includes a terminal section T located in the peripheral region SA. A flexible circuit board, for example, that supplies voltage and signals for driving the display device DSP, is connected to the terminal section T.

[0016] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0017] The display area DA is arranged with multiple scan lines GL that supply scan signals to the pixel circuit 1 of each sub-pixel SP, multiple signal lines SL that supply video signals to the pixel circuit 1 of each sub-pixel SP, and multiple power lines PL. In the example in Figure 1, the scan lines GL and power lines PL extend in the first direction X, and the signal lines SL extend in the second direction Y.

[0018] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element DE.

[0019] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0020] Figure 2 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP2 and SP3 are aligned with sub-pixel SP1 in the first direction X. Furthermore, sub-pixels SP2 and SP3 are aligned in the second direction Y.

[0021] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP2 and SP3 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP1 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0022] A rib layer 5 is arranged in the display area DA. In this embodiment, the rib layer 5 is an example of an inorganic insulating layer. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, pixel aperture AP1 is larger than pixel aperture AP2, and pixel aperture AP2 is larger than pixel aperture AP3. That is, among the sub-pixels SP1, SP2, and SP3, sub-pixel SP1 has the largest aperture ratio, and sub-pixel SP3 has the smallest aperture ratio. However, the sizes of pixel apertures AP1, AP2, and AP3 are not limited to this example.

[0023] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the pixel aperture AP3.

[0024] The portion of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlaps with the pixel aperture AP1 constitutes the display element DE1 of the sub-pixel SP1. The portion of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlaps with the pixel aperture AP2 constitutes the display element DE2 of the sub-pixel SP2. The portion of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlaps with the pixel aperture AP3 constitutes the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0025] A conductive partition wall 6 (second partition wall) is positioned above the rib layer 5. The partition wall 6 serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition wall 6 overlaps with the rib layer 5 overall and has a similar planar shape to the rib layer 5.

[0026] Specifically, partition wall 6 has partition opening 601A in sub-pixel SP1, partition opening 602A in sub-pixel SP2, and partition opening 603A in sub-pixel SP3. Partition openings 601A, 602A, and 603A overlap with the entirety of pixel openings AP1, AP2, and AP3, respectively. Furthermore, partition openings 601A, 602A, and 603A overlap with the entirety of display elements DE1, DE2, and DE3, respectively. In other words, partition wall 6 surrounds display elements DE1, DE2, and DE3.

[0027] Figure 3 is a schematic cross-sectional view of the display panel PNL along the line III-III in Figure 2. A circuit layer 11 is placed on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring, such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11.

[0028] The lower electrodes LE1, LE2, and LE3 are positioned on top of the organic insulating layer 12. The rib layer 5 is positioned on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross-section of Figure 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12.

[0029] The partition wall 6 includes a conductive lower part 61 positioned on the rib layer 5 and an upper part 62 positioned on the lower part 61. In this embodiment, the lower part 61 of the partition wall 6 corresponds to the second lower part, and the upper part 62 of the partition wall 6 corresponds to the second upper part.

[0030] The upper section 62 has a greater width than the lower section 61. As a result, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of the partition wall 6 is called an overhang.

[0031] In the example shown in Figure 3, the lower section 61 has a bottom layer 63 positioned on top of the rib layer 5 and an axial layer 64 positioned on top of the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the axial layer 64. Also, in the example shown in Figure 3, both ends of the bottom layer 63 protrude from the sides of the axial layer 64.

[0032] Furthermore, in the example shown in Figure 3, the upper section 62 comprises a first top layer 65 and a second top layer 66 positioned on top of the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, it is not limited to this, and the first top layer 65 and the second top layer 66 may have equivalent widths.

[0033] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surface of the lower part 61 of the partition wall 6.

[0034] Display element DE1 includes a cap layer CP1 placed on top of the upper electrode UE1. Display element DE2 includes a cap layer CP2 placed on top of the upper electrode UE2. Display element DE3 includes a cap layer CP3 placed on top of the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively.

[0035] In the following explanation, a multilayer containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as multilayer film FL1, a multilayer containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as multilayer film FL2, and a multilayer containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as multilayer film FL3.

[0036] Sub-pixels SP1, SP2, and SP3 are each fitted with sealing layers SE11, SE12, and SE13, respectively. Sealing layer SE11 continuously covers the laminated film FL1 and the partition wall 6 surrounding sub-pixel SP1. Sealing layer SE12 continuously covers the laminated film FL2 and the partition wall 6 surrounding sub-pixel SP2. Sealing layer SE13 continuously covers the laminated film FL3 and the partition wall 6 surrounding sub-pixel SP3.

[0037] In the example shown in Figure 3, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the same partition wall 6. Also, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the same partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact above the partition wall 6.

[0038] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6. The laminated films FL1, FL2, FL3 may be placed in at least a portion of these gaps.

[0039] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0040] In the example shown in Figure 3, the touch panel electrode TP is placed on the sealing layer SE2. The touch panel electrode TP is covered by a resin layer RS2. The touch panel electrode TP can be formed by metal wiring. This wiring may face the partition wall 6 in the third direction Z. Furthermore, this wiring may have a planar shape similar to that of the partition wall 6.

[0041] A cover member, such as a polarizing plate, protective film, or cover glass, may be further placed above the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer, such as OCA (Optical Clear Adhesive).

[0042] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1, RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0043] The lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of this reflective layer, respectively. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0044] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0045] The organic layers OR1, OR2, and OR3 are composed of multiple thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in the third direction Z in sequence. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including multiple emissive layers.

[0046] The cap layers CP1, CP2, and CP3 have a laminated structure in which multiple transparent layers are stacked, for example. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from those of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. Note that at least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0047] The bottom layer 63 and axial layer 64 of the partition wall 6 are formed of a metallic material. For example, the metallic material for the bottom layer 63 can be molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb). For example, the metallic material for the axial layer 64 can be aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). The axial layer 64 may also be formed of an insulating material.

[0048] The first top layer 65 of the partition wall 6 is formed of, for example, a metallic material. The second top layer 66 of the partition wall 6 is formed of, for example, a conductive oxide. As the metallic material forming the first top layer 65, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy can be used. As the conductive oxide forming the second top layer 66, for example, ITO or IZO can be used. The upper part 62 may consist of three or more layers, or it may be formed of a single layer. Furthermore, the upper part 62 may include a layer formed of an insulating material.

[0049] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the sides of the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the video signal on the signal line SL through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0050] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the wavelength range of the first color. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the wavelength range of the second color. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the wavelength range of the third color.

[0051] During the manufacturing of a display device DSP, a large motherboard is created that includes multiple areas corresponding to the display panel PNL. The following describes the configurations that can be applied to this motherboard.

[0052] Figure 4 is a schematic plan view of the motherboard MB (display device motherboard) according to this embodiment. The motherboard MB is rectangular in shape as shown in the figure, but it may also be circular or have other shapes.

[0053] The motherboard MB has multiple panel sections PP arranged in a matrix. In the example shown in Figure 4, the multiple panel sections PP are arranged continuously in the first direction X and the second direction Y. However, the arrangement of the multiple panel sections PP on the motherboard MB is not limited to this example.

[0054] Figure 5 is a schematic plan view of a portion of the motherboard (MB). In Figure 5, we focus on one of the panel sections (PP) shown in Figure 4.

[0055] In the example shown in Figure 5, the shape of the panel PP in plan view is square. However, the shape of the panel PP in plan view may also be a rectangle that is elongated in the first direction X, or a rectangle that is elongated in the second direction Y. Furthermore, the shape of the panel PP in plan view may include multiple straight and curved sections.

[0056] The outline of each panel section PP corresponds to the cut line CL1 used to cut each panel section PP from the motherboard MB. The cut line CL1 is formed in a grid pattern. Focusing on a single panel section PP, the cut line CL1 is formed in a square shape.

[0057] Furthermore, a cut line CL2 is formed on the panel portion PP. The cut line CL2 corresponds to the outer shape of the display panel PNL shown in Figure 1. In other words, the cut line CL2 is formed in a circular shape. The cut line CL2 corresponds to the cut line for cutting out a portion of the display area DA and the surrounding area SA from the panel portion PP.

[0058] The panel section PP has the display area DA and the peripheral area SA described above. The peripheral area SA includes the margin area FA outside the cut line CL2. The margin area FA corresponds, for example, to the area between cut line CL1 and cut line CL2. Cut line CL1 corresponds to the cut line for cutting out the display area DA and the margin area FA from the motherboard MB.

[0059] The panel section PP is divided by cut line CL2 into a portion including the display area DA and a portion including the margin area FA. Between cut line CL1 and cut line CL2, several inspection pads (not shown) for checking the operation of the display panel PNL are arranged.

[0060] In this embodiment, a partition wall 7 (first partition wall) is positioned in the peripheral region SA, which includes the margin region FA. In Figure 5, a dot pattern is shown in the region where the partition wall 7 may be positioned. The partition wall 7 can be positioned in the region between the display region DA and the cut line CL2, the margin region FA, etc. However, the partition wall 7 does not have to be positioned in at least one of these regions. Furthermore, the position and planar shape of the partition wall 7 in these regions can be determined as appropriate.

[0061] From the viewpoint of efficiently cutting out the panel portion PP, it is preferable that a partition wall 7 is not provided at the cut line CL1. Similarly, it is preferable that a partition wall 7 is not provided at the cut line CL2.

[0062] The margin area FA has multiple island-shaped portions IP. Specifically, the multiple island-shaped portions IP are arranged around the cut line CL2 in a plan view. More specifically, the multiple island-shaped portions IP are arranged between the cut line CL1 and the cut line CL2 in a plan view. In addition, the multiple island-shaped portions IP are arranged away from the cut line CL2.

[0063] In the example shown in Figure 5, each island-shaped IP is positioned at a corner CN of the cut line CL1. The corner CN is formed by a straight section extending in the first direction X and a straight section extending in the second direction Y of the cut line CL1. In Figure 5, each island-shaped IP is given a diagonal pattern.

[0064] In this embodiment, four island-shaped IPs are arranged around one panel section PP. The number and position of the island-shaped IPs arranged around one panel section PP can be changed as appropriate.

[0065] The island-shaped IP protrudes in the third direction Z more than the rest of the area within the margin region FA. In other words, the island-shaped IP has a greater thickness than the rest of the area within the margin region FA. The island-shaped IP is formed by laminating multiple layers (for example, sealing layers SE1x, SE2 and resin layer RS3, which will be described later) above the partition wall 7.

[0066] Each island-shaped IP has a similar shape, for example, centered on the display area DA. Furthermore, the shape of the island-shaped IP in plan view is not limited to the example in Figure 5. The shapes of the island-shaped IPs may differ. Here, we will focus on one island-shaped IP (island-shaped IP1 in Figure 5) and describe its shape in plan view.

[0067] The island-shaped portion IP1 has sides M1, M2, and M3. In other words, the island-shaped portion IP1 has a side surface that includes sides M1, M2, and M3. This side surface extends upward from the substrate 10. Side M1 extends in the first direction X. Side M2 ​​extends in the second direction Y. The length of side M1 is, for example, approximately equal to the length of side M2.

[0068] Edge M3 extends in a direction different from the first direction X and the second direction Y. Specifically, edge M3 is formed along the cut line CL2. In the example in Figure 5, edge M3 may be formed in a curved shape or in a straight shape. These edges M1, M2, and M3 are connected by shorter sides SM that are shorter than the edges M1, M2, and M3. Note that edges M1, M2, and M3 may also be directly connected to each other.

[0069] Here, we will focus on the island-shaped section IP1 and its vicinity in Figure 5 and explain the configuration of the marginal area FA. Figure 6 is a schematic plan view showing the island-shaped section IP1 and its vicinity. As mentioned above, partition walls 7 are located in the marginal area FA.

[0070] The partition wall 7 has multiple segments 71 and 72. In this embodiment, segment 71 corresponds to the first segment, and segment 72 corresponds to the second segment. In the marginal area FA, segment 71 is arranged in the island-shaped portion IP, and segment 72 is arranged in areas other than the island-shaped portion IP.

[0071] Here, within the marginal area FA, the area where the island-shaped portion IP is placed is defined as area A1, and the area surrounding the island-shaped portion IP is defined as area A2. In this embodiment, area A1 corresponds to the first area, and area A2 corresponds to the second area. The marginal area FA has, for example, multiple areas A1 and area A2. In Figure 6, area A1 is given a grid pattern, and area A2 is given a diagonal line pattern. In this embodiment, area A1 corresponds to the area where segment 71 is placed, and area A2 corresponds to the area where segment 72 is placed.

[0072] Region A2 is formed to surround region A1, as shown in Figure 6. Segment 72 may also be located in the peripheral region SA between the cut line CL2 and the display region DA.

[0073] Figure 7 is a schematic enlarged view showing section VII in Figure 6. As described above, the partition wall 7 has a plurality of segments 71 located in region A1 and a plurality of segments 72 located in region A2. The segments 71 and 72 are spaced apart in the first direction X and the second direction Y.

[0074] Here, we will describe the planar shapes of segments 71 and 72.

[0075] Segment 72 has a different planar shape from segment 71. The outer shape of segments 71 and 72 is rectangular. Here, "rectangular" includes not only squares but also rectangles and other shapes. Also, the corners of segments 71 and 72 are not limited to right angles, but may be rounded (R-shaped).

[0076] The area of ​​segment 71 is, for example, equal to the area of ​​segment 72. The areas of segments 71 and 72 correspond to the size of the outer shape in a plan view. Note that the area of ​​segment 71 may be different from the area of ​​segment 72.

[0077] Each segment 71 has the same planar shape. Each segment 72 has the same planar shape. As shown in the lower part of Figure 7, segments 71 and 72 each have wall portions 71W and 72W. In this embodiment, wall portion 71W corresponds to the first wall portion, and wall portion 72W corresponds to the second wall portion. Wall portions 71W and 72W each form a closed region, which will be described later.

[0078] The wall section 71W has a frame-shaped outer wall 710 and an inner wall 71X extending from the outer wall 710 in a direction opposite to the first direction X. The inner wall 71X does not divide the interior of the outer wall 710. Segment 71 has a partition opening 71A defined by the outer wall 710 and the inner wall 71X. The area inside the partition opening 71A corresponds to a closed region CA10 (first closed region). In other words, segment 71 has a closed region CA10.

[0079] The planar shape of the partition opening 71A (closed region CA10) is U-shaped. In addition, as shown in the example in Figure 7, a protrusion 71a is formed at the end of the inner wall 71X, projecting in the second direction Y and in the direction opposite to the second direction Y. A slit 71S is formed between the end of the inner wall 71X (protrusion 71a) and the outer wall 710. Note that the protrusion 71a may or may not be formed.

[0080] The wall section 72W has a frame-shaped outer wall 720, an inner wall 72X extending from the outer wall 720 in the direction opposite to the first direction X, and an inner wall 72Y extending in the second direction Y. The inner wall 72Y divides the interior of the outer wall 710. The inner wall 72X extends from the outer wall 720 to the inner wall 72Y in the second direction Y.

[0081] Segment 72 has partition openings 72A, 72B, and 72C defined by the outer wall 720 and the inner walls 72X and 72Y. The areas inside the partition openings 72A, 72B, and 72C correspond to closed regions CA21, CA22, and CA23 (second closed regions). In other words, segment 72 has closed regions CA21, CA22, and CA23.

[0082] The planar shapes of the partition openings 72A, 72B, and 72C (closed regions CA21, CA22, CA23) are the same as the planar shapes of the partition openings 601A, 602A, and 603A shown in Figure 2. The planar shapes of the partition openings 72A, 72B, and 72C are, for example, rectangular.

[0083] In the example in Figure 7, the bulkhead openings 72B and 72C are aligned with bulkhead opening 72A in the first direction X. Furthermore, bulkhead openings 72B and 72C are aligned in the second direction Y. Also, bulkhead openings 72B and 72C are smaller than bulkhead opening 71A. Note that the shape and relative positional relationship of bulkhead openings 72A, 72B, and 72C are not limited to the example in Figure 7.

[0084] Compared to segment 71, the planar shapes of the closed regions CA21, CA22, and CA23 in segment 72 are different from the planar shapes of the closed region CA10 in segment 71. Segment 72 has more closed regions CA21, CA22, and CA23 than segment 71 has. In this embodiment, segment 71 has one closed region, while segment 72 has multiple (e.g., three) closed regions.

[0085] The area of ​​closed region CA10 in segment 71 is larger than the area of ​​each of the closed regions CA21, CA22, and CA23 in segment 72. In other respects, the ratio of the area of ​​closed region CA10 to the area of ​​segment 71 is larger than the ratio of the combined area of ​​closed regions CA21, CA22, and CA23 to the area of ​​segment 72.

[0086] The area of ​​wall section 72W of segment 72 is larger than the area of ​​wall section 71W of segment 71. In other respects, the ratio of the area of ​​wall section 71W to the area of ​​segment 71 is smaller than the ratio of the area of ​​wall section 72W to the area of ​​segment 72.

[0087] Figure 8 is a schematic cross-sectional view along the line VIII-VIII in Figure 7. In Figure 8, the partition wall 7 is viewed in the direction opposite to the first direction X.

[0088] The aforementioned organic insulating layer 12 and rib layer 5 are also formed in the surrounding region SA, including the margin region FA. In Figure 8, elements below the organic insulating layer 12 are omitted.

[0089] The partition wall 7 (segments 71 and 72) is positioned on the rib layer 5. Segments 71 and 72 each have similar cross-sectional structures. Like the partition wall 6, segments 71 and 72 include a lower section 61 and an upper section 62. In this embodiment, the lower section 61 of the partition wall 7 corresponds to the first lower section, and the upper section 62 of the partition wall 7 corresponds to the first upper section.

[0090] The upper part 62 has a greater width than the lower part 61. The lower part 61 of partition wall 7 includes a bottom layer 63 and an axial layer 64, just like partition wall 6. The upper part 62 of partition wall 7 includes a first top layer 65 and a second top layer 66, just like partition wall 6.

[0091] The bottom layer 63, axial layer 64, first top layer 65, and second top layer 66 of partition wall 7 are formed of the same material as the bottom layer 63, axial layer 64, first top layer 65, and second top layer 66 of partition wall 6.

[0092] The multilayer film FLx is located in region A1 (island-shaped portion IP) within the margin region FA, but not in region A2. In region A1, the multilayer film FLx is located on the wall portion 71W of segment 71, on the rib layer 5 of the closed region CA10 of segment 71, and on the rib layer 5 between adjacent segments 71.

[0093] The multilayer film FLx is formed using the same process and materials as any of the multilayer films FL1, FL2, or FL3 shown in Figure 3. In other words, the multilayer film FLx consists of the same layers as any of the multilayer films FL1, FL2, or FL3. For example, the multilayer film FLx is formed using the same process and materials as multilayer film FL3. Therefore, the cap layer CP3 is also located in the margin region FA.

[0094] The sealing layer SE1x is located in region A1 (island-shaped portion IP) within the margin region FA, but not in region A2. For example, the edge of the sealing layer SE1x corresponds to the edge of region A1. The sealing layer SE1x is located on top of the multilayer film FLx. The multilayer film FLx is located between segment 71 and the sealing layer SE1x.

[0095] The sealing layer SE1x continuously covers each segment of the laminated film FLx and the partition wall 7. Focusing on segment 71, the sealing layer SE1x is in contact with the lower 61 and upper 62 of segment 71. Therefore, segment 71 is not exposed from the sealing layer SE1x. In contrast, the sealing layer SE1x is not positioned above segment 72.

[0096] The sealing layer SE1x is formed using the same process and materials as any of the sealing layers SE11, SE12, or SE13 shown in Figure 3. For example, the sealing layer SE1x is formed using the same process and materials as the sealing layer SE13. In this embodiment, sealing layers SE11, SE12, SE13, and SE1x correspond to the first sealing layer.

[0097] The resin layer RS3 is located in region A1 (island-shaped section IP) within the margin region FA, but not in region A2. The resin layer RS3 is located on top of the sealing layer SE1x. The resin layer RS3 is formed using the same process and material as the resin layer RS1 (shown in Figure 3) in the display region DA. The island-shaped section IP includes segment 71, the laminated film FLx, the sealing layer SE1x, the resin layer RS3, and the sealing layer SE2.

[0098] The thickness of resin layer RS3 is, for example, less than the thickness of resin layer RS1 (shown in Figure 3). Furthermore, the island-like portion IP (resin layer RS3) is separated from resin layer RS1. In other words, resin layer RS3 is isolated from resin layer RS1.

[0099] Focusing on the end S1E of the sealing layer SE1x, the end R3E of the resin layer RS3 is located above the sealing layer SE1x. Here, the end includes the end and the surrounding region. End R3E overlaps with end S1E. In other words, the resin layer RS3 does not protrude beyond end S1E. Also, the resin layer RS3 is not located above segment 72.

[0100] Note that the position of the end portion R3E of the resin layer RS3 is not limited to the example in Figure 8. For example, the end portion R3E may be located further inside the island-shaped portion IP1 than in the example in Figure 8. Also, although the end portion R3E is located above the segment 71 of the partition wall 7, it does not have to be located above the segment 71.

[0101] The sealing layer SE2 is located in regions A1 and A2, respectively. In this embodiment, the sealing layer SE2 corresponds to the second sealing layer. Focusing on region A1, the sealing layer SE1x and the resin layer RS3 are each covered by the sealing layer SE2. Segment 71 is not in contact with the sealing layer SE2. Focusing on region A2, the rib layer 5 and segment 72 are covered by the sealing layer SE2.

[0102] Next, an example of a method for manufacturing a display device DSP will be described. Figure 9 is a flowchart of an example of a method for manufacturing a display device DSP. Figures 10A to 10J are schematic cross-sectional views showing the manufacturing process of a display device DSP. In Figures 10A to 10J, the focus is mainly on the display area DA, and elements below the organic insulating layer 12 are omitted.

[0103] In forming the panel portion PP, first a mother board MB substrate 10 is prepared, and a circuit layer 11 and an organic insulating layer 12 are formed on it (step PR1 in Figure 9). Next, as shown in Figure 10A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR2 in Figure 9).

[0104] Next, as shown in Figure 10B, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed over the entire motherboard MB (step PR3 in Figure 9). At this point, the pixel apertures AP1, AP2, and AP3 are not provided on the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0105] After the formation of the rib layer 5, a process for forming the partition wall 6 is carried out (process PR4 in Figure 9). In process PR4, as shown in Figure 10C, a first layer L1 for processing into the bottom layer 63, a second layer L2 for processing into the axial layer 64, a third layer L3 for processing into the first top layer 65, and a fourth layer L4 for processing into the second top layer 66 are sequentially formed over the entire motherboard MB. Furthermore, a resist R1 is placed on top of the fourth layer L4. The resist R1 is patterned to the shape of the partition wall 6. The first layer L1, second layer L2, third layer L3, and fourth layer L4 can be formed, for example, by sputtering.

[0106] Subsequently, the first layer L1, second layer L2, third layer L3, and fourth layer L4 are patterned using the resist R1 as a mask. In one example, the first layer L1 is formed of titanium nitride, the second layer L2 is formed of aluminum, the third layer L3 is formed of titanium, and the fourth layer L4 is formed of ITO. In this case, the patterning may include wet etching to remove the portion of the fourth layer L4 exposed from the resist R1, dry etching to remove the portions of the first layer L1, second layer L2, and third layer L3 exposed from the resist R1, and wet etching to reduce the width of the second layer L2.

[0107] After step PR4, a partition wall 6 is formed in the display area DA, as shown in Figure 10D. After the formation of the partition wall 6, the resist R1 is removed (peeled off). In the wet etching process described above, which reduces the width of the second layer L2, the second top layer 66 (fourth layer L4) may also be slightly eroded. If this erosion occurs, the width of the second top layer 66 becomes smaller than the width of the first top layer 65.

[0108] Next, a process is carried out to create pixel apertures AP1, AP2, and AP3 (process PR5 in Figure 9). In this process PR5, a resist R2 is formed to cover the partition wall 6, as shown in Figure 10E. Furthermore, dry etching is performed on the rib layer 5 using the resist R2 as a mask. As a result, pixel apertures AP1, AP2, and AP3 that expose the lower electrodes LE1, LE2, and LE3 are formed on the rib layer 5, as shown in Figure 10F. After the dry etching, the resist R2 is removed (peeled off).

[0109] After process PR5, a process is performed to remove the rib layer 5 from the inspection pad located in the margin area FA (process PR6 in Figure 9). In process PR6, the resist that has been opened in the inspection pad is placed on top of the rib layer 5, and dry etching is performed on the rib layer 5.

[0110] After step PR6, a process for forming the display element DE1 is carried out (step PR7 in Figure 9). In forming the display element DE1, first, as shown in Figure 10G, a multilayer film FL1 and a sealing layer SE11 are formed. As shown in Figure 3, the multilayer film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel aperture AP1, an upper electrode UE1 that covers the organic layer OR1, and a cap layer CP1 that covers the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed, for example, by vapor deposition. The sealing layer SE11 can be formed, for example, by CVD.

[0111] The laminated film FL1 and the sealing layer SE11 are formed on the entire motherboard MB, including not only the display area DA of each panel PP but also the surrounding area SA. The laminated film FL1 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6.

[0112] Next, the multilayer film FL1 and the sealing layer SE11 are patterned. In this patterning process, as shown in Figure 10G, a resist R3 is placed on top of the sealing layer SE11. The resist R3 covers the subpixel SP1 and a portion of the surrounding partition wall 6.

[0113] Subsequently, an etching process is performed using the resist R3 as a mask. As a result, as shown in Figure 10H, the portions of the multilayer film FL1 and the sealing layer SE11 that are exposed from the resist R3 are removed. In other words, the portions of the multilayer film FL1 and the sealing layer SE11 that overlap with the lower electrode LE1 are left, and the other portions are removed. This forms the display element DE1 on the sub-pixel SP1. For example, in the peripheral region SA, the multilayer film FL1 and the sealing layer SE11 are removed by this etching process. This etching process may include wet etching or dry etching performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, the resist R3 is removed (peeled off).

[0114] After step PR7, a process for forming the display element DE2 is carried out (step PR8 in Figure 9). The display element DE2 can be formed using the same procedure as the display element DE1. That is, in forming the display element DE2, the multilayer film FL2 and the sealing layer SE12 are formed over the entire mother substrate MB. As shown in Figure 3, the multilayer film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel aperture AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2.

[0115] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed, for example, by vapor deposition. The sealing layer SE12 can be formed, for example, by CVD. The multilayer film FL2 is divided into multiple parts by overhanging partitions 6. The sealing layer SE12 continuously covers each divided part of the multilayer film FL2 and the partitions 6. By patterning the multilayer film FL2 and the sealing layer SE2, a display element DE2 is formed on the sub-pixel SP2, as shown in Figure 10I. For example, in the peripheral region SA, the multilayer film FL2 and the sealing layer SE12 are removed by etching during the patterning process.

[0116] After step PR8, a process for forming the display element DE3 is carried out (step PR9 in Figure 9). The display element DE3 can be formed using the same procedure as the display elements DE1 and DE2. That is, in forming the display element DE3, the multilayer film FL3 and the sealing layer SE13 are formed over the entire mother substrate MB. As shown in Figure 3, the multilayer film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel aperture AP3, an upper electrode UE3 that covers the organic layer OR3, and a cap layer CP3 that covers the upper electrode UE3.

[0117] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed, for example, by vapor deposition. The sealing layer SE13 can be formed, for example, by CVD. The multilayer film FL3 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE13 continuously covers each divided part of the multilayer film FL3 and the partition walls 6. By patterning the multilayer film FL3 and the sealing layer SE13, a display element DE3 is formed on the sub-pixel SP3, as shown in Figure 10J. For example, in the peripheral region SA, a portion of the multilayer film FL3 and the sealing layer SE13 is removed by etching during the patterning process.

[0118] However, in the areas within the margin region FA where multiple island-shaped IPs are formed, the laminated film FL3 and the sealing layer SE13 remain without being removed by etching. These remaining laminated film FL3 and sealing layer SE13 correspond to the laminated film FLx and sealing layer SE1x shown in Figure 8, respectively.

[0119] Note that, while this example assumes that the display elements DE1, DE2, and DE3 are formed in this order, they may be formed in any other order.

[0120] Figures 11A to 11D are schematic cross-sectional views showing the structure of the margin area FA in the manufacturing process of a display device DSP.

[0121] The partition wall 7 (segments 71, 72) of the margin area FA is formed together with the partition wall 6 in process PR4. After process PR4, as shown in Figure 11A, overhang-shaped segments 71 and 72, each having a lower part 61 and an upper part 62, are formed. The bottom layer 63, axial layer 64, first top layer 65, and second top layer 66 of these segments 71 and 72 are formed by processing the first layer L1, second layer L2, third layer L3, and fourth layer L4 described above, respectively.

[0122] Furthermore, after step PR9, the laminated film FLx and sealing layer SE1x are formed in region A1 (island-shaped portion IP), as shown in Figure 11B. The laminated film FLx is formed on the wall portion 71W of segment 71, in the closed region CA10 of segment 71, and between adjacent segments 71, as explained using Figure 8. In contrast, the laminated film FLx and sealing layer SE1x are not formed in region A2. In this way, the laminated film FLx and sealing layer SE1x are formed in the blank region FA by patterning the laminated film FL3 and sealing layer SE13.

[0123] As described above, the multilayer film FLx is finely divided by the segment 71. This prevents the divided multilayer film FLx and the sealing layer SE1x covering them from peeling off from the substrate.

[0124] After step PR9, a process for forming the resin layer RS1 is carried out (step PR10 in Figure 9). The resin layer RS1 can be formed inside the dam structure DS (shown in Figure 1), for example, by an inkjet method. The dam structure DS serves to contain the resin layer RS1 before it hardens. Step PR10 includes multiple coating steps (for example, three times).

[0125] Furthermore, in step PR10 of Figure 9, as shown in Figure 11C, a resin layer RS3 is formed on the sealing layer SE1x of the island-shaped IP. The resin layer RS3 is formed in the margin region FA (between cut line CL1 and cut line CL2). Specifically, the resin layer RS3 is formed at the corner CN of cut line CL1 (shown in Figure 5).

[0126] More specifically, resin layer RS3 is formed in region A1. This resin layer RS3 is formed to be thinner than resin layer RS1. Specifically, resin layer RS3 is formed by fewer layers than resin layer RS1. In contrast, resin layer RS3 is not formed in region A2.

[0127] As shown in Figure 11B, droplets D that form the resin layer RS3 are ejected from the nozzle NZ toward the sealing layer SE1x. Figure 11B shows how droplets D are ejected toward the mother substrate MB when the resin layer RS3 is formed by the inkjet method in the above-described process PR10.

[0128] The outer edge of the area where droplet D is ejected is located in a position that overlaps with the sealing layer SE1x. In Figures 6 and 7, the outer edge of the area where droplet D is ejected is shown as the inkjet pattern PT. Droplet D is ejected inside the inkjet pattern PT.

[0129] As shown in Figure 6, focusing on one island-shaped IP, the area of ​​the inkjet pattern PT is smaller than the area of ​​the island-shaped IP (region A1). Furthermore, outside the inkjet pattern PT, as shown in Figure 7, multiple segments 71 are arranged to surround the inkjet pattern PT.

[0130] For example, in the second direction Y, at least one segment 71 is positioned between the outermost segments 71 and 72 that overlap the inkjet pattern PT. Similarly, in the first direction X, at least one segment 71 is positioned between the outermost segments 71 and 72 that overlap the inkjet pattern PT. The distance between the inkjet pattern PT and the edge of the sealing layer SE1x (distance D1 shown in Figure 7) is, for example, about 100 μm.

[0131] The droplet D ejected from nozzle NZ spreads over the sealing layer SE1x, forming a resin layer RS3. At this time, the surface tension near the edge S1E suppresses the spreading of the resin layer RS3. As a result, the sealing layer SE1x becomes larger than the inkjet pattern PT and is less likely to extend beyond the upper surface of the sealing layer SE1x.

[0132] In this way, the droplet D is ejected onto the sealing layer SE1x, allowing the resin layer RS3 to be positioned as intended. In other words, the sealing layer SE1x has the function of positioning the resin layer RS3. In Figure 7, a dot pattern is applied to the region where the resin layer RS3 is formed.

[0133] After step PR10, for example, a sealing layer SE2 is formed over the entire motherboard MB by CVD (step PR11 in Figure 9). The sealing layer SE1x and resin layer RS3 of the island-shaped IP are covered by the sealing layer SE2, as shown in Figure 11D. In addition, the segment 72 and rib layer 5 of region A2 are covered by the sealing layer SE2.

[0134] As a result, island-shaped IPs are formed in the blank area FA, as shown in Figure 5. By forming island-shaped IPs in the blank area FA in this way, variations in the thickness of the resist applied in the process described later can be suppressed. Specifically, by placing island-shaped IPs in the blank area FA, the difference in the speed of the resist flowing through the panel area PP can be reduced, thereby suppressing uneven application of the resist. As a result, the resist functions reliably as a mask, preventing the removal of layers placed below the resist, and reducing the likelihood of malfunctions in the manufactured display device DSP.

[0135] After step PR11, a step is performed to remove the rib layer 5 and sealing layer SE2 covering the terminal portion T (step PR12 in Figure 9). Furthermore, a step is performed to remove the sealing layer SE2 around the terminal portion T (step PR13 in Figure 9).

[0136] After step PR13, the touch panel electrode TP is formed on the sealing layer SE2 (step PR14 in Figure 9). Specifically, first, a conductive layer for processing into the touch panel electrode TP is formed over the entire mother substrate MB. Next, a resist in the shape corresponding to the touch panel electrode TP is placed, and the conductive layer is etched using this resist as a mask. After this etching, the resist is removed (peeled off).

[0137] After step PR14, a resin layer RS2 is formed (step PR15 in Figure 9). The resin layer RS2 can be formed inside the dam structure DS, for example, by an inkjet method. The dam structure DS plays the role of blocking the resin layer RS2 before it hardens.

[0138] The resin layer RS2 may be formed by a photolithography process. In this case, first, a photosensitive resin for processing into the resin layer RS2 is formed over the entire motherboard MB. Then, the resin layer RS2 is formed on each panel portion PP through the processes of pre-baking, exposure, development, and firing of the photosensitive resin.

[0139] After step PR15, each panel section PP is cut out from the motherboard MB along the cut line CL1 (step PR16 in Figure 9). Furthermore, the margin area FA is cut along the cut line CL2 (step PR17 in Figure 9). This completes the display panel PNL.

[0140] As in this embodiment, when forming a resin layer RS3 in the margin area FA, as described above, the droplet D is discharged onto the pre-placed sealing layer SE1x, thereby suppressing the spreading of the droplet D and allowing the resin layer RS3 to be placed at the desired position.

[0141] Depending on the shape of the closed region (partition opening) of the partition located below the sealing layer SE1x, when droplet D is discharged, air may remain in this closed region, potentially causing areas in the island-shaped IP where droplet D does not flow in sufficiently. This can lead to areas in the island-shaped IP where the resin layer RS3 is not formed (coating gaps).

[0142] In this embodiment, a segment 71 of the partition wall 7 is arranged in the island-shaped section IP. Specifically, segment 71 has one undivided closed region CA10. Compared to segment 72, the area of ​​closed region CA10 is larger than the closed regions CA21, CA22, and CA23 of segment 72.

[0143] Therefore, as the discharged droplet D flows, air can easily escape from the closed region CA10, allowing the droplet D to spread sufficiently within the closed region CA10. Specifically, since the closed region CA10 is not divided, when the droplet D enters the closed region CA10, it can flow into the entire closed region CA10. As a result, in the island-shaped portion IP, areas where the resin layer RS3 is not formed on the island-shaped portion IP are less likely to occur, and the resin layer RS3 can be distributed across the entire island-shaped portion IP.

[0144] Furthermore, placing segment 71 in areas other than the island-shaped IP (area A2) may lead to other problems. Specifically, because the closed region CA10 of segment 71 is large, if the sealing layer SE2 is placed on top of segment 71 in area A2, sufficient adhesion with the sealing layer SE2 may not be ensured, which could cause the sealing layer SE2 to peel off.

[0145] In this regard, in this embodiment, segments 72 of the partition wall 7 are arranged in the area other than the island-shaped IP (area A2). Specifically, each segment 72 has partition wall openings 72A, 72B, and 72C, which are divided into multiple sections.

[0146] As a result, the sealing layer SE2 is positioned to fit into the partition openings 72A, 72B, and 72C, respectively, improving adhesion to the substrate and suppressing peeling of the sealing layer SE2. Since region A2 is a region where the resin layer RS3 is not placed, the area of ​​each of the closed regions CA21, CA22, and CA23 may be smaller than the area of ​​closed region CA10.

[0147] Thus, the margin region FA has a region A1 (where segment 71 is located) to suppress the occurrence of areas where the resin layer RS3 is not formed, and a region A2 (where segment 72 is located) to suppress the peeling of the sealing layer SE2. As a result, the yield of the display device DSP can be improved by reliably forming the resin layer RS3 and the sealing layer SE2 in the margin region FA.

[0148] In this embodiment, the yield of the display device DSP can be improved by appropriately arranging the segments 71 and 72 of the partition wall 7 according to the position, shape, and size of the island-shaped portion IP located in the margin area FA.

[0149] In this embodiment, the sealing layer SE1x is placed in the island-shaped portion IP within the margin region FA. In other words, the area in which the sealing layer SE1x is placed is reduced. By reducing the area in which the sealing layer SE1x is placed in this way, it becomes easier to suppress the peeling of the sealing layer SE1x.

[0150] Next, other embodiments will be described. In the other embodiments described below, components similar to those in the first embodiment described above will be given the same reference numerals as in the first embodiment, and their detailed descriptions may be omitted or simplified. The configuration of the display device DSP, which is not specifically mentioned, can be the same as in the first embodiment.

[0151] [Second Embodiment] Figure 12 is a schematic enlarged view showing a part of the display device DSP according to this embodiment. In Figure 12, the same positions as in Figure 7 described above are shown. In this embodiment, the configuration of the island-shaped IP differs from that of the first embodiment. In Figure 12, a dot pattern is applied to the region where the sealing layer SE1x is formed. The planar shapes of segments 71 and 72 are the same as in the first embodiment. Segments 71 and 72 are arranged with spacing in the first direction X and the second direction Y.

[0152] The partition wall 7 further has multiple segments 73 (third segments). In this embodiment, segments 71, 72, and 73 are arranged in the island-shaped section IP. In other words, region A1 corresponds to the region where segments 71, 72, and 73 are arranged, and region A2 corresponds to the region where segment 72 is arranged. Segment 73 is formed together with segments 71 and 72 in step PR4 of Figure 9.

[0153] Multiple segments 73 are arranged between multiple segments 71 and multiple segments 72. Multiple segments 73 are arranged, for example, to surround multiple segments 71. Gaps are formed between adjacent segments 73 in the first direction X and between adjacent segments 73 in the second direction Y.

[0154] Segment 73 has a different planar shape from segments 71 and 72. The multiple segments 73 include linear segments 731 and curved segments 732. The linear segments 731 include segments that are elongated in the first direction X and segments that are elongated in the second direction Y. The shapes of these segments are not limited to the examples described above, and may include, for example, segments that include curved portions.

[0155] The interval between segment 71 and segment 73, and the interval between segment 73 and segment 72, are greater than the interval between adjacent segments 71, and the interval between adjacent segments 72.

[0156] In the example shown in Figure 12, the multiple segments 73 are located in the central part between segments 71 and 72, but this is not the only example. When the distance between segments 71 and 72 is approximately 100 μm, the distances between segments 71 and 73, and between segments 73 and 72, are formed to be, for example, 30 μm or more.

[0157] Figure 13 is a schematic cross-sectional view along the line XIII-XIII in Figure 12. In Figure 13, the partition wall 7 is viewed in the direction opposite to the first direction X.

[0158] Similar to the first embodiment, the organic insulating layer 12 and the rib layer 5 are also formed in the peripheral region SA, including the margin region FA. In Figure 13, elements below the organic insulating layer 12 are omitted.

[0159] The partition wall 7 (segments 71, 72, and 73) is positioned on top of the rib layer 5. Segment 73, like partition wall 6, includes a lower section 61 and an upper section 62. The upper section 62 of segment 73 has a greater width than the lower section 61. The lower section 61 of segment 73, like partition wall 6, includes a bottom layer 63 and an axial layer 64. The upper section 62 of segment 73, like partition wall 6, includes a first top layer 65 and a second top layer 66.

[0160] The bottom layer 63, axial layer 64, first top layer 65, and second top layer 66 of segment 73 are formed of the same material as the bottom layer 63, axial layer 64, first top layer 65, and second top layer 66 of partition wall 6.

[0161] The sealing layer SE1x is located in area A1 (island-shaped area IP) within the margin area FA, but not in area A2. Specifically, the sealing layer SE1x is positioned to cover segments 71 and 72. In contrast, the sealing layer SE1x is not positioned above segment 73. In other words, segment 73 is not covered by the sealing layer SE1x. In this embodiment, for example, the edge of the sealing layer SE1x covering segment 72 corresponds to the edge of area A1.

[0162] Furthermore, a dam DM1 is formed between the sealing layer SE1x covering segment 71 and the sealing layer SE1x covering segment 72. Segment 73 is located inside the dam DM1. The dam DM1 includes the region between segment 71 and segment 73, and the region between segment 73 and segment 72.

[0163] Focusing on the multilayer film FLx, it is positioned between segments 71 and 72 and the sealing layer SE1x. In contrast, the multilayer film FLx is not positioned on segment 73.

[0164] The resin layer RS3 is located in region A1 (island-shaped section IP) within the margin region FA, but not in region A2. Specifically, the resin layer RS3 is located on top of the sealing layer SE1x, which is positioned above segment 71.

[0165] Furthermore, the resin layer RS3 is also positioned above segment 73. Specifically, the resin layer RS3 is positioned to cover segment 73. In contrast, the resin layer RS3 is not positioned above the sealing layer SE1x positioned above segment 72. In other words, the sealing layer SE1x positioned above segment 72 is in contact with the sealing layer SE2.

[0166] The resin layer RS3 is formed using the same process and materials as the resin layer RS1 of the display area DA (shown in Figure 3). The area to which the material forming the resin layer RS3 is applied is, for example, the same as in the first embodiment.

[0167] Dam DM1 plays the role of blocking the resin layer RS3 before it hardens. Therefore, even if misalignment occurs during the manufacturing process, the resin layer RS3 before hardening is blocked by dam DM1. The island-shaped IP includes segments 71, 72, 73, the laminated film FLx, the sealing layer SE1x, the resin layer RS3, and the sealing layer SE2.

[0168] In this embodiment as well, the same effects as in the first embodiment can be obtained. In this embodiment, a dam DM1 is formed in the island-shaped IP. As a result, the resin layer RS3 before hardening is blocked by the dam DM1, making it easier to form the resin layer RS3 in a desired area. Furthermore, by placing a segment 73 in the dam DM1, it is possible to suppress the region where the dam DM1 is formed from becoming the starting point for film peeling.

[0169] In the example shown in Figure 13, the dam DM1 is shown to be filled with the resin layer RS3, but the dam DM1 does not necessarily have to be filled with the resin layer RS3.

[0170] [Third Embodiment] Figure 14 is a schematic enlarged view showing a part of the display device DSP according to this embodiment. This embodiment differs from the second embodiment in that the segment 73 is covered by the sealing layer SE1x.

[0171] In this embodiment, multiple segments 73 covered by a sealing layer SE1x are arranged to surround multiple segments 71. The sealing layer SE1x continuously covers the multiple segments 73. Specifically, the sealing layer SE1x is located in the gaps between adjacent segments 73. The multiple segments 73 are configured in the same way as in the second embodiment, but are not limited to this example.

[0172] Figure 15 is a schematic cross-sectional view along the line XV-XV in Figure 14. As described above, the sealing layer SE1x is located above segment 73. In other words, at least a portion of the sealing layer SE1x is located between segment 73 and the resin layer RS3.

[0173] This further improves the function of the dam DM1 in preventing the uncured resin layer RS3 from overflowing. Specifically, by placing the sealing layer SE1x above the segment 73, the height H3 becomes greater than the height H2 (shown in Figure 13). Height H3 corresponds to the distance along the third direction Z from the top surface of the rib layer 5 to the top surface of the sealing layer SE1x covering the segment 73, and height H2 corresponds to the distance along the third direction Z from the top surface of the rib layer 5 to the top surface of the second top layer 66 of the segment 73. By increasing the height H3, it becomes more difficult for the uncured resin layer RS3 to overflow the sealing layer SE1x covering the segment 73.

[0174] In this embodiment, the same effects as in the second embodiment can be obtained. In this embodiment, segment 73 is covered by a sealing layer SE1x. As a result, the resin layer RS3 before curing is less likely to pass over the sealing layer SE1x covering segment 73, making it easier to form the resin layer RS3 over a desired area compared to the second embodiment.

[0175] In the example shown in Figure 15, the dam DM1 is shown to be filled with the resin layer RS3, but the dam DM1 does not necessarily have to be filled with the resin layer RS3.

[0176] According to the embodiments described above, it is possible to improve the yield of the display device DSP.

[0177] In this embodiment, an example is disclosed in which the margin area FA includes areas A1 and A2, but the margin area FA may further include other areas.

[0178] Furthermore, while the embodiments described above disclose examples in which the island-shaped IP is arranged at the four corners of the margin area FA of the panel portion PP, the arrangement of the island-shaped IP is not limited to this example. The island-shaped IP may be arranged in areas other than the four corners of the margin area FA, or it may be arranged in both the four corners and areas other than the four corners.

[0179] Furthermore, although the embodiments described above disclose examples in which the thickness of the resin layer RS3 is smaller than the thickness of the resin layer RS1, the thickness of the resin layer RS3 may be the same as the thickness of the resin layer RS1.

[0180] Furthermore, differences in the planar shape of segments 71 and 72, as in the embodiments described above, and cases where the resin layer RS3 is formed to extend undesirably beyond the sealing layer SE1x, can be confirmed visually.

[0181] All display devices, motherboards, and manufacturing methods that can be implemented by those skilled in the art by appropriately modifying the design based on the display devices, motherboards, and manufacturing methods described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0182] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or change the design of any of the above-described embodiments, or to add, omit, or change the conditions of any process, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0183] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0184] 5...Rib layer, 6...Partition wall, 7...Partition wall, 10...Substrate, 11...Circuit layer, 12...Organic insulating layer, 61...Lower part, 62...Upper part, 71...Segment, 71A...Partition wall opening, 71W...Wall section, 72...Segment, 72A, 72B, 72C...Partition wall opening, 72W...Wall section, 73...Segment, A1...Region, A2...Region, CA10...Closed region, CA21, CA22, CA23...Closed region, CL1, CL2...Cut line, CP1, CP2, CP3...Cap layer, DA...Display region, DE DE1, DE2, DE3… Display elements, DSP… Display device, FA… Blank area, FL1, FL2, FL3, FLx… Multilayer film, IP… Island-shaped part, LE1, LE2, LE3… Lower electrode, MB… Motherboard, OR1, OR2, OR3… Organic layer, PNL… Display panel, PX… Pixel, R3E… Edge, RS1, RS2, RS3… Resin layer, S1E… Edge, SA… Peripheral area, SE1x, SE2, SE11, SE12, SE13… Sealing layer, UE1, UE2, UE3… Upper electrode.

Claims

1. The display area for displaying the image, The margin area outside the cut line for cutting out the aforementioned display area, A display element arranged in the aforementioned display area, The first partition wall, which is arranged in the margin area and includes a plurality of first segments and a plurality of second segments, It comprises a first sealing layer formed of an inorganic insulating material, positioned above the display element and the first segment, and not positioned above the second segment, The second segment has a different planar shape from the first segment. Motherboard for display devices.

2. Each of the first segments has the same planar shape, The second segments each have the same planar shape. Mother board for display device according to claim 1.

3. The first segment has a first closed region in a plan view, The second segment has a second closed region with a different planar shape from the first closed region in a planar view. Motherboard for display device according to claim 2.

4. In a plan view, the second segment has more of the second closed region than the first closed region of the first segment. Motherboard for display device according to claim 3.

5. The first segment has one of the first closed regions in a plan view, The second segment has a plurality of the second closed regions in a plan view. Mother board for display device according to claim 4.

6. The area of ​​the first closed region is larger than the area of ​​the second closed region. Motherboard for display device according to claim 3.

7. The first segment comprises a first wall portion forming the first closed region, The second segment has a second wall portion that forms the second closed region, The area of ​​the second wall is larger than the area of ​​the first wall. Motherboard for display device according to claim 3.

8. The aforementioned margin area is, The first region in which the first segment is arranged, The second region in which the second segment is arranged has Mother board for display device according to any one of claims 1 to 7.

9. The margin region has a plurality of first regions, The second region surrounds the first region. Mother board for display device according to claim 8.

10. The display area for displaying the image, The margin area outside the cut line for cutting out the aforementioned display area, An inorganic insulating layer arranged in the display area and the margin area, A display element arranged in the aforementioned display area, In the margin region, a first partition wall is provided, which is located above the inorganic insulating layer and includes a plurality of first segments and a plurality of second segments. A first sealing layer, formed of an inorganic insulating material, is positioned above the display element and the first segment, and not positioned above the second segment, The margin region comprises a resin layer disposed on the first sealing layer, Motherboard for display devices.

11. The end of the resin layer is located on the first sealing layer. Mother board for display device according to claim 10.

12. The end of the resin layer overlaps the end of the first sealing layer. Mother board for display device according to claim 11.

13. The resin layer is not located above the second segment. Mother board for display device according to claim 11.

14. The first segment and the second segment are A first lower part disposed on the inorganic insulating layer, It has a first upper part positioned on the first lower part and protruding from the side surface of the first lower part, Mother board for display device according to claim 11.

15. The display area is further provided with a second partition wall that surrounds the display element, The aforementioned second partition wall is A second lower part disposed on the inorganic insulating layer, It has a second upper part positioned above the second lower part and protruding from the side surface of the second lower part, Mother board for display device according to claim 14.

16. The display element further comprises a laminated film including an organic layer and an upper electrode, The laminated film is disposed between the first segment and the first sealing layer. Mother board for display device according to claim 11.

17. The laminated film is located in the closed region of the first segment. Mother board for display device according to claim 16.

18. The laminated film is arranged between adjacent first segments. Mother board for display device according to claim 17.

19. The laminated film further includes a cap layer disposed on the upper electrode, The cap layer is located in the margin region. Mother board for display device according to claim 18.

20. It is formed of an inorganic insulating material and further comprises a second sealing layer that covers the resin layer and the second segment, Mother board for display device according to any one of claims 10 to 19.

21. The display area for displaying the image, The margin area outside the cut line for cutting out the aforementioned display area, A display element arranged in the aforementioned display area, The first partition wall, which is arranged in the margin area and includes a plurality of first segments, a plurality of second segments, and a plurality of third segments, It comprises a first sealing layer formed of an inorganic insulating material and disposed above the display element and the first segment, The first segment, the second segment, and the third segment have different planar shapes from each other. Motherboard for display devices.

22. The third segment is located between the first segment and the second segment in a plan view. Mother board for display device according to claim 21.

23. The plurality of third segments are positioned in a plan view so as to surround the plurality of first segments. Motherboard for display device according to claim 22.

24. The display area for displaying the image, The margin area outside the cut line for cutting out the aforementioned display area, An inorganic insulating layer arranged in the display area and the margin area, A display element arranged in the aforementioned display area, In the margin region, a first partition wall is provided, which is positioned above the inorganic insulating layer and includes a plurality of first segments, a plurality of second segments, and a plurality of third segments located between the plurality of first segments and the plurality of second segments. A first sealing layer formed of an inorganic insulating material and positioned above the display element, the first segment, and the second segment, The margin region includes a resin layer positioned above the first segment and the third segment, but not above the second segment. Motherboard for display devices.

25. The first sealing layer is further positioned above the third segment. Mother board for display device according to claim 24.

26. It further comprises a second sealing layer formed of an inorganic insulating material that covers the resin layer, The second sealing layer is in contact with the first sealing layer, which is positioned above the second segment. Mother board for display device according to claim 24 or 25.

Images