Camera device with verification support function, verification support device, and method for supporting the verification of a camera device.

Abstract

This enables observation of each observation item, corresponding to input / output signals to the camera device, control signals from the control PC, and internal signals of the camera device, with nanosecond-level accuracy. [Solution] In a camera device in which multiple control units that operate in response to multiple commands are controlled, log data of the control of each control unit is stored in a log storage circuit located in relation to each control unit. This log data integrates a timestamp with nanosecond precision and data for checking control items.

Description

Technical Field

[0001] Embodiments of the present invention relate to a camera device having a verification support function, a verification support device, and a verification support method for a camera device.

Background Art

[0002] For example, a video system has been introduced for automation in factories and the like. The video system monitors the inside of the factory by arranging camera devices at multiple locations inside the factory.

[0003] Here, it is assumed that problems such as malfunction or error may occur in the video system. In such a case, in order to find the root cause, a verification operation for each camera device itself is required.

[0004] Conventionally, in the verification of the operation of a camera device itself, it is common to use measuring instruments such as an oscilloscope and a logic analyzer. By probing the signal to be observed, parallel input / output signals and internal signals can be observed. However, there are limitations on the signals that can be observed.

[0005] For the video system, a system control unit (usually using a PC (personal computer), hereinafter referred to as a control PC) that controls the video system from the outside is connected to the camera device. In order to perform detailed verification, it is required that the control PC controls the camera device and observes whether the camera device is correctly responding to this control (so-called control status). However, since the control PC has a serial interface, it has been difficult to observe the overall control status with the above-mentioned measuring instruments such as an oscilloscope and a logic analyzer for this part.

[0006] To resolve this issue, a known technique involved observing the serial interface using a measuring instrument similar to a bus analyzer. However, this method has the drawback that it can only verify information output to the serial interface, and therefore cannot directly observe the input / output signals or internal signals of the camera device mentioned earlier.

[0007] Depending on the nature of the verification, there may be cases where it is necessary to simultaneously observe both the input / output signals and internal signals of the camera device (observation using the first measurement method) and the control status from the control PC (observation using the second measurement method). For example, if exposure start control is initiated internally by the camera device to begin exposure, and exposure time change control is performed from an external control device to change the exposure time, it may be necessary to observe these two types of control on the same time axis. In such cases, it is necessary to perform observation using both the first and second measurement methods described above. In other words, The first measurement method involves using measuring instruments such as the oscilloscope and logic analyzer mentioned above to verify the internal operation of the camera device. The second measurement method involves observing the serial interface using a measuring instrument similar to a bus analyzer.

[0008] However, the method using the two different measuring instruments described above has a drawback: it is not possible to simultaneously observe multiple control states for the camera device on the same time axis.

[0009] Furthermore, adopting the first and second measurement methods described above would require using measuring equipment separate from the camera system, making it difficult to integrate them seamlessly into a factory environment where the camera system is actually in operation.

[0010] To resolve this issue, a known technique involved using the CPU (Central Processing Unit) built into the control PC or camera device to create verification logs via software control. Since the camera's verification function is configured by software on the CPU, dedicated measuring equipment is unnecessary, eliminating the connection problems associated with such equipment. However, a drawback is that the temporal accuracy depends on the performance of the control PC or camera's built-in CPU, resulting in lower accuracy compared to dedicated measuring equipment (which can measure in milliseconds). [Prior art documents] [Patent Documents]

[0011] [Patent Document 1] Japanese Patent Publication No. 2012-023644 [Patent Document 2] Japanese Patent Publication No. 2013-211606 [Patent Document 3] Japanese Patent Application Publication No. 10-93754 [Overview of the project] [Problems that the invention aims to solve]

[0012] As mentioned above, conventional video systems have the problem that it is difficult to accurately observe the timing of changes in the operating state of each part of the camera device on the same time axis in relation to the timing of input of various control signals to the camera device. Furthermore, in situations where connecting measuring equipment is difficult, a technique can be considered in which logs are created using software that controls a control PC or camera device. However, this method has the problem of reducing temporal accuracy because log creation takes milliseconds.

[0013] Therefore, in order to solve the above problems, the present invention aims to provide a camera device, a verification support device, and a verification support method for a camera device that enable the observation of each observation item corresponding to the control signal from the control PC and the internal signal of the camera device on the same time axis, and furthermore, have a verification support function that enables the storage of each single log data, in which each observation item and a timestamp common to each observation item are integrated, in a storage circuit with an independent hardware configuration. [Means for solving the problem]

[0014] According to one embodiment, a packet transmission and reception circuit that receives serial data from a computer, A camera control circuit that receives control data from the packet transmission / reception circuit, An image sensor control circuit, which is controlled by the aforementioned camera control circuit and controls the image sensor, A timestamp control circuit that outputs a timestamp, When control is given to each of the packet transmission / reception circuit, the camera control circuit, and the image sensor control circuit to instruct their operation, a first log storage circuit, a second log storage circuit, and a third log storage circuit, each configured in hardware, store log data that integrates the timestamp and the control item check data for each of the packet transmission / reception circuit, the camera control circuit, and the image sensor control circuit. A camera device is provided that has a verification support function and includes a memory for storing the log data of the first log storage circuit, the second log storage circuit, and the third log storage circuit in the chronological order of the timestamps. [Brief explanation of the drawing]

[0015] [Figure 1] Figure 1 is a block diagram showing the overall configuration of a camera device according to one embodiment. [Figure 2] Figure 2 is a block diagram showing the internal configuration of the log memory 101 in Figure 1. [Figure 3]FIG. 3 is a timing chart showing an operation example of a main part of the camera device according to the present embodiment.

Embodiment for Carrying Out the Invention

[0016] Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 shows an overall configuration when one embodiment is applied to a camera device 1. The camera device of this embodiment is assumed to use an interface such as USB3.0, Ethernet, CameraLink, CoaXPress, etc. that enables high-speed communication.

[0017] A control PC 3 is connected to the camera device 1 via a serial interface 2. In the operation during normal times, the control PC 3 stores imaging conditions (commands) such as exposure time and white balance in a packet, and transmits it to the camera device 1 via the serial interface 2.

[0018] The camera device 1 receives the packet sent from the control PC 3 by a packet transceiver circuit 107, extracts the command, and transmits it to a camera control circuit 108. The camera control circuit 108 gives control to an image sensor control circuit 109 according to the content of the command, and the image sensor control circuit 109 controls an image sensor 110. For example, the image sensor control circuit 109 controls the exposure time of the image sensor 110, reads out the video data captured by the image sensor 1, and converts the video data into a predetermined format. The converted video data is sent to the packet transceiver circuit 107 by the camera control circuit 108. The video data is constructed into a packet by the packet transceiver circuit 107 and transmitted to the control PC 3 via the serial interface 2. Also, the camera control circuit 108 may send the video data to an external input / output control circuit 111.

[0019] The external input / output control circuit 111 can receive control for camera control from the outside of the camera device 1, and inputs the control for camera control to the camera control circuit 108. This control for camera control is transmitted via a parallel interface.

[0020] The above external input / output control circuit 111 is often used by on-site users within the factory. In contrast, the control PC 3 is mainly installed by the manufacturer that delivered this video system, the administrator of the factory where this camera device is used, etc., and is used to perform pre-set system control.

[0021] Next, a system for acquiring log data on the operation and control status of the camera device 1 will be described.

[0022] First, 101 is a log memory, 102 is a log data transmission / reception circuit, and 103 to 106 are log storage circuits. The log memory 101 can store the log data held by the log storage circuits 103, 104, 105, and 106. The log data transmission / reception circuit 102 can read out the log data stored in the log memory 101 in response to the control from the packet transmission / reception circuit 107 and input it to the packet transmission / reception circuit 107. The above log processing block is composed of hardware and may be constructed on a dedicated substrate, for example.

[0023] The previous log storage circuit 103 stores data in pairs, which is a part or all of the received command and the time stamp at the time of reception from the time stamp control circuit 112.

[0024] In this specification, the data sent from the control PC 3 is referred to as a "command", and responding to this is referred to as an "acknowledge". In contrast, the internal control by the control data generated inside the camera device (for example, generated by the camera control unit 108) is referred to as "control". Based on this, the following control item check data is defined. In other words, the "control item check data" may be data consisting of a pair of a command (either all or part of it) and a timestamp, hereinafter referred to as "single log data." Here, the "control item check data" may also be the camera's control content, control location, or a code combining these. Furthermore, the "control item check data" may also be a code of identification data (for example, an address, name, or operation name) assigned to an internal function of the camera device (which may also be called the controlled unit) that should be controlled by the command. Furthermore, to control the various functions of the camera, an address is assigned to each camera function (control unit), and a so-called memory-mapped I / O method may be incorporated into the "control item check data" and used. In short, the data should be such that it is possible to verify what kind of control was performed on which part of the camera device. The same can be said for the log data which will be explained later.

[0025] The above single log data is written from log storage circuits 103, 104, 105, and 106 to log memory 101 (details of log memory 101 are shown in Figure 2).

[0026] The camera control circuit 108 also interprets commands received from the packet transmission / reception circuit 107, sends back an acknowledgment, and performs control (change, switch, adjust, etc.) of the operating state of the camera device 1. For example, if the control content of the received command relates to the operating state of the image sensor 110, it sends the control data to the image sensor control circuit 109. In this case, the control data may include setting the shutter timing (exposure time), readout control, and selecting / switching the readout area.

[0027] This system allows the image sensor 110 to set the frame angle of view and switch the readout area, and it is also possible to set the frame frequency of the readout video data to a high frequency.

[0028] In the above operation, the log saving circuit 105 saves the change in the operating state of the camera control circuit 108 and the timestamp of the timestamp control circuit 112 at that time as a single log data. Subsequently, this single log data is written to the log memory 101.

[0029] The basic clock for the operation of the camera control circuit 108 is synchronized with the basic clock from the timestamp control circuit 112. The timestamp control circuit 112 is also connected to and synchronizes with timestamp control circuits or camera control circuits of other camera devices (not shown).

[0030] The log storage circuit 105 may also store the internal temperature, power supply voltage, and power saving status of the camera device, as known by the camera control circuit 108, as log data within the control item check data. These conditions can be displayed on the display unit of the control PC3.

[0031] The image sensor control circuit 109 controls the image sensor 110 based on the control content (such as setting the exposure time and selecting / switching the readout area) provided by the camera control circuit 108.

[0032] At this time, the log storage circuit 106 stores a single log data set consisting of control item check data (part or all of the control, or identification data, etc.) and a timestamp received from the timestamp control circuit 112, when various controls based on the control content are specifically executed on the image sensor 110. This single log data is then written to the log memory 101.

[0033] The video data acquired by the image sensor 110 reaches the packet transmission / reception circuit 107 via the image sensor control circuit 109 and the camera control circuit 108. Even when the video data acquired by the image sensor 110 reaches the packet transmission / reception circuit 107 via the image sensor control circuit 109 and the camera control circuit 108, control item check data and timestamps are stored in the corresponding log storage circuits 106, 105, and 103, respectively.

[0034] The video data is constructed into packets by the packet transmission / reception circuit 107 and transmitted to the control PC 3 via the serial interface 2.

[0035] At this time, the log storage circuit 103 saves the control item check data indicating that video data has been transmitted, along with a timestamp, as a single log data. This single log data is then written to the log memory 101.

[0036] Furthermore, the log storage circuit 103 also receives information such as the occurrence of errors on the communication path and the recovery processing status from the status of the packet transmission / reception circuit 107, and can store these observed items as log data along with a timestamp as a single log data. This single log data is then written to the log memory 101.

[0037] Furthermore, the camera device 1 has an external input / output control circuit 111. This external input / output control circuit 111 has a function to receive control input from an external source. For example, when the external input / output control circuit 111 receives an image capture start control from an external source, it notifies the camera control circuit 108 of this control. Also, for example, if the camera device 1 is set to output an image capture timing pulse, the image capture timing pulse generated by the camera control circuit 108 can be output via the external input / output control circuit 111.

[0038] When the external input / output control circuit 111 receives the external control described above, the log saving circuit 104 saves the control item check data and the timestamp at that time. At this time, the control item check data will of course include identification data that indicates that the external input / output control circuit 111 has received the control.

[0039] External inputs and outputs are connected to devices other than the control PC3, such as photoelectric sensors. These devices and the control PC3 are not synchronized, and the commands input to the packet transmission / reception circuit 107 and the controls input to the external input / output circuit 111 are asynchronous. In such cases, it was sometimes difficult to identify the input order of the above commands and controls, and the order in which they are propagated to the camera control circuit 108. However, in this embodiment, as will be explained later in Figure 3, such identification becomes possible with nanosecond-level accuracy.

[0040] As described above, based on the timestamp provided by the timestamp control circuit 112, the log storage circuits 103, 104, 105, and 106 can save status information inside the camera device with nanosecond precision, which is finer than millisecond precision on the time axis. This is because the log storage circuits 103, 104, 105, and 106 are configured in hardware with a one-to-one correspondence to the packet transmission / reception circuit 107, the external input / output control circuit 111, the camera control circuit 108, and the image sensor circuit 109, respectively. With this configuration, there is no influence from software processing steps based on the CPU processing speed.

[0041] The contents of the single log data stored in log storage circuits 103, 104, 105, and 106 can be summarized as follows: Log saving circuit 103... Command, acknowledge, communication line error occurred, Log saving circuit 104... Changes in the state of external input / output, Log saving circuit 105... Camera internal state changes, temperature changes, power supply voltage changes, power saving state, Log saving circuit 106... Image sensor operating status.

[0042] Next, we will describe the command packets transmitted and received on the serial interface 2 described above. The command packets output by the camera control PC3 during PC control include data indicating the access mode (read / write), address (e.g., a memory-mapped I / O address), and write data (during write access). However, the method is not limited to the above, and means of identifying each part of the camera device, such as circuit names or function names, may be used as data for checking control items. In the case of memory-mapped I / O addresses, if the same address is controlled consecutively, a count value of 1 is added to the same address each time it is controlled. The reset of the increment value of the memory-mapped I / O address is performed, for example, after the entire log data in the log memory 101 has been read.

[0043] Furthermore, the acknowledgment packet sent from camera device 1 to camera control PC 3 may include control status (successful completion / error, etc.) and read data (from read access) in the control item check data.

[0044] As described above, the overall log data, which is collected from the individual log data stored in the log memory 101, can be read by the control PC 3 at any time. When the control PC 3 requests to read the overall log data, the log data transmission / reception circuit 102 sends the overall log data stored in the log memory 101 to the packet transmission / reception circuit 107. The packet transmission / reception circuit 107 generates the overall log data into a packet and sends it to the control PC 3 via the serial interface 2. Through this operation, the control PC 3 can read the overall log data stored in the log memory 101 via the serial interface 2 at any time.

[0045] The log memory 101 described above is not restricted to any particular implementation form, such as a FIFO (First-In First-Out) or ring buffer. Furthermore, it is not a separate memory but can be shared with other memory used for purposes such as image memory. In addition to memory functionality, it also includes write arbitration, and functions for pausing and resuming the save operation of log storage circuits 103, 104, 105, and 106 (or the controlled portion thereof).

[0046] Figure 2 shows an example in which the log memory 101 is configured with randomly accessible memory.

[0047] 1011 is the read control circuit, 1012 is the memory, 1013 is the write control circuit, and 1014 is the write arbitration circuit.

[0048] The single log data transmitted from log storage circuits 103, 104, 105, and 106 are selected for writing by the write arbitration circuit 1014, in order of oldest timestamp value. Any other single log data that is not selected for writing is temporarily stored in log storage circuits 103, 104, 105, and 106 and is therefore not lost. The single log data selected for writing is sent to the write control circuit 1013. The write control circuit 1013 writes the single log data to the end of the overall log data.

[0049] When the log data transmission / reception circuit 102 requests the transmission of the entire log data, the read control circuit 1011 reads the entire log data from the memory 1012 and transmits it to the log data transmission / reception circuit 102. At this time, the read control circuit 1011 controls the transmission of timestamp values ​​in chronological order from the oldest, while referring to the write address pointer of the write control circuit 1013 as needed.

[0050] The write control circuit 1013 also controls the transition between enabled and disabled states of the overall log data writing operation. The write control circuit 1013 receives commands from the control PC 3 and can accept requests for temporary suspension and resumption of saving overall log data, and can control state transitions such as automatically suspending saving based on pre-set trigger conditions. Commands related to the above transitions are provided directly to the log memory 101 from the packet transmission / reception circuit 107.

[0051] The overall log data stored in the log memory 101 can also include, in addition to the commands, controls, changes in the camera's internal state due to those controls, the image sensor's operating state, and changes in the state of external inputs and outputs, as well as changes in the camera's surrounding conditions, such as errors occurring on the communication line and recovery processing status, temperature, power supply voltage, and power saving status.

[0052] As described above, according to this embodiment, information necessary for verification work, such as commands from the control PC, the operating status in image sensor control, and changes in the state of GPIO (General-purpose input / output), is stored in the log memory with high-precision timestamps that share a common time axis. Therefore, there is an advantage in that verification can be performed by referring to various data on the same time axis.

[0053] Furthermore, logging is performed using the camera's timestamp as the time axis. This has the advantage of not relying on a control PC, and therefore achieving nanosecond or even finer time axis accuracy (higher accuracy than the clock frequency of the camera control circuit being used) even when no measuring equipment is used.

[0054] Figure 3 is an explanatory diagram showing an example of a log data acquisition sequence in chronological order when acquiring log data in the camera device according to this embodiment.

[0055] This is a timing chart showing when events occur in the packet transmission / reception circuit 107, external input / output control circuit 111, camera control circuit 108, and image sensor control circuit 109 that warrant saving as logs, and when the write control circuit 1013 (shown in Figure 2) writes these events to memory 1012 (shown in Figure 2). Log saving circuits 103-106 are omitted for simplification.

[0056] When the packet transmission / reception circuit 107 receives command X1 sent from the control PC 3, the log saving circuit 103 sends the command along with the timestamp T1 from the timestamp control circuit 112 to the log memory 101.

[0057] The write control circuit 1013 (Figure 2) in the log memory 101 immediately writes the received timestamp T1 and command W1 to memory 1012 because there are no other write operations (T1, W1).

[0058] Next, if the camera control circuit 108 changes the operating state X2 of the camera device 1 based on the command X1, the log saving circuit 105 sends the change in operating state along with the timestamp T2 of the timestamp control circuit 112 to the log memory 101. The write control circuit 1013 (shown in Figure 2) in the log memory 101 is writing the command at this time, so it writes the timestamp T2 and the change in operating state W2 after the writing operation W1 of this command is completed.

[0059] In the above case, the writing of the operating state change W2 of the write control circuit 1013 will be in a standby state, but the timestamp T2 will not shift due to the delay in writing, because the log storage circuit 105 holds the value of the time when the operating state change X2 occurred.

[0060] Next, we will explain an example where the external input / output change X3 in the external input / output control circuit 111 and the image sensor control X4 in the image sensor control circuit 109 occur almost simultaneously.

[0061] When there is an external input / output change X3 in the external input / output control circuit 111, the log saving circuit 104 transmits the external input / output change X3 along with the timestamp T3 of the timestamp control circuit 112 to the log memory 101. Almost simultaneously with, or slightly later than, this transmission, if the image sensor control circuit 109 performs image sensor control X4 based on a change in the operating state X2 of the camera control circuit 108, the log saving circuit 106 transmits the image sensor control X4 along with the timestamp T4 of the timestamp control circuit 112 to the log memory 101.

[0062] At this time, the write control circuit 1013 is writing the operating state change W2, so the external input / output change W3 and the image sensor control W4 are waiting to be written. After the writing of the operating state change W2 is completed, the write control circuit 1013 starts writing to the timestamp T3 and the external input / output change W3, and then to the timestamp T4 and the image sensor control W4, in the order in which the write operations arrived.

[0063] Furthermore, when the packet transmission / reception circuit 107 sends an acknowledgment X5 for a command while the external input / output change W3 is being written, the log storage circuit 103 sends the acknowledgment along with the timestamp T5 of the timestamp control circuit 112 to the log memory 101. At this time, since the writing of the image sensor control W4 is in a waiting state first, the write control circuit 1013 writes the image sensor control W4, and then writes the timestamp T5 and the acknowledgment W5. Thus, in this system, when the writing process of a single log data that should be saved first to the memory 101 has not been completed, a single log data that should be saved next may be generated in the memory 101. In such cases, the generation order of multiple single log data to be saved can be managed by multiple log storage circuits in hardware configuration using timestamps with a high-speed clock.

[0064] Once all write waiting states are resolved, the write control circuit 1013 returns to the operation of immediately writing upon arrival of a write request. When the packet transmission / reception circuit 107 transmits video data information X6, the log storage circuit 103 sends the video data information along with the timestamp T6 from the timestamp control circuit 112 to the log memory 101. Since there are no writes in the waiting state, the write control circuit 1013 immediately starts writing the timestamp T6 and video data information W6.

[0065] As described above, according to this embodiment, even if the timing of a command being given and the period during which the system operates in response do not coincide (i.e., even if the interval is very short, such as a nanosecond), the timing of the command being given is managed chronologically using a timestamp.

[0066] This allows for precise management of the control timing for the camera device and its corresponding operational status. The control PC 3 also receives log data from the memory 101 that stores the log data and includes means for displaying, for example, an identification mark for each log data in chronological order of the timestamp. The identification mark for the log data may be identification data that identifies the data used for checking control items, or it may be a predetermined sequence of colors or patterns set in the controlled unit. Furthermore, since it is possible to identify data that has been transmitted via the external input / output control circuit 111, it is also possible to easily analyze the status of external access. In the figure, one log storage circuit 105 is provided in correspondence with the camera control circuit 108, however, multiple log storage circuits may be provided in parallel.

[0067] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. Furthermore, even if each component of a claim is expressed by dividing it, by combining multiple components, or by combining them, it remains within the scope of the present invention. Multiple embodiments may also be combined, and embodiments composed of such combinations also fall within the scope of the invention.

[0068] Furthermore, the present invention applies to any claim expressed as control logic, as a program containing instructions for a computer to execute, or as a computer-readable recording medium containing such instructions. The use of names and terms is also not limited; other expressions, if substantially the same in content and intent, are included in the present invention. [Explanation of symbols]

[0069] 1...Camera device, 2...Serial interface, 3...Control PC, 101...Log memory, 102...Log data transmission / reception circuit, 103, 104, 105, 106...Log storage circuit, 107, 212...Packet transmission / reception circuit, 108...Camera control circuit, 109...Image sensor control circuit, 110...Image sensor, 111...External input / output control circuit, 1011...Read control circuit,...Memory, 1013...Write control circuit, 1014...Write arbitration circuit.

Claims

1. A packet transmission and reception circuit that receives serial data from a computer, A camera control circuit that receives control data from the packet transmission / reception circuit, An image sensor control circuit, which is controlled by the aforementioned camera control circuit and controls the image sensor, A timestamp control circuit that outputs a timestamp, When a command to instruct the operation of each of the packet transmission / reception circuit, the camera control circuit, and the image sensor control circuit is given, a first log storage circuit, a second log storage circuit, and a third log storage circuit, each configured in hardware, store log data that integrates the timestamp and the control item check data for each of the packet transmission / reception circuit, the camera control circuit, and the image sensor control circuit, respectively. A memory that stores the log data of the first log storage circuit, the second log storage circuit, and the third log storage circuit in the chronological order of the timestamps, A camera device equipped with verification support functions.

2. The camera device having the verification support function according to claim 1, further comprising a fourth log storage circuit, the fourth log storage circuit receiving log data including control item check data and a timestamp from an external input / output control circuit that receives control different from the interface of the serial data received by the packet transmission / reception circuit.

3. The camera device according to claim 1, wherein a log data transmission and reception circuit for transmitting the log data to an external source is connected to the memory.

4. A verification support device to which the camera device described in claim 1 is connected, The computer is a verification support device that includes means for receiving the log data from a memory that stores the log data and displaying it in chronological order of the timestamps.

5. A method for supporting the verification of a camera device, comprising: a camera control circuit that receives control data from a packet transmission / reception circuit that receives serial data from a computer; an image sensor control circuit controlled by the camera control circuit and controlling an image sensor; and a timestamp control circuit that outputs a timestamp, When a command is given to each of the first, second, and third log storage circuits, which are configured in hardware, to instruct the packet transmission / reception circuit, the camera control circuit, and the image sensor control circuit to operate, each of these log data, which integrates the timestamp and the control item check data for the packet transmission / reception circuit, the camera control circuit, and the image sensor control circuit, is stored. A method for supporting the verification of a camera device, which stores each of the aforementioned log data in memory in the chronological order of the timestamps.

6. The verification support method for a camera device according to claim 5, wherein the stored log data is transmitted to an external source.

Images