A self-seeded randomizer for randomizing data in flash memory.

Abstract

This invention provides a method and memory device that enable efficient internal copyback operations. [Solution] The method identifies data (including host data and metadata) to be written to a first set of one or more memory cells of a memory device, generates a first seed value for the host data and a second seed value for the metadata in response to the receipt of data, scrambles the host data by converting the host data using a scrambling algorithm and the first seed value to generate scrambled host data, scrambles the metadata by converting the metadata using a scrambling algorithm and the second seed value to generate scrambled metadata, and writes the scrambled host data and metadata together with the first seed value and the second seed value to a first set of memory cells on a first die of the memory device.

Description

[Technical Field]

[0001] Priority application This application claims priority to U.S. Application No. 16 / 837,315, filed on April 1, 2020, which is incorporated herein by reference in its entirety.

[0002] The embodiments relate to memory devices. Some embodiments relate to enabling efficient internal copyback operations for copying data between two different locations within the same memory die in a memory device, while maintaining data randomization and updating the metadata of the data subject to the copyback operation. [Background technology]

[0003] Memory devices for computers or other electronic devices can be categorized into volatile memory and non-volatile memory. Volatile memory requires power to maintain its data and includes, among others, random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM). Non-volatile memory can retain stored data when power is not supplied and includes, among others, flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), resistive variable memory, phase-change memory, storage class memory, resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM).

[0004] Flash memory is used as non-volatile memory for a wide range of electronic applications. Flash memory devices typically contain one or more groups of transistors, such as floating-gate or charge-trap memory cells, which enable high memory density, high reliability, and low power consumption.

[0005] In drawings that are not necessarily drawn to a consistent scale, similar numbers may describe similar components in different drawings. Similar numbers with different letter suffixes may represent other examples of similar components. Drawings generally illustrate various embodiments discussed in this document as examples, not limitations. [Brief explanation of the drawing]

[0006] [Figure 1] This disclosure shows diagrams of memory devices, such as storage devices, as examples of several devices. [Figure 2] This disclosure shows some illustrative schematic diagrams of some NAND architecture semiconductor memory arrays by example. [Figure 3] This disclosure provides illustrative schematic diagrams of several examples of 3D NAND architecture semiconductor memory. [Figure 4] The following are illustrative block diagrams of memory dies in several examples from this disclosure. [Figure 5] The data flow of a write operation is shown in several examples of this disclosure. [Figure 6] The data flow of several read operations is shown in this disclosure. [Figure 7] This disclosure provides flowcharts illustrating several examples of how to write data to a memory device. [Figure 8] This disclosure provides flowcharts illustrating several examples of how to read data from a memory device. [Figure 9] The data flow of a write operation is shown by several examples of this disclosure, where metadata and host data are encoded separately. [Figure 10] The data flow of an internal copyback operation involving metadata updates is shown by several examples of this disclosure, where metadata and host data are encoded separately. [Figure 11] This disclosure provides flowcharts illustrating several examples of how to write data to a memory device. [Figure 12]A flowchart showing a method of writing data to a memory device during an internal copy-back operation according to some examples of the present disclosure. [Figure 13] A flowchart showing a method of an internal copy-back operation on a memory device according to some examples of the present disclosure. [Figure 14] A block diagram of an exemplary machine in which any one or more of the techniques (e.g., methodologies) discussed herein may be performed.

DETAILED DESCRIPTION OF THE INVENTION

[0007] Memory devices often consist of multiple physical memory dies connected to a controller via an internal communication interface such as a bus. In a particular operation of a memory device, it is necessary to copy data from a cell at one location on a die to a cell at another location on the same die. One example is a copy operation from an SLC cache block to a TLC / QLC storage block. Many TLC / QLC memory systems use SLC blocks as write caches for performance reasons. When the data in these SLC cache blocks needs to be moved to the slower (but higher density) TLC / QLC blocks, a copy operation is required. In the conventional approach, the data has been transferred from the die to the controller via the internal communication interface for processing and then returned to the die via the internal I / O bus and stored at a different location.

[0008] To reduce I / O bus traffic and decrease controller utilization, an internal copyback operation can be performed to move data from one location to another within the same memory die of a memory device without transferring data to the controller via the communication interface. Using an internal copyback operation saves controller resources (e.g., processing cycles and working memory), interface bandwidth, reduces energy consumption, and shortens latency when completing the operation. Because the memory die does not have the resources to process the data in the same way as the controller, an internal copyback operation does not process the data in any computationally intensive way. Typically, an internal copyback copies the data without making any changes or processing.

[0009] Writing data without modification or processing can affect the reliability of the memory device and the written data. This lack of processing can cause problems with internal copyback operations. While it is possible to perform these processing steps by modifying individual memory dies, this would increase the cost and complexity of these devices to an unacceptable degree.

[0010] For example, randomizers are typically used in memory devices because the data patterns stored in memory cells must meet specific requirements to achieve reliability targets. As will be discussed later, NAND flash memory cells are arranged in a grid by word lines (WLs) connecting rows of memory cells and bit lines (BLs) connecting columns of cells. NAND memory devices typically ensure that each WL has approximately equal numbers of bits with values ​​0 and 1, and each BL has approximately equal numbers of bits with values ​​0 and 1. Furthermore, if each memory cell stores more than one bit in MLC / TLC / QLC, etc., each cell has more than two threshold voltage states. In these examples, the memory device ensures that the number of cells in each state is approximately equal within the same WL. Ensuring this data pattern distribution reduces storage errors.

[0011] These data pattern distribution requirements are typically met by using a scrambler. While the memory system cannot control the data patterns that the user can choose to write, a scrambler "scrambles" the data being written, making it more likely that a balanced number of 0s and 1s will be programmed into the medium. The scrambler can be implemented within the controller or within the memory die itself.

[0012] Reliability is improved by storing a balanced number of values ​​1 and 0 across both word lines and bit lines. Typically, the distribution requirements along the BL, and the distribution requirements for multiple pages within the same WL, are met by ensuring proper scrambler seeding. Physical address-based seeding is widely used for this purpose. For example, an input word to be written is XORed with a random number sequence seeded by the physical address of the page to which the word is written. When data is read, the data read is again XORed with the physical address to produce unscrambled data. Using physical page addresses as part or as part of the scrambled data ensures that the data programmed into the medium is randomized across the bit lines, even if the same data pattern is written to each page in the block.

[0013] Physical address-based scrambling is incompatible with internal copyback. As already explained, internal copyback typically does not alter the data being copied. If the scrambler performs scrambling using physical page addresses (for example, if the scrambler is "seeded" by physical pages), the physical address of the pages will change after the internal copyback operation is complete. If you descramble the data using the data's current physical address (for example, the physical address after internal copyback) instead of the original physical address, you cannot attempt to descramble the data during a read operation. While a memory device could provide a mechanism to track the original physical page of the data for decoding purposes, this could be too costly in terms of the memory required to store such data.

[0014] Another issue with internal copyback operations is updating metadata created when data is first written. This metadata is written along with the data received from the host (host data). Metadata can be specific to the state of the memory device at the time of the write operation. For example, it could include the time the data was written, the temperature of the memory device during the initial write, the write voltage, and the initial write verification indicator. These fields allow the memory device to read the host data more reliably. Internal copyback operations cannot update this metadata because they do not decode or descramble the data. The inability to update the metadata can result in reliability and / or performance issues later on (for example, when attempting to read the data later). While a memory die can decode the metadata, update the values, and restore the data, this requires additional processing and volatile memory resources on the memory die. This increases the cost and complexity of each memory die.

[0015] Disclosed in several examples are methods, systems, devices, and machine-readable media that provide techniques for scrambling and / or updating metadata, enabling efficient internal copyback operations. In some examples, improved data distribution techniques allow copyback operations while maintaining data distribution requirements across the memory device by decoupling the scramble key from the physical address. A controller can generate a seed value, which is used by an algorithm to scramble host data and metadata before this data is written. This seed value is then encoded and written to the page along with the encoded versions of the scrambled user data and metadata. That is, the random seed is written without scrambling the random seed itself. When reading the data, the seed can be easily descrambled because it is stored with the data. In some examples, the seed value is a random number generated by a random number generator.

[0016] In some cases, to update metadata, metadata and host data are separated, with only the metadata sent to the controller and updated during the modified internal copyback operation. Host data is not sent to the controller. Sending metadata utilizes resources from the communication link between the memory die and the controller, but far fewer resources are used than if host data were also sent. To send host data and metadata separately, the metadata and host data are scrambled and encoded so that the metadata can be descrambled and decoded separately even if the host data is not present. For example, by encoding and / or scrambling the host data and metadata separately.

[0017] By employing the techniques described above, various problems related to internal copyback operations can be avoided. Firstly, since physical addresses are not used as keys to the scrambler, host data and metadata can be copied from one memory location to another without being altered. This thus preserves the improved data reliability made possible by scrambling the data, while simultaneously allowing the data that has undergone an internal copyback operation to be descrambled. Secondly, since metadata and host data are scrambled and encoded in such a way that they can be descrambled and decoded separately, metadata may be sent back to the controller for updating before the internal copyback is complete. This updates the metadata with minimal controller communication and processing resources used, as well as minimal interface bandwidth between the memory die and the controller.

[0018] Overview of memory devices As mentioned earlier, flash memory is used as non-volatile memory for a wide range of electronic applications. Flash memory typically contains one or more groups of transistors, such as floating-gate or charge-trap memory cells, enabling high memory density, high reliability, and low power consumption. Two common types of flash memory array architectures include NAND architecture and NOR architecture, named after the logical form in which their respective basic memory cell configurations are arranged. Memory cells in a memory array are typically arranged in a matrix. In one example, the gate of each memory cell in a row of the array is coupled to an access line (e.g., a word line). In the NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In the NAND architecture, the drain of each memory cell in a string of the array is coupled in series from source to drain between the source line and the bit line.

[0019] Both NOR and NAND architecture semiconductor memory arrays are accessed via decoders that activate specific memory cells by selecting word lines coupled to their gates. In NOR architecture semiconductor memory arrays, when activated, the selected memory cells place their data values ​​into bit lines, resulting in different currents flowing depending on the programmed state of the particular cell. In NAND architecture semiconductor memory arrays, a high bias voltage is applied to the drain-side selected gate (SGD) line. Word lines coupled to the gates of the unselected memory cells in each group are driven with a specified pass voltage (e.g., Vpass) to cause the unselected memory cells in each group to act as pass transistors (e.g., allowing current to flow in a manner not limited by the stored data value). The current then flows from the source line through each series-coupled group to the bit line, limited only by the selected memory cells in each group, thereby placing the currently encoded data values ​​of the selected memory cells into the bit lines.

[0020] Flash memory cells in a semiconductor memory array with a NOR or NAND architecture can be programmed individually or collectively into one or more programmed states. For example, a single-level cell (SLC) can represent one of two programmed states (e.g., 1 or 0) that represent one bit of data. However, flash memory cells can also represent one of more than two programmed states, and each cell can represent multiple binary numbers (e.g., bits greater than 1), making it possible to manufacture high-density memory without increasing the number of memory cells. Such cells may be called multi-state memory cells, multi-digit cells, or multi-level cells (MLCs). In specific examples, an MLC may refer to a memory cell that can store 2 bits of data per cell (e.g., one of four programmed states), a triple-level cell (TLC) may refer to a memory cell that can store 3 bits of data per cell (e.g., one of eight programmed states), and a quad-level cell (QLC) may store 4 bits of data per cell. In this specification, MLC is used in a broader context and may refer to any memory cell capable of storing two or more bits of data per cell (i.e., capable of representing more than two programmed states).

[0021] Conventional memory arrays are two-dimensional (2D) structures arranged on the surface of a semiconductor substrate. To increase memory capacity over a given area and reduce costs, the size of individual memory cells has been reduced. However, there are technical limitations to the reduction in the size of individual memory cells, and therefore to the memory density of 2D memory arrays. In response, 3D memory structures, such as semiconductor memory devices with three-dimensional (3D) NAND architecture, are being developed to further increase memory density and reduce memory costs.

[0022] The 3D NAND device in question often includes a string of storage cells coupled in series (e.g., coupled from drain to source) between one or more source-side selection gates (SGS) adjacent to the source and one or more drain-side selection gates (SGD) adjacent to the bit lines. In embodiments, the SGS or SGD may include one or more field-effect transistor (FET) or metal-oxide-semiconductor (MOS) devices, etc. In some embodiments, the string extends vertically through multiple vertically spaced layers, each containing a word line. A semiconductor structure (e.g., a polysilicon structure) may extend adjacent to the string of storage cells to form a channel for the storage cells of the string. In embodiments of vertical strings, the polysilicon structure may take the form of vertically extending pillars. In some embodiments, the string may be "folded" and thus arranged relative to a U-shaped pillar. In other embodiments, multiple vertical structures may be stacked on top of each other to form a stacked array of strings of storage cells.

[0023] Memory arrays or devices can be combined to form a storage volume for a memory system, such as a solid-state drive (SSD), or one of various forms of managed memory devices. Managed memory devices may be configured and operated according to recognized industry standards. For example, a managed NAND device could be a universal flash storage (UFS®) device or an embedded memory cell device (eMMC®) (as an example). For example, in the above example, a UFS device may be configured according to the Joint Electron Device Engineering Council (JEDEC) standard, e.g., JEDEC standard JESD223D, and / or an updated or subsequent version of such standard, titled "JEDEC UFS Flash Storage 3.0". Similarly, an identified eMMC device may be configured according to the JEDEC standard JESD84-A51, e.g., and / or an updated or subsequent version of such standard, titled "JEDEC eMMC standard 5.1".

[0024] SSDs, in particular, can be used as the main storage device in computers and are superior to traditional hard drives with moving parts in terms of performance, size, weight, durability, operating temperature range, and power consumption. For example, SSDs can reduce seek times, latency, or other delays associated with magnetic disk drives (e.g., electromechanical drives). SSDs make drives more versatile and compact by using non-volatile memory cells such as flash memory cells, eliminating the need for internal battery power supply requirements.

[0025] An SSD may include multiple memory devices, each containing multiple dies or logical units (e.g., logical unit numbers or LUNs), and may include one or more processors or other controllers that execute logical functions necessary for an external system to operate the memory devices or interfaces. Such an SSD may include one or more flash memory dies, each containing multiple memory arrays and peripheral circuits on them. A flash memory array may contain multiple blocks of memory cells organized into multiple physical pages. In many embodiments, the SSD also includes DRAM or SRAM (or other forms of memory dies or other memory structures). The SSD may receive commands from a host in relation to memory operations such as read or write operations that transfer data (e.g., user data and associated integrity data, such as error data and address data) between the memory device and the host, or erase operations that erase data from the memory device.

[0026] A memory device includes individual memory dies, each of which may include a storage area having one or more arrays of memory cells, for example, implementing one or more selected storage techniques. Such memory dies often include support circuitry for operating the memory array(s). Another example, sometimes commonly known as a “managed memory device,” includes an assembly of one or more memory dies associated with a controller function configured to control the operation of one or more memory dies. Such a controller function can simplify interoperability with external devices, such as a “host,” as described later herein. In such managed memory devices, the controller function may be implemented on one or more dies that also incorporate the memory arrays, or on separate dies. In another example, one or more memory devices can be combined with a controller function to form a solid-stage drive (SSD) storage volume. The term “memory system” is used herein to include one or more memory dies and, if present, any controller functions of such memory dies, and therefore includes individual memory devices, managed memory devices, and SSDs.

[0027] For the purposes of this description, exemplary embodiments include managed memory devices that implement NAND flash memory cells, referred to as “managed NAND” devices. Such managed NAND devices may generally be constructed and operated in accordance with the JEDEC UFS Flash Storage 3.0 specification described herein and may be modified as appropriate to incorporate the structures and functions described herein. However, the functions described may also be implemented in other types of memory devices, as described above, which may incorporate other storage technologies, some non-exclusive examples of which are described earlier herein and may be configured to operate in accordance with other industry standards or non-industry standard protocols as described above.

[0028] Electronic devices, such as mobile electronic devices (e.g., smartphones, tablets), electronic devices used in automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety or comfort systems), and internet-connected appliances or devices (e.g., Internet of Things (IoT) devices), have diverse storage needs, particularly depending on the type of electronic device, the operating environment, and the expected performance.

[0029] An electronic device can be broken down into several main components, namely, a processor (e.g., a central processing unit (CPU) or other main processor), memory (e.g., one or more volatile or non-volatile random access memory (RAM) memory devices, such as dynamic RAM (DRAM), mobile or low-power double data rate synchronous DRAM (DDR SDRAM), etc.), and storage devices (e.g., non-volatile memory (NVM) devices, such as flash memory, read-only memory (ROM), SSD, MMC, or other memory card structures or assemblies, etc.). In certain examples, an electronic device may also include a user interface (e.g., a display, touchscreen, keyboard, one or more buttons, etc.), a graphics processing unit (GPU), power management circuits, a baseband processor, or one or more transceiver circuits, etc.

[0030] Figure 1 shows a diagram of a memory device 100, such as a storage device, according to some examples of the present disclosure. The memory device 100 may include one or more host interfaces 123 that can utilize one or more protocols, such as a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an eMMC® interface, or one or more other connectors or interfaces, for communication with a host device 135. The host 135 can send one or more commands, such as read commands, write commands, and erase commands, to the memory device 100 via the host interfaces 123. The host interfaces 123 may be part of the controller 105 or may be implemented by separate circuitry.

[0031] The memory device 100 may include one or more controllers 105. The controllers 105 may include a processing circuit 110 which may include one or more processors 115. The processors 115 may be general-purpose hardware processors that execute firmware or other software instructions for performing operations on the memory device, including implementing a host interface 123 and a memory die interface 125. In other examples, the processor(s) 115 may be dedicated hardware processors specifically designed to perform operations on the memory device 100 by hardware logic and / or by executing software instructions. The processing circuit 110 may also include logic circuits and other circuit components configured to perform various control functions and memory management operations, or parts thereof, examples of which are described below.

[0032] In the illustrated example, the memory device 100 includes a host interface 123 that provides communication to an external host device 135 via a host bus 137. The configuration of the host interface 123 can take various forms depending on the specific configuration of the memory device 100 (sometimes referred to as the “memory system”). For example, in the example where the memory device 100 is a UFS device, the host interface conforms to the applicable UFS standard.

[0033] Furthermore, the memory device 100 incorporates one or more memory die interfaces 125 between the processing circuit 110 of the controller 105 and at least some of the memory dies 130-A to 130N+1 within the memory device 100. The memory die interfaces 125 may be part of the controller 105 or may be implemented by separate circuits. For example, in the case of a UFS device, one or more of the memory die interfaces 125 are appropriate memory interfaces, such as ONFI, as defined by the Open NAND Flash Interface ("ONFI") 4.0 specification or a later version or revision.

[0034] Components of the memory device 100, such as the controller 105, may include random access memory 120 for performing operations on the memory device 100. The random access memory 120 may be separate from the controller 105, or it may be integrated into the controller 105, as shown. In some examples, the random access memory 120 may be located within the controller 105 or separately from the controller 105.

[0035] The controller 105 can handle one or more functions of memory by interacting with memory cells of memory devices that are part of one or more memory dies 130-A to 130N+1. A schematic diagram of an exemplary implementation of memory die 130 is shown in Figure 4. The controller 105 can communicate with these memory dies via an internal communication interface 127, such as an I / O bus, via a memory die interface 125. In some examples, memory dies may have their own device controllers, including processing circuits and processors, to control operations on each memory die. Such device controllers may be formed on a die common to the device storage array, or on a die separate from the die containing the device storage array. Both configurations are included by the identified “memory dies” (130A to N+1) described herein. The memory dies may be NAND dies, 3D NAND dies, phase-change memory dies, etc.

[0036] The host device 135 may be a personal computer, smartphone, tablet, part of an integrated circuit, or an Internet of Things (IoT) device (e.g., a refrigerator or other electrical appliance, a sensor, motor or actuator, a mobile communication device, an automobile, a drone, etc.).

[0037] For the purposes of describing the present invention, exemplary memory operations and management functions may be described in the context of NAND memory. Those skilled in the art will recognize that other forms of non-volatile memory may have similar memory operations or management functions. Such NAND management functions include wear leveling (e.g., garbage collection or reclamation), error detection or error correction, block retirement, or one or more other memory management functions.

[0038] Memory dies 130-A to 130-N+1 can contain several memory cells arranged in multiple planes, subblocks, blocks, or pages, for example. As an example, a 48GB TLC NAND memory device can contain 18,592 bytes(B) of data per page (16,384 + 2208 bytes), 1536 pages per block, 548 blocks per plane, and four or more planes per device. Another example is a 32GB MLC memory device (storing 2 bits of data per cell (i.e., 4 programmable states)) which can contain 18,592 bytes(B) of data per page (16,384 + 2208 bytes), 1024 pages per block, 548 blocks per plane, and four planes per device, but requires half the write time and twice the program / erase (P / E) cycles compared to the corresponding TLC memory device. Other examples may include other numbers or arrangements. In some embodiments, the memory device or a portion thereof may be selectively operated in SLC mode or in a desired MLC mode (TLC, QLC, etc.).

[0039] During operation, data is typically written to or read from memory device 100 in page units, or erased in block units. However, one or more memory operations (e.g., read, write, erase) can be performed on larger or smaller groups of memory cells as needed. The data transfer size of memory device 100 is typically called a page, while the data transfer size of the host is typically called a sector.

[0040] A page of data may contain several bytes of user data (e.g., a data payload containing data from several sectors) and its corresponding metadata, but the page size often refers only to the number of bytes used to store the user data. For example, a page with a page size of 4KB may contain not only 4KB of user data (e.g., 8 sectors assuming a sector size of 512B) but also several bytes of metadata corresponding to the user data (e.g., 32B, 54B, etc.), such as integrity data, address data (e.g., logical address data), or other metadata associated with the user data.

[0041] Different types of memory cells may offer different page sizes or require different amounts of metadata. For example, different memory device types may have different bit error rates, which can result in different amounts of metadata required to ensure the integrity of data pages (for instance, a memory device with a higher bit error rate may require more bytes of error correction code than a memory device with a lower bit error rate). As an example, a multi-level cell (MLC) NAND flash device may have a higher bit error rate than a corresponding single-level cell (SLC) NAND flash device. Therefore, an MLC device may require more metadata bytes for error data than a corresponding SLC device.

[0042] Figure 2 shows an exemplary schematic diagram of a portion of a NAND architecture semiconductor memory array 300, which includes a plurality of memory cells 202 arranged in a two-dimensional array of strings (e.g., strings 205-207) and tiers (e.g., shown as word lines (WL) WL0-WL7 210-217, drain-side selected gate (SGD) line 225, source-side selected gate (SGS) line 230, etc., respectively), and a sense amplifier or device 260, according to some examples of the present disclosure. For example, the memory array 200 may show an exemplary schematic diagram of a portion of one physical page of memory cells of the memory die 130 from Figure 1.

[0043] Each string of memory cells is coupled to a source line (SRC) 235 using its respective source-side selection gate (SGS) (e.g., SGS231-233) and to its respective data line (e.g., bit lines (BL) BL0-BL2 220-222) using its respective drain-side selection gate (SGD) (e.g., SGD226-228). The example in Figure 2 is shown using eight tiers (e.g., using word lines (WL) WL0-WL7 210-217) and three data lines (BL0-BL2 226-228), but other examples can include strings of memory cells with more or fewer tiers or data lines as desired.

[0044] In a NAND architecture semiconductor memory array, such as the exemplary memory array 200, the state of a selected memory cell 202 can be accessed by sensing a change in current or voltage associated with a specific data line containing the selected memory cell. The memory array 200 can be accessed using one or more drivers (e.g., by a control circuit, one or more processors, digital logic, etc.). In one embodiment, one or more drivers can activate a specific memory cell or set of memory cells by driving a specific potential to one or more data lines (e.g., bit lines BL0-BL2), access lines (e.g., word lines WL0-WL7), or selection gates, depending on the type of operation desired to be performed on the specific memory cell or set of memory cells.

[0045] To program a memory cell or write data to it, a programming voltage (Vpgm) (e.g., one or more programming pulses) can be applied to a selected word line (e.g., WL4) and, by extension, to the control gates of each memory cell coupled to the selected word line (e.g., control gates (CG) 241-243 of the memory cells coupled to WL4). The programming pulses can start at, for example, 15V or around 15V, and in certain embodiments, their magnitude can be increased during the application of each programming pulse. While the programming voltage is applied to the selected word line, a potential such as ground potential (e.g., Vss) can be applied to the data line (e.g., bit line) and substrate (and thus the channel between source and drain) of the memory cell to be programmed, resulting in charge transfer from the channel of the target memory cell to a charge storage structure (e.g., direct injection or Fowler-Nordheim (FN) tunneling). Such charge storage structures may include, for example, the floating gate or charge trap region of each memory cell. In floating-gate memory cells, charge is stored in an isolated polysilicon structure, whereas in charge-trapped memory cells, charge is typically stored in a dielectric structure.

[0046] In contrast, a pass-through voltage (Vpass) may be applied to one or more word lines containing memory cells not intended for programming, for example, to prevent charge from moving from the channels of those unprogrammed memory cells to the charge storage structure, or a blocking voltage (Vcc, etc.) may be applied to data lines (such as bit lines) containing memory cells not intended for programming. The pass-through voltage may be variable, for example, depending on whether the applied pass-through voltage is close to a word line intended for programming. The blocking voltage may include a power supply voltage (Vcc) relative to ground potential (e.g., Vss), for example, a voltage from an external power supply or source (e.g., a battery, AC / DC converter, etc.).

[0047] For example, if a programming voltage (e.g., 15V or higher) is applied to a specific word line such as WL4, a path voltage of 10V can be applied to one or more other word lines such as WL3 and WL5 to prevent programming of untargeted memory cells or to retain values ​​stored in such untargeted memory cells. As the distance between the applied programming voltage and the untargeted memory cells increases, the path voltage required to prevent programming of untargeted memory cells can be reduced. For example, if a programming voltage of 15V is applied to WL4, a path voltage of 10V can be applied to WL3 and WL5, an 8V path voltage to WL2 and WL6, and a 7V path voltage to WL1 and WL7. In other examples, the path voltage or the number of word lines, etc., can be higher or lower, or more or fewer.

[0048] A sense amplifier 260 coupled to one or more data lines (for example, the first, second, or third bit lines (BL0~BL2) 220~222) can detect the state of each memory cell in each data line by sensing the voltage or current on a specific data line.

[0049] During the application of one or more programming pulses (e.g., Vpgm), a verification operation can be performed to determine whether the selected memory cell has reached its intended programmed state. If the selected memory cell has reached its intended programmed state, further programming of that memory cell can be prohibited. If the selected memory cell has not reached its intended programmed state, additional programming pulses can be applied. If the selected memory cell has not reached its intended programmed state after a certain number of programming pulses (e.g., a maximum number), the selected memory cell, or any string, block, or page associated with such a selected memory cell, can be marked as bad.

[0050] In a single-level cell (SLC), there are two possible voltage levels that can be programmed into the cell: one representing binary "1" and the other representing binary "0". In a multi-level cell (MLC), there are four possible voltage levels that can be programmed into the cell: the four possible voltage levels represent "00", "01", "10", and "11". To program an MLC cell, multiple programming pulses are applied. The first pulse programs the first "page" of data representing either the most significant or least significant bit of the cell. The second pulse programs the second "page" of data representing the other bit of the cell that was not programmed by the first pulse. Similarly, a triple-level cell (TLC) stores eight possible voltage levels, and a quad-level cell (QLC) stores sixteen possible voltage levels.

[0051] To read a value stored in one or more memory cells, a read voltage is applied to the word line of the selected cell. If the voltage stored in the word line cell is greater than the read voltage, the cell passes the voltage to the sense amplifier. For SLC cells, the read voltage is selected to be between two voltages representing "1" and "0". For MLC, TLC, and QLC, multiple read operations are used to read each bit stored in the cell, and each read operation utilizes a different read voltage.

[0052] To erase a memory cell or group of memory cells (for example, erasure is typically performed on a block or subblock), an erase voltage (Vers) can be applied to the substrate of the memory cell to be erased (and thus the channel between the source and drain) (for example, by selecting the gate using one or more bit lines) while the word line of the memory cell to be erased is held at a potential such as ground potential (e.g., Vss), thereby transferring charge from the charge storage structure of the memory cell to be erased to the channel (e.g., direct injection or Fowler-Nordheim (FN) tunneling).

[0053] FIG. 3 shows an exemplary schematic diagram of a 3D NAND architecture semiconductor memory array 300 including a plurality of memory cell strings (e.g., A0 memory cell strings 305A0 to 307A0, A n memory cell string 305A n memory cell string 305A n memory cell string 305A n memory cell string 305A n memory cell string 305A n memory cell string 305A n memory cell string 305A n memory cell string 305A n memory cell string 305A n memory cell string 305A

[0054] Each string of memory cells is connected to a source line (SRC) 335 or a source side select gate (SGS) (e.g., A0 SGS 331A0 to 333A0, A n SGS 331A n memory cell string 305A n memory cell string 305A n SGS 331B n memory cell string 305A n memory cell string 305A n SGD 326A n memory cell string 305A n memory cell string 305A n SGD 326B n memory cell string 305A nBetween (etc.), in the Z direction, there are several layers of charge storage transistors (e.g., floating gate transistors, charge trap structures, etc.) stacked from source to drain. Each string of memory cells in the 3D memory array can be arranged as a data line (e.g., bit line (BL) BL0~BL2 320~322) along the X direction and as a physical page along the Y direction.

[0055] Within a physical page, each tier represents a row of memory cells, and each string of memory cells represents a column. A subblock can contain one or more physical pages. A block can contain several subblocks (or physical pages) (e.g., 128, 256, 384, etc.). In this specification, we show two blocks, each block having two subblocks, each subblock having a single physical page, each physical page having a string of three memory cells, and each string having eight tiers of memory cells; however, in other embodiments, the memory array 300 can contain more or fewer blocks, subblocks, physical pages, strings of memory cells, memory cells, or tiers. For example, each string of memory cells may optionally contain more or fewer tiers (e.g., 16, 32, 64, 128, etc.), as well as one or more additional tiers of semiconductor material above or below charge storage transistors (e.g., selection gates, data lines, etc.). For example, a 48GB TLC NAND memory device can contain 18,592 bytes (B)(16,384 + 2208 bytes) of data per page, 1536 pages per block, 548 blocks per plane, and four or more planes per device.

[0056] Each memory cell in the memory array 300 includes a control gate (CG) coupled to an access line (e.g., word line (WL) WL00~WL70310A~317A, WL01~WL71310B~317B, etc.) (e.g., electrically or otherwise operablely connected), and the access line collectively couples control gates (CG) across a dedicated tier or portion of a tier, as needed. A particular tier in the 3D memory array, and accordingly, a particular memory cell in a string, can be accessed or controlled using its respective access line. A group of selection gates can be accessed using various selection lines. For example, A0SGD326A0~328A0 can be accessed using the A0SGD line SGDA0325A0, and A n SGD326A n ~328A n , SGD line SGDA n 325A n It can be accessed using B0SGD326B0~328B0, and B0SGD line SGDB0325B0 can be accessed using B n SGD326B n ~328B n B n SGD Line SGDB n 325B n It can be accessed using A0SGS331A0~333A0 and A n SGS331A n ~333A n This can be accessed using gate selection line SGS0330A, B0SGS331B0~333B0 and B n SGS331B n ~333B n This can be accessed using the gate selection line SGS1330B.

[0057] For example, the memory array 300 may include several levels of semiconductor material (e.g., polysilicon) configured to connect control gates (CGs) (or parts of CGs or selection gates) of each memory cell or selection gate in each tier of the array. A particular string of memory cells in the array may be accessed, selected, or controlled using a combination of bit lines (BLs) and selection gates, and a particular memory cell in one or more tiers within a particular string may be accessed, selected, or controlled using one or more access lines (e.g., word lines).

[0058] Figure 4 shows an exemplary block diagram of a memory die 400, which includes a memory array 402 having a plurality of memory cells 404, and one or more circuits or components that provide communication with the memory array 402 or perform one or more memory operations thereon, according to some examples of the present disclosure. The memory die 400 may include a row decoder 412, a column decoder 414, a sense amplifier 420, a page buffer 422, a selector 424, an input / output (I / O) circuit 426, and a memory control unit 430.

[0059] The memory cells 404 of the memory array 402 can be arranged in blocks such as the first and second blocks 402A, 402B, etc. Each block can contain subblocks. For example, the first block 402A may contain the first and second subblocks 402A0, 402A n It may include, and the second block 402B is the first and second subblocks 402B0, 402B nIt may include several subblocks, each containing several physical pages, and each page containing several memory cells 404. In this specification, it is shown as having two blocks, each containing two subblocks, and each subblock containing several memory cells 404, but in other examples, the memory array 402 may contain more or fewer blocks, subblocks, memory cells, etc. In other examples, the memory cells 404 may be arranged in several rows, columns, pages, subblocks, blocks, etc., and can be accessed using, for example, an access line 406, a first data line 410, or one or more selection gates, source lines, etc.

[0060] The memory control unit 430 can control memory operations of the memory die 400 in accordance with one or more signals and / or instructions / commands received by the memory controller on the control line 432 in the memory interface (as described with respect to the controller 105 and host interface 123 of the memory device 100 in Figure 1). Such signals and / or instructions may include, for example, one or more clock signals and / or control signals indicating a desired operation (e.g., write, read, erase, etc.), or address signals (A0-AX) received on one or more address lines 416. One or more devices outside the memory die 400 can control the values ​​of the control signals on the control line 432 or the address signals on the address line 416. Examples of devices outside the memory die 400 may include, but are not limited to, a host, a memory controller, a processor, or one or more circuits or components not shown in Figure 4.

[0061] The memory die 400 can transfer data to (e.g., write to or erase) or transfer data from (e.g., read from) one or more of the memory cells 404 using the access line 406 and the first data line 410. The row decoder 412 and column decoder 414 can receive and decode address signals (A0~AX) from the address line 416, determine which memory cell 404 to access, and, as described above, provide signals to one or more of the access line 406 (e.g., one or more of the word lines (WL0~WLm)) or the first data line 410 (e.g., one or more of the bit lines (BL0~BLn)).

[0062] The memory die 400 may include sense circuits, such as sense amplifiers 420, configured to use a first data line 410 to identify (e.g., read) the value of data in a memory cell 404, or to determine the value of data to be written thereto. For example, in a selected string of memory cells 404, one or more sense amplifiers 420 may read the logic level of the selected memory cell 404 in response to a read current flowing through the selected string in the memory array 402 to the data line 410.

[0063] One or more devices outside the memory die 400, such as the controller 105, can communicate with the memory die 400 using I / O lines (DQ0~DQN) 408, address lines 416 (A0~AX), or control lines 432. The input / output (I / O) circuit 426 can transfer data values ​​to and from the memory die 400, such as to and from the page buffer 422 or the memory array 402, using I / O line 408, for example, according to control lines 432 and address lines 416. The page buffer 422 can store data received from one or more devices outside the memory die 400 before the data is programmed into the relevant part of the memory array 402, or it can store data read from the memory array 402 before the data is sent to one or more devices outside the memory die 400.

[0064] The column decoder 414 can receive address signals (A0~AX) and decode them into one or more column selection signals (CSEL1~CSELn). The selector 424 (e.g., a selection circuit) can receive the column selection signals (CSEL1~CSELn) and select data in the page buffer 422 that represents the values ​​of data to be read from or programmed into the memory cell 404. The selected data can be transferred between the page buffer 422 and the I / O circuit 426 using a second data line 418. In some examples, a flash translation layer (not shown) can read data from the memory array 402 by mapping addresses provided by the host to physical memory addresses used by the row decoder 412 and column decoder 414.

[0065] The memory control unit 430 can receive positive and negative power signals, such as the power supply voltage (Vcc) 434 and the negative power supply (Vss) 436 (e.g., ground potential), from an external power supply or power source (e.g., an internal or external battery, an AC / DC converter, etc.). In certain examples, the memory control unit 430 may include a regulator 428 for internally supplying the positive or negative power signals.

[0066] Internal copyback compatible scrambler As mentioned above, scrambling data using physical page addresses to satisfy data pattern requirements when writing to a memory device prevents internal copyback operations from performing an operation that does not modify the data, but instead directly copies the data from one location on the die to another. Because the address changes from the address to which the data was initially written, it is not possible to descramble the data after an internal copyback operation using the physical address of the cell where the data is currently stored.

[0067] As stated above, this disclosure describes a method, system, and machine-readable medium providing a seed generator for generating a seed value, which is used by a scrambler to scramble either host data and / or metadata together or separately. The seed is then appended to the scrambled host data and metadata and written to a memory device. Any subsequent internal copyback operation may copy the data, including the seed, exactly as it was written. A read operation then descrambles the data read from the memory device by first reading the seed (stored in an unscrambled state), and then using that seed to reverse the scrambling operation and retrieve the host data and metadata. This read operation also works after an internal copyback operation because the scrambler's seed is stored in an unscrambled state along with the data written to the memory device.

[0068] As mentioned earlier, in some examples, a scrambler uses the same seed value to scramble and unscramble data, while in other examples, it uses a different value to unscramble the data than the one used to scramble it. For example, the first encryption key of a key pair can be used to scramble one or both of the host data and metadata (by encrypting them), and the second encryption key of the key pair can be used to unscramble the data. In these examples, the value used by the unscrambler to unscramble the data (e.g., the second key) is stored with the data.

[0069] Figure 5 shows the data flow of a write operation in some examples of the present disclosure. Host data 615 is received from the host for writing to the memory device. Metadata 610 is created by the memory device, such as the controller 105 and the memory die 130, or a portion of the metadata 610 may be created by both the controller 105 and the memory die 130. The metadata may include information about the host data and information about the conditions under which the host data was stored, such as the write temperature and other details.

[0070] Next, the host data 615 and metadata 610 are input to the scrambler 620. The scrambler 620 can be any algorithm that can reversibly transform the host data 615 and metadata 610 into different values ​​using one or more seed values. For example, XOR operations, cryptographic operations (e.g., RSA, data encryption standards, Triple DES, RSA, Blowfish, Advanced Encryption Standard (AES), etc.). Those skilled in the art will understand that, for example, multiple seed values ​​may be used in a scrambler algorithm that uses multiple keys or other values ​​used to descramble the metadata and host data, or in some examples the metadata and host data may be split and scrambled with different seeds. In examples where multiple seeds are used, each seed used to descramble the data may be stored together with the scrambled host data and metadata.

[0071] Seed 630 may be used by a scrambler to generate scrambled metadata and host data 635. Seed 630 may be generated by a seed generator 625. In some examples, the seed generator 625 may be a random number generator. The seed generator 625 may be a hardware random number generator, a software random number generator, etc. The seed generator 625 may be a true random number generator or a pseudo-random number generator. In other examples, the seed generator 625 may be a cryptographic key generator, etc. The seed generator 625 may select from a list of previously determined seed values, or it may generate a new seed value (for example, based on an expression or the execution of hardware logic). Since each seed may be generated in response to the reception of host data 615 in particular, the first seed of the first host data may be different from the second seed of the host data received later.

[0072] In some cases, the seed generator 625 may need to be seeded. For example, if the seed generator 625 is a pseudorandom number generator, the seed generator may be seeded initially, at each startup of the memory device, periodically and / or similar times, etc. The seed generator 625 may be seeded by the current time, the current temperature, the physical address corresponding to the last written word on the memory device or part of the memory device (e.g., die), the next written physical address, etc. As mentioned above, the seed generator may have its seed refreshed periodically (e.g., after a predetermined period).

[0073] Each page written to a memory device may have a seed generated or selected for that page, which a scrambler can use to scramble host data and / or metadata. In some examples, a single seed is generated for both metadata and host data, while in others, different seeds are generated for metadata and host data. In some examples, seed 630 and scrambler 620 can operate to scramble host data and metadata in such a way that metadata can be descrambled without knowing the host data, so that host data and metadata can be descrambled independently of each other.

[0074] When the seed is generated and used, it is added to the scrambled metadata and host data (as shown, it is added before the scrambled metadata and host data, but it may also be added after the scrambled metadata and host data). The combined seed and scrambled metadata and host data are then encoded by the error correction code encoder 640 to generate encoded data 645, which is programmed into the memory cells of the memory device.

[0075] Figure 6 shows the data flow of a read operation in some examples of the present disclosure. The host sends a read request containing a logical address to the memory device. The memory device translates this to a physical address using a Log-to-Physical (L2P) table. The command is then issued to the appropriate memory die corresponding to that physical address. The memory cell at that physical address is then read by applying an appropriate read voltage to the memory cell. The resulting encoded data 645 is decoded by the ECC decoder 650. If the ECC decoding is successful, the scrambled metadata and host data 635 and the seed 630 are recovered. The seed is then used by the unscrambler 655 to descramble the scrambled metadata and host data 635 back to the original metadata 610 and host data 615. The unscrambler 655 can apply the reverse operation of the operation performed by the scrambler 620. For example, if the scrambler 620 applies an XOR operation to XOR the metadata 610 and host data 615 with a random number sequence having a seed 630, the unscrambler 655 applies an XOR operation to XOR the random number sequence having the seed with the scrambled metadata and host data 635, thereby obtaining the unscrambled metadata 610 and host data 615.

[0076] Figure 7 shows a flowchart of a method 700 for writing data to a memory device according to some examples of the present disclosure. In operation 710, the memory device can receive data and write it to a memory cell. For example, a host can instruct the memory device to write host data to the memory device. This instruction allows the host to provide host data and write it to the memory device.

[0077] In operation 715, a seed value may be generated. The seed value may be generated in response to the reception of data to be written (for example, by being generated simultaneously with the reception of data). The seed value may be an integer. The seed value may be newly generated or selected each time the memory device writes new data to a memory cell. A particular seed value may be different from a previously generated seed value. In some examples, the seed value may be unique within a particular plane, a particular die, a particular memory device, etc. In other examples, the seed value may not be unique, but may eventually be repeated after a series of different seed values. The seed value may be random or pseudorandom. As mentioned above, the seed value may be a randomly generated value, a cryptographic key, etc.

[0078] In operation 720, the data to be written may be scrambled using a seed value. For example, the data received in operation 710 may be combined with metadata generated by the memory device and transformed by a scrambling algorithm using the seed value. For example, the algorithm may be an XOR algorithm, and the data and metadata may be XORed with the seed to produce a scrambled value. In other examples, the data and metadata may be encrypted with the seed. The scrambling algorithm may be any algorithm that takes at least two inputs (data (e.g., combined host data and metadata) and a seed value) and produces an output that is different from this data but is also reversible in that the function can convert the scrambled data using the seed value back to the original data. In some examples, the metadata and host data may be scrambled so that the metadata can be descrambled without knowledge of the host data. In some examples, to achieve this, the metadata and host data may be scrambled separately with the same seed or different seeds. If the host data and metadata are scrambled with different seeds, each seed may be stored together with the encoded and scrambled metadata and host data (e.g., operation 730).

[0079] In operation 725, the seed value may be concatenated with scrambled data (e.g., host data and metadata) and encoded, for example using an error correction coding (ECC) scheme. This encoded data can then be written in operation 730 to a first set of memory cells on a die of the memory device (e.g., shown as the first die). For example, the encoded data may be written to a set of memory cells forming a word of the memory device. As previously mentioned, if multiple seed values ​​are used, the multiple seed values ​​may be concatenated and stored together with the host data and metadata.

[0080] In operation 735, the memory device may later identify that data is copied to a second set of memory cells on the first die, where the first and second sets of memory cells may be different. For example, the first set of memory cells may include an SLC cache, from which data may need to be moved out of the cache to MLC, TLC, or QLC storage. In operation 740, data may be copied to a second set of memory cells. In some examples, no data is transferred (e.g., to a controller) via the memory device's internal communication interface. In some examples, as described below, the metadata portion may be transferred via the memory device's internal communication interface to a location where the metadata is updated (e.g., to a controller), and then transferred back to a location where the metadata is combined with the host data for storage during internal copyback. In these examples, the host data portion is not transferred via the memory device's (e.g., controller's) internal communication interface, only the metadata is transferred. In yet another example, both the host data and metadata may be transferred (e.g., to a controller) via the memory device's internal communication interface, then transferred back, and stored in a second set of cells. Operations 735 and 740 may occur independently of operations 710-730. In other words, the copy-back operations described in operations 735-740 may occur later or may not occur at all.

[0081] Figure 8 shows a flowchart of method 800 for reading data from a memory device according to some examples of the present disclosure. In operation 810, the memory device can receive a request to read data stored in the memory device. For example, a host can request data stored at a specific logical address in the memory device. In operation 815, the data is read from the memory device at the indicated location. The read data is encoded. In operation 820, the encoded data is decoded. The decoded data includes one or more seed values ​​and scrambled data (host data and metadata). In operation 825, the seed value(s) are extracted from the decoded data. For example, the seed values ​​may be stored before, after, or adjacent to the scrambled data (e.g., host data and metadata). In operation 830, the scrambled data may be unscrambled with the seed values ​​by an unscrambler. The unscrambler may be any algorithm that applies the reverse transformation of the scrambler. The host data is then sent to the host in operation 835. In some cases, host data can be further processed before being sent to the host in operation 835.

[0082] Metadata update As mentioned earlier, conventional internal copyback operations do not decode or descramble the data, and therefore do not update the appropriate metadata associated with the host data. This can lead to reliability issues, as these metadata values ​​may be used to properly read the host data. In some cases, to address this issue, the metadata may be separated from the host data, and only the metadata may be transmitted via the internal I / O interface and updated by the controller. The updated metadata is then sent back to the memory die, combined with the host data (which may be stored in a memory buffer while awaiting the updated metadata), and written to a new location on the die. While transmitting the metadata affects the internal I / O interface, the I / O usage is typically less than 1% of the I / O required to send both the metadata and host data back to the controller.

[0083] In conventional methods, host data and metadata are scrambled and encoded together. If host data is not transmitted with metadata, the controller cannot properly update the ECC information (such as ECC parity bits) stored with the data. This results in inaccurate decoding because the ECC information is calculated based on both host data and metadata. In some cases, to solve this problem, a memory device can store separate ECC information (e.g., separate parity bits) for metadata and host data, and apply separate ECC processes to metadata and host data. When metadata is updated and encoded, the parity bits associated with the metadata are updated. Since the host data was not affected, the ECC information of the host data is not affected and does not need to be updated. Therefore, even if the metadata has changed, the host data can be properly decoded.

[0084] Figure 9 shows the data flow of a write operation in some examples of this disclosure, where metadata and host data are encoded separately. Metadata 910 and host data 915 are input to a scrambler 920. A seed generator 925 generates a seed 930, which is used to scramble the metadata and host data to generate scrambled host data 937. The metadata and host data may need to be scrambled in a way that allows the metadata to be updated even if host data is not received, by allowing the metadata to be descrambled even if scrambled host data is not present.

[0085] This can be achieved by using a scrambling algorithm that does not utilize host data when calculating scrambled metadata. For example, an XOR operation that XORs a random number sequence with a seed with the data in a bitwise manner can be reversed by applying the same XOR value to the scrambled data. In these examples, descrambling still works even if the metadata is separated from the host data. In these examples, the same seed value can be used to scramble both the metadata and the host data.

[0086] In other examples, metadata 910 and host data 915 may be scrambled with different seed values. For example, if scrambler 920 performs an operation (e.g., some cryptographic algorithm) that requires both metadata and host data to be present in order to descramble (e.g., decrypt) the data (e.g., the value of the unscrambled metadata), then metadata and host data may be scrambled separately with separate seeds. In these examples, both seeds may be stored, or only one seed may be stored if one seed can be inferred from the other seed. In other examples, they may have the same seed value, but the scrambling operation is performed in such a way that knowledge of the host data (either scrambled or unscrambled) is not required to descramble the metadata.

[0087] When the scrambled metadata 935 and seed 930 can be input to the ECC encoder 940, encoded metadata 945 can be generated. Separately, when the scrambled host data 937 can be fed to the ECC encoder 940, encoded host data 947 can be generated. The encoded metadata 950 and encoded host data 952 can then be written (along with ECC information such as parity bits) to the memory cells of the memory device. As shown, the seed 930 is encoded together with the scrambled metadata 935, but in other examples, the seed 930 may be encoded together with the scrambled host data 937, or together with both the scrambled metadata 935 and the scrambled host data 937.

[0088] Figure 10 shows the data flow 1000 of an internal copyback operation with metadata updates, in some examples of the present disclosure, where metadata and host data are encoded separately. The encoded metadata 1010 and encoded host data 1015 are read from the medium. The encoded host data 1015 is stored in a memory buffer, such as a page buffer 1020. In some examples, the encoded metadata 1010 is also stored in a buffer (if the metadata does not need to be updated).

[0089] The encoded metadata 1010 is transferred to the controller via the communication interface, where it is decoded by the decoder 1025 and descrambled by the unscrambler 1030. ECC information and seed (which may be encoded together with the metadata, host data, or both), such as parity data for the scrambler, can also be transferred and used by the decoder 1025 and unscrambler 1030. If the ECC check of the metadata fails, the memory device may abort the internal copyback operation and enter a data recovery step.

[0090] Once metadata can be read, 1035 can determine whether the metadata needs to be updated. For example, the drive's write temperature, write time, etc. If the metadata does not need to be updated, an indication may or may not be sent back to the memory die. For example, a message indicating that no changes are needed. In other cases, even if the metadata is not updated, it may be re-randomized, re-encoded, and sent back. This has the advantage of ensuring that the metadata is error-free. In some cases, if the written metadata is sufficiently close (e.g., within a specified distance), the system may decide not to update the metadata. Therefore, if the drive temperature when the data was first written is close to the current temperature, the metadata may not need to be updated. In some cases, this decision is optional, as the system may be configured to always update the metadata (e.g., update the write timestamp). In some cases, all metadata is updated, and in others, only some fields of the metadata are updated. In some cases, whether a particular field of metadata is updated may depend on certain rules. For example, one particular field may always be updated, while the remaining fields are only updated if the rule evaluates and indicates that the metadata field needs to be updated. For example, the rule could be that if the difference between the temperature at which the data was first written and the current temperature exceeds a threshold, the write temperature can be updated; otherwise, the write temperature cannot be updated.

[0091] If 1035 determines that the metadata needs to be updated, the metadata updater 1040 updates the metadata, for example by incorporating various measurements from various sensors in the memory device (e.g., temperature, time, etc.). The scrambler 1045 then scrambles the updated metadata using the same key that was initially used to scramble the metadata. The encoder 1050 then encodes the scrambled and updated metadata to generate new ECC information. The encoded metadata, with the associated updated ECC information (e.g., parity bits), is then sent back to the memory die and combined with the encoded host data in the page buffer 1020. This combination of updated metadata and host data is then written to the medium.

[0092] Figure 11 shows a flowchart of a method 1100 for writing data to a memory device according to some examples of the present disclosure. Figure 11 may be performed by a controller of the memory device, such as controller 105 in Figure 1. In operation 1110, the controller may receive a write request containing host data. In operation 1115, the controller may determine metadata corresponding to the host data, such as the write temperature and the time the data was written. In operation 1120, the controller scrambles the metadata and host data so that the metadata can be descrambled without knowing the host data. In other words, the scrambling process does not utilize the host data, so knowledge of the host data is not required to descramble the metadata. For example, the metadata may be scrambled in a separate operation from the host data with a seed or key (either the same seed or key used to scramble the host data, or a different seed or key). In yet another example, for a particular scrambling algorithm, separate processing may not be required. That is, the nature of the scrambling algorithm allows for independent descrambling of bits once a seed is given. For example, the value of the descrambled bits in metadata does not depend on the value of any bits other than the metadata (such as host data), except for the key value.

[0093] In operation 1125, the scrambled host data and metadata are encoded separately with separate encoding information. In operation 1130, the controller can cause the encoded metadata and encoded host data to be stored in a memory device. For example, the controller can send a command via an internal communication interface to the memory die instructing it to program the physical word line(s) of the memory cell to store the encoded metadata and encoded host data.

[0094] Figure 12 shows a flowchart of method 1200 for writing data to a memory device during an internal copyback operation, according to some examples of the present disclosure. Figure 12 may be performed by a controller of the memory device, such as controller 105 in Figure 1. In operation 1210, the memory die may send and the controller may receive encoded and scrambled metadata in response to an internal copyback command (either issued by the controller or generated within the memory die). This metadata is encoded and / or scrambled so that it can be decoded and / or descrambled without host data. In other words, no host data is sent by the memory die to the controller.

[0095] In operation 1215, the metadata is decoded using the encoding information. As previously stated, if decoding fails (for example, if the metadata contains an uncorrectable ECC error), the memory device cancels the internal copyback operation and attempts to recover the data through a recovery operation. In operation 1220, the controller descrambles the decoded metadata from operation 1215, for example, by using a seed added to the decoded metadata or a seed sent by the memory die. As previously stated, the seed may not be scrambled. Operation 1220 descrambles the decoded metadata without knowledge of the host data or the data corresponding to the host data. That is, the descrambling in operation 1220 does not require knowledge of the host data, encoded host data, scrambled host data, encoded and scrambled host data, etc.

[0096] Next, in operation 1225, the descrambled and decoded metadata is updated. For example, the write temperature or write time may be updated. As mentioned above, in some examples, metadata or fields of metadata may be selectively updated based on the evaluation results of one or more rules, the current metadata, the current state of the memory device (e.g., temperature, time, etc.). The metadata may be updated based on the current state of the memory device. In operation 1230, the updated metadata is scrambled with a seed. In operation 1235, the scrambled and updated metadata is encoded. In operation 1240, the encoded, scrambled and updated metadata is sent back to the memory die, where it is combined with the stored scrambled and encoded host data and written to the memory cell.

[0097] Figure 13 shows a flowchart of an internal copyback operation method 1300 on a memory device according to some examples of the present disclosure. Figure 13 may be performed by a memory die of a memory device, such as the memory die 130 in Figure 1. The memory die 130 may have processing circuitry and working memory (e.g., volatile memory). The processing circuitry may be one or more processors configured to perform method 1300. In operation 1310, the memory die 130 may identify an internal copyback command to one or more memory locations within the memory die. For example, a controller may issue a command, and various triggers may be identified to move data stored in memory cells corresponding to an SLC cache to MLC, TLC, or QLC storage. Various triggers may include idle time, SLC cache utilization, controller commands, etc. Both the SLC cache and the final target MLC, TLC, or QLC storage may be on the same memory die. In these examples (for example, identified as having a source and destination on the same memory die), an internal copyback operation can be performed to copy data (host data and metadata) from a first location on the die to a second location on the same die without transferring the entire data over the communication interface with the controller.

[0098] In operation 1315, the source memory location of the internal copyback is read to retrieve metadata and host data. Both this metadata and host data are scrambled and encoded. In operation 1320, the encoded and scrambled host data read from the source memory location is copied to a buffer, such as a page buffer. In some examples, the encoded and scrambled metadata may also be copied to the same buffer, such as a page buffer, as the encoded and scrambled host data.

[0099] In operation 1325, the encoded and scrambled metadata may be sent to the controller for updating via an internal communication interface (e.g., a communication bus). In operation 1330, the memory die may receive an indication that the metadata has been updated, or that the metadata does not need to be updated. In operation 1335, the memory die may write the encoded and scrambled host data, along with the encoded and scrambled and updated metadata (or the original metadata if the metadata does not need to be updated), to the destination memory cell.

[0100] Figure 14 shows a block diagram of an exemplary machine 1400 in which any one or more of the techniques (e.g., methodologies) discussed herein may be performed. For example, the memory device 100 may include or be implemented by one or more components of Figure 14. The host 135 may be one or more components of machine 1400 or include it. In these examples, the memory device 100 may be mass storage 1421. One or more components of machine 1400 may implement one or more of the methods or structures shown in Figures 1-13, for example by operating instruction 1424.

[0101] In alternative embodiments, machine 1400 may operate as a standalone device or be connected to other machines (e.g., networked). In a networked deployment, machine 1400 can operate as a server machine, a client machine, or both in a server-client network environment. For example, machine 1400 can function as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. Machine 1400 can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, web appliance, IoT device, automotive system, host device, memory device, or any machine capable of executing instructions (sequentially or otherwise) that specify actions to be performed by that machine. The components of machine 1400 may reside in memory devices (e.g., processor, main memory, mass storage, etc.). Furthermore, although only a single machine is shown, the term “machine” shall also be interpreted as including any collection of machines that individually or collectively execute a set (or set) of instructions to implement any one or more methodologies of the methodologies described herein, such as cloud computing, software as a service (SaaS), and other computer cluster configurations.

[0102] The embodiments described herein may include or operate by logic, components, devices, packages, or mechanisms. An electrical circuit is a collection (e.g., a set) of circuits implemented on a tangible entity that includes hardware (e.g., simple circuits, gates, logic, etc.). Components of an electrical circuit may be flexible to the passage of time and the variability of the underlying hardware. An electrical circuit includes components that can perform a specific task when in operation, either individually or in combination. In one embodiment, the hardware of an electrical circuit may be designed immutably to perform a specific operation (e.g., hardwired). In one embodiment, the hardware of an electrical circuit may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) that include a computer-readable medium that is physically modified (e.g., magnetic, electrical, movable arrangement of invariant mass particles, etc.) to encode instructions for a specific operation. When connecting physical components, the underlying electrical properties of the hardware components may be changed, for example, from an insulator to a conductor, or vice versa. This instruction allows the relevant hardware (e.g., an execution unit or load mechanism) to create network components within the hardware via variable connections, enabling it to perform a portion of a specific task during operation. Thus, computer-readable media are communicatively coupled to other components of the network while the device is operating. In one example, any physical component can be used in multiple elements of multiple networks. For instance, during operation, an execution unit might be used in the first circuit of the first network at one point, and then reused at another point by the second circuit of the first network or the third circuit of the second network.

[0103] The machine (e.g., computer system) 1400 (e.g., host device 135, memory device 100, etc.) may include hardware processors 1402 (e.g., central processing unit (CPU), graphics processing unit (GPU), hardware processor cores, or any combination thereof such as processor 115 of memory controller 105, etc.), main memory 1404, and static memory 1406, some or all of which may communicate with each other via interlink (e.g., bus) 1408. The machine 1400 may further include a display unit 1410, an alphanumeric input device 1412 (e.g., keyboard), and a user interface (UI) navigation device 1414 (e.g., mouse). In one example, the display unit 1410, the input device 1412, and the UI navigation device 1414 may be touchscreen displays. The machine 1400 may further include sensors 1416, a signal generating device 1418 (e.g., speaker), and a network interface device 1420. Sensor 1416 may include a Global Positioning System (GPS) sensor, a compass, an accelerometer, and / or other sensors. Machine 1400 may include an output controller 1428, such as a serial (e.g., Universal Serial Bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near-field communication (NFC)) connection, to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0104] The mass storage device 1421 may include a machine-readable medium 1422 that stores one or more sets of data structures or instructions 1424 (e.g., software) that incorporate or utilize any one or more of the technologies or functions described herein. The instructions 1424 may also reside fully or at least partially in main memory 1404, static memory 1406, or hardware processor 1402 while they are being executed by machine 1400. In one example, one or any combination of hardware processor 1402, main memory 1404, static memory 1406, or mass storage device 1416 may constitute the machine-readable medium 1422.

[0105] Although machine-readable medium 1422 is shown as a single medium, the term “machine-readable medium” may include a single or multiple mediums configured to store one or more instructions 1424 (for example, a centralized or distributed database, or associated caches and servers).

[0106] The term “machine-readable medium” can include any medium that can store, encode, or carry instructions for execution by machine 1400, and can store, encode, or carry data structures used by or associated with such instructions, or that cause machine 1400 to execute one or more of the technologies of this disclosure. Examples of non-limiting machine-readable mediums may include solid-state memory, as well as optical and magnetic media. In some examples, machine-readable medium 1422 is a non-temporary machine-readable medium. In one embodiment, a massed machine-readable medium includes a machine-readable medium having a plurality of particles having an immutable (e.g., stationary) mass. Thus, a massed machine-readable medium is not a temporary propagating signal. Specific embodiments of massed machine-readable mediums may include semiconductor memory devices (e.g., non-volatile memory such as electrically programmable read-only memory (EPROM), electronically erasable programmable read-only memory (EEPROM), and flash memory devices), magnetic disks such as internal hard disks and removable disks, magneto-optical disks, as well as CD-ROM and DVD-ROM disks.

[0107] Instructions 1424 (e.g., software, programs, operating systems (OS), etc.) or other data are stored in a mass storage device 1421 and accessible by memory 1404 for use by the processor 1402. Memory 1404 (e.g., DRAM) is a different type of storage than storage device 1421 (e.g., SSD), which is generally fast but volatile and therefore suitable for long-term storage, including periods of being in an "off" state. Instructions 1424 or data used by the user or machine 1400 are typically loaded into memory 1404 for use by the processor 1402. When memory 1404 is full, virtual space from storage device 1421 can be allocated to supplement memory 1404, but since storage device 1421 is typically slower than memory 1404, with write speeds typically at least twice as slow as read speeds, the use of virtual memory (in contrast to memory 1404, e.g., DRAM) can significantly degrade the user experience due to the latency of the storage device. Furthermore, using storage device 1421 for virtual memory could significantly reduce the usable lifespan of storage device 1421.

[0108] In contrast to virtual memory, virtual memory compression (e.g., the Linux® kernel feature "ZRAM") uses a portion of memory as compressed block storage to avoid paging to storage device 1421. Paging is performed in compressed blocks until it becomes necessary to write such data to storage device 1421. Virtual memory compression increases the usable size of memory 1404 while reducing wear on storage device 1421.

[0109] Storage devices such as mass storage 1421 may also be memory devices such as NAND memory devices. Storage devices such as mass storage 1421, including MMC solid-state storage devices (e.g., micro Secure Digital (microSD®) cards), can be optimized for mobile electronic devices or mobile storage. MMC devices include multiple parallel interfaces with the host device (e.g., 8-bit parallel interfaces) and are often detachable and isolated from the host device. In contrast, eMMC® devices are mounted on a circuit board, considered components of the host device, and offer read speeds comparable to Serial ATA® (Serial AT (Advanced Technology) Attachment, or SATA) based SSD devices. However, the demand for performance in mobile devices continues to grow, including enabling virtual or augmented reality devices and taking advantage of increasing network speeds. To meet this demand, storage devices have shifted from parallel communication interfaces to serial communication interfaces. Universal flash storage (UFS) devices, including the controller and firmware, communicate with the host device using a low-voltage differential-signaling (LVDS) serial interface with dedicated read / write paths to further improve read / write speeds.

[0110] Instruction 1424 may further be transmitted or received over a communication network 1426 using a transmission medium via a network interface device 1420 that utilizes any one of several transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Examples of communication networks may include, among others, local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone service (POTS) networks, and wireless data networks (e.g., the IEEE 802.11 family of standards known as Wi-Fi®, the IEEE 802.16 family of standards known as WiMax®), the IEEE 802.15.4 family of standards, and peer-to-peer (P2P) networks. In one example, the network interface device 1420 may include one or more physical jacks (e.g., Ethernet, coaxial jacks, or telephone jacks) or one or more antennas to connect to the communication network 1426. For example, the network interface device 1420 may include multiple antennas for wireless communication using at least one of the following technologies: single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO). The term “transmission medium” shall be interpreted as including any intangible medium that can store, encode, or carry instructions for execution by machine 1400, and including digital or analog communication signals or other intangible medium to facilitate communication of such software.

[0111] The above detailed description includes references to accompanying drawings that form part of the detailed description. The drawings illustrate specific embodiments in which the present invention can be carried out. These embodiments are also referred to herein as “Examples.” Such examples may include elements in addition to those illustrated or described. However, the inventors also intend to provide examples in which only those illustrated or described elements are provided. Furthermore, the inventors also intend to provide examples that use any combination or variation of those illustrated or described elements (or one or more aspects thereof) with respect to a particular embodiment (or one or more aspects thereof) illustrated or described herein, or to other embodiments (or one or more aspects thereof).

[0112] In this text, the terms “a” or “an” are used to include one or more, as is common in patent documents, and are not related to any other examples or uses of “at least one” or “one or more.” In this text, the term “or” is used to mean non-exclusively, or unless otherwise indicated, “A or B” is used to include “A but not B,” “B but not A,” and “A and B.” In the attached claims, the terms “including” and “in which” are used as readily understandable English equivalents of the terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are in open-ended form. In other words, a system, device, article, or process containing an element, in addition to the element indicated after such term in the claim, is also considered to be within the scope of that claim. Furthermore, in the following claims, terms such as “first,” “second,” and “third” are used merely as labels and are not intended to impose any numerical requirements on their subject matter.

[0113] In various embodiments, the components, controllers, processors, units, engines, or tables described herein may, among other things, include physical circuits or firmware stored in a physical device. As used herein, “processor” means any type of computing circuit, such as any other type of processor or processing circuit, including, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or a group of processors or multicore devices.

[0114] The various embodiments described herein, as disclosed herein, include memories that utilize a vertical structure of memory cells (e.g., a NAND string of memory cells). As used herein, directional adjectives are interpreted with respect to the surface of the substrate on which the memory cells are formed (i.e., the vertical structure is interpreted as extending away from the substrate surface, the bottom end of the vertical structure is interpreted as the end closest to the substrate surface, and the top end of the vertical structure is interpreted as the end furthest from the substrate surface).

[0115] The directional adjectives used herein, such as horizontal, vertical, perpendicular, parallel, and right-angle, may refer to relative orientation and are not intended to require strict adherence to specific geometric characteristics unless otherwise specified. For example, a vertical structure used herein does not need to be strictly perpendicular to the substrate surface, but instead may be generally perpendicular to the substrate surface and may form an acute angle (e.g., 60–120 degrees) with the substrate surface.

[0116] In some embodiments described herein, different doping configurations may be applied to the source-side selection gate (SGS), control gate (CG), and drain-side selection gate (SGD), each of which may consist of polysilicon, or contain at least polysilicon, thereby allowing these layers (e.g., polysilicon) to have different etching rates when exposed to an etching solution. For example, in the process of forming monolithic pillars in a 3D semiconductor device, the SGS and CG may form depressions, while the SGD may remain in a slightly depressed or non-depressed state. Thus, these doping configurations may enable selective etching of separate layers (e.g., SGS, CG, and SGD) of a 3D semiconductor device using an etching solution (e.g., tetramethylammonium hydroxide (TMCH)).

[0117] Operating memory cells as used herein includes reading from, writing to, or erasing memory cells. An operation that brings a memory cell to an intended state is referred to herein as “programming” and may include both writing to or erasing from a memory cell (for example, a memory cell may be programmed to an erased state).

[0118] According to one or more embodiments of the present disclosure, a memory controller (e.g., a processor, controller, firmware, etc.) located inside or outside a memory device can determine (e.g., select, set, adjust, calculate, change, clear, communicate, adapt, derive, define, utilize, modify, apply, etc.) the amount of wear cycles or wear conditions (e.g., recording wear cycles, counting the operation of the memory device when a wear cycle occurs, tracking the operation of the memory device to initiate the count, evaluating the memory device characteristics corresponding to the wear conditions).

[0119] According to one or more embodiments of the present disclosure, a memory access device may be configured to provide wear cycle information to the memory device for each memory operation. A memory device control circuit network (e.g., control logic) may be programmed to compensate for changes in memory device performance corresponding to the wear cycle information. The memory device may receive the wear cycle information and, in response to this wear cycle information, determine one or more operating parameters (e.g., values, characteristics).

[0120] When an element is said to be "on" another element, "connected to" another element, or "coupled with" another element, it is understood that the element can be directly on another element, directly connected to another element, directly coupled to another element, or there may be an intervening element. In contrast, when an element is said to be "directly on" another element, "directly connected to" another element, or "directly coupled with" another element, there is no intervening element or layer. If two elements are shown in a drawing with a line connecting them, unless otherwise indicated, the two elements are either connectable or directly connectable.

[0121] Embodiments of the methods described herein can be implemented, at least in part, on a machine or computer. Some examples may include computer-readable or machine-readable media encoded with instructions that can be operated to configure an electronic device to perform the methods described in the above examples. Such implementations of the methods may include code such as microcode, assembly language code, or high-level language code. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, the code may be stored in tangible form on one or more volatile or non-volatile tangible computer-readable media during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cassettes, memory cards or memory sticks, random access memory (RAM), read-only memory (ROM), solid-state drives (SSDs), universal flash storage (UFS) devices, embedded MMC (eMMC) devices, and the like.

[0122] The above description is illustrative and not limiting. For example, the above examples (or one or more embodiments thereof) may be used in combination with one another. Other embodiments may be used by those skilled in the art when considering the above description. This is provided with the understanding that it is not to be used to interpret or limit the claims or their meaning. Also, in the embodiments for carrying out the above invention, various features may be grouped together to streamline the disclosure. This should not be construed as meaning that any disclosed features not claimed are essential to any claim. Rather, the subject matter of the invention may lie in features that are not all of a particular disclosed embodiment. Thus, the following claims are incorporated herein into embodiments for carrying out the invention, and each claim stands alone as a separate embodiment, and such embodiments may be combined with one another in various combinations or variations. The scope of the invention should be determined by referring to the claims and the entire scope of equivalents to which such claims are granted.

[0123] Other notes and examples Embodiment 1 is a method for storing data in a non-volatile memory device, the method comprising: receiving data and writing it to a plurality of memory cells of the memory device; generating a scrambler seed value for the data in response to receiving the data; scrambling the data by transforming the data using a scrambling algorithm and the seed value to generate scrambled data; encoding both the seed value and the scrambled data to create encoded data; writing the encoded data to a first plurality of memory cells on a first die of the memory device; identifying that the encoded data is to be copied to a second plurality of memory cells in the first die; and, in response to identifying that the encoded data is to be copied to a second plurality of memory cells, the method comprising copying the encoded data to the second plurality of memory cells without transferring the host data portion of the encoded data from the first die to the controller of the memory device.

[0124] In Example 2, the subject of Example 1 includes generating the seed value, which involves obtaining a random number.

[0125] In Example 3, the subject of Example 2 is extended to include the use of a hardware random number generator to obtain the random numbers.

[0126] In Example 4, the theme of Examples 2 and 3 is that the random numbers are pseudorandom numbers generated from a pseudorandom number generator.

[0127] In Example 5, the theme of Examples 1 to 4 is expanded to include the fact that the seed value is an encryption key.

[0128] In Example 6, the subject matter of Examples 1 to 5 is that the scrambling algorithm is an XOR algorithm, and scrambling the data includes performing an XOR operation on the data with a random number sequence generated by the seed value to generate the scrambled data.

[0129] In Example 7, the subject matter of Examples 1 to 6 is further expanded to include the fact that the scrambling algorithm is an encryption algorithm, and that the process of generating the scrambled data by transforming the data using the encryption algorithm and the seed value includes encrypting the data by the seed value.

[0130] In Example 8, the themes of Examples 1 to 7 include receiving a request to read the data, reading the encoded data from the second plurality of memory cells, decoding the encoded data to generate the scrambled data and the seed value, and descrambling the scrambled data with the seed value to generate the data.

[0131] Embodiment 9 is a memory device, the memory device comprising a first memory die containing a plurality of memory cells, a controller, the controller configured to perform operations including receiving data and writing it to the plurality of memory cells, generating a scrambler seed value for the data in response to receiving the data, scrambling the data by transforming the data using a scrambling algorithm and the seed value to generate scrambled data, encoding both the seed value and the scrambled data to create encoded data, causing the encoded data to be written to a first plurality of memory cells of the first die, identifying that the encoded data is to be copied to a second plurality of memory cells in the first die, and, in response to identifying that the encoded data is to be copied to the second plurality of memory cells, causing the encoded data to be copied to the second plurality of memory cells without transferring the host data portion of the encoded data from the first die to the controller of the memory device.

[0132] In Example 10, the subject of Example 9 is further expanded to include the operation of generating the seed value, which involves obtaining a random number.

[0133] In Example 11, the subject of Example 10 is further expanded to include the memory device including a hardware random number generator, and the operation of obtaining the random number including obtaining the random number from the hardware random number generator.

[0134] In Example 12, the theme of Examples 10-11 is that the random numbers are pseudorandom numbers generated from a pseudorandom number generator.

[0135] In Example 13, the theme of Examples 9 to 12 is expanded to include the fact that the seed value is an encryption key.

[0136] In Example 14, the subject matter of Examples 9 to 13 is further described by the fact that the scrambling algorithm is an XOR algorithm, and the operation of scrambling the data includes performing an XOR operation on the data with a random number sequence generated by the seed value to generate the scrambled data.

[0137] In Example 15, the subject matter of Examples 9 to 14 is further expanded to include the fact that the scrambling algorithm is an encryption algorithm, and the operation of scrambling the data and generating the scrambled data by transforming the data using the encryption algorithm and the seed value includes encrypting the data by the seed value.

[0138] In Example 16, the subject matter of Examples 9 to 15 is further expanded to include the operation of receiving a request to read the data, reading the encoded data from the second plurality of memory cells, decoding the encoded data to generate the scrambled data and the seed value, and descrambling the scrambled data with the seed value to generate the data.

[0139] Embodiment 17 is a non-temporary machine-readable medium for storing instructions, the instructions, when executed, cause a memory device to perform operations including receiving data and writing it to a plurality of memory cells of the memory device; generating a scrambler seed value for the data in response to receiving the data; scrambling the data by transforming the data using a scrambling algorithm and the seed value to generate scrambled data; encoding both the seed value and the scrambled data to create encoded data; causing the encoded data to be written to a first plurality of memory cells of the first die; identifying that the encoded data is to be copied to a second plurality of memory cells in the first die; and, in response to identifying that the encoded data is to be copied to the second plurality of memory cells, causing the encoded data to be copied to the second plurality of memory cells without transferring the host data portion of the encoded data from the first die to the controller of the memory device.

[0140] In Example 18, the subject of Example 17 is further expanded to include the operation of generating the seed value, which involves obtaining a random number.

[0141] In Example 19, the subject of Example 18 is further expanded to include the memory device including a hardware random number generator, and the operation of obtaining the random number including obtaining the random number from the hardware random number generator.

[0142] In Example 20, the subject matter of Examples 18-19 is expanded to include the fact that the random numbers are pseudorandom numbers generated from a pseudorandom number generator.

[0143] In Example 21, the theme of Examples 17-20 is that the seed value is an encryption key.

[0144] In Example 22, the subject matter of Examples 17-21 is further described by the fact that the scrambling algorithm is an XOR algorithm, and the operation of scrambling the data comprises performing an XOR operation on the data with a random number sequence generated by the seed value to produce the scrambled data.

[0145] In Example 23, the subject matter of Examples 17-22 is further expanded to include the fact that the scrambling algorithm is an encryption algorithm, and the operation of scrambling the data and generating the scrambled data by transforming the data using the encryption algorithm and the seed value includes encrypting the data by the seed value.

[0146] In Example 24, the subject matter of Examples 17-23 is further expanded to include the operation of receiving a request to read the data, reading the encoded data from the second plurality of memory cells, decoding the encoded data to generate the scrambled data and the seed value, and descrambling the scrambled data with the seed value to generate the data.

[0147] Example 25 is at least one machine-readable medium containing instructions, which, when executed by a processing circuit, cause the processing circuit to perform an operation that implements any of Examples 1 to 24.

[0148] Example 26 is an apparatus that includes means for implementing any of Examples 1 to 24.

[0149] Example 27 is a system that implements any of Examples 1 to 24.

[0150] Example 28 is a method for implementing any of Examples 1 to 24.

[0151] Example 29 is a method for storing data in a non-volatile memory device, the method comprising: receiving data and writing it to a plurality of memory cells of the memory device; generating a scrambler seed value for the data in response to receiving the data; scrambling the data by transforming the data using a scrambling algorithm and the seed value to generate scrambled data; encoding both the seed value and the scrambled data to create encoded data; writing the encoded data to a first plurality of memory cells on a first die of the memory device; identifying that the encoded data is to be copied to a second plurality of memory cells in the first die; and, in response to identifying that the encoded data is to be copied to a second plurality of memory cells, the method comprising copying the encoded data to the second plurality of memory cells without transferring the host data portion of the encoded data from the first die to the controller of the memory device.

[0152] In Example 30, the subject of Example 29 is extended to include generating the seed value by obtaining a random number.

[0153] In Example 31, the subject of Example 30 is extended to include the use of a hardware random number generator to obtain the random numbers.

[0154] In Example 32, the theme of Examples 30-31 is that the random numbers are pseudorandom numbers generated from a pseudorandom number generator.

[0155] In Example 33, the theme of Examples 29-32 is that the seed value is an encryption key.

[0156] In Example 34, the subject matter of Examples 29 to 33 is further expanded to include the fact that the scrambling algorithm is an XOR algorithm, and that scrambling the data involves performing an XOR operation on the data with a random number sequence generated by the seed value to produce the scrambled data.

[0157] In Example 35, the subject matter of Examples 29-34 is further defined as follows: the scrambling algorithm is an encryption algorithm, and the process of generating the scrambled data by transforming the data using the encryption algorithm and the seed value includes encrypting the data by the seed value.

[0158] In Example 36, the subject matter of Examples 29 to 35 includes receiving a request to read the data, reading the encoded data from the second plurality of memory cells, decoding the encoded data to generate the scrambled data and the seed value, and descrambling the scrambled data with the seed value to generate the data.

[0159] Embodiment 37 is a memory device, the memory device comprising a first memory die containing a plurality of memory cells, a controller, the controller configured to perform operations including receiving data and writing it to the plurality of memory cells, generating a scrambler seed value for the data in response to receiving the data, scrambling the data by transforming the data using a scrambling algorithm and the seed value to generate scrambled data, encoding both the seed value and the scrambled data to create encoded data, causing the encoded data to be written to a first plurality of memory cells of the first die, identifying that the encoded data is to be copied to a second plurality of memory cells in the first die, and, in response to identifying that the encoded data is to be copied to the second plurality of memory cells, causing the encoded data to be copied to the second plurality of memory cells without transferring the host data portion of the encoded data from the first die to the controller of the memory device.

[0160] In Example 38, the subject of Example 37 is further expanded to include the operation of generating the seed value, which involves obtaining a random number.

[0161] In Example 39, the subject of Example 38 is further expanded to include the memory device including a hardware random number generator, and the operation of obtaining the random number including obtaining the random number from the hardware random number generator.

[0162] In Example 40, the subject matter of Examples 38-39 is that the random numbers are pseudorandom numbers generated from a pseudorandom number generator.

[0163] In Example 41, the theme of Examples 37-40 is that the seed value is an encryption key.

[0164] In Example 42, the subject matter of Examples 37 to 41 is further described by the fact that the scrambling algorithm is an XOR algorithm, and the operation of scrambling the data includes performing an XOR operation on the data with a random number sequence generated by the seed value to generate the scrambled data.

[0165] In Example 43, the subject matter of Examples 37-42 is further expanded to include the fact that the scrambling algorithm is an encryption algorithm, and the operation of scrambling the data and generating the scrambled data by transforming the data using the encryption algorithm and the seed value includes encrypting the data by the seed value.

[0166] In Example 44, the subject matter of Examples 37-43 is further comprising the operation of receiving a request to read the data, reading the encoded data from the second plurality of memory cells, decoding the encoded data to generate the scrambled data and the seed value, and descrambling the scrambled data with the seed value to generate the data.

[0167] Embodiment 45 is a non-temporary machine-readable medium for storing instructions, the instructions, when executed, cause a memory device to perform operations including receiving data and writing it to a plurality of memory cells of the memory device; generating a scrambler seed value for the data in response to receiving the data; scrambling the data by transforming the data using a scrambling algorithm and the seed value to generate scrambled data; encoding both the seed value and the scrambled data to create encoded data; causing the encoded data to be written to a first plurality of memory cells of the first die; identifying that the encoded data is to be copied to a second plurality of memory cells in the first die; and, in response to identifying that the encoded data is to be copied to the second plurality of memory cells, causing the encoded data to be copied to the second plurality of memory cells without transferring the host data portion of the encoded data from the first die to the controller of the memory device.

[0168] In Example 46, the subject of Example 45 is further expanded to include the operation of generating the seed value, which involves obtaining a random number.

[0169] In Example 47, the subject of Example 46 is further expanded to include the memory device including a hardware random number generator, and the operation of obtaining the random number including obtaining the random number from the hardware random number generator.

[0170] In Example 48, the subject matter of Examples 46-47 is that the random numbers are pseudorandom numbers generated from a pseudorandom number generator.

[0171] In Example 49, the theme of Examples 45-48 is expanded to include the fact that the seed value is a cryptographic key.

[0172] In Example 50, the subject matter of Examples 45-49 is the same, wherein the scrambling algorithm is an XOR algorithm, and the operation of scrambling the data includes performing an XOR operation on the data with a random number sequence generated by the seed value to generate the scrambled data.

[0173] In Example 51, the subject matter of Examples 45-50 is further described by the fact that the scrambling algorithm is an encryption algorithm, and the operation of scrambling the data and generating the scrambled data by transforming the data using the encryption algorithm and the seed value includes encrypting the data by the seed value.

[0174] In Example 52, the subject matter of Examples 45-51 is further expanded to include the operation of receiving a request to read the data, reading the encoded data from the second plurality of memory cells, decoding the encoded data to generate the scrambled data and the seed value, and descrambling the scrambled data with the seed value to generate the data.

[0175] Example 53 is at least one machine-readable medium containing instructions, which, when executed by a processing circuit, cause the processing circuit to perform an operation that implements any of Examples 29 to 52.

[0176] Example 54 is an apparatus that includes means for implementing any of Examples 29 to 52.

[0177] Example 55 is a system that implements any of Examples 29 to 52.

[0178] Example 56 is a method for implementing any of Examples 29 to 52.

[0179] Embodiment 57 is a method for performing a copyback operation on a memory device, the method comprising: in the memory controller of the memory device, receiving encoded metadata from a memory die via an internal communication interface of the memory device in response to the commencement of a copyback operation, wherein host data corresponding to the metadata is not transmitted by the memory die via the internal communication interface; decoding the encoded metadata to generate decoded metadata; descrambling the decoded metadata using a key value to generate descrambled metadata, wherein the key value is stored as part of the decoded metadata; updating the descrambled metadata to generate updated metadata; scrambling the updated metadata with the key value to generate scrambled updated metadata; encoding the scrambled updated metadata to generate encoded updated metadata; and transmitting the encoded updated metadata to the memory die, wherein the encoded updated metadata is combined with encoded host data and written to a new location on the memory die.

[0180] In Example 58, the subject of Example 57 is extended to include updating the descrambled metadata, which includes updating the write temperature.

[0181] In Example 59, the subject matter of Examples 57-58 is extended to include updating the descrambled metadata, which includes updating the write time.

[0182] In Example 60, the subject matter of Examples 57-59 is extended to include, in the memory die of the memory device, identifying an internal copyback command for a first memory location; reading the first memory location to obtain the encoded metadata and the encoded host data; storing the encoded host data in a memory buffer on the memory die; transmitting the encoded metadata to the memory controller; receiving the encoded and updated metadata from the memory controller; and writing the encoded and updated metadata, together with the encoded host data stored in the memory buffer, to the new location on the memory die.

[0183] In Example 61, the subject matter of Examples 57-60 is extended to include descrambling the decoded metadata using the key value to generate descrambled metadata, which involves applying an XOR operation to the decoded metadata and the key value.

[0184] In Example 62, the subject matter of Examples 57-61 is expanded to include the encoded metadata including encoding information used for decoding.

[0185] In Example 63, the subject of Example 62 is further expanded to include the encoding information having at least one parity bit.

[0186] In Example 64, the subject matter of Examples 62-63 is expanded to include the fact that the encoding information of the encoded metadata is different from the second encoding information contained in the encoded host data corresponding to the host data.

[0187] Embodiment 65 is a memory device including a memory controller, the memory controller is configured to perform operations including receiving encoded metadata from a memory die via an internal communication interface of the memory device in response to the initiation of a copyback operation, wherein host data corresponding to the metadata is not transmitted by the memory die via the internal communication interface; generating by decoding the encoded metadata to generate decoded metadata; generating by descrambling the decoded metadata using a key value to generate descrambled metadata, wherein the key value is stored as part of the decoded metadata; updating the descrambled metadata to generate updated metadata; scrambling the updated metadata with the key value to generate scrambled updated metadata; encoding the scrambled updated metadata to generate encoded updated metadata; and transmitting the encoded updated metadata to the memory die, wherein the encoded updated metadata is combined with encoded host data and written to a new location on the memory die.

[0188] In Example 66, the subject of Example 65 is expanded to include the operation of updating the descrambled metadata, which includes updating the write temperature.

[0189] In Example 67, the subject matter of Examples 65-66 is expanded to include the operation of updating the descrambled metadata, which includes updating the write time.

[0190] In Example 68, the subject of Examples 65-67 includes the memory die, the memory die includes a processor, the processor is configured to perform operations including: identifying an internal copyback command for a first memory location; reading the first memory location to obtain the encoded metadata and the encoded host data; storing the encoded host data in a memory buffer on the memory die; transmitting the encoded metadata to the memory controller; receiving the encoded and updated metadata from the memory controller; and writing the encoded and updated metadata, together with the encoded host data stored in the memory buffer, to the new location on the memory die.

[0191] In Example 69, the subject matter of Examples 65-68 is further expanded to include the operation of using the key value to descramble the decoded metadata and generate descrambled metadata, wherein the operation involves applying an XOR operation to the decoded metadata and the key value.

[0192] In Example 70, the subject matter of Examples 65-69 is further described by the fact that the encoded metadata includes encoding information used for decoding.

[0193] In Example 71, the subject of Example 70 is further expanded to include the fact that the encoded information has at least one parity bit.

[0194] In Example 72, the subject matter of Examples 70-71 is expanded to include the fact that the encoding information of the encoded metadata is different from the second encoding information contained in the encoded host data corresponding to the host data.

[0195] Embodiment 73 is a non-temporary machine-readable medium for storing instructions, wherein when the instruction is executed by the memory device, the instruction receives encoded metadata from the memory die via the internal communication interface of the memory device in response to the start of a copyback operation, wherein host data corresponding to the metadata is not transmitted by the memory die via the internal communication interface; the instruction receives; the encoded metadata is decoded to produce decoded metadata; and the descrambled metadata is descrambled using a key value to produce descrambled metadata, wherein the key value is decoded The memory device is made to perform an operation which includes generating, updating the descrambled metadata to generate updated metadata, scrambling the updated metadata with the key value to generate scrambled updated metadata, encoding the scrambled updated metadata to generate encoded updated metadata, and transmitting the encoded updated metadata to the memory die, wherein the encoded updated metadata is combined with encoded host data and written to a new location on the memory die.

[0196] In Example 74, the subject of Example 73 is further expanded to include the operation of updating the descrambled metadata, which includes updating the write temperature.

[0197] In Example 75, the subject matter of Examples 73-74 is expanded to include the operation of updating the descrambled metadata, which includes updating the write time.

[0198] In Example 76, the subject matter of Examples 73-75 is further comprising the operation of identifying an internal copyback command for a first memory location on the memory die, reading the first memory location to obtain the encoded metadata and the encoded host data, storing the encoded host data in a memory buffer on the memory die, transmitting the encoded metadata to the memory controller, receiving the encoded and updated metadata from the memory controller, and writing the encoded and updated metadata together with the encoded host data stored in the memory buffer to the new location on the memory die.

[0199] Embodiment 77 is at least one machine-readable medium containing an instruction, which, when executed by a processing circuit, causes the processing circuit to perform an operation that implements any of Embodiments 57 to 76.

[0200] Example 78 is an apparatus that includes means for implementing any of Examples 57 to 76.

[0201] Example 79 is a system that implements any of Examples 57 to 76.

[0202] Example 80 is a method for implementing any of Examples 57 to 76.

Claims

1. A method for performing an internal copyback operation on a memory device, Reading encoded metadata and encoded host data from a first memory location on the memory die, The encoded host data is stored in the page buffer on the memory die, Without transferring the encoded host data to the controller of the memory device, the encoded metadata is transferred from the memory die to the controller via an internal communication interface. In the aforementioned controller, Decoding the encoded metadata to generate the decoded metadata, The decoded metadata is descrambled using the seed value, and the descrambled metadata is generated. Determine whether to update the descrambled metadata, In response to the determination to update the descrambled metadata, the descrambled metadata is updated to generate updated metadata. The update metadata is scrambled using the seed value to generate scrambled update metadata, Encoding the scrambled update metadata to generate encoded update metadata, Transferring the encoded update metadata to the memory die, In the memory die, The encoded update metadata is combined with the encoded host data stored in the page buffer. The combined encoded update metadata and encoded host data are written to a second memory location on the memory die. A method that includes this.

2. The method according to claim 1, wherein the metadata includes at least one of the following associated with the encoded host data: write temperature, write time, write voltage, or write verification indicator.

3. The method according to claim 1, wherein decoding the encoded metadata includes applying error-correcting coding (ECC) decoding using parity bits stored with the encoded metadata.

4. The method according to claim 1, wherein the seed value includes a random number generated by a seed generator in the controller, and the seed value is stored together with the encoded metadata and the encoded host data in an unscrambled state.

5. The method according to claim 1, wherein each of the decoded metadata and the updated metadata is performed by applying an XOR operation using a random number sequence generated from the seed value.

6. The method according to claim 1, wherein updating the descrambled metadata includes updating at least one of the following: a write temperature field having the current temperature of the memory device, or a write time field having the current time.

7. The aforementioned page buffer includes volatile memory on the memory die, The method according to claim 1, wherein the encoded host data remains stored in the page buffer from the time the first memory location is read until the combined encoded update metadata and encoded host data are written to the second memory location.

8. The method according to claim 1, wherein determining whether to update the descrambled metadata includes evaluating one or more rules based on the current memory device state and the descrambled metadata.

9. The method according to claim 1, further comprising, in response to a determination not to update the descrambled metadata, rescrambling and re-encoding the metadata before writing the encoded host data together to the second memory location.

10. The method according to claim 1, wherein the internal communication interface includes an I / O bus between the memory die and the controller.

11. A memory device for performing internal copyback operations, A memory die including a first memory location, a second memory location, and a page buffer, Internal communication interface, Includes a controller connected to the memory die via the internal communication interface, The controller includes a processing circuit, The aforementioned processing circuit is The encoded metadata and seed value are received from the memory die, and the encoded host data read from the first memory location is not transferred to the controller but is stored in the page buffer on the memory die. The encoded metadata is decoded to generate the decoded metadata. Using the aforementioned seed value, the decoded metadata is descrambled to generate the descrambled metadata. Determine whether to update the descrambled metadata. In response to the determination to update the descrambled metadata, the descrambled metadata is updated to generate updated metadata. The update metadata is scrambled using the seed value to generate scrambled update metadata. The scrambled update metadata is encoded to generate encoded update metadata. A memory device configured to transfer the encoded update metadata to the memory die in combination with the encoded host data stored in the page buffer, in order to write the encoded update metadata to the second memory location.

12. The memory device according to claim 11, wherein the metadata includes at least one of the following associated with the encoded host data: write temperature, write time, write voltage, or write verification indicator.

13. The memory device according to claim 11, wherein the processing circuit is configured to decode the encoded metadata by applying error correction coding (ECC) decoding using parity bits stored together with the encoded metadata.

14. The controller further includes a seed generator configured to generate the seed value as a random number, The memory device according to claim 11, wherein the seed value is stored in the first memory location in an unscrambled state together with the encoded metadata and the encoded host data.

15. The memory device according to claim 11, wherein the processing circuit is configured to scramble the decoded metadata and the updated metadata by applying an XOR operation using a random number sequence generated from the seed value.

16. The memory device according to claim 11, wherein the processing circuit is configured to update the descrambled metadata by updating at least one of a write temperature field having the current temperature of the memory device or a write time field having the current time.

17. The aforementioned page buffer includes volatile memory on the memory die, The memory device according to claim 11, wherein the encoded host data remains stored in the page buffer from the time the first memory location is read until the combined encoded update metadata and encoded host data are written to the second memory location.

18. The memory device according to claim 11, wherein the processing circuit is configured to determine whether to update the descrambled metadata by evaluating one or more rules based on the current memory device state and the descrambled metadata.

19. The memory device according to claim 11, wherein the processing circuit is further configured to re-scramble and re-encode the metadata before writing the encoded host data to the second memory location in response to a determination that the de-scrambled metadata is not to be updated.

20. The memory device according to claim 11, wherein the internal communication interface includes an I / O bus between the memory die and the controller.

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