Semiconductor equipment

Abstract

To provide a semiconductor device with minimal variation in transistor characteristics. [Solution] A semiconductor device having a transistor, the transistor having a first insulator 224, first oxides 230a and 230b on the first insulator, first conductors 242a and second conductors 242b on the first oxide, second oxide 230c disposed between the first and second conductors, second insulator 250 on the second oxide, and third conductor 260 on the second insulator, wherein the upper surface of the first oxide in the region 234 overlapping with the third conductor is lower than the upper surface of the first oxide in the regions 231a and 231b overlapping with the first and second conductors, the first oxide has a curved surface between its side surface and upper surface in the region overlapping with the third conductor, and the radius of curvature of the curved surface is 1 nm or more and 15 nm or less.

Description

Technical Field

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, and an electronic device. Further, one aspect of the present invention relates to a method for manufacturing a semiconductor device. Further, one aspect of the present invention relates to a semiconductor wafer and a module.

[0002] In the present specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices are one aspect of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, and electronic devices may be said to have semiconductor devices in some cases.

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in the present specification and the like relates to an article, a method, or a manufacturing method. Further, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

Background Art

[0004] Techniques for constructing transistors using semiconductor thin films formed on substrates having insulating surfaces have attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials. )]]

[0005] In oxide semiconductors, CAAC (c-axis ali) is neither single crystal nor amorphous. gned crystalline) structure and nc (nanocrystalline) structure A structure has been found (see Non-Patent Documents 1 and 2).

[0006] Non-patent documents 1 and 2 describe using an oxide semiconductor having a CAAC structure. The technology for manufacturing a lunger has been disclosed. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Overview of the project] [Problems that the invention aims to solve]

[0008] One aspect of the present invention provides a semiconductor device with less variation in transistor characteristics. This is one of the challenges. Furthermore, one aspect of the present invention provides a semiconductor device with a large on-current. This is one of the challenges. Furthermore, one aspect of the present invention provides a semiconductor device having good electrical characteristics. One of the objectives is to provide a solution that enables miniaturization or high integration. One of the objectives is to provide a semiconductor device with good reliability. One of the objectives is to provide a good semiconductor device. Furthermore, one aspect of the present invention is to provide a low-power consumption device. One of our objectives is to provide semiconductor devices that can withstand high power.

[0009] Furthermore, the description of these problems does not preclude the existence of other problems. One approach does not require that all of these issues be resolved. The title will become clear from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the drawings, claims, etc. [Means for solving the problem]

[0010] One aspect of the present invention is a semiconductor device having a transistor, wherein the transistor is a first An insulator, a first oxide on the first insulator, and a first conductor on the first oxide, second A conductor, and a second oxide disposed between the first conductor and the second conductor. , comprising a second insulator on a second oxide and a third conductor on the second insulator, the third The upper surface of the first oxide in the region overlapping with the conductor is in the region overlapping with the first conductor. Below the upper surface of the first oxide, the first oxide overlaps with the third conductor in the region where it is located. It has a curved surface between the side and top surfaces, and the radius of curvature of the curved surface is between 1 nm and 15 nm. .

[0011] In the semiconductor device described above, when the lower surface of the first insulator is used as a reference, the third conductor overlaps The height of the upper surface of the first oxide in the region and the upper surface of the first oxide in the region overlapping with the first conductor The difference between the height of and is preferably between 1 nm and 5 nm.

[0012] Furthermore, in the above semiconductor device, in the channel width direction of the transistor, the first conductive The length of the underside of the first oxide in the region overlapping with the body, and the length of the first oxide in the region overlapping with the third conductor Preferably, half of the difference between the length of the bottom surface of the object and the length of the object is between 2 nm and 10 nm.

[0013] Furthermore, in the above semiconductor device, the transistor comprises a third oxide and a fourth oxide, The third oxide is positioned between the first oxide and the first conductor, and the fourth oxide The material is placed between the first oxide and the second conductor, in the direction of the transistor's channel length. In this case, the lower surface of the second oxide is lower than the lower surface of the third oxide and the lower surface of the fourth oxide. It is preferable that the value is also low.

[0014] Another aspect of the present invention is a semiconductor device having a plurality of transistors, wherein the plurality of transistors The inverter comprises a first insulator, a first oxide on the first insulator, and a first oxide on the first oxide. A conductor, a second conductor, and a device disposed between the first and second conductors. A second oxide, a second insulator on the second oxide, and a third conductor on the second insulator. The upper surface of the first oxide in the region overlapping with the third conductor is the same as the region overlapping with the first conductor. Lower than the upper surface of the first oxide in the region, the first oxide overlaps with the third conductor in the region. It has a curved surface between the side and the top surface, and in the Id-Vg characteristics of multiple transistors, Vs The standard deviation σ of h is less than 60mV.

[0015] In the above semiconductor device, the channel length of the multiple transistors is 40 nm to 80 nm. The following conditions apply, and the channel width of multiple transistors is between 40nm and 80nm. This is preferable.

[0016] Furthermore, in the above semiconductor device, the radius of curvature of the curved surface is 1 nm or more and 15 nm or less. , is preferable.

[0017] Another aspect of the present invention is a semiconductor device having a transistor, wherein the transistor is A first insulator, a first oxide on the first insulator, and a first conductor on the first oxide, A second conductor, and a second oxide disposed between the first and second conductors. A material, a second insulator on a second oxide, a third conductor on the second insulator, and a first conductive The second is positioned in contact with the upper surface of the body, the upper surface of the second conductor, and a portion of the side surface of the first oxide. It has three insulators and overlaps with the first conductor in the channel width direction of the transistor. The length of the underside of the first oxide in the region is the length of the underside of the first oxide in the region that overlaps with the third conductor. Larger than the length, the first oxide has sides and top surfaces in the region where it overlaps with the third conductor. It has a curved surface between the first oxide and the element M (where M is gallium, it The material has (aluminum or tin) and zinc, and the third insulator is an impurity of the first oxide. On the side surface of the first oxide in the region that contains the element and overlaps with the third conductor, with respect to element M The concentration ratio of the element is such that, on the surface of the first oxide in the region overlapping with the first conductor, element M It is smaller than the elemental concentration ratio relative to [the other element].

[0018] In the above semiconductor device, the element of the third insulator is aluminum. preferable.

[0019] Furthermore, in the above semiconductor device, the radius of curvature of the curved surface is 1 nm or more and 15 nm or less. , is preferable. [Effects of the Invention]

[0020] According to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics is provided. This is possible. Furthermore, according to one aspect of the present invention, a semiconductor device with a large on-current is provided. This is possible. Furthermore, according to one aspect of the present invention, a semiconductor device having good electrical characteristics is provided. This is possible. Furthermore, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated is possible. This can provide a semiconductor device with good reliability according to one aspect of the present invention. It can be provided. Furthermore, according to one aspect of the present invention, a low-power semiconductor device can be provided. It is possible.

[0021] Furthermore, the description of these effects does not preclude the existence of other effects. One embodiment does not need to have all of these effects. Other effects are described in the specification. This will become clear from the description in the drawings, claims, etc., and the specification, drawings, claims From descriptions such as these, it is possible to extract other effects. [Brief explanation of the drawing]

[0022] [Figure 1] Figure 1A is a top view of a semiconductor device according to one aspect of the present invention. Figures 1B to 1D are cross-sectional views of a semiconductor device according to one aspect of the present invention. [Figure 2] Figure 2 is a cross-sectional view of a semiconductor device according to one aspect of the present invention. [Figure 3] Figures 3A and 3B are perspective views of a semiconductor device according to one embodiment of the present invention. [Figure 4] Figure 4A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 4B to 4D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 5]Figure 5A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 5B to 5D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 6] Figure 6A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 6B to 6D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 7] Figure 7A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 7B to 7D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 8] Figure 8A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 8B to 8D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 9] Figure 9A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 9B to 9D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 10] Figure 10A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 10B to 10D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 11] Figure 11A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 11B to 11D are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 12] Figure 12A is a top view of a semiconductor device according to one aspect of the present invention. Figures 12B to 12D are cross-sectional views of a semiconductor device according to one aspect of the present invention. [Figure 13] Figures 13A and 13B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 14] Figure 14 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. [Figure 15] Figure 15 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. [Figure 16] Figures 16A and 16B are block diagrams showing an example of the configuration of a storage device according to one aspect of the present invention. [Figure 17] Figures 17A to 17H are circuit diagrams showing an example of the configuration of a storage device according to one aspect of the present invention. [Figure 18] Figures 18A and 18B are schematic diagrams of a semiconductor device according to one aspect of the present invention. [Figure 19] Figures 19A to 19E are schematic diagrams of a storage device according to one aspect of the present invention. [Figure 20] Figures 20A to 20H show an electronic device according to one embodiment of the present invention. [Figure 21] Figure 21 shows a normal probability plot of the Shift value of the sample according to the example. [Figure 22] Figure 22 shows the stress time dependence of ΔVsh in the +GBT stress test according to the example. [Figure 23] Figure 23A shows the stress time dependence of Ion in the +GBT stress test according to the example. Figure 23B shows the stress time dependence of S value in the +GBT stress test according to the example. Figure 23C shows the stress time dependence of μFE in the +GBT stress test according to the example. [Figure 24] Figure 24 shows the Id-Vg characteristics of a transistor according to an embodiment. [Figure 25] Figure 25A shows the normal probability plot of Vsh in the example. Figure 25B shows the normal probability plot of Ion in the example. Figure 25C shows the Vbg dependence of Vsh in the example. [Figure 26] Figure 26A shows ΔVsh in the +GBT stress test according to the example. Figure 26(B) shows the stress time dependence of the S value according to the example. [Modes for carrying out the invention]

[0023] The embodiments will be described below with reference to the drawings. However, many embodiments are described. It can be implemented in different ways, without deviating from its purpose and scope. It will be readily apparent to those skilled in the art that the form and details can be varied in various ways. Therefore, the present invention shall not be construed as being limited to the contents described in the following embodiments.

[0024] Furthermore, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. This may be the case. Therefore, it is not necessarily limited to that scale. Note that the drawing is an ideal This is a schematic example and is not limited to the shapes or values ​​shown in the diagram. For example, In the actual manufacturing process, processes such as etching can cause layers and resist masks to be altered as intended. Although there may be some reduction in volume, this may not be reflected in the diagram for the sake of easier understanding. In drawings, the same reference numeral is used for identical parts or parts having similar functions across different drawings. It is used in common, and explanations of its repetition may be omitted. Also, in cases where similar functions are referred to... In some cases, the hatch patterns are the same, and no specific designation is assigned.

[0025] Furthermore, the invention is made easier to understand, especially in top views (also called "plan views") and perspective views. Therefore, the description of some components may be omitted. Also, some hidden lines and other markings may be omitted. The word "included" may be omitted in some cases.

[0026] Furthermore, the ordinal numbers used in this specification, etc., as "1st," "2nd," etc., are used for convenience only. It does not indicate the order of processes or stacking order. Therefore, for example, "the first" should be written as "the second". This can be explained by appropriately replacing it with "of" or "the third of," etc. The ordinal numbers described herein do not correspond to the ordinal numbers used to specify one aspect of the present invention. There are cases where this is the case.

[0027] Furthermore, in this specification, phrases indicating placement such as "above" and "below" refer to the relative positions of the components. The positional relationships are used for convenience in explaining them by referring to the diagram. Also, the positions of the components are shown. The relationships change as appropriate depending on the direction in which each component is described. Therefore, in the specification... The terms explained are not limited to those used in the text; they can be appropriately rephrased depending on the context.

[0028] For example, in this specification, it is explicitly stated that X and Y are connected. In this case, X and Y are electrically connected, and X and Y are functionally connected. The cases disclosed in this specification, etc., include cases where X and Y are directly connected. Therefore, it is limited to predetermined connection relationships, for example, connection relationships shown in a diagram or text. Furthermore, connections other than those shown in the diagram or text are also disclosed in the diagram or text. Let X and Y be the objects (e.g., devices, elements, circuits, wiring, electrodes, terminals). (Conductive film, layer, etc.)

[0029] Furthermore, in this specification, the term "transistor" includes a gate, a drain, and a source. It is an element having at least three terminals. And, drain (drain terminal, drain Between the drain region (or drain electrode) and the source (source terminal, source region, or source electrode) It has a region where channels are formed (hereinafter also called the channel-forming region), This design allows current to flow between the source and drain through a flannel-formed region. In this specification, the channel-forming region refers to the region through which electric current primarily flows.

[0030] Furthermore, the source and drain functions may differ when using transistors with different polarities, or when the circuit The direction of the current may change during operation, which can cause the current to switch positions. In detailed documents, the terms "source" and "drain" may be used interchangeably. ru.

[0031] Note that channel length refers to, for example, the length of the semiconductor (or transistor) in a top view of a transistor. When the inverter is ON, the part of the semiconductor through which current flows and the gate electrode overlap each other. In the region or channel-forming region, the source (source region or source electrode) and This refers to the distance between the drain (drain region or drain electrode) and the other element. In a zista, the channel length is not necessarily the same across all regions. That is, one The channel length of the transistor may not be fixed to a single value. Therefore, this specification So, the channel length is any one value, maximum value, minimum value, or This will be the average value.

[0032] Channel width refers to, for example, the top view of a transistor, the semiconductor (or transistor) The region where the gate electrode and the part of the semiconductor through which current flows when the gate electrode is ON overlap each other. Channels in a region or channel-forming region, perpendicular to the channel length direction. This refers to the length of the formation region. Note that in a single transistor, the channel width encompasses the entire region. They do not necessarily take the same value. In other words, the channel width of a single transistor is a single value. It may not be fixed. Therefore, in this specification, the channel width is defined as the channel formation region. This is one of the values, the maximum value, the minimum value, or the average value.

[0033] In this specification, depending on the transistor structure, channel formation may actually occur. The channel width in the region (hereinafter also referred to as the "effective channel width") and the transition The channel width shown in the top view of the stylus (hereinafter also referred to as the "apparent channel width") is as follows. ) and may differ. For example, when the gate electrode covers the side of the semiconductor, the effective ch When the channel width becomes larger than the apparent channel width, and its effect can no longer be ignored. For example, in a transistor that is very small and whose gate electrode covers the side of the semiconductor, the semiconductor In some cases, the proportion of channel-forming regions formed on the sides may increase. In such cases, the apparent The effective channel width will be larger than the channel width shown above.

[0034] In such cases, it can be difficult to estimate the effective channel width through actual measurements. For example, in order to estimate the effective channel width from the design value, the shape of the semiconductor is known. A certain assumption is necessary. Therefore, if the shape of the semiconductor is not precisely known, the effective It is difficult to accurately measure channel width.

[0035] In this specification, when simply referred to as "channel width," it refers to the apparent channel width. There is. Or, in this specification, when simply referred to as channel width, it means effective channel It can refer to width. Note that it can also refer to channel length, channel width, effective channel width, or apparent width. Channel width and other parameters can be determined by analyzing cross-sectional TEM images, etc. can.

[0036] Furthermore, semiconductor impurities refer to components other than the main components that make up the semiconductor, for example, concentrated Elements with a concentration of less than 0.1 atomic percent are considered impurities. The presence of impurities can, for example, lead to... In some cases, this can lead to an increase in the defect level density of semiconductors or a decrease in crystallinity. If the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, oxide semiconductors Other components besides the main component include transition metals, such as hydrogen, lithium, sodium, silicon, These include boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen vacancies (V) in oxide semiconductors. O :oxygen va In some cases, cancy (also known as cancy) may form.

[0037] In this specification, silicon oxidnitride is defined as having a composition that contains more oxygen than nitrogen. It has a high content of [something]. Also, silicon nitride oxide, in terms of its composition, has more oxygen than [something]. It has a high nitrogen content.

[0038] Furthermore, in this specification, the term "insulator" shall be replaced with "insulating film" or "insulating layer." It is possible to replace the term "conductor" with "conductive film" or "conductive layer." This is possible. Also, the term "semiconductor" can be replaced with "semiconductor film" or "semiconductor layer." can.

[0039] Furthermore, in this specification, "parallel" means that two straight lines have an angle of -10 degrees or more and 10 degrees or less. This refers to a state where objects are arranged in degrees. Therefore, it also includes cases where the angle is between -5 degrees and 5 degrees. Furthermore, "approximately parallel" refers to a state where two straight lines are positioned at an angle of -30 degrees or more and 30 degrees or less. This refers to a straight line. Furthermore, "perpendicular" means that two straight lines are positioned at an angle of 80 degrees or more and 100 degrees or less. This refers to a state where something is perpendicular. Therefore, it also includes cases where the angle is between 85 degrees and 95 degrees. "A straight line" refers to a state in which two straight lines are positioned at an angle between 60 degrees and 120 degrees.

[0040] In this specification, metal oxide refers to metal in a broad sense. It is an oxide. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). . ), oxide semiconductor (also called Oxide Semiconductor or simply OS) They are classified into categories such as . ) For example, when a metal oxide is used in the semiconductor layer of a transistor, The metal oxide in question is sometimes referred to as an oxide semiconductor. Therefore, it is sometimes described as an OS transistor. In such cases, it can be rephrased as a transistor having a metal oxide or oxide semiconductor. It is possible.

[0041] Furthermore, in this specification, normally off means not applying a potential to the gate, or When the gate is given a ground potential, the amount of drape flowing through the transistor per 1 μm of channel width is The current is 1 × 10 at room temperature. -20 A or less, 1 × 10 at 85℃ -18 Below A , or 1 × 10 at 125℃ -16 This means being less than or equal to A.

[0042] (Embodiment 1) In this embodiment, a semiconductor device having a transistor 200 according to one aspect of the present invention Let me explain with an example.

[0043] <Example of semiconductor device configuration> Figures 1A to 1D are top and cross-sectional views of a semiconductor device having a transistor 200. Yes. Figure 1A is a top view of the semiconductor device. Figures 1B to 1D are also shown. This is a cross-sectional view of the body apparatus. Here, Figure 1B shows the area indicated by the dashed line A1-A2 in Figure 1A. This is a cross-sectional view, and also a cross-sectional view of transistor 200 in the channel length direction. Also, Figure 1C is Figure 1A shows a cross-sectional view of the area indicated by the dashed line A3-A4, and the channel of transistor 200. This is also a cross-sectional view in the width direction of the panel. Furthermore, Figure 1D shows the section indicated by the dashed line A5-A6 in Figure 1A. This is a cross-sectional view of the position. Note that in the top view of Figure 1A, some elements have been omitted for clarity. Yes, they are.

[0044] A semiconductor device according to one aspect of the present invention comprises an insulator 212 on a substrate (not shown) and an insulator 212 The insulator 214 above, the transistor 200 on the insulator 214, and the transistor 200 above Insulator 280, insulator 282 on insulator 280, insulator 283 on insulator 282, It has an insulator 274 on an insulator 283 and an insulator 281 on an insulator 274. 212, insulator 214, insulator 280, insulator 282, insulator 283, insulator 274, o The insulator 281 functions as an interlayer film. It is also electrically connected to the transistor 200. , having a conductor 240 (conductor 240a and conductor 240b) that functions as a plug. Furthermore, an insulator 241 (insulator 24) is placed in contact with the side surface of the conductor 240 which functions as a plug. 1a, and insulator 241b) are provided. Also, on the insulator 281 and conductor 24 On 0, there is a conductor 246 (conductor 2) which is electrically connected to the conductor 240 and functions as wiring. 46a and conductor 246b are provided.

[0045] Also, insulator 254, insulator 280, insulator 282, insulator 283, insulator 274, An insulator 241a is provided in contact with the inner wall of the opening of the insulator 281, and on the side of the insulator 241a A first conductive element of the conductive material 240a is provided in contact with the surface, and further inside is a second conductive element of the conductive material 240a. Two conductive materials are provided. In addition, insulators 254, 280, 282, and an insulating material are provided. The insulator 241b is provided in contact with the inner wall of the opening of the body 283, the insulator 274, and the insulator 281. The first conductor of the conductor 240b is provided in contact with the side surface of the insulator 241b, and A second conductor, the conductor 240b, is provided inside. Here, the upper surface of the conductor 240 The height of the transistor and the height of the top surface of the insulator 281 can be made to be approximately the same. Regarding the configuration in which the first conductor and the second conductor of the conductor 240 are laminated: Although shown, the present invention is not limited thereto. For example, the conductor 240 may be a single layer, Alternatively, it may be configured as a laminated structure of three or more layers. In some cases, ordinal numbers are assigned to distinguish between elements based on their order of formation.

[0046] [Transistor 200] As shown in Figures 1A to 1D, the transistor 200 is located on the insulator 214. 6 and a conductor 205 (conductor 205a, o) arranged to be embedded in the insulator 216. The conductor 205b), the insulator 222 on the insulator 216, and the insulator 222 on the conductor 205, An insulator 224 on the edge body 222, an oxide 230a on the insulator 224, and an oxide 230a Oxide 230b, conductor 242a, conductor 242b on oxide 230b, and oxidation Material 230c, an insulator 250 on the oxide 230c, and an oxide 2 located on the insulator 250. The conductor 260 (conductor 260a and conductor 260b) overlaps with 30c, and the insulator 22 Part of the top surface of 4, part of the side surface of oxide 230a, part of the side surface of oxide 230b, conductor 2 The side surface of 42a, the top surface of conductor 242a, the side surface of conductor 242b, and the conductor 242b It has an insulator 254 that is in contact with the upper surface. The oxide 230c is on the side surface of the insulator 254. , it is in contact with the side surface of conductor 242a and the side surface of conductor 242b, respectively. Here, Figure 1B As shown, the upper surface of the conductor 260 is the upper surface of the insulator 250 and the upper surface of the oxide 230c. They are arranged in roughly the same order as the conductor 260, the insulator 250, and the oxide. It is in contact with the upper surfaces of 230c and the insulator 280.

[0047] The insulators 280 and 254 are provided with openings that reach the oxide 230b. The oxide 230c, the insulator 250, and the conductor 260 are arranged within the opening. Furthermore, in the channel length direction of transistor 200, conductor 242a and conductor 242 A conductor 260, an insulator 250, and an oxide 230c are provided between b. 250 has a region that overlaps with the side surface of the conductor 260 and a region that overlaps with the bottom surface of the conductor 260. It possesses. Furthermore, in the region overlapping with oxide 230b, oxide 230c is oxide 230 The region in contact with b, the region overlapping with the side surface of the conductor 260 via the insulator 250, and the insulator 2 It has a region that overlaps with the bottom surface of the conductor 260 via 50.

[0048] Transistor 200 contains an oxide 230 (oxide 230a, oxide) including a channel formation region. In material 230b and oxide 230c), a metal oxide (hereinafter referred to as oxide) that functions as a semiconductor is added. It is preferable to use a material semiconductor (also called a solid semiconductor).

[0049] Furthermore, metal oxides that function as semiconductors have a band gap of 2 eV or more, preferably It is preferable to use gold with a band gap of 2.5 eV or higher. By using a specific oxide, the off-current of the transistor can be reduced.

[0050] Transistors using metal oxides in the channel formation region exhibit leakage current in the non-conductive state. Because the current is extremely low, it is possible to provide semiconductor devices with low power consumption. Also, metal oxides are Because it can be formed using methods such as puttering, transients can be used to form transistors in highly integrated semiconductor devices. It can be used in sta.

[0051] For example, In-M-Zn, which has indium, element M, and zinc as oxide 230. Oxides (elements M include aluminum, gallium, yttrium, tin, copper, vanadium, and beryllium) Rium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, ra Tantalum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium It is preferable to use one or more metal oxides selected from among others. For 230, In-Ga oxide or In-Zn oxide may be used.

[0052] Oxide 230 consists of oxide 230a placed on the insulator 224 and oxide 230a The oxide 230b is placed on top, and the oxide 230b is placed on top of the oxide 230b, and at least a portion of it is acid It is preferable to have oxide 230c in contact with the upper surface of oxide 230b. b has oxide 230a below it, so the structure formed below oxide 230a Furthermore, the diffusion of impurities into oxide 230b can be suppressed. Having oxide 230c, from structures formed above oxide 230c, This can suppress the diffusion of impurities into oxide 230b.

[0053] In transistor 200, oxide 230 consists of oxide 230a, oxide 230b, The present invention is not limited to a configuration in which three layers of oxide 230c are stacked. It is not something that can be done. For example, a single layer of oxide 230b, and oxide 230a and oxide 230b A two-layer structure, a two-layer structure of oxide 230b and oxide 230c, or a laminated structure of four or more layers is provided. The configuration may be such that oxide 230a, oxide 230b, and oxide 230c are each It may have a layered structure.

[0054] Furthermore, oxide 230a and oxide 230b, and oxide 230b and oxide 230c are oxygen-free. It is preferable that the oxide 230a and acid Defect levels at the interface with oxide 230b and at the interface between oxide 230b and oxide 230c The interfacial density can be reduced. Therefore, the influence of interfacial scattering on carrier conduction is small. As a result, transistor 200 can obtain a large on-current and high frequency characteristics. ru.

[0055] Conductors 242 (conductors 242a and 242b) are provided on the oxide 230b. Conductors 242a and 242b are the saws of transistor 200, respectively. It functions as a drain electrode or a drain electrode.

[0056] The conductor 260 has a conductor 260a and a conductor 260b, and the bottom surface of the conductor 260b And a conductor 260a is positioned to wrap around the sides. The conductor 260 is transistor 2 It functions as the first gate (also called the top gate) electrode of 00.

[0057] Figure 2 shows an enlarged cross-sectional view of a portion of transistor 200 shown in Figure 1B. As shown, the oxide 230 functions as a channel formation region for the transistor 200. Region 234 and region 231 (region 231a) which functions as a source region or drain region. , and region 231b) and . Region 231 has a high carrier concentration and low resistance. This is the region. Also, region 231 may include a part of the low-resistance region mentioned above. Region 234 is a region with a lower carrier concentration than region 231. At least a portion of region 231b, and at least a portion of region 231b, are conductors 242a, It also has a region that is in contact with the conductor 242b.

[0058] In Figure 2, regions 231 and 234 are formed in oxide 230b. The configuration is shown, but is not limited to this; for example, region 231 or region 234 These may be formed in oxide 230a and oxide 230b, or oxide 230b and It may be formed on oxide 230c, or on oxide 230a, oxide 230b, and oxide It may be formed at 230c.

[0059] Furthermore, in Figure 2, the boundary between region 231 and region 234 is defined relative to the lower surface of oxide 230b. Although shown almost vertically, this embodiment is not limited to this. For example, region 2 34 spreads towards the conductor 240 near the surface of oxide 230b, and under oxide 230b Near the surface, the shape may become narrower.

[0060] In a transistor using an oxide semiconductor for the channel formation region, the channel formation region When a low-resistance region is formed, the source electrode and drain electrode of the transistor are connected in that low-resistance region. Leakage current (parasitic channel) is likely to occur between the poles. Also, due to this parasitic channel... This involves the normally-on state of the transistor, increased leakage current, and threshold due to stress application. Voltage fluctuations (shifts) and other transistor characteristic defects are more likely to occur. If the processing precision of the transistor is low, the parasitic channel will vary from transistor to transistor, This can lead to variations in the characteristics of the transistors.

[0061] Furthermore, in transistors using oxide semiconductors, the channel formation region in the oxide semiconductor is incomplete. The presence of pure materials and oxygen vacancies can cause the oxide semiconductor to exhibit low resistance. Electrical properties are prone to fluctuations, which can lead to poor reliability. Examples of such impurities include A Examples include luminium (Al) and silicon (Si). These impurities are mixed into the channel-forming region. Upon entry, defect levels or oxygen vacancies may be formed.

[0062] Aluminum and silicon have a bonding energy with oxygen that is greater than that of indium and zinc. The amount is also large. For example, when In-M-Zn oxide is used as an oxide semiconductor, the oxidation When aluminum is mixed into a semiconductor, the oxygen contained in the oxide semiconductor becomes aluminum This can lead to the formation of oxygen deficiencies near indium or zinc. ru.

[0063] If the channel-forming region in a metal oxide contains oxygen vacancies, the transistor will not be normal. Leone properties may occur. Furthermore, if hydrogen enters the oxygen vacancy in the metal oxide, Oxygen deficiency and hydrogen combine to form V OSometimes H is formed. A defect in which hydrogen is placed in an oxygen vacancy. V O H) can function as a donor, and electrons, which are carriers, can be generated. Also, water In some cases, a portion of the element combines with oxygen, which is bonded to a metal atom, to generate electrons, which act as carriers. Therefore, transistors using metal oxides that contain a lot of hydrogen are normally ohms. It tends to develop negative properties. Also, hydrogen in metal oxides is affected by stress such as heat and electric fields. Because it is easily broken down, if metal oxides contain a lot of hydrogen, the reliability of transistors deteriorates. There is also fear.

[0064] Therefore, in the channel formation region of the oxide semiconductor and its vicinity, the impurity It is preferable that oxygen deficiency be minimized as much as possible.

[0065] Therefore, the channel formation region of the transistor and the structures in its vicinity are given the shape described later. It is preferable to do so. By making the structure constituting the transistor have the shape described later, By reducing the low-resistance region formed in the channel formation region, the generation of parasitic channels can be suppressed. Therefore, it is possible to suppress variations in transistor characteristics caused by parasitic channels. Here, transistor characteristics refer to the current value in the ON state (ON current value) and the OFF state. Current value in state (off-current value), threshold voltage, subthreshold swing value (S value) ), and field-effect mobility, etc. Also, the channel formation region of oxide semiconductors and its vicinity. This can reduce the impurity concentration and improve the reliability of the transistor.

[0066] <Preferred shape of the channel-forming region and the surrounding structures> The following describes the preferred shape of the channel-forming region and the structures in its vicinity. For the sake of simplicity, the channel formation region of transistor 200 will function as follows: The region is assumed to be formed in oxide 230b.

[0067] Figure 3A is a perspective view of the transistor 200 and its vicinity shown in Figures 1A to 1D. Furthermore, Figure 3B shows an enlarged perspective view of a portion of transistor 200 shown in Figure 3A. Note that some elements have been omitted in the perspective views of Figures 3A and 3B for clarity. .

[0068] The oxide 230b is in contact with at least a portion of the conductor 242a in region 231a (Figure 3A, (Not shown in Figure 3B) and the region 231b that is in contact with at least a part of the conductor 242b (Figure 3 A (not shown in Figure 3B) and between region 231a and region 231b, a transistor It has a region 234 that functions as a channel-forming region. Region 234 is oxidized The material 230b has a region where the oxide 230b and the conductor 260 overlap. Of the oxide 230b, the region where the oxide 230b and the conductor 242a overlap is called region 231 This can be rephrased as a, and the region where oxide 230b and conductor 242b overlap is called region 2 This can be rephrased as 31b.

[0069] As shown in Figures 1C and 3B, in a cross-sectional view of transistor 200 in the channel width direction... And, in region 234, between the side surface of oxide 230b and the top surface of oxide 230b, It is preferable that it has a curved surface. That is, the end of the side surface and the end of the top surface are curved. It is preferable to have a rounded shape (hereinafter also referred to as a rounded shape).

[0070] Here, as shown in Figures 2 and 3B, the cross-section of transistor 200 in the channel length direction. In terms of sight, the distance between the side ends of the conductors 242a and 242b facing each other Let the distance be L. Note that L is the distance in a cross-sectional view of transistor 200 in the channel length direction. This can also be described as the length of the upper surface of the oxide 230b in the region that does not overlap with the conductor 242.

[0071] Furthermore, as shown in Figure 3B, in a cross-sectional view of transistor 200 in the channel width direction, Of the upper surface of the oxide 230b in the region where the oxide 230b and the conductor 260 overlap, Let W be the length of the region that does not have a curved surface.

[0072] Furthermore, as shown in Figure 3B, the radius of curvature of the curved surface is denoted as La. Note that La is, In a cross-sectional view of transistor 200 in the channel width direction, the lower surface of insulator 224 is used as a reference. In the region where the oxide 230b and the conductor 260 overlap, the upper part of the oxide 230b The difference between the height of the surface and the height of the lower end of the curved surface region on the side of oxide 230b. This may be considered in some cases.

[0073] La is greater than 0 nm and less than the film thickness of oxide 230b in the region overlapping with conductor 242. It is preferable that it is smaller than or equal to half of the above W. Specifically, La is 0 nm or The larger the wavelength, the less than or equal to 20 nm, preferably 1 nm to 15 nm, and more preferably 2 nm or less. The upper part should be 10 nm or less. By making it this shape, an electric field will be formed between the side surface and the top surface. This suppresses the concentration of W and reduces fluctuations in transistor characteristics. This prevents a decrease and suppresses the reduction in the on-current and mobility of transistor 200. Therefore, it is possible to provide a semiconductor device with good electrical characteristics.

[0074] Furthermore, by adopting the above shape, the effective channel on the side of the oxide 230b in region 234 The channel length becomes greater than the effective channel length on the upper surface of oxide 230b, thereby the side surface The current flowing decreases. Therefore, the influence of the parasitic channels formed on that side surface is suppressed. The S value of transistor 200 can be reduced. Also, the parasitic Because the influence of channel-to-transistor variations is reduced, the transistor characteristics are improved. This allows us to provide semiconductor devices with less rattling.

[0075] In a cross-sectional view of transistor 200 in the channel width direction, oxide 230b and conductor 26 The length of the region of oxide 230b that does not have a curved surface, in the region where it overlaps with 0. Let this be Lb. Note that in the region where oxide 230b and conductor 260 overlap, If the side surface of 230b has a tapered shape, Lb is the length of the tapered portion of oxide 230b. It can also be rephrased as follows. Furthermore, Lb is the reference value when the lower surface of the insulator 224 is used as the reference point. The height of the upper end of the region that does not have the curved surface, and the height of the lower end of the region that does not have the curved surface. It is sometimes considered to be the difference between and . Lb is La, the film thickness of oxide 230b, and the amount of oxide 230b It depends on the taper angle, etc. Here, the taper angle is the difference between the side surface of a tapered film and the This refers to the angle between the bottom surface of the membrane and the point of contact.

[0076] Furthermore, the upper surface of the oxide 230b in the region where the oxide 230b and the conductor 260 overlap. Let Lc be the amount of film loss. Lc is, for example, the cross-section of transistor 200 in the channel width direction. In a surface view, the acid in the region overlapping with the conductor 242, with the bottom surface of the insulator 222 as the reference point. The height of the upper surface of oxide 230b and the height of the upper surface of oxide 230b in the region overlapping with conductor 260. It can be calculated as the difference between and .

[0077] As will be described later, the elements contained in the conductive layer 242B provided in contact with the oxide 230b If the element has the function of absorbing oxygen from oxide 230b, then oxide 230b and conductive layer 24 When a partially low-resistance region is formed between 2B and the oxide 230b, or near the surface of the oxide 230b. There is also an insulating material provided so as to be in contact with the side surface of the channel-forming region of oxide 230b. If the elements contained in film 254A have the function of absorbing oxygen from oxide 230b, oxidation Between material 230b and insulating film 254A, or near the side of the channel-forming region of oxide 230b In some cases, a partially low-resistance region may be formed nearby. In other words, these elements are oxide semi-semi These impurities can be present in the conductor. In this case, the low-resistance region may contain impurities or oxygen deficiencies. Impurities that enter the loss (hydrogen, nitrogen, metallic elements, etc.) function as donors, and carrier concentration The number may increase.

[0078] Furthermore, when impurities are mixed into an oxide semiconductor, defect levels or oxygen vacancies may be formed. Therefore, when impurities are mixed into the channel formation region of the oxide semiconductor, The electrical characteristics of transistors using conductors are prone to fluctuations, which can lead to poor reliability. Furthermore, if the channel formation region contains an oxygen vacancy, the transistor exhibits normally-on characteristics. (A channel exists even without applying voltage to the gate electrode, and current flows through the transistor.) (It is easy to become sexual.)

[0079] Therefore, the upper surface of the oxide 230b in region 234 overlaps with the conductor 242. It is preferable that it is lower than the upper surface of the oxide 230b. For example, Lc is greater than 0 nm. It is preferable that the thickness is smaller than the thickness of the oxide 230b in the region overlapping with the conductor 242. Specifically, this refers to a wavelength greater than 0 nm and less than or equal to 15 nm, preferably between 0.5 nm and 10 nm. Furthermore, it is more preferably 1 nm to 5 nm. By having this shape, the above By removing impurities and reducing the low-resistance region formed near the upper surface of region 234, parasitic channels This can suppress the occurrence of [unclear]. The effective channel length on the upper surface of region 234 is L It becomes +2 × Lc. Therefore, by reducing Lc, the on-current of the transistor decreases. It can be suppressed.

[0080] Furthermore, the side of the oxide 230b in the region where the oxide 230b and the conductor 260 overlap. Let We be the amount of film loss. We is, for example, the cross-section of transistor 200 in the channel width direction. In a surface view, the side surface of the oxide 230b in the region overlapping with the conductor 242 and the curved surface mentioned above It can be calculated as the difference between the side surface of oxide 230b in the region where there is no oxide. Also, for example, In a cross-sectional view of transistor 200 in the channel width direction, the acid in the region overlapping with the conductor 242 The length of the lower surface of oxide 230b and the lower surface of oxide 230b in the region that does not overlap with conductor 242 It can be calculated as half the difference between the length and .

[0081] We is greater than 0 nm and less than or equal to the film thickness of oxide 230b in the region overlapping with conductor 242. It is preferable to do so. Specifically, We prefer a wavelength greater than 0 nm and less than or equal to 20 nm. The wavelength should be between 1 nm and 15 nm, more preferably between 2 nm and 10 nm. We is 0n By making it larger than m, impurities near the side surface of region 234 are removed, reducing the low-resistance region. This can suppress the development of parasitic channels.

[0082] Therefore, the low-resistance region formed in the channel-forming region is reduced, and the generation of parasitic channels is suppressed. This can suppress variations in transistor characteristics caused by parasitic channels. It can be suppressed. Also, impurities in the channel formation region and its vicinity in oxide semiconductors. By reducing the concentration, the reliability of the transistor can be improved.

[0083] The channel formation region of transistor 200 and the structures in its vicinity are given the above shape. This reduces variations in transistor characteristics. For example, variations in Vsh It can be reduced. In this specification, Vsh is the Id-Vg curve of the transistor. And the drain current Id = 1.0 × 10 -12 V is defined by the gate voltage Vg at A. The variability of sh can be evaluated, for example, using the standard deviation σ. n (where n is 3 or greater) It is an integer. The standard deviation σ of Vsh in ) transistors is expressed by the following formula.

[0084]

number

[0085] In the above equation, x i The V of the i-th transistor (where i is an integer between 1 and n, inclusive) The value of sh is the average value of Vsh across n transistors, where μ is the average value of Vsh across n transistors.

[0086] In the Id-Vg characteristics of transistor 200, the standard deviation σ of Vsh is, specifically, 60 It is below mV, preferably below 40 mV, more preferably below 20 mV.

[0087] Also, by making the structure in the channel formation region of the transistor 200 and its vicinity have the above shape, it is possible to reduce the impurity concentration in the channel formation region of the oxide semiconductor and its vicinity. Specifically, in the channel formation region of the oxide semiconductor and its vicinity, the concentration of impurities obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectroscopy) is made to be 1×10 atoms / cm 18 or less, preferably 3 2×10 atoms / cm 16 or less. Alternatively, in the channel formation region of the oxide semiconductor and its vicinity, the concentration of impurities obtained by elemental analysis using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy) 3 is made to be 1.0 atomic% or less. When using an oxide containing the element M as the oxide semiconductor, in the channel formation region of the oxide semiconductor and its vicinity the concentration ratio of impurities to the element M is made to be less than 0.10, preferably less than 0.05. Here, the concentration of the element M used when calculating the concentration ratio may be the concentration in the same region as the region where the impurity concentration was calculated, or the concentration in the oxide semiconductor . Also, when using an oxide containing the element M as the oxide semiconductor, in the channel formation region of the oxide semiconductor and its vicinity the concentration ratio of impurities to the element M is made to be less than 0.10, preferably less than 0.05. Here, the concentration of the element M used when calculating the concentration ratio may be the concentration in the same region as the region where the impurity concentration was calculated, or the concentration in the oxide semiconductor.

[0088] Also, the impurity concentration on the side surface of the oxide 230b in the channel formation region is made smaller than the impurity concentration on the side surface of the oxide 230b in the region overlapping with the conductor 242. Or, the concentration ratio of impurities to the element M on the side surface of the oxide 230b in the channel formation region The ratio is the impurity of element M on the side surface of oxide 230b in the region overlapping with conductor 242. Make it smaller than the concentration ratio of the substance. Also, on the upper surface of the oxide 230b in the channel-forming region The concentration ratio of impurities to element M is on the upper surface of oxide 230b in the region overlapping with conductor 242. The concentration ratio of impurities to element M is made smaller than that of the given material.

[0089] <Detailed configuration of the semiconductor device> Hereinafter, a semiconductor device according to one aspect of the present invention, and the transients of said semiconductor device This section will explain the detailed configuration of the ST200.

[0090] Insulator 212, insulator 214, insulator 254, insulator 282, insulator 283 and insulation Body 281 is affected by impurities such as water and hydrogen entering from the substrate side or from above the transistor 200. It is preferable that it acts as a barrier insulating film to suppress diffusion from to transistor 200. Therefore, insulator 212, insulator 214, insulator 254, insulator 282, insulator 283 and insulator 281 contain hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and oxides. It has the function of suppressing the diffusion of impurities such as nitrogen molecules (N2O, NO, NO2, etc.) and copper atoms. It is preferable to use an insulating material that does not easily allow the above impurities to permeate. Alternatively, oxygen ( For example, it has the function of suppressing the diffusion of at least one of the following: oxygen atoms, oxygen molecules, etc. (as described above) It is preferable to use an insulating material (that is impermeable to oxygen).

[0091] For example, silicon nitride may be used as the insulator 212, insulator 283, and insulator 281. Using aluminum oxide as the insulator 214, insulator 254, and insulator 282, It is preferable to use such a material. This allows impurities such as water and hydrogen to be absorbed into the insulator 212, The diffusion from the substrate side to the transistor 200 side via the insulator 214 is suppressed. Yes, it is possible. Alternatively, oxygen contained in insulator 224, etc., can be absorbed by insulator 212 and insulator 21 Diffusion to the substrate side via 4 can be suppressed. Also, impurities such as water and hydrogen can be suppressed. The insulators 280 and conductors 246, etc., which are positioned above the insulator 254, This can suppress diffusion into the inside of transistor 200 via 254. Transistor 200 has a function to suppress the diffusion of impurities such as water and hydrogen, and oxygen. The insulators 212, 214, 254, 282, and 283 It is preferable to have a structure that surrounds it.

[0092] Furthermore, it is preferable to lower the resistivity of insulators 212, 283, and 281. There are cases where this is difficult. For example, the resistivity of insulators 212, 283, and 281. Approximately 1 × 10 13 By setting it to Ωcm, processing using plasma, etc. in semiconductor device manufacturing processes. In this, insulator 212, insulator 283, and insulator 281 are conductor 205, conductor It may be possible to mitigate the charge-up of 242 or conductor 260. Insulator The resistivity of insulators 212, 283, and 281 is preferably 1 × 10⁻⁶. 10 Ωc m or more 1×10 15 The density should be less than or equal to Ωcm.

[0093] Furthermore, insulators 216, 280, and 274 have a dielectric constant greater than insulator 214. A low rate is preferable. By using a material with a low dielectric constant as the interlayer film, parasitic activity between wiring is reduced. The capacity can be reduced. For example, insulator 216, insulator 280, and insulator 27 4. Silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, fluorine silicon oxide with added carbon, silicon oxide with added carbon and nitrogen Silicon, porous silicon oxide, or other suitable materials can be used as appropriate.

[0094] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. The conductor 205 is preferably provided embedded in the insulator 214 or insulator 216. stomach.

[0095] Conductor 260 may function as the first gate electrode. Also, conductor 205 It may function as a second gate electrode. In that case, the potential applied to the conductor 205 By changing this independently of the potential applied to the conductor 260, the transient The threshold voltage (Vth) of the sta 200 can be controlled. In particular, negative voltage to the conductor 205 By applying a potential, the Vth of transistor 200 is increased, and the off-current is increased. It becomes possible to reduce it. Therefore, applying a negative potential to the conductor 205 makes the mark Compared to when no potential is applied, the drain current when the potential applied to the conductor 260 is 0V is reduced. It is possible.

[0096] Furthermore, as shown in Figure 1A, the conductor 205 is made of the conductor 242a of oxide 230 and conductor It is preferable to provide a larger area than the area that does not overlap with the electric body 242b. In particular, as shown in Figure 1C Thus, the conductor 205 extends beyond the edge that intersects the channel width direction of the oxide 230. In the region as well, elongation is preferable. That is, in the channel width direction of the oxide 230. On the outer side of the side, the conductor 205 and the conductor 260 are superimposed with an insulator in between. It is preferable that the conductive material functions as the first gate electrode. The electric field of body 260 and the electric field of conductor 205, which functions as a second gate electrode, cause oxidation. The channel-forming region of object 230 can be electrically surrounded. In this specification, the first The electric fields of the first gate and the second gate electrically surround the channel formation region. The structure of the transistor is a surrounded channel (S-channel) structure. It is called construction.

[0097] In this specification, etc., an S-channel transistor refers to a pair of gates. The electric fields of one and the other electrodes electrically surround the channel formation region. This represents the structure of the sta. Furthermore, in this specification, the S-channel structure is the source electrode. and oxides in contact with conductors 242a and 242b, which function as drain electrodes. The sides and periphery of 230 are characterized by being type I, just like the channel-forming region. Furthermore, the sides and periphery of the oxide 230 in contact with the conductors 242a and 242b are insulated. Because it is in contact with the edge body 280, it can be type I, similar to the channel-forming region. In written documents and other materials, Type I can be treated the same as the high-purity genuine type described later. The S-channel structure disclosed in the detailed document is different from the Fin-type structure and the Planar-type structure. Yes. By adopting an S-channel structure, resistance to short-channel effects is increased. In other words, it can be made into a transistor that is less prone to short-channel effects.

[0098] Furthermore, as shown in Figure 1C, the conductor 205 is extended to function as wiring. However, without being limited to this, a conductor that functions as a wiring may be provided under the conductor 205. Also, the conductor 205 does not necessarily need to be provided one by one for each transistor. For example, the conductor 205 may be configured to be shared by a plurality of transistors.

[0099] In the transistor 200, the conductor 205 is shown in a configuration where the conductor 205a and the conductor 205b are laminated, but the present invention is not limited to this. For example, the conductor 205 may be provided in a single-layer or a laminated structure of three or more layers. When the structure has a laminated structure, ordinal numbers may be assigned in the order of formation for distinction.

[0100] Here, the conductor 205a preferably uses a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2, etc.), and copper atoms. Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0101] By using a conductive material having a function of suppressing the diffusion of oxygen for the conductor 205a, it is possible to suppress the oxidation of the conductor 205b and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used. Therefore, the conductor 205a may be a single layer or a laminate of the above conductive materials. For example, the conductor 205a may be a laminate of tantalum, tantalum nitride, ruthenium, or ruthenium oxide and titanium or titanium nitride. ​​​​​​​​​​​​​​

[0102] Furthermore, the conductor 205b is a conductive material mainly composed of tungsten, copper, or aluminum. It is preferable to use a material with properties. Although the conductor 205b is shown as a single layer, a laminated structure is also possible. This may also be done, for example, by laminating titanium or titanium nitride with the conductive material. .

[0103] Insulators 222 and 224 function as gate insulators.

[0104] The insulator 222 suppresses the diffusion of hydrogen (for example, at least one such as a hydrogen atom or hydrogen molecule). It is preferable that it has a function to control oxygen. Also, the insulator 222 is oxygen (for example, oxygen atoms, It is preferable that the function suppresses the diffusion of at least one of the following: oxygen molecules. For example, Insulator 222 suppresses the diffusion of hydrogen and / or oxygen more effectively than insulator 224. It is preferable that it has a function.

[0105] The insulator 222 is made of either or both aluminum and hafnium, which are insulating materials. It is preferable to use an insulator containing an oxide. Suitable insulators include aluminum oxide and hafni oxide. Using oxides containing um, aluminum, and hafnium (hafnium aluminate), etc. It is preferable that such a material is used to form the insulator 222. 2 is the release of oxygen from the oxide 230 to the substrate side, and oxidation from the periphery of the transistor 200. It functions as a layer that suppresses the diffusion of impurities such as hydrogen into material 230. Therefore, insulator 222 By providing this feature, the diffusion of impurities such as hydrogen into the inside of transistor 200 is suppressed. This can suppress the formation of oxygen vacancies in the oxide 230. Also, the conductor 205 is an absolute It is possible to suppress the reaction with the oxygen contained in the insulator 224 or the oxide 230.

[0106] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide , niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. Also, the insulator 222 may be used by laminating silicon oxide, silicon oxynitride or silicon nitride on these insulators.

[0107] Also, the insulator 222 may be, for example, an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc., used in a single layer or in a laminate. As the transistor miniaturization and high integration progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0108] The insulator 224 in contact with the oxide 230 preferably desorbs oxygen by heating. For example, the insulator 224 may appropriately use silicon oxide, silicon oxynitride, etc. By providing an oxygen-containing insulator in contact with the oxide 230, the oxygen deficiency in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved.

[0109] Specifically, as the insulator 224, an oxide material in which some oxygen desorbs by heating, in other words Therefore, it is preferable to use an insulating material that has an excess oxygen region. Oxygen is removed by heating. The oxide film that is separated is TDS (Thermal Desorption Spectroscopy). (copy) Analysis showed that the amount of oxygen molecules removed was 1.0 × 10⁻⁶. 18 molecular / cm² 3 Preferably 1.0 × 10 19 molecular / cm² 3 More preferably 2.0×10 19 molecular / cm² 3 Above, or 3.0 × 10 20 molc ules / cm 3 The above describes the oxide film. Note that the surface temperature of the film during the above TDS analysis was The preferred temperature range is between 100°C and 700°C, or between 100°C and 400°C. stomach.

[0110] Furthermore, the insulator having the above excess oxygen region and the oxide 230 are brought into contact and heat treated, One or more of the following processes may be performed: Kuroh wave processing or RF processing. By doing so, water or hydrogen can be removed from oxide 230. For example, oxide In 230, a defect (V) is formed when hydrogen is added to an oxygen vacancy. O A reaction occurs in which the bond of H is broken. In other words, "V O H→V O The reaction "+H" occurs, allowing for dehydrogenation. Some of the hydrogen generated at this time combines with oxygen to form H2O, which is an oxide 230, or an acid It may be removed from the insulator near the ion 230. Also, some of the hydrogen is removed from the conductor 242. They may be dispersed or captured (also known as gettering).

[0111] The above microwave processing is, for example, an apparatus having a power supply for generating high-density plasma, It is preferable to use a device that has a power supply that applies RF to the substrate side. For example, oxygen-containing By using a gas and a high-density plasma, high-density oxygen radicals can be generated. This can be achieved by applying RF to the substrate side, and by generating oxygen in the high-density plasma. The ability to efficiently introduce dical into oxide 230 or the insulator near oxide 230 is Yes, it is possible. Furthermore, the above microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher. Furthermore, it is preferable to set it to 400 Pa or higher. Also, within the apparatus that performs microwave processing For example, oxygen and argon are used as the gases introduced, with an oxygen flow rate ratio of (O2 / (O2). The process should be carried out with 2+Ar) at a concentration of 50% or less, preferably between 10% and 30%.

[0112] Furthermore, during the manufacturing process of transistor 200, the surface of oxide 230 is exposed. Therefore, heat treatment is preferable. This heat treatment is, for example, 100°C to 450°C. More preferably, the heating should be carried out at a temperature of 350°C to 400°C. The heat treatment is performed using nitrogen gas. Alternatively, an inert gas atmosphere, or an oxidizing gas at 10 ppm or more, 1% or more, The procedure should be carried out in an atmosphere containing 10% or more of the substance. For example, heat treatment is preferably carried out in an oxygen atmosphere. This allows oxygen to be supplied to oxide 230, thereby reducing oxygen deficiency. Furthermore, The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out using nitrogen gas or an inert gas. After heat treatment in this atmosphere, an oxidizing gas is added at a concentration of 10 ppm or more to replenish the desorbed oxygen. The procedure may be carried out in an atmosphere containing 1% or more, or 10% or more, of an oxidizing gas. After heat treatment in an atmosphere containing pm or more, 1% or more, or 10% or more, nitrogen gas is continuously applied. Heat treatment may be performed in an atmosphere of s or an inert gas.

[0113] Furthermore, by performing an oxygenation treatment on oxide 230, the oxygen deficiencies in oxide 230 are supplied. It is repaired by the oxygen that is used, in other words, "V O This promotes the reaction "+O → null". Furthermore, the oxygen supplied reacts with the hydrogen remaining in oxide 230. This allows the hydrogen to be removed as H2O (dehydrated). This eliminates oxidation. The hydrogen remaining in substance 230 recombines with the oxygen vacancy and V O Suppresses the formation of H It is possible.

[0114] The insulators 222 and 224 may have a laminated structure of two or more layers. In that case, it is not limited to laminated structures made of the same material, but also applies to laminated structures made of different materials. good.

[0115] It is preferable that oxide 230 has a layered structure composed of oxides with different chemical compositions. Specifically, in the metal oxide used in oxide 230a, the metal element that is the main component is The atomic ratio of element M is the main component of the metal oxide used in oxide 230b. It is preferable that the ratio of element M to the atomic number of elements is greater than the ratio of elements to the atomic number of elements. Also, when used in oxide 230a In the metal oxides, the atomic ratio of element M to In is the same as that of the gold used in oxide 230b. In the group oxide, it is preferable that the atomic ratio of element M to In is greater than that of acid. In the metal oxide used in 230b, the atomic ratio of In to element M is such that the oxide 2 It is preferable that the atomic ratio of In to element M in the metal oxide used for 30a is greater than that of In. It seems so. Also, oxide 230c can be used with oxide 230a or oxide 230b. A suitable metal oxide can be used.

[0116] Furthermore, if you want to increase the on-current of transistor 200, add I to oxide 230. n-Zn oxide is preferable. When using In-Zn oxide for oxide 230, For example, if oxide 230a is In-Zn oxide, and oxides 230b and 230 A layered structure using In-M-Zn oxide for c, or In-M-Zn oxide for oxide 230a. Using an oxide, either oxide 230b or oxide 230c is converted to an In-Zn oxide. Examples include laminated structures using [a specific material / technology].

[0117] Furthermore, it is preferable that oxides 230b and 230c have crystalline properties. For example However, as will be described later, CAAC-OS (c-axis aligned crystalline It is preferable to use an oxide semiconductor. Oxides with crystalline properties such as these have few impurities or defects (such as oxygen vacancies) and have high crystallinity. , it has a dense structure. Therefore, the oxide 23 by the source electrode or drain electrode This suppresses the abstraction of oxygen from 0b. As a result, even after heat treatment, acid Since the extraction of oxygen from ion 230b can be reduced, transistor 200 is manufactured It is stable against high temperatures (so-called thermal budget) during the manufacturing process.

[0118] Furthermore, it is preferable to use CAAC-OS as oxide 230c, and oxide 230 The c-axis of the crystal of c is oriented in a direction approximately perpendicular to the surface or top surface of the oxide 230c. It is preferable that it is present. CAAC-OS has the property of easily moving oxygen in the direction perpendicular to the c-axis. It possesses. Therefore, the oxygen contained in oxide 230c is efficiently supplied to oxide 230b. It is possible.

[0119] Furthermore, the lower end of the conduction band of oxide 230a and oxide 230c is the conduction band of oxide 230b. It is preferable that the lower end is closer to the vacuum level. In other words, oxide 230a and oxide 2 The electron affinity of 30c is preferably smaller than that of oxide 230b. In addition, oxide 230c can use a metal oxide that can be used in oxide 230a. This is preferable. In this case, the main carrier pathway is oxide 230b.

[0120] Here, at the junction of oxide 230a, oxide 230b, and oxide 230c, The lower end of the conduction band changes gradually. In other words, oxide 230a, oxide 230b, and The lower end of the conduction band at the junction of the oxide 230c is continuously changing or continuous junction. It can be said that... , and the defect level density of the mixed layer formed at the interface between oxide 230b and oxide 230c Lowering it would be good.

[0121] Specifically, oxide 230a and oxide 230b, and oxide 230b and oxide 230c, By having a common element other than oxygen as a main component, a mixed layer with a low defect level density is formed. This is possible. For example, if oxide 230b is In-Ga-Zn oxide, then oxide 23 As 0a and oxide 230c, In-Ga-Zn oxide, Ga-Zn oxide, and Ga oxide You may also use materials such as Lium.

[0122] Specifically, for oxide 230a, In:Ga:Zn = 1:3:4 [atomic ratio], Alternatively, a metal oxide with an atomic ratio of In:Ga:Zn = 1:1:0.5 can be used. As oxide 230b, In:Ga:Zn = 1:1:1 [atomic ratio], or In:G A metal oxide with an atomic ratio of a:Zn = 4:2:3 can be used. Also, oxide 230c For example, In:Ga:Zn=1:3:4 [atomic ratio], In:Ga:Zn=4:2:3 [ [Atomic ratio], Ga:Zn=2:1 [Atomic ratio], or Ga:Zn=2:5 [Atomic ratio] You can use a metal oxide.

[0123] Furthermore, when depositing metal oxides by sputtering, the above atomic ratio is used for the deposition of the film. Not limited to the atomic ratio of the metal oxides, the sputtering target used for depositing metal oxide films The atomic ratio of the set may also be acceptable.

[0124] By configuring oxide 230a and oxide 230c as described above, oxide 230a and oxide Defect level density at the interface with 230b and at the interface between oxide 230b and oxide 230c The degree can be reduced. Therefore, the influence of interfacial scattering on carrier conduction becomes smaller. Therefore, transistor 200 can obtain a large on-current and high frequency characteristics.

[0125] Examples of conductors 242 (conductors 242a and 242b) include tantalum. Nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten Materials, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum It is preferable to use such materials. In one embodiment of the present invention, a nitride containing tantalum is particularly Preferred. Also, for example, ruthenium oxide, ruthenium nitride, strontium and ruthenium Oxides containing lanthanum, oxides containing lanthanum and nickel, etc., may also be used. These materials Because it is a conductive material that is resistant to oxidation, or a material that maintains its conductivity even when it absorbs oxygen. ,preferable.

[0126] Furthermore, when the conductor 242 and the oxide 230b come into contact, oxygen in the oxide 230b is conductor The conductor 242 may diffuse into the conductive material 242, causing it to oxidize. Therefore, there is a high probability that the conductivity of conductor 242 will decrease. Diffusion into the conductive material 242 is described as the conductor 242 absorbing oxygen from the oxide 230b. It can be replaced.

[0127] Furthermore, oxygen in oxide 230b diffuses into conductors 242a and 242b. And between the conductor 242a and the oxide 230b, and between the conductor 242b and the oxide 230b A layer may be formed between the two. This layer is formed between the conductor 242a or the conductor 242b. Because it contains a large amount of oxygen, the layer is presumed to have insulating properties. At this time, conductor 24 The three-layer structure of 2a or conductor 242b, the said layer, and oxide 230b is a metal-insulator. -It can be considered a three-layer structure made of semiconductors, MIS (Metal-Insulator Diode junction structure mainly consisting of r-semiconductor (R-Semiconductor) structure or MIS structure It can be seen as a construction.

[0128] Furthermore, hydrogen contained in oxide 230b, etc., in conductor 242a or conductor 242b Diffusion may occur. In particular, conductors 242a and 242b contain nitrogen containing tantalum. By using the ion, the hydrogen contained in oxide 230b, etc., becomes conductor 242a or conductive It readily diffuses into body 242b, and the diffused hydrogen has conductor 242a or conductor 242b It can combine with nitrogen. In other words, hydrogen contained in oxides such as 230b is a conductor. It may be absorbed by 242a or conductor 242b.

[0129] Furthermore, there may be a curved surface between the side surface of the conductor 242 and the top surface of the conductor 242. In other words, the edges of the sides and the edges of the top surface may be curved. Curved surfaces are, for example, guide At the end of the electric body 242, the radius of curvature is 3 nm or more and 10 nm or less, preferably 5 nm. The above is 6 nm or less. By not having corners at the edges, the film coverage in subsequent film deposition processes is improved. This will improve.

[0130] As shown in Figure 1B, the insulator 254 is located on the top and side surfaces of the conductor 242a, and the conductor 24 The top and sides of 2b, the sides of oxide 230a, the sides of oxide 230b, and the insulator It is preferable that it contacts a part of the upper surface of 224. With this configuration, the insulator 28 0 is separated from insulator 224, oxide 230a and oxide 230b by insulator 254. To be separated.

[0131] Furthermore, the insulator 254, like the insulator 222, expands one or both of hydrogen and oxygen. It is preferable that the insulator 254 has a function to suppress dispersion. For example, the insulator 254 is an insulator 224, It has the function of suppressing the diffusion of hydrogen and / or oxygen more effectively than insulator 280. This is preferable. This allows the hydrogen contained in the insulator 280 to react with the oxide 230a and acid It is possible to suppress diffusion into the compound 230b. Furthermore, the insulator 222 and the insulating Body 254 surrounds the insulator 224, oxide 230, etc., thereby allowing water, hydrogen, etc. The diffusion of impurities from the outside into the insulator 224 and oxide 230 is suppressed. Yes, it is possible. Therefore, good electrical characteristics and reliability can be given to transistor 200. ru.

[0132] The insulator 254 is preferably formed using a sputtering method. The insulating film of the insulator 224 is formed by depositing it using the sputtering method in an oxygen-containing atmosphere. Oxygen can be added to the vicinity of the region in contact with body 254. This allows oxygen to be released from that region. Oxygen can be supplied to the oxide 230 via the insulator 224. Here, insulator 2 54 has the function of suppressing the upward diffusion of oxygen, thereby preventing oxygen from being isolated from oxides 230. This prevents diffusion to the edge 280. Also, the insulator 222 prevents oxygen from going downwards. By having a function that suppresses diffusion, it prevents oxygen from diffusing from oxide 230 to the substrate side. This can be done. In this way, oxygen is supplied to the channel-forming region of the oxide 230. This reduces oxygen vacancies in oxide 230 and suppresses the normally-on state of the transistor. It can be controlled.

[0133] As the insulator 254, for example, an acid made of either or both aluminum and hafnium. It is preferable to deposit an insulator containing an admixture. In this case, insulator 254 is deposited by atomic layer deposition (ALD: It is preferable to deposit the film using the Atomic Layer Deposition method. The ALD method is a film deposition method with good coverage, so the unevenness of the insulator 254 prevents stepped breaks. This can prevent the formation of stagnation.

[0134] Furthermore, as the insulator 254, for example, an insulator containing aluminum nitride may be used. This allows for the creation of a film with excellent insulating properties and excellent thermal conductivity, thus enabling the translucency process. This improves the heat dissipation of the heat generated when operating the ZISTA 200. Also, nitriding silicon Materials such as silicon nitride can also be used.

[0135] Furthermore, as the insulator 254, for example, an oxide containing gallium may be used. Oxides containing um have the function of inhibiting the diffusion of one or both hydrogen and oxygen. This is preferable because it has the following properties. Note that gallium-containing oxides include gallium oxide and zinc gallium. Oxides, indium gallium zinc oxide, etc., can be used. Note that insulator 254 When using indium gallium zinc oxide, the gallium atoms relative to indium A larger number ratio is preferable. Increasing the atomic number ratio improves the insulating properties of the oxide. It can be done.

[0136] Furthermore, the insulator 254 can have a multilayer structure of two or more layers. When forming a laminated structure, the above method is used to form the lower and upper layers of the insulator 254. The lower and upper layers of the insulator 254 can be deposited using the same method. A different method may be used. For example, as insulator 254, spat in an oxygen-containing atmosphere. The lower layer of insulator 254 is deposited using the taring method, and then the insulator 254 is processed using the ALD method. The upper layer may also be formed. The ALD method is a film deposition method with good coverage, so the unevenness of the first layer... This prevents the formation of steps or other defects.

[0137] Furthermore, the above materials can be used for the lower and upper layers of the insulator 254, and the insulator 25 The lower and upper layers of 4 may be made of the same material or different materials. For example, acid Silicon oxide, silicon oxide nitride, silicon nitride oxide, or silicon nitride, and hydrogen and other inertia It may also be a laminated structure of an insulator that has the function of suppressing the permeation of pure substances and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, An insulator containing oxides of luminium and / or hafnium can be used. ru.

[0138] Insulator 250 functions as a gate insulator. Insulator 250 has a small amount of oxide 230c. It is preferable that it be placed in contact with at least a part of it. The insulator 250 is silicon oxide, nitrogen oxide Silicon oxide, silicon nitride, silicon nitride, silicon oxide with added fluorine, carbon Silicon oxide with added carbon and nitrogen, silicon oxide with voids Cones can be used. In particular, silicon oxide and silicon oxide nitride are heat resistant. It is preferable because it is stable.

[0139] Insulator 250, like insulator 224, uses an insulator that releases oxygen when heated. It is preferable to form an insulator that releases oxygen upon heating, as insulator 250. By providing it in contact with at least a portion of oxide 230c, channels of oxide 230b are formed. This effectively supplies oxygen to the formation region and reduces oxygen deficiency in the channel formation region of oxide 230b. This is possible. Therefore, it is possible to suppress fluctuations in electrical characteristics and have stable electrical characteristics. Together, we can provide transistors with improved reliability. Also, insulator 224 Similarly, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. The thickness of the insulator 250 is preferably between 1 nm and 20 nm.

[0140] Note that in Figures 1A to 1C, the insulator 250 is shown as a single layer, but it can also be a laminated structure of two or more layers. This may also be done. When the insulator 250 has a two-layer laminated structure, the lower layer of the insulator 250 is heated The insulator is formed using an insulator that releases oxygen, and the upper layer of the insulator 250 suppresses the diffusion of oxygen. It is preferable to form it using an insulator that has a controlling function. Therefore, the diffusion of oxygen contained in the lower layer of the insulator 250 into the conductor 260 is suppressed. Yes, it is possible. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to oxide 230. Also, This can suppress the oxidation of the conductor 260 by oxygen contained in the layer beneath the insulator 250. For example, the lower layer of the insulator 250 may be made of a material that can be used for the insulator 250 as described above. The upper layer of the insulator 250 can be made using the same material as the insulator 222. .

[0141] Furthermore, when silicon oxide or silicon oxide nitride is used as the lower layer of the insulator 250, The upper layer of body 250 may be made of an insulating material, which is a high-k material with a high dielectric constant. The gate insulator is constructed with a laminated structure consisting of a lower layer of insulator 250 and an upper layer of insulator 250. A layered structure that is stable against heat and has a high dielectric constant can be created. Therefore, the gate The gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the insulator. This becomes possible. Also, a thin film of equivalent oxide film thickness (EOT) of an insulator that functions as a gate insulator. This makes transformation possible.

[0142] Specifically, the upper layer of insulator 250 is made of hafnium, aluminum, gallium, and Thorium, zirconium, tungsten, titanium, tantalum, nickel, germanium, A metal oxide containing one or more metals selected from magnesium, or an acid Metal oxides that can be used as oxide 230 can be used. In particular, aluminum It is preferable to use an insulator containing oxides of um and / or hafnium.

[0143] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The material preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 is reduced. Dispersion is suppressed. In other words, the decrease in the amount of oxygen supplied to oxide 230 can be suppressed. Furthermore, the oxidation of the conductor 260 by oxygen in the insulator 250 can be suppressed.

[0144] Furthermore, it is preferable that the above metal oxide functions as part of the first gate electrode. For example, a metal oxide that can be used as oxide 230 is the above metal oxide. It can be used in this way. In that case, the conductive material 260a is deposited by sputtering. The electrical resistance of the above metal oxide can be reduced to make it a conductor. This is called OC(O It can be called an xide conductor electrode. For example, it is used with oxide 230. By reducing the resistance of oxide semiconductors that can be used, they can be used as the above-mentioned metal oxides. can.

[0145] Having an upper layer of the insulator 250 and / or the metal oxide, the conductor 260 This allows for an improvement in the on-current of transistor 200 without weakening the effect of the electric field. Furthermore, due to the physical thickness of the insulator 250 and the metal oxide, the conductor 260 and By maintaining a distance between the conductor 260 and the oxide 230, leakage current between the conductor 260 and the oxide 230 is reduced. The flow can be suppressed. In addition, the laminated structure of the insulator 250 and the metal oxide is By providing this, the physical distance between the conductor 260 and the oxide 230, and the conductor 260 The electric field strength applied from to the oxide 230 can be easily and appropriately adjusted.

[0146] The conductor 260 consists of a conductor 260a and a conductor 260b placed on top of the conductor 260a. It is preferable that the conductor 260a has the bottom surface and of the conductor 260b. It is preferable that it be arranged so as to enclose the sides. Note that in Figures 1A to 1C, the conductor 26 Although 0 is shown as a two-layer structure of conductor 260a and conductor 260b, a single-layer structure is also acceptable. Furthermore, it may have a laminated structure of three or more layers.

[0147] Conductor 260a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules. It is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms. Alternatively, a device that inhibits the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule). It is preferable to use a conductive material that has conductivity.

[0148] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, the insulator 250 The oxygen contained in the material suppresses the oxidation of the conductor 260b, which reduces its conductivity. Yes, it is possible. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum and nitrogen. It is preferable to use tantalum oxide, ruthenium oxide, or the like.

[0149] Furthermore, since the conductor 260 also functions as wiring, a highly conductive material should be used. This is preferable. For example, the conductor 260b is mainly composed of tungsten, copper, or aluminum. A conductive material can be used. Furthermore, the conductor 260b may also be in a laminated structure. For example, a laminated structure of titanium or titanium nitride and the above-mentioned conductive material may be used.

[0150] Furthermore, in transistor 200, the conductor 260 is formed on an insulator 280 or the like. The conductor 260 is formed in a self-aligning manner to fill the opening. Therefore, the conductor 260 is positioned in the region between the conductor 242a and the conductor 242b. It can be positioned reliably without any problems.

[0151] Furthermore, as shown in Figure 1C, in the channel width direction of transistor 200, insulator 2 When the bottom surface of 22 is used as a reference, the conductor 260 and the oxide 230b overlap. The height of the bottom surface of the region that does not undergo this process is preferably lower than the height of the bottom surface of oxide 230b. The conductor 260, which functions as a electrode, transmits oxide 230b via an insulator 250, etc. By configuring the channel formation region to cover the sides and top surface, the electric field of the conductor 260 is oxidized. This makes it easier to apply the effect to the entire channel formation region of component 230b. Therefore, transistor 200 The on-current can be increased and the frequency characteristics can be improved. Based on the bottom surface of the insulator 222 When considered as a standard, the oxides 230a and 230b and the conductor 260 do not overlap. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in region i is, 0 nm to 100 nm, preferably 3 nm to 50 nm, more preferably 5 The range should be between 20 nm and 20 nm.

[0152] Insulator 280 consists of insulator 224, oxide 230a, oxide 230b, conductor 242, and It is provided on the insulator 254. The upper surface of the insulator 280 may also be flattened. stomach.

[0153] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. By using the material as an interlayer film, parasitic capacitance occurring between wiring can be reduced. Insulator 28 It is preferable that 0 be provided using a material similar to that of the insulator 216, for example. In particular, oxide Silicon oxide and silicon nitride are preferred because they are thermally stable. In particular, silicon oxide Materials such as silicon oxidnitride and silicon oxide with voids release oxygen upon heating. This is preferable because it allows for the easy formation of a region containing [the specified element].

[0154] Furthermore, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. Furthermore, it is preferable that the insulator 280 has a low hydrogen concentration and is in the excess oxygen region or contains excess oxygen. For example, it may be provided using the same material as the insulator 216. Also, insulator 280 This can also be a structure in which the above materials are stacked, for example, an oxide film deposited by sputtering. Recon and chemical vapor deposition (CVD) applied on top of it. A layered structure of silicon oxide nitride deposited by the deposition method can be used. Furthermore, silicon nitride may be laminated on top of it.

[0155] Insulator 282 or insulator 283 is susceptible to impurities such as water and hydrogen from above. It is preferable that it functions as a barrier insulating film that suppresses diffusion. Also, insulator 28 2 or insulator 283 is preferred to function as a barrier insulating film that suppresses oxygen permeation. For example, insulators 282 and 283 may be aluminum oxide, silica nitride, etc. An insulator such as silicon nitride can be used. For example, as insulator 282, acid Aluminum oxide, which has high blocking properties against the element, is used as the insulator 283, and hydrogen Alternatively, silicon nitride, which has high blocking properties, can be used.

[0156] Furthermore, it is preferable to provide an insulator 274 that functions as an interlayer film on top of the insulator 282. Insulator 274, like insulator 224, has a low concentration of impurities such as water and hydrogen in the film. It is preferable that it be reduced.

[0157] Conductors 240a and 240b are primarily composed of tungsten, copper, or aluminum. It is preferable to use conductive materials as components. Also, conductor 240a and conductor 24 0b may be a layered structure.

[0158] Furthermore, when the conductor 240a and the conductor 240b are in a laminated structure, the insulator 281, In contact with insulators 274, 283, 282, 280, and 254 The conductor used is a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen. Preferably, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, It is preferable to use ruthenium oxide or similar materials. Furthermore, it is important to suppress the permeation of impurities such as water and hydrogen. A conductive material having the function of being used may be used in a single layer or in a laminate. As a result, the oxygen added to the insulator 280 is absorbed by the conductors 240a and 240b. This can prevent it from happening. Also, it can prevent water, hydrogen, and other insulators contained in the layer above the insulator 281 from being absorbed. This prevents the pure substance from mixing with the oxide 230 through the conductors 240a and 240b. It is possible.

[0159] Examples of insulators 241a and 241b include silicon nitride and aluminum oxide. Insulators such as um and silicon nitride can be used. Insulator 241a and Insulator 24 Since 1b is provided in contact with the insulator 254, water, hydrogen, etc. contained in the insulator 280, Which impurities are introduced into the oxide 230 through conductors 240a and 240b? This can suppress hydrogen. In particular, silicon nitride has high blocking properties for hydrogen. It is preferable. Also, the oxygen contained in the insulator 280 is suitable for conductors 240a and conductor 240b. This can prevent it from being absorbed.

[0160] Furthermore, the upper surfaces of the conductor 240a and the upper surfaces of the conductor 240b function as wiring. Conductors 246 (conductors 246a and conductors 246b) may be arranged. 46 uses a conductive material whose main component is tungsten, copper, or aluminum. This is preferable. The conductor may also be in a laminated structure, for example, titanium or titanium nitride. The conductive material may be laminated with the above conductive material. The conductive material is provided with an opening in the insulator. It may be shaped to be embedded in the mouth.

[0161] <Component materials for semiconductor devices> The following describes the constituent materials that can be used in semiconductor devices.

[0162] <<Substrate>> Examples of substrates for forming the transistor 200 include an insulating substrate, a semiconductor substrate, and A conductive substrate can be used. Examples of insulating substrates include glass substrates, quartz substrates, and Fire substrate, stabilized zirconia substrate (such as yttria-stabilized zirconia substrate), resin substrate There are plates and the like. Also, semiconductor substrates are made of materials such as silicon and germanium. Semiconductor substrates, or silicon carbide, silicon germanium, gallium arsenide, phosphate Examples include compound semiconductor substrates composed of zinc, zinc oxide, and gallium oxide. Furthermore, as mentioned above... A semiconductor substrate having an insulating region inside the semiconductor substrate, for example, SOI (Silicon Examples include on-insulator substrates. Conductive substrates include graphite substrates and metal substrates. These include alloy substrates, conductive resin substrates, etc. Alternatively, substrates containing metal nitrides, metal acids There are substrates containing monoxides, etc. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate. A substrate, a semiconductor substrate provided with a conductor or insulator, a conductive substrate provided with a semiconductor or insulator There are substrates with edges provided. Alternatively, substrates on which elements are provided can be used. This may also be done. The elements provided on the substrate may include capacitive elements, resistive elements, switching elements, and light-emitting elements. These include children, memory elements, etc.

[0163] <<Insulator>> Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, and metal oxides. Examples include metal oxides, metal nitrides, and metal nitride oxides.

[0164] For example, as transistors become smaller and more integrated, the gate insulator can be made thinner. This can lead to problems such as leakage current. By using high-k materials, the physical film thickness is maintained while lowering the voltage during transistor operation. This becomes possible. On the other hand, for the insulator that functions as an interlayer film, a material with a low dielectric constant is used. This reduces parasitic capacitance between wires. Therefore, it is possible to reduce the parasitic capacitance that occurs between wires. Then, you should select the materials.

[0165] Furthermore, insulators with high dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. Oxides containing aluminum, aluminum, and hafnium, aluminum and hafnium Oxidized nitrides, silicon and hafnium oxides, silicon and hafnium Examples include oxide nitrides containing um, or nitrides containing silicon and hafnium.

[0166] Furthermore, examples of insulators with low dielectric constant include silicon oxide, silicon oxide nitride, and silicon nitride oxide. Silicon oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, Silicon oxide with added carbon and nitrogen, porous silicon oxide, or resins, etc. be.

[0167] Furthermore, transistors using metal oxides suppress the permeation of impurities such as hydrogen and oxygen. By surrounding it with an insulator that has the function of stabilizing the electrical characteristics of the transistor. This is possible. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, For example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, Phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum An insulator containing fluorine, neodymium, hafnium, or tantalum is used in a single layer or in a multilayer structure. That's all that's needed. Specifically, an insulating material that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As a body, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, acid Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, acid Metal oxides such as tantalum oxide, aluminum nitride, silicon nitride, silicon nitride, etc. Metal nitrides can be used.

[0168] Furthermore, the insulator that functions as a gate insulator has regions containing oxygen that is released by heating. It is preferable that the insulator has a region containing oxygen that is desorbed by heating. By creating a structure in which silicon oxide or silicon oxide nitride is in contact with oxide 230, This can compensate for the oxygen deficiency present in 230.

[0169] <<Conductive material>> Examples of conductive materials include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and crystalline silver. Tun, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Zium, zirconium, beryllium, indium, ruthenium, iridium, strontium A metallic element selected from um, lanthanum, etc., or an alloy containing the aforementioned metallic elements. It is preferable to use an alloy or the like that which combines the above-mentioned metal elements. For example, tantalum nitride Titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Nitrides containing ruthenium, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use oxides containing lanthanum and nickel. Tantalum, titanium nitride, titanium and aluminum nitrides, tantalum and aluminum Includes nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium oxides Oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation, or that absorb oxygen. It is preferable because it is a material that maintains conductivity even when subjected to certain conditions. Furthermore, it does not contain impurity elements such as phosphorus. Highly electrically conductive semiconductors such as polycrystalline silicon and nickel silicides. Silicide may also be used.

[0170] Furthermore, multiple conductive layers formed from the above materials may be stacked and used. For example, as described above. A laminated structure may be formed by combining a material containing a metallic element with a conductive material containing oxygen. Furthermore, a laminate combining the aforementioned metal element-containing material and a nitrogen-containing conductive material is also used. It may also be used as a structure. Furthermore, a material containing the aforementioned metal element, a conductive material containing oxygen, and nitrogen A laminated structure combining conductive materials containing elements may also be used.

[0171] Furthermore, when an oxide is used in the channel formation region of a transistor, the gate electrode and A conductor that functions as such includes a material containing the aforementioned metal element and a conductive material containing oxygen. It is preferable to use a combined laminated structure. In this case, an oxygen-containing conductive material is used. It is preferable to place it on the channel formation region side. A conductive material containing oxygen should be placed on the channel formation region side. This makes it easier for oxygen released from the conductive material to be supplied to the channel-forming region.

[0172] In particular, as a conductor that functions as a gate electrode, it is included in the metal oxide in which the channel is formed. It is preferable to use a conductive material containing metallic elements and oxygen. Conductive materials containing group elements and nitrogen may be used. For example, titanium nitride, tantalum nitride Conductive materials containing nitrogen, such as indium tin oxide and tungsten oxide, may also be used. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium dioxide, indium tin oxide containing titanium dioxide, indium zinc oxide Indium tin oxide with added silicon may also be used. Moogarium zinc oxide may also be used. Using such a material allows for channel formation. In some cases, hydrogen contained in the metal oxide can be captured. Alternatively, the outer atmosphere In some cases, it may be possible to capture hydrogen that has been introduced from surrounding materials.

[0173] <<Metal Oxides>> As oxide 230, a metal oxide (oxide semiconductor) that functions as a semiconductor is used. Preferably. Below, metal oxides applicable to oxide 230 according to one aspect of the present invention are described. I will explain.

[0174] The metal oxide preferably contains at least indium or zinc. In particular, indium Preferably, it contains aluminum and zinc. In addition, aluminum and gallium It is preferable that it contains yttrium, tin, etc. Also, boron, titanium, iron, nitrile Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Ha One or more elements selected from phnium, tantalum, tungsten, magnesium, etc. It may include

[0175] Here, the metal oxide is In-M-Zn oxide, which has indium, element M, and zinc. Let's consider the case where it is a substance. Note that element M is aluminum, gallium, yttrium, and Let M be tin. Other elements that can be used for element M include boron, titanium, iron, and nickel. Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium Examples include um, tantalum, tungsten, and magnesium. However, as for element M, as mentioned above... In some cases, it is acceptable to combine multiple elements.

[0176] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). They are sometimes collectively referred to as metal oxynitrides (metal oxides). Also, metal oxides containing nitrogen are sometimes called metal oxynitrides (metal oxides). It may also be called tal oxynitride.

[0177] [Structure of metal oxides] Oxide semiconductors (metal oxides) include single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. It can be divided into conductors and conductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS, multi-phase crystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous (us-like oxide semiconductors), and amorphous oxide semiconductors It has a body, etc.

[0178] CAAC-OS has c-axis orientation and multiple nanocrystals are linked in the ab-plane direction. It has a crystalline structure that is linked and distorted. Note that distortion refers to the linkage between multiple nanocrystals. Within a region, between a region with a aligned grid arrangement and another region with a aligned grid arrangement, the grid arrangement This refers to the point where the orientation has changed.

[0179] Nanocrystals are based on a hexagonal shape, but they are not necessarily regular hexagons; they can also be non-regular hexagonal. Furthermore, the distortion may have a grid arrangement such as a pentagon or heptagon. In CAAC-OS, even near strain, clear grain boundaries are present. It is difficult to confirm this. In other words, the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. It can be seen that it is controlled. This is because CAAC-OS has oxygen atoms in the ab plane direction. The arrangement of atoms is not dense, and the substitution of metal elements changes the bond distance between atoms. This is because distortion can be tolerated through various means.

[0180] Furthermore, CAAC-OS consists of a layer containing indium and oxygen (hereinafter referred to as the In layer), and A layered crystal in which layers containing element M, zinc, and oxygen (hereinafter referred to as (M,Zn) layers) are stacked. It tends to have a structure (also called a layered structure). Note that indium and element M are relative to each other. It is interchangeable, and if element M in the (M,Zn) layer is replaced with indium, then (In,M,Zn It can also be represented as a layer. Furthermore, if the indium in the In layer is replaced by element M, (In, It can also be represented as layer M.

[0181] CAAC-OS is a highly crystalline metal oxide. On the other hand, CAAC-OS has a clear bond. Because it is difficult to confirm grain boundaries, a decrease in electron mobility caused by grain boundaries is less likely to occur. It can be said that... Also, the crystallinity of metal oxides decreases due to the inclusion of impurities and the formation of defects. Because this can sometimes occur, CAAC-OS is a metal oxide with few impurities or defects (such as oxygen deficiencies). It can also be said that metal oxides containing CAAC-OS have stable physical properties. Therefore, metal oxides containing CAAC-OS are heat-resistant and highly reliable.

[0182] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially regions larger than 1 nm). It has periodicity in the atomic arrangement in the region of 3 nm or less. Also, nc-OS has different na No regularity is observed in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analytical method, nc-OS may be a-like OS or amorphous oxide semiconductor. It can sometimes be indistinguishable from the body.

[0183] Furthermore, In- is a type of metal oxide containing indium, gallium, and zinc. Ga-Zn oxide (hereinafter referred to as IGZO) adopts a stable structure when formed into the nanocrystals described above. In some cases, IGZO tends to have difficulty growing crystals in the atmosphere, so large bonds may form. Crystals smaller than crystals (here, crystals of several millimeters or several centimeters) (for example, as mentioned above) In some cases, forming the material into nanocrystals can result in a more structurally stable material.

[0184] a-like OS is a metallic acid having a structure between nc-OS and amorphous oxide semiconductors. It is a monster. a-like OS has porous or low-density regions. That is, a-li ke OS has lower crystallinity compared to nc-OS and CAAC-OS.

[0185] Oxide semiconductors (metal oxides) can take on diverse structures, each possessing different properties. An oxide semiconductor according to one aspect of the present invention is an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, and a-li It may have two or more of the following: ke OS, nc-OS, and CAAC-OS.

[0186] [impurities] Here, we will explain the effects of various impurities in metal oxides.

[0187] When impurities are introduced into oxide semiconductors, defect levels or oxygen vacancies may be formed. Therefore, when impurities are mixed into the channel formation region of the oxide semiconductor, the oxide semiconductor is affected. The electrical characteristics of the transistors used can be prone to fluctuations, which can lead to poor reliability. If the channel formation region contains oxygen vacancies, the transistor will exhibit normally-on characteristics. It's cheap.

[0188] Transistors using metal oxides are affected by impurities and oxygen vacancies in the metal oxide. The electrical characteristics fluctuate, and the normally-on characteristics (even without applying voltage to the gate electrode) are affected. In addition, suitable metal oxides exist, which makes it easy for current to flow through the transistor. If the transistor is driven while it has an excess of oxygen exceeding the specified value, the excess oxygen will When the valence of the child changes, the electrical characteristics of the transistor fluctuate, leading to a decrease in reliability. There is.

[0189] Therefore, transistors use metal oxides with low carrier concentrations in the channel formation region. It is preferable to use it. When the carrier concentration of metal oxide is low, metal oxide The solution is to lower the concentration of impurities in the material and reduce the defect level density. In this specification, impurities A substance with a low concentration of material and a low defect level density is called a high-purity intrinsic or substantially high-purity intrinsic substance. In this specification, the carrier concentration of the metal oxide in the channel-forming region is 1 × 10⁻⁶. 16 cm -3 The following cases are defined as substantially high-purity genuine:

[0190] Furthermore, the carrier concentration of the metal oxide in the channel-forming region is 1 × 10⁻⁶ 18 cm -3 Below It is preferable that there be a 1 × 10 17 cm -3 More preferably, 1 × 10 1 6 cm -3 It is even more preferable that the following conditions apply: 1 × 10 13 cm -3 Being less than More preferably, 1 × 10 12 cm -3 It is even more preferable that it be less than [a certain value]. There are no particular limitations on the lower limit of the carrier concentration of the metal oxide in the formation region, but for example, 1 x 10 -9 cm -3 It can be done this way.

[0191] Examples of impurities in metal oxides include hydrogen, nitrogen, alkali metals, and alkalis. These include earth metals, iron, nickel, silicon, etc. In particular, hydrogen contained in metal oxides is a metal Because it reacts with oxygen that bonds to atoms to form water, it can sometimes form oxygen vacancies in metal oxides. Yes. If the channel-forming region in the metal oxide contains oxygen vacancies, the transistor will be no - Marione properties may occur. Furthermore, when hydrogen enters the oxygen vacancy in the metal oxide... In combination, oxygen-deficient atoms and hydrogen combine to form V O Sometimes H is formed. A vacancy where hydrogen is placed in an oxygen vacancy. (V O H) can function as a donor, and electrons, which are carriers, may be generated. When some of the hydrogen combines with oxygen that is bonded to a metal atom, it generates electrons, which are carriers. Therefore, transistors using metal oxides that contain a lot of hydrogen are normally It tends to exhibit ionic properties. Also, hydrogen in metal oxides is affected by stress such as heat and electric fields. Because it moves easily, if metal oxides contain a lot of hydrogen, the reliability of transistors deteriorates. There is a risk that this may happen.

[0192] In one embodiment of the present invention, V in oxide 230 O Reduce H as much as possible, high purity intrinsic Alternatively, it is preferable to make it substantially high-purity intrinsic. Thus, V O H was sufficiently reduced. To obtain metal oxides, impurities such as water and hydrogen must be removed from the metal oxide (dehydration). (This is sometimes referred to as dehydrogenation treatment.) This involves supplying oxygen to the metal oxide to compensate for the oxygen deficiency. It is important to do this (sometimes referred to as oxygenation treatment). V O Impurities such as H By using a sufficiently reduced metal oxide in the channel formation region of the transistor, stability is achieved. It is possible to impart specific electrical characteristics.

[0193] A defect in which hydrogen is inserted into an oxygen vacancy (V O H) can function as a donor for metal oxides. However, it is difficult to quantitatively evaluate the defect in metal oxides. In some cases, the evaluation is based on the carrier concentration rather than the donor concentration. Therefore, this specification, etc. So, as a parameter for metal oxides, instead of donor concentration, let's consider the state where no electric field is applied. In some cases, the assumed carrier concentration may be used. That is, the "carrier concentration" described in this specification, etc. " can sometimes be rephrased as "donor concentration." Also, as described in this specification, etc. "Carrier concentration" can be rephrased as "carrier density."

[0194] Therefore, it is preferable that the hydrogen content in the metal oxide be reduced as much as possible. Specifically, In metal oxides, the hydrogen concentration obtained by SIMS is 1 × 10⁻⁶. 20 atom / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Less than and The metal oxide, in which impurities such as hydrogen have been sufficiently reduced, is used in the channel formation region of the transistor. By using it in this region, stable electrical characteristics can be imparted.

[0195] Furthermore, the above defect levels may include trap levels. (Metal oxide traps) Charges trapped in energy levels take a long time to disappear, almost like fixed charges. This behavior can occur. Therefore, metal oxides with a high trap level density can form channels in the channel formation region. The transistors in this device may exhibit unstable electrical characteristics.

[0196] Furthermore, if impurities are present in the channel formation region of an oxide semiconductor, the channel formation region will Crystallinity may be low, and the crystallinity of the oxide provided in contact with the channel formation region The value may be low. If the crystallinity of the channel formation region is low, the stability of the transistor may also be affected. This tends to worsen reliability. Also, the oxide formation adjacent to the channel formation region If the crystallinity is low, interface states may form, which can worsen the stability or reliability of the transistor. There is.

[0197] Therefore, in order to improve the stability or reliability of transistors, oxide semiconductor chips Reducing the impurity concentration in the channel formation region and its vicinity is effective. These include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and others. Metal oxides with reduced impurity concentrations have a lower defect level density, and therefore a lower trap level density. This can happen.

[0198] <<Other Semiconductor Materials>> The semiconductor materials that can be used for oxide 230 are not limited to the metal oxides mentioned above. As monster 230, semiconductor materials with a band gap (not zero-gap semiconductors) Conductive materials may be used. For example, semiconductors of elemental silicon, gallium arsenide, etc. Which compound semiconductors, layered materials that function as semiconductors (also known as atomic layer materials, two-dimensional materials, etc.) It is preferable to use materials such as (u) as semiconductor materials. In particular, layered materials that function as semiconductors It is preferable to use this as a semiconductor material.

[0199] Here, in this specification, etc., "layered material" is a general term for a group of materials having a layered crystalline structure. Yes, it exists. Layered crystal structures are formed by layers created by covalent or ionic bonds, such as van der Wa. It is a structure in which layers are attached via weaker bonds than covalent or ionic bonds, such as the Ruhls force. Layered materials have high electrical conductivity within a single layer, meaning they have high two-dimensional electrical conductivity. A material that functions as a semiconductor and has high two-dimensional electrical conductivity is used in the channel formation region. This makes it possible to provide transistors with a large on-current.

[0200] Examples of layered materials include graphene, silicene, and chalcogenides. It is a compound containing chalcogens. Furthermore, chalcogens are a general term for elements belonging to Group 16. It contains oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides. .

[0201] For example, a transition metal chalcogenide that functions as a semiconductor can be used as oxide 230. Preferably, a transition metal chalcogenide applicable as oxide 230 is specified. These include molybdenum sulfide (typically MoS2) and molybdenum selenide (typically MoS2) e2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically W S2), tungsten selenide (typically WSe2), tungsten tellurium (typically (WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically (HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (alternative) Examples include ZrSe2).

[0202] <Method for fabricating semiconductor devices> Next, Figure 4 shows a method for manufacturing a semiconductor device, which is one embodiment of the present invention, as shown in Figures 1A to 1D. This will be explained using Figures A through 11D.

[0203] Figures 4A, 5A, 6A, 7A, 8A, 9A, 10A, and 11A show the top view. Figures are shown. Also, Figures 4B, 5B, 6B, 7B, 8B, 9B, 10B, and Figure 11B corresponds to Figures 4A, 5A, 6A, 7A, 8A, 9A, 10A, and This is a cross-sectional view corresponding to the area shown by the dashed line A1-A2 in Figure 11A, and is a transistor. This is also a cross-sectional view of the channel in the direction of the channel length of 200. Also, Figures 4C, 5C, 6C, 7C, and Figures 8C, 9C, 10C, and 11C are derived from Figures 4A, 5A, 6A, and 7A, respectively. This corresponds to the area indicated by the dashed line A3-A4 in Figures 8A, 9A, 10A, and 11A. This is a cross-sectional view, and is also a cross-sectional view of transistor 200 in the channel width direction. Also, Figure 4 Figures D, 5D, 6D, 7D, 8D, 9D, 10D, and 11D are, respectively, Figures 4A, 5A, 6A, 7A, 8A, 9A, 10A, and 11A show A5- This is a cross-sectional view of the area indicated by the dashed line in A6. Note that Figures 4A, 5A, 6A, 7A, and In the top views of 8A, 9A, 10A, and 11A, some elements are omitted for clarity. It is omitted.

[0204] First, a substrate (not shown) is prepared, and an insulator 212 is deposited on the substrate. The deposition of 212 can be done by sputtering, CVD, or molecular beam epitaxy (MBE). cular beam epitaxy (PLD) method, pulsed laser deposition (PLD) This can be done using methods such as laser deposition or ALD.

[0205] Furthermore, the CVD method is a type of plasma CVD (PECVD) that utilizes plasma. Enhanced CVD (Enhanced CVD), Thermal CVD (TCVD: Thermal CCVD) which utilizes heat. It can be classified into methods such as the VD method and the photoCVD method which utilizes light. Depending on the source gas used, the process can be metal CVD (MCVD) or organometallic CVD. It can be divided into (MOCVD: Metal Organic CVD) methods.

[0206] Plasma CVD can produce high-quality films at relatively low temperatures. Thermal CVD, on the other hand, is a method that can produce high-quality films at low temperatures. A film deposition method that does not use Zuma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) included in semiconductor devices. ) and others can be charged up by receiving an electric charge from the plasma. In cases where the accumulated charge destroys the wiring, electrodes, and elements contained in the semiconductor device. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage occurs. Therefore, the yield of semiconductor devices can be increased. Also, in the thermal CVD method, Because plasma damage does not occur within the film, a film with fewer defects can be obtained.

[0207] Furthermore, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer. This allows for the deposition of extremely thin films, enabling film deposition on structures with high aspect ratios, and pinholes. It enables film formation with fewer defects such as blemishes, enables film formation with excellent coverage, and enables film formation at low temperatures. What are the effects? Also, the ALD method includes PEALD (Plasma), which utilizes plasma. This also includes the Enhanced ALD method. By using plasma, it is possible to perform the process at lower temperatures. A film can be formed, which is preferable in some cases. Note that the precursor used in the ALD method may contain carbon, etc. Some contain impurities. For this reason, films formed by the ALD method may not be suitable for other film formation methods. Compared to the prepared film, it may contain more impurities such as carbon. Furthermore, the quantitative determination of impurities... X-ray photoelectron spectroscopy (XPS) This can be done using roscopy.

[0208] CVD and ALD are film deposition methods in which particles emitted from a target or other source are deposited. Unlike other methods, this is a film-forming method in which a film is formed by a reaction on the surface of the object being treated. This film-forming method is less affected by the shape of the workpiece and has good step-level coverage. Furthermore, the ALD method has excellent step coverage and excellent thickness uniformity, thus aspect ratio This method is suitable for coating the surface of high-aperture openings, etc. However, the ALD method is relatively suitable for film formation. Because of its slow rate, it should be used in combination with other film deposition methods that have a faster deposition rate, such as CVD. In some cases, this may be preferable.

[0209] The CVD and ALD methods control the composition of the resulting film by adjusting the flow rate ratio of the source gases. This is possible. For example, in the CVD method and ALD method, the flow rate ratio of the raw material gas can be adjusted as needed. A film with the following composition can be formed. Furthermore, for example, in the CVD method and ALD method, film formation can be performed. By changing the flow rate ratio of the raw material gas while simultaneously depositing a film with a continuously changing composition. This is possible. When forming a film while changing the flow rate ratio of the raw material gas, multiple deposition chambers can be used. Compared to the method of film deposition using a conveyor belt, it eliminates the time required for transport and pressure adjustment, thus reducing the time required for film deposition. The interval can be shortened. Therefore, the productivity of semiconductor devices can be increased. There is.

[0210] In this embodiment, silicon nitride is deposited as the insulator 212 by the CVD method. Thus, as the insulator 212, an insulator that is impermeable to copper, such as silicon nitride, is used. This allows easily diffusible metals such as copper to penetrate the conductor layer (not shown) below the insulator 212. Even when used, it is possible to suppress the upward diffusion of the metal through the insulator 212. Furthermore, by using an insulator that is less permeable to impurities such as water and hydrogen, such as silicon nitride... This makes it possible to suppress the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212. Cut.

[0211] Next, an insulator 214 is deposited on the insulator 212. The insulator 214 is deposited by sputtering. This can be performed using methods such as the vaping method, CVD method, MBE method, PLD method, and ALD method. In this application, aluminum oxide is used as the insulator 214.

[0212] Next, an insulator 216 is deposited on the insulator 214. The insulator 216 is deposited by sputtering. This can be performed using methods such as the vaping method, CVD method, MBE method, PLD method, and ALD method.

[0213] Next, an opening is formed in the insulator 216 that reaches the insulator 214. An opening is, for example, a groove or This also includes slits, etc. Furthermore, the term "opening" can sometimes refer to the area where an opening has been formed. The opening can be formed using wet etching, but dry etching is preferable. This is preferable for microfabrication. In addition, the insulator 214 forms grooves by etching the insulator 216. It is preferable to select an insulator that functions as an etching stopper film during the etching process. When silicon oxide is used for the insulator 216 that forms the groove, the insulator 214 is silicon nitride. Aluminum oxide and hafnium oxide are good choices.

[0214] As a dry etching apparatus, a capacitively coupled plasma (CCP) system with parallel plate electrodes is used. (Capacitively Coupled Plasma) Etching apparatus is used. Capacitively coupled plasma etching apparatus having parallel plate electrodes can be used. Alternatively, a high-frequency voltage may be applied to one electrode of the type electrode. Or, one of the parallel plate type electrodes. Alternatively, a configuration in which multiple different high-frequency voltages are applied to the electrodes may be used. Or a parallel plate type electrode Alternatively, a configuration in which the same high-frequency voltage is applied to each of them is also possible. Alternatively, a configuration in which high-frequency voltages of different frequencies are applied may be used. Or, a high-density plasma source may be used. A dry etching apparatus can be used. Dry etching with a high-density plasma source. The device is, for example, an inductively coupled plasma (ICP) device. Etching equipment such as an ed Plasma etching device can be used.

[0215] After the opening is formed, a conductive film that will become the conductor 205a is formed. The conductive film allows oxygen to permeate. It is desirable to include a conductor that has a suppressive function. For example, tantalum nitride, tan nitride Gusten, titanium nitride, etc. can be used. Alternatively, a function to suppress oxygen permeation can be used. Conductors possessing tantalum, tungsten, titanium, molybdenum, aluminum, copper, and It can be formed as a laminated film with a rib-den tungsten alloy. The conductive film is deposited by sputtering. This can be performed using methods such as the ring method, CVD method, MBE method, PLD method, and ALD method.

[0216] In this embodiment, the conductive film that becomes the conductor 205a has a multilayer structure. First, sputtering A tantalum nitride film is formed by a tangent molding process, and titanium nitride is then laminated on top of the tantalum nitride film. By using such a metal nitride as the lower layer of the conductor 205b, the conductor 20 described later Even if a diffusible metal such as copper is used as the conductive film for 5b, if the metal is conductor 205 This can prevent diffusion from a to the outside.

[0217] Next, a conductive film that will become the conductor 205b is formed. The formation of this conductive film is done by plating, spalling, etc. This can be done using methods such as Taring, CVD, MBE, PLD, and ALD. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film.

[0218] Next, by performing CMP treatment, a conductive film that becomes conductor 205a and conductor 205b are formed. A portion of the conductive film is removed, exposing the insulator 216. As a result, only the opening is conductive. Body 205a and conductor 205b remain. As a result, the top surface of conductor 205 is flat. This can form (see Figures 4B to 4D). Furthermore, this CMP process can create an absolute A portion of the edge 216 may be removed.

[0219] In the above, the conductor 205 was formed to be embedded in the opening of the insulator 216. However, this embodiment is not limited to this. For example, a conductor 20 on an insulator 214 Form 5, deposit an insulator 216 on the conductor 205, and perform CMP treatment on the insulator 216. This means that a portion of the insulator 216 can be removed, exposing the surface of the conductor 205.

[0220] Next, an insulator 222 is formed on the insulator 216 and the conductor 205. As such, an insulating film containing an oxide of aluminum and / or hafnium is formed. It is good to do so. Insulators containing oxides of aluminum and / or hafnium are acid It has barrier properties against hydrogen and water. The insulator 222 has barrier properties against hydrogen and water. Due to its barrier properties, the hydrogen contained in the structure provided around transistor 200 , and the diffusion of water into the transistor 200 through the insulator 222 is suppressed. This makes it possible to suppress the formation of oxygen vacancies in oxide 230.

[0221] The insulator 222 was deposited using sputtering, CVD, MBE, PLD, and ALD methods. This can be done using methods such as [mention specific methods].

[0222] Next, it is preferable to perform a heat treatment. The heat treatment is preferably performed at a temperature of 250°C to 650°C. It is preferable to carry it out at a temperature of 300°C to 500°C, and more preferably at 320°C to 450°C. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or with an oxidizing gas for 10 minutes. The process should be carried out in an atmosphere containing ppm or more, 1% or more, or 10% or more. Furthermore, the heat treatment should be performed under reduced pressure. It may be carried out in a normal state. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere. After processing, to replenish the removed oxygen, an oxidizing gas is added at a concentration of 10 ppm or more, 1% or more, Heat treatment may be carried out in an atmosphere containing 10% or more of the substance.

[0223] In this embodiment, as a heat treatment, after the insulator 222 is formed, it is heated in a nitrogen atmosphere at 400°C. After processing at this temperature for 1 hour, the following process is carried out continuously in an oxygen atmosphere at 400°C for 1 hour. The process is carried out. This heat treatment removes impurities such as water and hydrogen contained in the insulator 222. It is possible to remove it, etc. Also, the heat treatment can be performed at a timing such as after the film formation of the insulator 224. It is also possible to do so.

[0224] Next, an insulator 224 is deposited on the insulator 222. The insulator 224 is deposited by sputtering. This can be performed using methods such as the vaping method, CVD method, MBE method, PLD method, and ALD method. In this application, a silicon oxidizride film is formed as the insulator 224 by the CVD method.

[0225] Here, in order to form an excess oxygen region in the insulator 224, a plasma containing oxygen is used under reduced pressure. Plasma treatment may be performed. Oxygen-containing plasma treatment can be performed, for example, using high-density microwaves. It is preferable to use a device that has a power supply for generating rasma. Alternatively, RF( It may have a power supply that applies radio frequency. By doing so, high-density oxygen radicals can be generated, and RF can be applied to the substrate side. This efficiently guides the oxygen radicals generated by the high-density plasma into the insulator 224. This is possible. Alternatively, after performing plasma treatment with an inert gas using this device, Plasma treatment containing oxygen may be performed to replenish the desorbed oxygen. By appropriately selecting the processing conditions, impurities such as water and hydrogen contained in the insulator 224 can be removed. It can be removed. In that case, heat treatment is not necessary.

[0226] Here, aluminum oxide is applied to the insulator 224, for example, by sputtering. After film formation, CMP treatment may be performed until the insulator 224 is reached. This process allows for the planarization and smoothing of the surface of the insulator 224. By placing nium on the insulator 224 and performing CMP processing, the endpoint detection of the CMP processing can be easily performed. It becomes easy. Also, due to the CMP treatment, a part of the insulator 224 is polished, and the insulator 224 The film thickness may become thin, but this can be corrected by adjusting the film thickness during the deposition of the insulator 224. 224 Planarizing and smoothing the surface prevents deterioration of the coverage of the oxide film that will be deposited later. This can sometimes prevent a decrease in the yield of semiconductor devices. Also, on the insulator 224 Then, by forming an aluminum oxide film using the sputtering method, an insulator 224 It is preferable because oxygen can be added to it.

[0227] Next, oxide films 230A and 230B are sequentially deposited on the insulator 224 (Figure 4B). See Figure 4D. Note that oxide films 230A and 230B are not exposed to the atmospheric environment. It is preferable to deposit the film continuously. By depositing the film without opening to the atmosphere, the oxide film 230A and to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230B. This allows the vicinity of the interface between oxide film 230A and oxide film 230B to be kept clean.

[0228] The oxide films 230A and 230B were deposited by sputtering, CVD, and MBE. This can be done using methods such as the PLD method and the ALD method.

[0229] For example, oxide film 230A and oxide film 230B are deposited by sputtering. In this case, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen in the puttering gas, excess oxygen in the formed oxide film... This can increase the amount. Also, when the above oxide film is deposited by sputtering: The above-mentioned In-M-Zn oxide targets can be used.

[0230] In particular, during the deposition of oxide film 230A, some of the oxygen contained in the sputtering gas acts as an insulator. It may be supplied to 224. Therefore, the oxygen contained in the sputtering gas The percentage should be 70% or more, preferably 80% or more, and more preferably 100%.

[0231] Furthermore, when forming oxide film 230B by sputtering, the sputtering gas contains The proportion of oxygen is greater than 30% and less than or equal to 100%, preferably between 70% and 100%. When a film is formed using this method, an oxygen-rich oxide semiconductor is created. The transistors used in the channel formation region offer relatively high reliability. However, this generation One aspect of the present invention is not limited thereto. When the oxide film 230B is formed by sputtering, The proportion of oxygen in the sputtering gas should be 1% or more and 30% or less, preferably 5% or more. When the film is deposited with an oxygen content of 0% or less, an oxygen-deficient oxide semiconductor is formed. Transistors using a monocrystalline semiconductor in the channel formation region can achieve relatively high field-effect mobility. Furthermore, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved. It can be done.

[0232] In this embodiment, the oxide film 230A is formed by sputtering, using the In:Ga: The film is deposited using an oxide target with a Zn = 1:3:4 [atomic ratio]. Also, oxide film 23 As 0B, by sputtering, In:Ga:Zn=4:2:4.1 [atomic ratio] The film is deposited using the oxide target of ]. Note that each oxide film is formed under different deposition conditions and atomic ratios. By selecting appropriately, the desired properties for oxide 230a and oxide 230b can be determined. It is good to form it.

[0233] Furthermore, the insulator 222, insulator 224, oxide film 230A, and oxide film 230B are exposed to air. It is preferable to deposit the film without exposure to the elements. For example, a multi-chamber type film deposition apparatus. You can use it.

[0234] Next, a heat treatment may be performed. This heat treatment may be carried out using the heat treatment conditions described above. This can be achieved. This heat treatment removes the water and hydrogen from the oxide film 230A and oxide film 230B. It is possible to remove impurities such as those mentioned above. In this embodiment, at 400°C in a nitrogen atmosphere After processing at this temperature for 1 hour, the following process is carried out continuously in an oxygen atmosphere at 400°C for 1 hour. Perform the process.

[0235] Next, a conductive film 242A is deposited on the oxide film 230B (see Figures 4B to 4D). The deposition of Electrode 242A can be performed using sputtering, CVD, MBE, PLD, ALD, etc. This can be done using [a specific method]. Note that heat treatment may be performed before the formation of the conductive film 242A. The heat treatment is carried out under reduced pressure, and the conductive film 242A is continuously heated without exposure to the atmosphere. A film may be formed. By performing such a treatment, adsorption occurs on the surface of the oxide film 230B, etc. It removes the water and hydrogen present, and further removes the water from oxide film 230A and oxide film 230B. The concentration and hydrogen concentration can be reduced. The heat treatment temperature is 100°C or higher. A temperature of 0°C or lower is preferred. In this embodiment, the heat treatment temperature is set to 200°C.

[0236] Next, using lithography, oxide film 230A, oxide film 230B, and conductive film 2 42A is processed into an island shape to form oxide 230a, oxide 230b, and conductive layer 242B. This process is achieved (see Figures 5A to 5D). Furthermore, this process can be performed using dry etching or wet etching. The etching method can be used. Dry etching is suitable for microfabrication. Furthermore, the processing of oxide film 230A, oxide film 230B, and conductive film 242A is carried out separately. The process may be carried out under different conditions. In addition, in this process, the oxide 230a of the insulator 224 The film thickness may become thinner in areas that do not overlap with other areas.

[0237] In lithography, the resist is first exposed through a mask. Next, exposure... The selected area is removed or left intact using a developer to form a resist mask. Next, By etching through the resist mask, conductors, semiconductors, insulators, etc. It can be processed into the desired shape. For example, KrF excimer laser light, ArF excimer laser Using light such as UV light and EUV (Extreme Ultraviolet) light, A resist mask can be formed by exposing the substrate to the liquid. A liquid immersion technique may be used, in which a body (for example, water) is filled and exposed. Alternatively, instead of the aforementioned light, Furthermore, electron beams or ion beams may be used. In this case, a mask is not necessary. Note that a resist mask is used in dry cleaning such as ashing. Perform etching, wet etching, dry etching followed by wet etching Perform wet etching, or perform dry etching after wet etching. By doing so, it can be removed.

[0238] Alternatively, a hard mask made of an insulator or conductor may be used instead of a resist mask. When using a hard mask, an insulating film or conductive material that will serve as the hard mask material will be placed on the conductive film 242A. Forming a film, forming a resist mask on it, and etching the hard mask material. A hard mask of the desired shape can be formed. Etching of the conductive film 242A is performed. You can either remove the resist mask before proceeding, or you can leave the resist mask in place. i. In the latter case, the resist mask may disappear during etching. Conductive film 242A The hard mask may be removed by etching after etching. If the material does not affect subsequent processes, or can be used in subsequent processes, a hard mask is not necessarily required. There is no need to remove it.

[0239] Here, oxide 230a, oxide 230b, and conductive layer 242B are at least partially It is formed so as to overlap with the conductor 205. Also, oxide 230a, oxide 230b, and Preferably, the side surface of the conductive layer 242B is substantially perpendicular to the upper surface of the insulator 222. The sides of oxide 230a, oxide 230b, and conductive layer 242B are on the upper surface of insulator 222. In contrast, being nearly perpendicular allows for miniaturization and high density when installing multiple transistors 200. This makes it possible to change the temperature. Also, the sides of oxide 230a, oxide 230b, and conductive layer 242B The angle between the surface and the upper surface of the insulator 222 may be set to a low angle. In that case, acid The sides of the oxide 230a, oxide 230b, and conductive layer 242B, and the upper surface of the insulator 222 The angle formed is preferably 60 degrees or more and less than 70 degrees. By adopting this shape, the subsequent In the process, the coating properties of the insulator 254 and other materials are improved, and defects such as porosity can be reduced. ru.

[0240] Furthermore, there is a curved surface between the side surface of the conductive layer 242B and the upper surface of the conductive layer 242B. Furthermore, it is preferable that the ends of the side surface and the ends of the top surface are curved. The curved surface is, for example If, at the end of the conductive layer 242B, the radius of curvature is 3 nm or more and 10 nm or less, preferably The film thickness should be between 5 nm and 6 nm. By having no corners at the edges, the film will be less likely to be affected in subsequent film deposition processes. The coverage is improved.

[0241] Next, on top of the insulator 224, oxide 230a, oxide 230b, and conductive layer 242B Then, an insulating film 254A is deposited (see Figures 6B to 6D).

[0242] The 254A insulating film is deposited using sputtering, CVD, MBE, PLD, and ALD. This can be done using laws and regulations. The insulating film 254A has the function of suppressing oxygen permeation. It is preferable to use an insulating film. For example, by sputtering or ALD, Aluminum oxide, silicon nitride, silicon oxide, or gallium oxide are deposited as thin films. A film of aluminum oxide is formed by sputtering, and on the aluminum oxide, A Aluminum oxide may be deposited using the LD method.

[0243] Next, an insulating film that will become an insulator 280 is deposited on the insulating film 254A. This is done using sputtering, CVD, MBE, PLD, ALD, etc. This can be done. In this embodiment, the insulating film is made by CVD or sputtering. Therefore, a silicon oxide film is formed. Note that a heat treatment may be performed before the formation of the insulating film. The heat treatment is carried out under reduced pressure, and the insulating film is continuously deposited without exposure to the atmosphere. This is also acceptable. By performing such a process, adsorbed material on the surface of the insulating film 254A may be removed. Removes moisture and hydrogen, and further removes oxide 230a, oxide 230b, and insulator 22 The water and hydrogen concentrations in 4 can be reduced. Using the heat treatment conditions described above... It is possible.

[0244] Furthermore, the insulating film may have a multilayer structure. For example, oxidation by sputtering. A silicon film is formed, and a silicon oxide film is formed on the silicon oxide film by CVD. It may also be structured in this way.

[0245] Next, the insulating film is subjected to CMP treatment to form an insulator 280 with a flat top surface (Figure 6B). (See Figure 6D.)

[0246] Microwave treatment may be performed here. Microwave treatment is performed in an oxygen-containing atmosphere. It is preferable to perform the process under reduced pressure. By performing microwave processing, the microwaves The electric field is applied to the insulator 280, oxide 230b, oxide 230a, etc. b, and V in oxide 230a O H is oxygen-deficient (V O ) and hydrogen (H) can be separated. Yes, it is possible. At this time, some of the hydrogen that is separated combines with the oxygen contained in the insulator 280 to form water molecules. It may be removed as follows. Also, some of the hydrogen is removed through the insulating film 254A to the conductive layer 2 It may gettered into 42B.

[0247] Alternatively, heat treatment may be performed while maintaining a reduced pressure state after microwave treatment. By performing this treatment, hydrogen in the insulator 280, oxide 230b, and oxide 230a is removed. It can efficiently remove [unclear / unclear]. The heat treatment temperature is between 300°C and 500°C. It is preferable to do so.

[0248] Furthermore, by performing microwave treatment, the film quality of the insulator 280 is modified, and hydrogen Therefore, the diffusion of water, impurities, etc. can be suppressed after the formation of the insulator 280. Subsequent processes, such as heat treatment, allow hydrogen, water, and impurities to enter through the insulator 280, which can lead to acid This can suppress the diffusion to the monster 230.

[0249] Next, a portion of the insulator 280, a portion of the insulating film 254A, and a portion of the conductive layer 242B are added. This process forms an opening that reaches oxide 230b. The opening overlaps with the conductor 205. It is preferable to form it in this way. By forming the opening, the insulator 254 and the conductor 242a , and form the conductor 242b (see Figures 7A to 7D).

[0250] In this case, it is preferable to thin the oxide 230b in the region overlapping with the opening. The amount of film loss in the region corresponds to Lc shown in Figure 3B. The oxide 230b in that region is thinned. This suppresses the formation of a low-resistance region near the upper surface of the channel-forming region, thereby preventing the formation of parasitic channels. This can suppress the generation of parasitic channels. Therefore, the transistor characteristics caused by parasitic channels can be suppressed. This can suppress variations.

[0251] Furthermore, it is preferable to remove a portion of the side surface of the oxide 230b in the region overlapping with the opening. The amount of film loss in this region corresponds to We shown in Figure 3B. This results in the channel formation region. This suppresses the formation of low-resistance regions near the sides and inhibits the generation of parasitic channels. Yes, it is possible. Therefore, it is possible to suppress variations in transistor characteristics caused by parasitic channels. can.

[0252] Furthermore, a portion of the insulator 280, a portion of the insulating film 254A, and a portion of the conductive layer 242B are added. The process may be carried out under different conditions. For example, a portion of the insulator 280 may be dry-etched. The insulating film 254A is processed by the etching method, and a portion of it is processed by the wet etching method to create the conductive layer 24 Part of 2B may be processed using the dry etching method.

[0253] Here, impurities such as oxide 230a and oxide 230b that are attached to the surface or diffused into the interior are considered. It is preferable to remove the substance. The impurities include the insulator 280, the insulating film 254A, and and components contained in conductive layer 242B, used in the apparatus used to form the above-mentioned opening Components contained in the material, components contained in the gas or liquid used for etching, etc. Examples of contributing factors include aluminum, silicon, and tungsten. Examples include fluorine and chlorine.

[0254] Washing treatment may be performed to remove the above-mentioned impurities. Washing methods include Wet cleaning using cleaning solutions, plasma treatment using plasma, and cleaning by heat treatment, etc. The above cleaning methods may be combined as appropriate.

[0255] For wet cleaning, use ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, etc., with carbonated water. Alternatively, the cleaning process may be carried out using an aqueous solution diluted with pure water, pure water, carbonated water, etc. Ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. These washing methods may be combined as appropriate.

[0256] Next, a heat treatment may be performed. This heat treatment is preferably carried out in an oxygen-containing atmosphere. Furthermore, the heat treatment is carried out under reduced pressure and without exposure to the atmosphere, continuously forming an oxide film 2 30C may be deposited (see Figures 8A to 8D). By performing such a process... Then, moisture and hydrogen adsorbed on the surface of oxide 230b are removed, and further oxide 2 The water and hydrogen concentrations in 30a and oxide 230b can be reduced. The heat treatment temperature is preferably between 100°C and 400°C. In this embodiment, the heat treatment is Let the temperature be 200°C.

[0257] The 230C oxide film can be deposited using sputtering, CVD, MBE, PLD, or ALD methods. This can be done using the following methods. Depending on the desired properties of the oxide film 230C, the oxide film 230 The oxide film 230C can be formed using the same film formation method as A or oxide film 230B. In this embodiment, the oxide film 230C is formed by sputtering using In:Ga: The film is deposited using an oxide target with an atomic ratio of Zn = 4:2:4.1.

[0258] The oxide film 230C may be layered. For example, by sputtering, The film was deposited using an oxide target with an atomic ratio of n:Ga:Zn=4:2:4.1. Next, a film is deposited using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. That's good too.

[0259] During the deposition of oxide film 230C, some of the oxygen contained in the sputtering gas becomes oxide 230 a and oxide 230b may be supplied. Alternatively, during the formation of oxide film 230C, In some cases, some of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the proportion of oxygen in the sputtering gas of oxide film 230C is preferably 70% or more. It should be 80% or more, more preferably 100%.

[0260] Next, a heat treatment may be performed. The heat treatment shall be carried out under reduced pressure and without exposure to the atmosphere. The insulating film 250A may be deposited continuously (see Figures 8A to 8D). By performing this process, moisture and hydrogen adsorbed on the surface of the oxide film 230C are removed. Furthermore, the water content in oxide 230a, oxide 230b, and oxide film 230C and water The elemental concentration can be reduced. The preferred heat treatment temperature is between 100°C and 400°C. It's nice.

[0261] Insulating film 250A can be produced using methods such as sputtering, CVD, MBE, PLD, and ALD. The film can be formed using the following method. In this embodiment, the insulating film 250A is used in the CVD method. Next, silicon oxidnitride is deposited. The deposition temperature when depositing insulating film 250A is: A temperature of 350°C or higher but less than 450°C is preferred, particularly around 400°C. The insulating film 250A By forming the film at 400°C, an insulating film with fewer impurities can be formed.

[0262] Furthermore, when the insulator 250 has a two-layer laminated structure, the insulating film that is the lower layer of the insulator 250 The insulating film that forms the upper layer of the insulator 250 can be continuously deposited without exposure to the atmospheric environment. Preferably. By forming the film without opening to the atmosphere, the insulating film that becomes the lower layer of the insulator 250, and Impurities or moisture from the atmospheric environment adhere to the insulating film that forms the upper layer of the insulator 250. This can prevent the insulating film that forms the lower layer of the insulator 250 and the insulating film that forms the upper layer of the insulator 250. The vicinity of the interface can be kept clean.

[0263] Here, after the insulating film 250A is formed, the microphone is subjected to an oxygen-containing atmosphere and under reduced pressure. Microwave processing may be performed. By performing microwave processing, the electric field due to microwaves is eliminated. It is applied to edge film 250A, oxide film 230C, oxide 230b, oxide 230a, etc., oxidation V in film 230C, oxide 230b, and oxide 230a O H to V O It separates into hydrogen and It can be broken. At this time, some of the hydrogen that is broken combines with oxygen to form H2O, which is an aqueous solution. Removed from the edge film 250A, oxide film 230C, oxide 230b, and oxide 230a. In some cases, hydrogen is also present in conductor 242 (conductor 242a, and conductor 242 b) Gettering may occur. In this way, by performing microwave treatment, insulation Hydrogen concentration in film 250A, oxide film 230C, oxide 230b, and oxide 230a The degree can be reduced. Also, in oxide 230a, in oxide 230b, and in the oxide film V in 230C O H to V O V that can exist after being separated into hydrogen O Oxygen is supplied to it And V O It can be repaired or compensated for.

[0264] Alternatively, heat treatment may be performed while maintaining a reduced pressure state after microwave treatment. By performing this treatment, the insulating film 250A, the oxide film 230C, the oxide 230b, and Hydrogen can be efficiently removed from the oxide 230a. In addition, some of the hydrogen is conductive. Body 242 (conductors 242a and 242b) may be gettered. Alternatively, the process involves performing a heat treatment multiple times while maintaining a reduced pressure state after microwave treatment. This can be repeated. By repeatedly performing the heat treatment, the oxide film 2 in the insulating film 250A Further efficient removal of hydrogen from 30C, oxide 230b, and oxide 230a. This can be done. It is preferable that the heat treatment temperature be between 300°C and 500°C. .

[0265] Furthermore, by performing microwave processing, the film quality of the insulating film 250A is modified, water The diffusion of elements, water, impurities, etc. can be suppressed. Therefore, the conductive film that becomes the conductor 260 Hydrogen and water are introduced through post-processing such as film formation or heat treatment via the insulator 250. This suppresses the diffusion of impurities into oxide 230b, oxide 230a, etc. Cut.

[0266] Next, conductive film 260A and conductive film 260B are deposited in sequence (see Figures 9A to 9D). The conductive films 260A and 260B were deposited using sputtering, CVD, and MBE methods. This can be done using methods such as the PLD method and the ALD method. In this embodiment, the ALD method is used. A conductive film 260A is formed, and then a conductive film 260B is formed using the CVD method.

[0267] Next, by CMP treatment, oxide film 230C, insulating film 250A, conductive film 260A, and By polishing the conductive film 260B until the insulator 280 is exposed, the oxide 230c , forming an insulator 250 and a conductor 260 (conductor 260a and conductor 260b) (See Figures 10A to 10C.) As a result, oxide 230c becomes oxide 230b It is positioned to cover the inner walls (side walls and bottom surface) of the opening that reaches [the specified depth]. Also, the insulator 250 The oxide 230c is positioned to cover the inner wall of the opening. 60 is positioned to fill the opening via the oxide 230c and the insulator 250. It will be done.

[0268] Next, heat treatment may be performed. In this embodiment, heat treatment is performed at a temperature of 400°C in a nitrogen atmosphere. The process is carried out for 1 hour. This heat treatment reduces the moisture content in the insulators 250 and 280. The temperature and hydrogen concentration can be reduced.

[0269] Next, on oxide 230c, insulator 250, conductor 260, and insulator 280 , an insulator 282 is formed (see Figures 11B to 11D). The deposition of the insulator 282 is performed by s This can be done using methods such as puttering, CVD, MBE, PLD, and ALD. As for the insulator 282, for example, aluminum oxide can be formed by sputtering. It is preferable to form a film. Using the sputtering method, in an oxygen-containing atmosphere, the insulator 282 By performing film formation, oxygen can be added to the insulator 280 while the film is being formed. It is preferable to deposit the insulator 282 while heating the substrate. Also, the conductor 26 By forming an insulator 282 in contact with the upper surface of 0, the insulator will be in contact with the upper surface of 0 during the subsequent heat treatment. This is preferable because it can suppress the absorption of oxygen from 280 into the conductor 260. stomach.

[0270] Next, an insulating film 283 is formed on the insulating film 282 (see Figures 11B to 11D). The film deposition of edge material 283 can be done using sputtering, CVD, MBE, PLD, ALD, etc. This can be done using [a specific method]. As the insulator 283, silicon nitride or silicon oxide nitride It is preferable to form a film of n.

[0271] Next, heat treatment may be performed. In this embodiment, heat treatment is performed at a temperature of 400°C in a nitrogen atmosphere. The process is carried out for 1 hour. This heat treatment causes the acid added by the film formation of the insulator 282 to be removed. The element is diffused into the insulator 280, and further, through the oxide 230c, the oxide 230a, and It can be supplied to oxide 230b. Note that this heat treatment is performed after film formation of insulator 283. This procedure is not limited to this; it may also be performed after the deposition of the insulator 282.

[0272] Next, an insulator 274 may be deposited on the insulator 283. The deposition of the insulator 274 is performed by spa This can be done using methods such as tarring, CVD, MBE, PLD, and ALD. .

[0273] Next, an insulator 281 may be deposited on the insulator 274. The deposition of the insulator 281 is performed by spa This can be done using methods such as tarring, CVD, MBE, PLD, and ALD. For example, silicon nitride can be deposited as the insulator 281 by sputtering. It is preferable.

[0274] Next, insulator 254, insulator 280, insulator 282, insulator 283, insulator 274, An opening is formed in the insulator 281 that reaches the conductors 242a and 242b. The opening can be formed using lithography.

[0275] Next, insulating films that will become insulators 241 (insulators 241a and 241b) are formed. The insulating film is then anisotropically etched to form an insulator 241. The deposition of the insulating film is performed by This can be done using methods such as puttering, CVD, MBE, PLD, and ALD. It is preferable to use an insulating film that has the function of suppressing oxygen permeation as the insulating film. For example, it is preferable to deposit silicon nitride using the PEALD method. Recon is preferable because it has high blocking properties for hydrogen.

[0276] Furthermore, as an anisotropic etching of the insulating film that becomes the insulator 241, for example, dry etching Methods such as the G method can be used. By providing an insulator 241 on the side wall of the opening, oxygen from the outside can be blocked. This suppresses the transmission of the current and prevents oxidation of the conductors 240a and 240b that are to be formed next. This can be done. Also, impurities such as water and hydrogen can be removed from conductors 240a and 240b. It can prevent it from spreading to the outside.

[0277] Next, conductive films that will become conductor 240a and conductor 240b are formed. It is desirable to have a laminated structure that includes a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. It seems so. For example, tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. It can be formed by lamination of do, to, and . The conductive film can be deposited by sputtering or CVD. This can be done using methods such as MBE, PLD, and ALD.

[0278] Next, by performing CMP treatment, the conductive films that become conductor 240a and conductor 240b are formed. A portion is removed to expose the insulator 281. As a result, the conductive film remains only in the aforementioned opening. This makes it possible to form conductors 240a and 240b with flat upper surfaces. (See Figures 1A to 1D.) Note that a portion of the insulator 281 is removed by the CMP treatment. There are cases where this can happen.

[0279] Next, a conductive film to become the conductor 246 is deposited. This conductive film is deposited by sputtering. This can be done using methods such as CVD, MBE, PLD, and ALD.

[0280] Next, a conductive film to become conductor 246 is processed by lithography, resulting in conductor 240a. The conductor 246a that is in contact with the upper surface of the conductor 240b, and the conductor 246b that is in contact with the upper surface of the conductor 240b Form (see Figures 1A to 1D).

[0281] Based on the above, a semiconductor device having the transistor 200 shown in Figures 1A to 1D is fabricated. This is possible. As shown in Figures 4A to 11D, the semiconductor device shown in this embodiment can be operated. By using this manufacturing method, transistor 200 can be produced.

[0282] <Modified examples of semiconductor devices> In the following, using Figures 12A to 12D, and Figures 13A and 13B, this invention An example of a semiconductor device, which is one aspect of the present invention, will be described.

[0283] [Example 1 of a semiconductor device] Figure 12A shows a top view of the semiconductor device. Figure 12B shows a top view of the same part as A1-A2 in Figure 12A. This is a cross-sectional view corresponding to the area indicated by the dashed line. Also, Figure 12C is a cross-sectional view of A3-A4 in Figure 12A. This is a cross-sectional view corresponding to the area indicated by the dashed line. Also, Figure 12D is a cross-sectional view of Figure 12A, A5-A6 This is a cross-sectional view corresponding to the area indicated by the dashed line. In the top view of Figure 12A, for clarity of the figure... Some elements have been omitted for this reason.

[0284] Furthermore, in the semiconductor device shown in Figures 12A to 12D, the <Example of Semiconductor Device Configuration> is shown Structures having the same function as the structures constituting the semiconductor device described above will be denoted by the same reference numeral. Regarding the components of semiconductor devices, the materials used are explained in detail in the section <Examples of Semiconductor Device Configurations>. The materials used can be used.

[0285] The semiconductor devices shown in Figures 12A to 12D are variations of the semiconductor devices shown in Figures 1A to 1D. This is an example. The semiconductor device shown in Figures 12A to 12D is the same as the semiconductor device shown in Figures 1A to 1D. The body device differs in the shape of the insulator 283. Also, oxide 243 (oxide 243a, and It differs in that it has oxide 243b). Also, oxide 230c and insulator 254 This shows a configuration in which it is provided as a two-layer laminated structure.

[0286] In the semiconductor device shown in Figures 12A to 12D, insulator 214, insulator 216, insulator 2 22, insulator 224, insulator 254 (insulator 254a and insulator 254b), insulator 280 and insulator 282 are patterned, and insulator 283 covers them. It is constructed in such a way that the insulator 283 is connected to the top and side surfaces of the insulator 282 and the insulator 2 The side of 80, the side of insulator 254, the side of insulator 224, the side of insulator 222, It is in contact with the side surface of insulator 216, the side surface of insulator 214, and the top surface of insulator 212. Insulators 214, 216, 222, and 222, which include oxide 230 and other materials. 4. Insulators 254, 280, and 282 are insulated from insulator 283 and insulator 212 It is isolated from the outside by this. In other words, transistor 200 is isolated from insulator 283. It is placed within the region sealed by the edge body 212.

[0287] Insulators 212 and 283 contain hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). It is preferable that the insulator 21 has a high function of suppressing the diffusion of water molecules. 2 and the insulator 283 are silicon nitride or oxide nitride, which have higher hydrogen barrier properties. It is preferable to use silicon.

[0288] With the above configuration, hydrogen contained outside the sealed region will enter the sealed region This can prevent contamination inside the container.

[0289] Furthermore, in the transistor 200 shown in Figures 12A to 12D, insulator 212, insulator 2 14. The present invention is shown in which the insulator 283 is provided as a single layer, but the present invention is not limited to this. It is not possible to do this. For example, insulator 212, insulator 214, insulator 283 in two or more layers It may also be configured as a layered structure.

[0290] Furthermore, the transistor 200 shown in Figures 12A to 12D is made of conductor 242 (conductor 24 A function to suppress oxygen permeation is provided between 2a and the conductor 242b) and the oxide 230. It has oxide 243 (oxide 243a and oxide 243b). Source electrode and The permeation of oxygen between the conductor 242, which functions as a drain electrode, and the oxide 230b is suppressed. By arranging oxide 243 which has the function of conductor 242, the space between conductor 242 and oxide 230b is created. This is preferable because it reduces the electrical resistance of transistor 20 This can improve the electrical characteristics of 0 and the reliability of transistor 200.

[0291] As oxide 243, a metal oxide containing element M may be used. In particular, element M is A Luminium, gallium, yttrium, or tin may be used. Oxide 243 is an oxide. It is preferable that the concentration of element M is higher than that of substance 230b. Also, as oxide 243, Gallium may be used. Alternatively, metal acids such as In-M-Zn oxide may be used as oxide 243. A compound may also be used. Specifically, in the metal oxide used in oxide 243, with respect to In The atomic ratio of element M in oxide 230b is the element relative to In in the metal oxide used in oxide 230b. It is preferable that the atomic ratio is greater than that of element M. Also, the film thickness of oxide 243 is 0.5 nm or less. Preferably, the wavelength is 5 nm or less, more preferably 1 nm to 3 nm, and even more preferably 1 nm. The wavelength is between m and 2 nm. Furthermore, it is preferable that oxide 243 is crystalline. If 43 is crystalline, the release of oxygen from the oxide 230 can be effectively suppressed. For example, if oxide 243 has a crystalline structure such as hexagonal, then the acid in oxide 230 In some cases, it may be possible to suppress the release of primary substances.

[0292] Furthermore, in a cross-sectional view of the transistor 200 in the channel length direction, it overlaps with the conductor 260. The lower surface of oxide 230c in the region is oxide 243 (oxide 243a, and oxide 243b To the same extent as the lower surface of ) or of oxide 243 (oxide 243a and oxide 243b) It is preferable that it be lower than the bottom surface. By making it this shape, oxide 230b and oxide Impurities near the interface with 230c are removed, and a low-resistance region is formed near the upper surface of region 234. This can reduce the amount of noise. For example, in a cross-sectional view of transistor 200 in the channel length direction, Then, with the lower surface of the insulator 224 as the reference, the height of the lower surface of the oxide 243 and the conductor 260 The difference between the height of the lower surface of oxide 230c in the overlapping region and is preferably between 0 nm and 10 nm. Or, more preferably, 0 nm to 5 nm, and more preferably 0 nm to 3 nm.

[0293] Furthermore, in the transistor 200 shown in Figures 12A to 12D, the oxide 230c is oxidized This shows a configuration in which material 230c1 and oxide 230c2 are stacked.

[0294] Oxide 230c2 is composed of the metal elements that make up the metal oxide used in oxide 230c1. It is preferable to include at least one, and more preferable to include all of the metal elements. For example, using In-Ga-Zn oxide or In-Zn oxide as oxide 230c1. As oxide 230c2, In-Ga-Zn oxide, Ga-Zn oxide, or Ga-Zn oxide It is good to use lium. This will allow the interface between oxide 230c1 and oxide 230c2 to This can lower the density of defect levels.

[0295] Furthermore, the lower end of the conduction band of oxide 230a and oxide 230c2 is the same as oxide 230b and It is preferable that the oxide 230c1 is closer to the vacuum level than the lower end of the conduction band. In other words, The electron affinity of material 230a and oxide 230c2 is that of oxide 230b and oxide 230 It is preferable that the electron affinity of c1 is smaller than that of oxide 2. A metal oxide that can be used in 30a is used, and oxide 230c1 is used in oxide 230b. It is preferable to use a metal oxide that can be used. In this case, the main carrier In some cases, oxide 230c1, as well as oxide 230b, can be the primary carrier pathway. Yes, it is possible to use a metal oxide that can be used in oxide 230b as oxide 230c1. Therefore, the effective channel length on the upper surface of the channel formation region is suppressed, and the transition This can suppress the decrease in the on-current of the STA200.

[0296] Specifically, as oxide 230c1, In:Ga:Zn=4:2:3 [atomic ratio] Alternatively, metal oxides with an atomic ratio of In:Ga:Zn = 5:1:6, or In-Zn oxide. Using the material, and considering the oxide 230c2, In:Ga:Zn = 1:3:4 [atomic ratio], Ga Gold:Zn=2:1 [atomic ratio], Ga:Zn=2:5 [atomic ratio], or gallium oxide A group oxide can be used.

[0297] Furthermore, oxide 230c2 suppresses oxygen diffusion or permeation more effectively than oxide 230c1. It is preferable that it be a metal oxide. Oxide 23 is placed between the insulator 250 and oxide 230c1. By providing 0c2, the diffusion of oxygen contained in the insulator 280 into the insulator 250 is suppressed. It can be controlled. Therefore, the oxygen can be controlled via oxide 230c1 to oxide 23 It can be efficiently supplied to 0b.

[0298] Furthermore, in the metal oxide used in oxide 230c2, the relationship between the main component metal element and The atomic ratio of In is the main component of the metal oxide used in oxide 230c1. By making the atomic ratio of In to the element smaller, In diffuses towards the insulator 250. It can be suppressed. The insulator 250 functions as a gate insulator, so In is insulated. If mixed into body 250, it will result in transistor performance defects. Therefore, oxide 23 By providing oxide 230c2 between 0c1 and insulator 250, a highly reliable semiconductor device is created. It will become possible to provide a place.

[0299] Note that oxide 230c1 may be provided for each transistor 200. The oxide 230c1 of transistor 200 and the transistor 20 adjacent to transistor 200 It is not necessary for the oxide 230c1 of transistor 0 to be in contact with it. Also, the oxide 2 of transistor 200 30c1 and the oxide 230c1 of transistor 200 adjacent to the transistor 200 in question. The two may be separated. In other words, oxide 230c1 is separated from transistor 200. Even if it is not positioned between the transistor 200 and the adjacent transistor 200 good.

[0300] In a semiconductor device in which multiple transistors 200 are arranged in the channel width direction, With this configuration, oxide 230c is provided independently for each transistor 200. Therefore, transistor 200 and transistor 2 adjacent to transistor 200. This suppresses the formation of parasitic transistors between 00 and 00, and prevents the formation of the above-mentioned leakage path. Therefore, it is possible to have good electrical properties and miniaturize or highly integrate it. We can provide a suitable semiconductor device.

[0301] For example, in the channel width direction of transistor 200, the transistors facing each other The side edge of the oxide 230c1 of transistor 200 and the transistor adjacent to the transistor 200 If we represent the distance L1 from the side edge of oxide 230c1 of STA200, then L1 is greater than 0nm. Also, in the channel width direction of transistor 200, the opposite of each other , the side end of the oxide 230a of transistor 200 and adjacent to the transistor 200 If we represent the distance between transistor 200 and the side edge of oxide 230a as L2, then relative to L2 The ratio of L1 (L1 / L2) is preferably greater than 0 and less than 1, more preferably 0. It is 1 or more and 0.9 or less, more preferably 0.2 or more and 0.8 or less. Note that L2 is mutual The side end of the oxide 230b of transistor 200 and the transistor 20 This could also be the distance between 0 and the side edge of the oxide 230b of the transistor 200 adjacent to it.

[0302] By reducing the ratio of L1 to L2 (L1 / L2) as described above, oxide 230c1 between transistor 200 and the transistor 200 adjacent to that transistor 200 Even if a misalignment occurs in the region that is not placed, the oxide 230c1 of transistor 200 and The oxide 230c1 of the transistor 200 adjacent to the transistor 200 is separated. It is possible.

[0303] Furthermore, by increasing the ratio of L1 to L2 (L1 / L2) as described above, the transistor Even if the distance between transistor 200 and the transistor 200 adjacent to that transistor 200 is narrowed, This ensures the minimum processing width, enabling further miniaturization or high integration of semiconductor devices. It can be measured.

[0304] Furthermore, the conductor 260, the insulator 250, and the oxide 230c2 are each adjacent to each other. It may be used in common among the transistors 200. That is, the conductor 26 of the transistor 200 0 is continuous with the conductor 260 of the transistor 200 adjacent to the transistor 200. It has a provided region. In addition, the insulator 250 of the transistor 200 It has a region that is continuous with the insulator 250 of the transistor 200 adjacent to the transistor 200. Furthermore, the oxide 230c2 of transistor 200 is adjacent to the transistor 200. The transistor 200 has a region that is continuously provided with the oxide 230c2.

[0305] Furthermore, with the above configuration, the oxide 230c2 is connected to the transistor 200 and the transistor There is a region between the transistor 200 and the adjacent transistor 200 that is in contact with the insulator 224. do.

[0306] Furthermore, similar to oxide 230c1, oxide 230c2 of transistor 200 and the said Even when separated, the oxide 230c2 of transistor 200 adjacent to transistor 200 remains intact. Good. At this time, the insulator 250 is adjacent to the transistor 200. There is a region in contact with the insulator 224 between the transistor 200 and the insulator 224.

[0307] Furthermore, in the transistor 200 shown in Figures 12A to 12D, the insulator 254 is an insulator This shows a configuration in which 254a and insulator 254b are stacked. Details regarding the materials and film deposition method of the insulator 254b are described in <Detailed Configuration of the Semiconductor Device>. You can refer to the descriptions of the lower layer and the upper layer of the insulator 254 provided below.

[0308] Furthermore, without providing the insulator 254, a barrier layer is placed between the upper surface of the conductor 242 and the insulator 280. An insulator that functions as such may be provided. With this configuration, the conductor 242 provides insulation. The absorption of excess oxygen present in the edge 280 can be suppressed. In addition, oxidation of the conductor 242 By suppressing this, the increase in contact resistance between transistor 200 and the wiring is suppressed. This is possible. Therefore, good electrical characteristics and reliability can be given to transistor 200. Cut.

[0309] Therefore, it is preferable that the above-mentioned insulator has the function of suppressing the diffusion of oxygen. For example If so, it is preferable that the above-mentioned insulator has a function that suppresses oxygen diffusion more effectively than insulator 280. stomach.

[0310] Examples of the above insulators include the oxidation of one or both aluminum and hafnium. It is preferable to deposit an insulating film containing a substance. In particular, when aluminum oxide is deposited by the ALD method... Good. By forming it using the ALD method, a dense material is produced with fewer defects such as cracks and pinholes. A film with reduced or uniform thickness can be formed. Also, as an insulator For example, an insulator containing aluminum nitride can be used.

[0311] [Modified example of semiconductor device 2] Figures 13(A) and 13(B) show multiple transistors (transistor 200_1). The transistor 200_n) is enclosed and sealed with insulator 283 and insulator 212. The configuration is shown below. Note that in Figures 13(A) and 13(B), transistor 2 Transistors 00_1 through 200_n appear to be aligned in the direction of the channel length, This is not the only example. Transistors 200_1 through 200_n are They may be arranged in the channel width direction, or in a matrix, or by a rule They may be placed without specifying a gender.

[0312] As shown in Figure 13(A), multiple transistors (transistor 200_1 to transistor 200_1) Outside of the ZISTA 200_n), the portion where the insulator 283 and the insulator 212 are in contact (hereinafter, A sealing portion 265 (sometimes referred to as a sealing portion 265) is formed. The sealing portion 265 is formed by the multiple traps. It is formed to surround the transistor (also called a group of transistors). By doing so, the multiple transistors are enclosed in insulators 283 and 212. This can be done. In other words, the four sides and top of the multiple transistors are insulated by insulator 283. The insulator 281 can be surrounded by the insulator 212 below. In this way, the sealing portion 2 Multiple transistor groups, each enclosed by a 65, will be provided on the circuit board.

[0313] Here, the distance between the sealing portion 265 and the oxide 230 closest to the sealing portion 265 is short. This is preferable. For example, the distance between the sealing portion 265 and the oxide 230 closest to the sealing portion 265. The thickness is preferably 1 μm or less, and more preferably 500 nm or less. Therefore, the volume of the insulator 280 that is sealed in the insulator 283 can be reduced, The amount of hydrogen contained in the insulator 280 can be reduced.

[0314] Also, a dicing line (scribe line, division line, or A cutting line may be provided. The above substrate is divided at the dicing line. Because it is disconnected, the group of transistors surrounded by the sealing portion 265 can be extracted as a single chip. It will become that.

[0315] Furthermore, in Figure 13(A), multiple transistors (transistor 200_1 to Transistor 200_1) An example has been shown in which the sta 200_n) is surrounded by a single sealing portion 265, but this is not the only example. No. As shown in Figure 13(B), multiple transistors (transistor 200_1) The transistor 200_n) may be surrounded by multiple sealing parts. In Figure 13(B), The multiple transistors are surrounded by the sealing portion 265a, and further surrounded by the outer sealing portion 265b. It is structured in such a way.

[0316] In this way, multiple transistors (transistor 200_1 to transistor 200_1) are enclosed in multiple sealing portions. By surrounding the zista 200_n), the part where the insulator 283 and the insulator 212 are in contact This increases the adhesion between insulator 283 and insulator 212, thereby further improving the adhesion between them. This allows for more reliable sealing of the multiple transistors.

[0317] In this case, even if a dicing line is provided overlapping the sealing portion 265a or the sealing portion 265b Alternatively, a dicing line may be provided between the sealing portion 265a and the sealing portion 265b.

[0318] In Figures 13A and 13B, the insulator 212 is insulated from the layer below the insulator 212. This shows a configuration in which the upper layer of the body 212 is laminated. For example, the lower layer of the insulator 212 is A silicon nitride film is formed by the PECVD method, and sputtering is applied as the upper layer of the insulator 212. Silicon nitride is deposited using the G method. This creates a layer beneath the insulator 212. Because it can be deposited at a faster rate than the upper layer, productivity can be improved. The hydrogen concentration in the upper layer of the insulator 212, which is positioned closer to the oxide 230 than the lower layer of the body 212, This can be reduced from the lower layer of the insulator 212. Thus, as the insulator 212, nitrogen By using an insulator that is resistant to the permeability of impurities such as water and hydrogen, such as silicon dioxide, insulation is achieved. The diffusion of impurities such as water and hydrogen from the layer below body 212 (not shown) can be suppressed. Furthermore, as the insulator 212, an insulator that copper does not easily permeate, such as silicon nitride, is used. Therefore, even if a diffusive metal such as copper is used in the conductor below the insulator 212, the gold This can suppress the upward diffusion of the compound through the insulator 212.

[0319] Furthermore, the above configuration is not limited to the lower layer or upper layer of the insulator 212. A single-layer structure with either one of them may also be used. Also, in Figures 13A and 13B, The structure is designed to include an insulator 214, but it is not limited to this, and the insulator 214 can be provided It's also acceptable to omit the structure altogether.

[0320] According to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics is provided. This is possible. Furthermore, according to one aspect of the present invention, a semiconductor device with a large on-current is provided. This is possible. Furthermore, according to one aspect of the present invention, a semiconductor device having good electrical characteristics is provided. This is possible. Furthermore, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated is possible. This can provide a semiconductor device with good reliability according to one aspect of the present invention. It can be provided. Furthermore, according to one aspect of the present invention, a low-power semiconductor device can be provided. It is possible.

[0321] The configurations and methods described in this embodiment are similar to those described in other embodiments and examples. It can be used in appropriate combination with other methods, etc.

[0322] (Embodiment 2) In this embodiment, one form of a semiconductor device will be described with reference to Figures 14 and 15.

[0323] [Storage device 1] Figure 14 shows an example of a semiconductor device (storage device) using a semiconductor device according to one aspect of the present invention. As shown. In one aspect of the present invention, a semiconductor device is provided in which transistor 200 is above transistor 300. The capacitive element 100 is provided on the side, and is above the transistor 300 and the transistor 200. It is provided in [location]. Note that transistor 200 is the same as the transistor described in the previous embodiment. Transistor 200 can be used. Therefore, transistor 200 and transistor With regard to the layer containing 200, the description of the previous embodiment can be considered.

[0324] Transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. It is a transistor. Transistor 200 is used in memory devices because it has a low off-current. This makes it possible to retain memory content for a long period of time. In other words, refresh Because it does not require any operation, or because the refresh operation is performed very infrequently, the memory Power consumption can be significantly reduced.

[0325] In the semiconductor device shown in Figure 14, wiring 1001 is connected to the source and electrical source of transistor 300. The wiring 1002 is electrically connected to the drain of transistor 300. Furthermore, wiring 1003 is electrically connected to either the source or the drain of transistor 200. The wiring 1004 is then electrically connected to the first gate of transistor 200, and the wiring 1 006 is electrically connected to the second gate of transistor 200. And, The gate of transistor 300, and the other of the source and drain of transistor 200, The wiring 1005 is electrically connected to one of the electrodes of the capacitance element 100, and the wiring 1005 is connected to the electrode of the capacitance element 100. It is electrically connected to the other side.

[0326] Furthermore, the memory device shown in Figure 14, when arranged in a matrix, allows the memory cell array to function as a matrix. It can be configured.

[0327] <Transistor 300> The transistor 300 is provided on the substrate 311 and has a conductor 316 that functions as a gate. , an insulator 315 that functions as a gate insulator, and a semiconductor region 31 which is part of the substrate 311 3, and a low-resistance region 314a that functions as a source region or drain region, and low It has a resistive region 314b. Transistor 300 is either a p-channel or n-channel type. Any type is acceptable.

[0328] Here, the transistor 300 shown in Figure 14 is in the semiconductor region 313 where the channel is formed. A portion of the substrate 311 has a convex shape. In addition, the side and top surfaces of the semiconductor region 313 are made of an insulating material. The conductive material 316 is provided so as to cover the edge 315. Materials that adjust the work function may be used. Such a transistor 300 is on a semiconductor substrate. It is also called a FIN-type transistor because it utilizes a protruding part. Furthermore, it may have an insulator that functions as a mask for forming the protrusion. This example shows a case where a protrusion is formed by processing a part of a semiconductor substrate, but when processing an SOI substrate... A semiconductor film having a convex shape may be formed.

[0329] Note that the transistor 300 shown in Figure 14 is just one example, and its structure is not limited to that example. A suitable transistor should be used depending on the configuration and driving method.

[0330] <Capacitive element 100> The capacitive element 100 is located above the transistor 200. The capacitive element 100 is the first A conductor 110 that functions as an electrode, a conductor 120 that functions as a second electrode, and a dielectric It has an insulator 130 that functions as a body.

[0331] Furthermore, for example, the conductor 112 provided on the conductor 240 and the conductor 110 are formed simultaneously. This is possible. Furthermore, the conductor 112 is connected to the capacitive element 100, the transistor 200, and It functions as a plug or wire that electrically connects to transistor 300.

[0332] In Figure 14, the conductors 112 and 110 are shown as single-layer structures, but this configuration is not limited to this. It is not specified, and may be a laminated structure of two or more layers. For example, a conductor with barrier properties and a highly conductive material A conductor with barrier properties and a conductor with high conductivity are bonded to each other. A highly conductive material may be formed.

[0333] Furthermore, the insulator 130 may be, for example, silicon oxide, silicon oxide nitride, or silicon oxide nitride. Silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, nitrile Aluminum oxide, hafnium oxide, hafnium oxide nitride, hafnium oxide nitride, hafnium nitride It can be made using materials such as nium, and can be constructed in layers or as a single layer.

[0334] For example, the insulator 130 may contain a material with high dielectric strength, such as silicon oxynitride, and a high dielectric strength material. It is preferable to use a laminated structure with a high-k material. With this configuration, the capacity element Child 100 has a high dielectric constant (high-k) insulator, which ensures sufficient capacitance. By having an insulator with high dielectric strength, the dielectric strength is improved, and the electrostatic discharge of the capacitive element 100 is reduced. It can suppress damage.

[0335] Furthermore, as an insulator of high-dielectric constant (high-k) materials (materials with a high relative permittivity), Having gallium, hafnium oxide, zirconium oxide, aluminum and hafnium Oxides, aluminum and hafnium-containing oxides and nitrides, silicon and hafnium Oxides having silicon and hafnium, oxidized nitrides having silicon and hafnium Examples include nitrides containing um.

[0336] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide and nitrogen oxide. Silicon oxide, silicon nitride, silicon nitride, silicon oxide with added fluorine, carbon Silicon oxide with added carbon and nitrogen, silicon oxide with voids Examples include concrete and resin.

[0337] <Wiring layer> Interlayers may be provided between each structure, including interlayer membranes, wiring, plugs, etc. Furthermore, multiple wiring layers can be provided depending on the design. Here, plugs or wiring Conductors that function as lines may have multiple structures grouped together and assigned the same code. Furthermore, in this specification, the wiring and the plug that electrically connects to the wiring are considered to be a single unit. It is also possible that a part of the conductor functions as wiring, and a part of the conductor It can also function as a plug.

[0338] For example, on transistor 300, there are insulators 320, 322, and an insulator as interlayer films. The edge body 324 and the insulator 326 are arranged in order in stacked layers. Also, the insulator 320, Insulators 322, 324, and 326 contain capacitive elements 100 or transients Conductors 328, 330, etc., which are electrically connected to the sta 200, are embedded within. Conductors 328 and 330 function as plugs or wires.

[0339] Furthermore, the insulator, which functions as an interlayer film, acts as a planarizing film that covers the uneven shape beneath it. It may function. For example, the upper surface of the insulator 322 may be chemically and mechanically polished to improve flatness. The surface may be flattened by a flattening treatment such as the CMP method.

[0340] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, as shown in Figure 14. The insulator 350, insulator 352, and insulator 354 are arranged in a sequential stacked configuration. Furthermore, a conductor 356 is formed on insulators 350, 352, and 354. Conductor 356 functions as a plug or wiring.

[0341] Similarly, insulators 210, 212, 214, and 216 are conductive Body 218 and the conductor (conductor 205) that constitutes the transistor 200 are embedded within it. Furthermore, the conductor 218 is electrically connected to the capacitive element 100 or the transistor 300. It has the function of a plug or wiring. Furthermore, it has a conductor 120 and an insulator 13 An insulator 150 is provided on top of 0.

[0342] Here, similar to the insulator 241 shown in the above embodiment, a conductor 2 that functions as a plug An insulator 217 is provided in contact with the side surface of 18. The insulator 217 is in contact with the insulator 210, insulator 212, insulator 214, and insulator 216 are provided in contact with the inner wall of the opening formed therein. In other words, insulator 217 is connected to conductor 218, insulator 210, insulator 212, insulator It is provided between 214 and the insulator 216. Note that the conductor 205 is conductor 2 Since it can be formed in parallel with 18, the insulator 217 is in contact with the side surface of the conductor 205. It may also be formed.

[0343] Examples of insulator 217 include silicon nitride, aluminum oxide, and silicon nitride oxide. Insulators such as the following can be used. Insulator 217 is an insulator 210, insulator 212, insulator 2 14, Since it is provided in contact with the insulator 216 and the insulator 222, the insulator 210, Impurities such as water and hydrogen contained in body 216, etc., are transferred to oxide 230 through conductor 218. Contamination can be suppressed. In particular, silicon nitride has blocking properties for hydrogen. It is suitable because it has a high conductivity. Also, the oxygen contained in the insulator 210 or insulator 216 is conductive. This prevents it from being absorbed by 218.

[0344] The insulator 217 can be formed in the same manner as the insulator 241. For example, PEA A silicon nitride film is deposited using the LD method, and the conductive material 356 is reached using anisotropic etching. You just need to form an opening.

[0345] Insulators that can be used as interlayer films include insulating oxides, nitrides, and acids. Examples include nitrides, nitride oxides, metal oxides, metal oxide nitrides, and metal nitride oxides.

[0346] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, wiring The parasitic capacitance that occurs between them can be reduced. Therefore, depending on the function of the insulator, the material You should choose this option.

[0347] For example, insulators 150, 210, 352, and 354 have relative permittivity It is preferable to have an insulator with low fluorine properties. For example, the insulator may be silicon nitride, nitride Silicon, fluorinated silicon oxide, carbon-added silicon oxide, carbon and nitrogen It is preferable that the material contains silicon oxide with added elements, silicon oxide with voids, resin, etc. i. Or, the insulator is silicon oxide, silicon oxide nitride, silicon nitride oxide, nitride Silicon, fluorinated silicon oxide, carbon-added silicon oxide, carbon and nitrogen It has a laminated structure of silicon oxide with added elements or silicon oxide having voids and a resin. It is preferable that silicon oxide and silicon oxide nitride are thermally stable, By combining it with fat, a thermally stable laminated structure with a low dielectric constant can be created. Examples of resins include polyester, polyolefin, and polyamide (nylon, aramid). Examples include polyimide, polycarbonate, and acrylic (such as d), etc.

[0348] Furthermore, transistors using oxide semiconductors suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has a controlling function, the electrical characteristics of the transistor are stabilized. Therefore, insulators 214, 212, 350, etc. contain hydrogen and other insulators. An insulator that has the function of suppressing the permeation of pure substances and oxygen should be used.

[0349] Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include, Boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, salt Element, argon, gallium, germanium, yttrium, zirconium, lanthanum, neo An insulator containing zym, hafnium, or tantalum may be used in a single layer or in a multilayer configuration. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide Umium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tan oxide Metal oxides such as tar, silicon nitride, and silicon nitride can be used.

[0350] Conductors that can be used in wiring and plugs include aluminum, chromium, copper, and silver. Gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanilla Dium, niobium, manganese, magnesium, zirconium, beryllium, indium, Materials containing one or more metallic elements selected from thenium and others can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like nitrates, Silicides such as nickel silicide may also be used.

[0351] For example, conductor 328, conductor 330, conductor 356, conductor 218, conductor 112, etc. Examples include metal materials, alloy materials, metal nitride materials, and metal oxide materials formed from the above materials. Conductive materials such as ferrous metals can be used in a single layer or in a laminated configuration. This achieves both heat resistance and conductivity. It is preferable to use high melting point materials such as tungsten and molybdenum. It is preferable to use [a specific material]. Alternatively, it may be formed from a low-resistance conductive material such as aluminum or copper. This is preferable. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0352] <Wiring or plugs in layers containing oxide semiconductors> Furthermore, when an oxide semiconductor is used for transistor 200, excess near the oxide semiconductor An insulator having an oxygen region may be provided. In that case, the insulator having the excess oxygen region A barrier-type insulator is provided between the insulator having the excess oxygen region and the conductor. It is preferable to provide one.

[0353] For example, in Figure 14, insulators 224 and 280 have excess oxygen, and conductor 2 It is preferable to provide an insulator 241 between 40 and 40. The insulator 241, the insulator 222, and the insulating By being provided in contact with the edge 254, the insulator 224 and the transistor 200 are A structure can be formed that is sealed with an insulator having barrier properties. Furthermore, insulator 24 It is preferable that 1 is also in contact with a part of the insulator 280. The insulator 241 is in contact with the insulator 274. By being present in this manner, the diffusion of oxygen and impurities can be further suppressed.

[0354] In other words, by providing the insulator 241, the excess insulation of the insulators 224 and 280 is eliminated. This can suppress the absorption of oxygen by the conductor 240. Also, the insulator 241 By having this, the impurity hydrogen diffuses to the transistor 200 via the conductor 240. This can suppress the action.

[0355] Furthermore, the insulator 241 is a device that suppresses the diffusion of impurities such as water and hydrogen, as well as oxygen. It is preferable to use insulating materials that have insulating properties. For example, silicon nitride, silicon nitride oxide, oxide It is preferable to use aluminum, hafnium oxide, etc. In particular, silicon nitride is hydrogen It is preferable because it has high blocking properties against [the substance]. In addition, for example, magnesium oxide Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide Metal oxides such as fluorine, neodymium oxide, and tantalum oxide can be used.

[0356] The above is a description of the example configuration. By using this configuration, a tortoise having an oxide semiconductor can be constructed. In semiconductor devices using transistors, the aim is to suppress fluctuations in electrical characteristics and improve reliability. It can be increased. Also, a transistor with an oxide semiconductor that has a large on-current can be provided. It can also provide a transistor having an oxide semiconductor with a low off-current. This is possible. Furthermore, it is possible to provide semiconductor devices with reduced power consumption.

[0357] [Storage device 2] Figure 15 shows an example of a storage device using a semiconductor device according to one aspect of the present invention. The memory device shown is transistor 200, transistor 300, and shown in Figure 14. In addition to a semiconductor device having a quantitative element 100, it also has a transistor 400.

[0358] Transistor 400 can control the second gate voltage of transistor 200. For example, the first and second gates of transistor 400 are connected to the source and diode. Connect the source of transistor 400 to the second gate of transistor 200. The configuration is as follows. When the negative potential of the second gate of transistor 200 is maintained in this configuration, The first gate-source voltage of transistor 400 and the second gate-source voltage The voltage becomes 0V. In transistor 400, the second gate voltage and the first gate voltage Because the drain current is very small when the voltage is 0V, transistor 200 and transistor 200 and Even without supplying power to transistor 400, the negative potential of the second gate of transistor 200 It can be maintained for a long time. This allows transistor 200 and transistor 4 A storage device containing 00 can retain its contents for a long period of time.

[0359] Therefore, in Figure 15, wiring 1001 is electrically connected to the source of transistor 300. Furthermore, wiring 1002 is electrically connected to the drain of transistor 300. Wiring 1003 is electrically connected to either the source or drain of transistor 200. Wire 1004 is electrically connected to the gate of transistor 200, and wire 1006 is connected to the transistor It is electrically connected to the second gate of transistor 200. And transistor 300 The gate, and the other of the source and drain of transistor 200, are of the capacitive element 100. The wiring 1005 is electrically connected to one electrode and to the other electrode of the capacitive element 100. It is connected. Wiring 1007 is electrically connected to the source of transistor 400, and wiring 1008 is electrically connected to the gate of transistor 400, and wiring 1009 is connected to the transistor Electrically connected to the second gate of transistor 400, wiring 1010 is the drain of transistor 400. It is electrically connected to the input. Here, wiring 1006, wiring 1007, wiring 1008, And wiring 1009 is electrically connected.

[0360] Furthermore, the storage device shown in Figure 15 is arranged in a matrix, similar to the storage device shown in Figure 14. This allows for the construction of a memory cell array. Note that one transistor 40 0 can control the second gate voltage of multiple transistors 200. Therefore, it is preferable to use fewer transistors 400 than transistors 200.

[0361] <Transistor 400> Transistor 400 is formed on the same layer as transistor 200 and is manufactured in parallel. It is a transistor that can be manufactured. Transistor 400 is the first gate. Conductive conductors 460 (conductors 460a and 460b), and a second gate A functional conductor 405, and insulators 222 and 224 that function as gate insulating layers, and an insulator 450, an oxide 430c having a channel-forming region, and a source that functions Conductors 442a, oxide 431a, and oxide 431b, and a drain function Conductor 442b, oxide 432a, and oxide 432b, and a conductive plug Body 440 (conductor 440a and conductor 440b), and barrier insulating film of conductor 440 and It has an insulator 441 (insulator 441a and insulator 441b) that functions as such.

[0362] Conductor 405 and conductor 205 are formed in the same layer. Oxide 431a and acid Oxide 432a and oxide 230a are formed in the same layer, oxide 431b and oxidation Material 432b and oxide 230b are formed in the same layer. Conductor 442a, and conductive Body 442b and conductor 242 are formed in the same layer. Oxide 430c and oxide 23 0c is formed in the same layer. Insulator 450 and insulator 250 are formed in the same layer. Conductor 460 and conductor 260 are formed in the same layer. Conductor 440 and conductor 240 is formed in the same layer. Insulator 441 and insulator 241 are formed in the same layer. It can be done.

[0363] Furthermore, structures formed in the same layer can be formed simultaneously. For example, oxide 4 30c can be formed by processing an oxide film that becomes oxide 230c.

[0364] Oxide 430c, which functions as the active layer of transistor 400, is the same as oxide 230, etc. As such, oxygen deficiency is reduced, and impurities such as hydrogen and water are reduced. The threshold voltage of the inverter 400 is increased, the off-current is reduced, and the second gate voltage and Furthermore, the drain current when the first gate voltage is 0V can be made very small.

[0365] <Dicing line> In the following, by dividing a large-area substrate into semiconductor elements, multiple semiconductor devices are created. Dicing lines (scribe lines, division lines) are provided when extracting chips. This explains the cutting line (which may also be called the cutting line). For example, the method of division is... First, grooves (dicing lines) are formed in the substrate to divide the semiconductor elements, In some cases, the semiconductor device may be cut during grinding, resulting in its division into multiple semiconductor devices.

[0366] Here, for example, as shown in Figure 15, the region where the insulator 254 and the insulator 222 are in contact. It is preferable to design it so that it becomes a dicing line. In other words, multiple transistors A memory cell having 200, and a dicing laser provided on the outer edge of the transistor 400 An opening is provided in the insulator 224 near the region that will be in. Also, the side of the insulator 224 An insulator 254 is provided to cover it.

[0367] In other words, at the opening provided in the insulator 224, the insulator 222 and the insulator 254 They come into contact. For example, in this case, the insulator 222 and the insulator 254 are made of the same material and the same method. They may be formed using the same material and method. The insulator 222 and the insulator 254 are provided using the same material and method. This can improve adhesion. For example, aluminum oxide is preferred. It's nice.

[0368] With this structure, the insulator 222 and the insulator 254, the insulator 224, the transistor It can enclose transistors 200 and 400. Insulator 222, and insulation Body 254 has the function of suppressing the diffusion of oxygen, hydrogen, and water, therefore, in this embodiment By dividing the substrate for each circuit region where the semiconductor element shown is formed, multiple chips can be formed. Even after processing, impurities such as hydrogen and water can enter from the side of the separated substrate, and the transistors can become damaged. This prevents diffusion to transistor 200 and transistor 400.

[0369] Furthermore, due to this structure, excess oxygen in the insulator 224 is transferred to the insulator 254 and the insulator 222 This prevents diffusion to the outside via the insulator 224. Therefore, excess oxygen in the insulator 224 Efficiently forms a channel in transistor 200 or transistor 400. It is supplied to the oxide. With this oxygen, transistor 200 or transistor 400 This can reduce the oxygen vacancy in the oxide where channels are formed. The oxide in which the channel is formed in transistor 200 or transistor 400 This allows for the creation of oxide semiconductors with low defect level density and stable properties. This suppresses fluctuations in the electrical characteristics of the transistor 200 or transistor 400, and also improves reliability. It can improve sexual performance.

[0370] The configurations and methods shown in this embodiment are not the same as the configurations and structures shown in other embodiments and examples. It can be used in appropriate combination with other methods, etc.

[0371] (Embodiment 3) In this embodiment, using Figures 16A and 16B, and Figures 17A to 17H Therefore, according to one aspect of the present invention, a transistor using an oxide as a semiconductor (hereinafter referred to as OS transistor) Sometimes referred to as "sta"), and memory devices to which capacitive elements are applied (hereinafter referred to as OS memory). This is sometimes called a memory device. The OS memory device consists of at least capacitive elements. It is a memory device that has an OS transistor that controls the charging and discharging of capacitive elements. Because the off-current of the zista is extremely small, the OS memory device has excellent retention characteristics and is non-volatile. It can be used as a storage memory.

[0372] <Example of a storage device configuration> Figure 16A shows an example of the configuration of the OS memory device. The storage device 1400 is connected to peripheral circuit 141 1, and a memory cell array 1470. Peripheral circuit 1411 is a row circuit 1420, It has a column circuit 1430, an output circuit 1440, and a control logic circuit 1460. .

[0373] The column circuit 1430 includes, for example, a column decoder, a pre-charge circuit, a sense amplifier, and a programming circuit. It has circuits, etc. The precharge circuit has the function of precharging the wiring. The amplifier has the function of amplifying the data signal read from the memory cell. The lines are wiring connected to memory cells in the memory cell array 1470, and more details The details will be explained later. The amplified data signal is sent via the output circuit 1440 to the data signal RDA. The TA is output to the outside of the storage device 1400. Also, the row circuit 1420 is, for example, row It has a decoder, a word line driver circuit, etc., and can select the row to access.

[0374] The storage device 1400 receives a low power supply voltage (VSS) from an external source as the power supply voltage, and peripheral circuits 14 The high power supply voltage (VDD) for 11 and the high power supply voltage (VIL) for the memory cell array 1470 are It is supplied. In addition, the storage device 1400 contains control signals (CE, WE, RE) and address signals. The address signal ADDR and the data signal WDATA are input from an external source. The address signal ADDR is the line The data signal WDATA is input to the decoder and column decoder, and then input to the writing circuit. ru.

[0375] The control logic circuit 1460 receives externally input control signals (CE, WE, R Process E) to generate control signals for the row decoder and column decoder. The control signal CE is a chip The write enable signal is the control signal R E is the read enable signal. The signal processed by the control logic circuit 1460 The signal is not limited to this; other control signals can be input as needed.

[0376] The memory cell array 1470 consists of multiple memory cells MC arranged in a matrix, and multiple It has the wiring. Note that the wiring connecting the memory cell array 1470 and the row circuit 1420 The number of lines is determined by the configuration of the memory cell MC, the number of memory cell MCs in a single row, and other factors. Also, the number of wires connecting the memory cell array 1470 and the column circuit 1430 is noted. This is determined by factors such as the configuration of the recell MC and the number of memory cell MCs in each row.

[0377] In Figure 16A, the peripheral circuit 1411 and the memory cell array 1470 are on the same plane. Although examples of how to form it have been shown, this embodiment is not limited to this. For example, As shown in Figure 16B, the memory cell array 1470 is superimposed on a portion of the peripheral circuit 1411. It may be provided in such a way. For example, so as to overlap below the memory cell array 1470, A configuration that includes a sense amplifier is also possible.

[0378] Figures 17A to 17H show examples of memory cell configurations that can be applied to the above-mentioned memory cell MC. I will explain.

[0379] [DOSRAM] Figures 17A to 17C show examples of circuit configurations for DRAM memory cells. And, DRAM using a 1OS transistor 1 capacitance element type memory cell is called DOSRAM. (Dynamic Oxide Semiconductor Random Acce It is sometimes called ss Memory. As shown in Figure 17A, memory cell 1471 is a tra It has a transistor M1 and a capacitive element CA. Note that the transistor M1 has a gate (top It has a front gate (sometimes called a back gate) and a back gate.

[0380] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, and transistor M The second terminal of 1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. Next, the back gate of transistor M1 is connected to wiring BGL. Capacitive element C The second terminal of A is connected to wiring CAL.

[0381] Wiring BIL functions as a bit line, and wiring WOL functions as a word line. CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. During data writing and reading, a low-level potential is applied to the wiring CAL. It is preferable to do so. Wiring BGL is used to apply potential to the back gate of transistor M1. It functions as wiring. By applying an arbitrary potential to wiring BGL, the transistor The threshold voltage of M1 can be increased or decreased.

[0382] Here, the memory cell 1471 shown in Figure 17A corresponds to the storage device shown in Figure 14. In other words, transistor M1 becomes transistor 200, and capacitive element CA becomes capacitive element 100. Wiring BIL to wiring 1003, wiring WOL to wiring 1004, wiring BGL to wiring 100 6. Wiring CAL corresponds to wiring 1005. Note that transistor 3 shown in Figure 14 00 is a transistor provided in the peripheral circuit 1411 of the storage device 1400 shown in Figure 16B. It corresponds to.

[0383] Furthermore, the memory cell MC is not limited to memory cell 1471, and the circuit configuration can be changed. This is possible. For example, a memory cell MC can be a memory cell 1472 as shown in Figure 17B. The back gate of transistor M1 is connected to the WOL wiring instead of the BGL wiring. It is also possible to do so. For example, the memory cell MC is like the memory cell 1473 shown in Figure 17C. In addition, a single-gate transistor, that is, a transistor without a back gate, M It may also be a memory cell composed of 1.

[0384] When the semiconductor device shown in the above embodiment is used as a memory cell 1471, etc., a transistor Transistor 200 is used as M1, and capacitive element 100 is used as capacitive element CA. This can be done. By using an OS transistor as transistor M1, the transistor The leakage current of the M1 can be made very small. In other words, the written data can be transmitted via Because it can be retained for a long time by the M1 converter, the frequency of memory cell refresh is reduced. The frequency can be reduced. Alternatively, the refresh operation of the memory cells can be made unnecessary. This is possible. Also, because the leakage current is very small, memory cell 1471, memory cell 14 72. Multilevel data or analog data can be stored in memory cell 1473. Cut.

[0385] Furthermore, in DOSRAM, as described above, overlaps below the memory cell array 1470 As shown, by using a configuration that includes a sense amplifier, the bit line can be shortened. This reduces the bit line capacitance and thus the memory cell retention capacity.

[0386] [NOSRAM] Figures 17D to 17G show the rotation of a gain cell type memory cell with two transistors and one capacitance element. An example of a circuit configuration is shown. As shown in Figure 17D, the memory cell 1474 is connected to transistor M2 and It has a transistor M3 and a capacitive element CB. Note that transistor M2 is the top gate ( It is sometimes simply called a gate, and has a back gate. In this specification, etc., A memory device having a gain cell type memory cell using an OS transistor in the transistor M2. , NOSRAM(Nonvolatile Oxide Semiconductor It is sometimes referred to as RAM.

[0387] The first terminal of transistor M2 is connected to the first terminal of the capacitive element CB, and transistor M The second terminal of 2 is connected to the wiring WBL, and the gate of transistor M2 is connected to the wiring WOL. Next, the back gate of transistor M2 is connected to wiring BGL. Capacitive element C The second terminal of B is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring R. The second terminal of transistor M3 is connected to BL, and the wiring SL is connected to transistor M The gate of 3 is connected to the first terminal of the capacitive element CB.

[0388] Wiring WBL functions as the write bit line, and wiring RBL functions as the read bit line. The wiring WOL functions as a word line. The wiring CAL is the second of the capacitive element CB. It functions as wiring to apply a predetermined potential to the terminal. When writing data, data retention During the process, when reading data, a low-level potential is applied to the wiring CAL. Preferred. Wiring BGL is wiring for applying potential to the back gate of transistor M2. It functions as follows: By applying an arbitrary potential to the wiring BGL, the transistor M2 The threshold voltage can be increased or decreased.

[0389] Here, the memory cell 1474 shown in Figure 17D corresponds to the storage device shown in Figure 14. In other words, transistor M2 becomes transistor 200, and capacitive element CB becomes capacitive element 100. Transistor M3 is connected to transistor 300, wiring WBL is connected to wiring 1003, wiring WOL Wire BGL goes to wire 1006, wire CAL goes to wire 1005, wire R BL corresponds to wiring 1002, and wiring SL corresponds to wiring 1001.

[0390] Furthermore, the memory cell MC is not limited to memory cell 1474, and the circuit configuration can be changed as appropriate. This is possible. For example, the memory cell MC is like the memory cell 1475 shown in Figure 17E. In this configuration, the back gate of transistor M2 is connected to the WOL wiring instead of the BGL wiring. It may also be made into a memory cell MC, as shown in Figure 17F, memory cell 1476 As shown above, a single-gate transistor, that is, a transistor without a back gate A memory cell composed of sta M2 may also be used. For example, the memory cell MC is shown in Figure 1. As shown in memory cell 1477 in 7G, the wiring WBL and wiring RBL are combined into a single wiring BIL. It would also be acceptable to use a structure that summarizes the information in this way.

[0391] When the semiconductor device shown in the above embodiment is used as a memory cell 1474, etc., a transistor Transistor 200 is used as M2, and transistor 300 is used as transistor M3. Capacitive element 100 can be used as the capacitive element CB. Transistor M2 By using an OS transistor, the leakage current of transistor M2 is made very small. This allows the written data to be stored for a long time by transistor M2. Because it can maintain this, the frequency of refreshing the memory cells can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Also, the leakage current is Because it is extremely small, the memory cell 1474 cannot store multi-level data or analog data. This is possible. The same applies to memory cells 1475 to 1477.

[0392] Note that transistor M3 is a transistor having silicon in the channel formation region (hereinafter (Sometimes called Si transistors) The conductivity type of Si transistor is It may be an n-channel type or a p-channel type. Si transistors are OS transistors In some cases, the field-effect mobility is higher than that of a transistor. Therefore, readout transistor A Si transistor may be used as transistor M3, which functions as a transistor. By using a Si transistor for transistor M3, a transistor can be stacked on top of transistor M3. Since a converter M2 can be provided, the occupied area of ​​the memory cell is reduced, and the storage device is high It is possible to integrate the resources.

[0393] Also, transistor M3 may be an OS transistor. Transistor M2 and When an OS transistor is used for transistor M3, the memory cell array 1470 is an n-type A circuit can be constructed using only transistors.

[0394] Figure 17H ​​also shows an example of a gain cell type memory cell with 3 transistors and 1 capacitance element. The memory cell 1478 shown in Figure 17H ​​consists of transistors M4 to M6, and It has a capacitive element CC. The capacitive element CC is provided as appropriate. The memory cell 1478 is wired Electrically connected to BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. The wiring GNDL is a wiring that provides a low level potential. Note that memory cell 1478 Alternatively, instead of wiring BIL, electrical connections may be made to wiring RBL and wiring WBL.

[0395] Transistor M4 is an OS transistor with a back gate, and the back gate is It is electrically connected to wiring BGL. Note that the back gate and gate of transistor M4 They may be electrically connected to each other. Alternatively, transistor M4 may have a back gate. It's not necessary.

[0396] Note that transistors M5 and M6 are n-channel type Si transistors. A t-channel or p-channel Si transistor may also be used. Alternatively, transistor M4 or a trans-transistor may be used. The Zistar M6 may also be an OS transistor; in this case, the memory cell array 1470 is an n-type transistor. A circuit can be constructed using only transistors.

[0397] When the semiconductor device shown in the above embodiment is used as the memory cell 1478, transistor M Transistor 200 is used as 4, and transistors M5 and M6 are trans Using the ZISTA 300, the capacitive element 100 can be used as the capacitive element CC. By using an OS transistor as transistor M4, the leakage current of transistor M4 is reduced. The flow can be made very small.

[0398] The configuration of the peripheral circuit 1411, memory cell array 1470, etc., as shown in this embodiment is , but not limited to, these circuits, and the wiring connected to them. The arrangement or function of path elements, etc., may be changed, deleted, or added as necessary.

[0399] The configuration shown in this embodiment can be appropriately combined with the configurations shown in other embodiments and examples. It can be used.

[0400] (Embodiment 4) In this embodiment, the semiconductor device of the present invention is mounted using Figures 18A and 18B. An example of chip 1200 is shown. Multiple circuits (systems) are mounted on chip 1200. This technology integrates multiple circuits (systems) onto a single chip. It is sometimes called a System on Chip (SoC).

[0401] As shown in Figure 18A, the chip 1200 consists of a CPU 1211, a GPU 1212, and It consists of multiple analog processing units 1213, one or more memory controllers 1214, and It has multiple interfaces 1215, one or more network circuits 1216, etc. ru.

[0402] The chip 1200 is provided with bumps (not shown), and as shown in Figure 18B, pre The first side of the Printed Circuit Board (PCB) 1201 It connects to this. In addition, multiple bumps 1202 are provided on the back surface of the first face of PCB1201. It is configured to connect to the motherboard 1203.

[0403] Motherboard 1203 includes memory devices such as DRAM 1221 and flash memory 1222. A place may be provided. For example, the DOSR shown in the previous embodiment may be placed in the DRAM1221. AM can be used. Also, for example, in the flash memory 1222, the above embodiment The NOSRAM shown can be used.

[0404] CPU1211 preferably has multiple CPU cores. Also, GPU1212 It is preferable that it has multiple GPU cores. Also, CPU1211 and GPU1 Each of 212 may have memory to temporarily store data. Or, CP The memory common to both U1211 and GPU1212 is provided on chip 1200. Alternatively, the aforementioned NOSRAM or DOSRAM can be used for this memory. Furthermore, the GPU1212 is suitable for parallel computation of large amounts of data, and is ideal for image processing and multiply-accumulate operations. It can be used. The GPU1212 can be used with an image processing circuit using the oxide semiconductor of the present invention. By providing a multiply-accumulate circuit, image processing and multiply-accumulate operations can be performed with low power consumption. This will become possible.

[0405] Furthermore, because the CPU1211 and GPU1212 are located on the same chip, The wiring between CPU1211 and GPU1212 can be shortened, and CPU1211 or Data transfer to GPU1212, and notes held by CPU1211 and GPU1212. Data transfer between the two systems, and after calculations on GPU1212, data transfer from GPU1212 to CPU12 The transfer of calculation results to 11 can be done at high speed.

[0406] The analog processing unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital / digital) conversion circuit. It has one or both of the digital / analog conversion circuits. Also, analog arithmetic unit 1213 The above-mentioned sum-of-accumulate circuit may be provided.

[0407] The memory controller 1214 is a circuit that functions as a controller for the DRAM 1221. It also has a circuit that functions as an interface for the flash memory 1222.

[0408] Interface 1215 is for display devices, speakers, microphones, cameras, and controllers. It has an interface circuit for connecting to external devices such as a torpedo. A controller is a motor This includes mice, keyboards, game controllers, etc. USB (Universal Serial Bus), HDMI (registered trademark) (H (using igh-Definition Multimedia Interface, etc.) It is possible to be there.

[0409] The network circuit 1216 is a LAN (Local Area Network), etc. It has a circuit for networking. It also has a circuit for network security. That's good too.

[0410] The above circuit (system) can be formed on chip 1200 using the same manufacturing process. It is possible. Therefore, even if the number of circuits required for chip 1200 increases, the manufacturing process does not need to be increased. This eliminates the need for additional processing, allowing for the low-cost manufacturing of the Chip 1200.

[0411] PCB1201 equipped with chip 1200 having GPU1212, DRAM122 1, and the motherboard 1203 equipped with flash memory 1222, GPU module It can be called Lure 1204.

[0412] The GPU module 1204 has a chip 1200 that uses SoC technology, Its size can be reduced. Also, because it excels at image processing, smart Phones, tablet devices, laptop PCs, portable (take-out) game consoles, etc. It is suitable for use in portable electronic devices. Also, a multiply-accumulate circuit using the GPU1212. This leads to the development of deep neural networks (DNNs) and convolutional neural networks. (CNN), Recurrent Neural Network (RNN), Autoencoder, Deep Boltzmann It is possible to implement techniques such as machine learning models (DBM) and deep belief networks (DBN). Therefore, the chip 1200 is the AI ​​chip, or the GPU module 1204 is the AI ​​system module. It can be used as a joule.

[0413] The configuration shown in this embodiment can be appropriately combined with the configurations shown in other embodiments and examples. It can be used.

[0414] (Embodiment 5) In this embodiment, regarding the application example of a memory device using the semiconductor device shown in the previous embodiment, Let me explain. The semiconductor device shown in the above embodiment is, for example, used in various electronic devices (for example, information Terminals, computers, smartphones, e-readers, digital cameras (including video cameras) This can be applied to storage devices (including recording and playback devices, navigation systems, etc.). In this context, a computer refers to a tablet computer, a notebook computer, a digital computer, etc. This includes not only desktop computers but also large computers such as server systems. Alternatively, the semiconductor device shown in the above embodiment may contain a memory card (for example, an SD card). Various removable devices such as USB memory sticks, SSDs (Solid State Drives), etc. This applies to removable storage devices. Figures 19A to 19E show several configurations of removable storage devices. An example is schematically shown. For example, the semiconductor device shown in the above embodiment is packaged It is processed into memory chips and used in various storage devices and removable memory.

[0415] Figure 19A is a schematic diagram of a USB memory device. The USB memory device 1100 consists of a casing 1101 and a key It has a cap 1102, a USB connector 1103 and a circuit board 1104. The circuit board 1104 is , housed in the casing 1101. For example, the circuit board 1104 has a memory chip 1105, A controller chip 1106 is installed. The memory chip 1105 and other components are installed as described above. The semiconductor device shown in the form of the installation can be incorporated.

[0416] Figure 19B is a schematic diagram of the external appearance of an SD card, and Figure 19C is a schematic diagram of the internal structure of an SD card. This is a diagram of the equation. The SD card 1110 consists of a housing 1111, a connector 1112, and a circuit board 111. It has 3. The circuit board 1113 is housed in the housing 1111. For example, the circuit board 1113 has A memory chip 1114 and a controller chip 1115 are mounted on the circuit board 11. By also providing a memory chip 1114 on the back side of 13, the capacity of the SD card 1110 can be increased. It is possible to do so. Furthermore, a wireless chip with wireless communication functionality may be provided on the circuit board 1113. Yes. This allows the memory chip to be controlled wirelessly between the host device and the SD card 1110. This enables reading and writing of data to the 1114. A semiconductor device as shown in the embodiment can be incorporated.

[0417] Figure 19D is a schematic diagram of the external appearance of an SSD, and Figure 19E is a schematic diagram of the internal structure of an SSD. The SSD1150 has a housing 1151, a connector 1152, and a circuit board 1153. The circuit board 1153 is housed in the casing 1151. For example, the circuit board 1153 has memory chips. The chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is the work memory of the controller chip 1156, for example D An OSRAM chip can be used. A memory chip 1154 is also provided on the back side of the circuit board 1153. By doing so, the capacity of the SSD1150 can be increased. (This can be done using memory chips 1154, etc.) The semiconductor device shown in the previous embodiment can be incorporated.

[0418] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and examples. It is possible to do so.

[0419] (Embodiment 6) A semiconductor device according to one aspect of the present invention includes a processor such as a CPU or GPU, or a chip. It can be used for the following. Figures 20A to 20H show a CPU and GPU according to one aspect of the present invention. This section provides specific examples of electronic devices equipped with such processors or chips.

[0420] <Electronic Equipment and Systems> A GPU or chip according to one aspect of the present invention can be mounted in various electronic devices. Examples of electronic devices include, for example, television equipment, desktop or notebook computers. Monitors for information terminals, digital signage (electronic signage) In addition to electronic devices with relatively large screens, such as billboards, pachinko machines and other large game machines, Digital cameras, digital video cameras, digital photo frames, e-book readers Examples include mobile phones, portable game consoles, personal digital assistants, and audio playback devices. Furthermore, by providing a GPU or chip according to one aspect of the present invention in an electronic device, It can be equipped with artificial intelligence.

[0421] An electronic device according to one aspect of the present invention may have an antenna. The antenna receives a signal. This allows the display unit to show images, information, etc. Also, the electronic device acts as an antenna. Furthermore, if a secondary battery is present, the antenna may be used for contactless power transmission.

[0422] An electronic device according to one aspect of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation). Number, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, electric current, voltage, power (including functions for measuring radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation) It is acceptable to have it.

[0423] An electronic device according to one aspect of the present invention can have various functions. For example, various information Functions to display (still images, videos, text images, etc.) on the display unit, touch panel function, calendar Functions to display the date or time, and to run various software (programs). Functions include: wireless communication, and reading programs or data recorded on a recording medium. It can have functions, etc. Figures 20A to 20H show examples of electronic devices.

[0424] [Information terminal] Figure 20A illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102, and an input interface - As a face, a touch panel is provided on the display unit 5102, and buttons are located on the housing 5101. It is provided.

[0425] The information terminal 5100 utilizes artificial intelligence by applying a chip according to one embodiment of the present invention. The application can be run. As an application utilizing artificial intelligence. For example, an application that recognizes a conversation and displays the content of that conversation on the display unit 5102. The display unit 5102 recognizes characters, shapes, etc., entered by the user on the touch panel. The application to be displayed on the display unit 5102, and the biometric authentication such as fingerprints and voiceprints are performed. Applications are one example.

[0426] Figure 20B shows a notebook-type information terminal 5200. Notebook-type information terminal 520 0 comprises an information terminal body 5201, a display unit 5202, and a keyboard 5203. .

[0427] Notebook-type information terminal 5200, like the information terminal 5100 described above, is one embodiment of the present invention. By applying the chip, it becomes possible to run applications that utilize artificial intelligence. Examples of applications utilizing artificial intelligence include design support software and text Examples include editing software and automatic menu generation software. Also, notebook-type information terminals... By using the 5200 chip, it is possible to develop new artificial intelligence.

[0428] In the above, smartphones and notebook computers were used as examples of electronic devices. As illustrated in Figures 20A and 20B, these are smartphones and notebook computers, respectively. Other information terminals can be used. (Smartphones and notebook computers are exceptions.) Examples of information terminals include PDAs (Personal Digital Assistants). Examples include tants, desktop information terminals, and workstations.

[0429] [Game console] Figure 20C shows a portable game console 5300, which is an example of a game console. 5300 consists of casing 5301, casing 5302, casing 5303, display unit 5304, and connection unit 53 05, it has an operation key 5306, etc. Housing 5302 and housing 5303 are housing 530 It can be removed from 1. The connection part 5305 provided on the housing 5301 can be connected to another By mounting it in a housing (not shown), the video output to the display unit 5304 can be displayed on another video device. The output can be sent to a device (not shown). At this time, housing 5302 and housing 5303 Each of these can function as a control unit. This allows multiple players to play simultaneously. The game can be played using the circuit boards of cabinets 5301, 5302, and 5303. The chip shown in the above embodiment can be incorporated into the chip provided therein.

[0430] Figure 20D also shows a home console, model 5400, which is an example of a game console. The 5400 home console can be connected to a controller 5402 either wirelessly or via a wired connection. Yes, they are.

[0431] One aspect of the present invention applies to game consoles such as the portable game console 5300 and the home game console 5400. By applying a GPU or chip, it is possible to create a low-power gaming console. Yes, it is possible. Furthermore, the low power consumption reduces heat generation from the circuit, thus reducing heat generation. This minimizes the impact on the circuit itself, surrounding circuits, and modules.

[0432] Furthermore, applying a GPU or chip according to one aspect of the present invention to a portable game console 5300... Therefore, it is possible to realize the 5300 portable game console equipped with artificial intelligence.

[0433] Originally, the progression of the game, the behavior of creatures appearing in the game, and the phenomena that occur in the game, etc. The expression is determined by the program of the game, but the portable game console 530 By applying artificial intelligence to 0, it becomes possible to create expressions that are not limited to game programs. For example, the questions the player asks, the game's progress, the time, and the characters that appear in the game. This allows for expressions that describe a change in a person's words and actions.

[0434] Furthermore, when playing games that require multiple players on the 5300 handheld game console, artificial intelligence is used. This allows for the creation of anthropomorphic game players, thus enabling the opponent to be represented by artificial intelligence. By making it a night game, it's possible to play the game even by yourself.

[0435] Figures 20C and 20D show examples of game consoles, including a handheld game console and a home console. Although a machine is shown in the illustration, a game machine to which a GPU or chip according to one aspect of the present invention is applied is this The invention is not limited to the above. Examples of game machines to which a GPU or chip according to one aspect of the present invention is applied include: For example, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) Examples include pitching machines for batting practice installed in sports facilities.

[0436] [Large computer] A GPU or chip according to one aspect of the present invention can be applied to a large computer.

[0437] Figure 20E shows the Supercomputer 5500, an example of a large-scale computer. Figure 20F shows the rack-mount type computer used by the Supercomputer 5500. This is a diagram of 5502.

[0438] The supercomputer 5500 consists of rack 5501 and multiple rack-mount computing devices. It has a machine 5502. Note that multiple computers 5502 are stored in a rack 5501. In addition, the computer 5502 is provided with multiple circuit boards 5504, and the above-mentioned actual It can be equipped with the GPU or chip described in the configuration.

[0439] The Supercomputer 5500 is a large computer primarily used for scientific and technical calculations. Yes. Scientific and technical computing requires high-speed processing of enormous calculations, so power consumption is high. The chip generates a lot of heat. A GPU according to one aspect of the present invention is installed in the supercomputer 5500. By applying this chip, it is possible to realize a low-power supercomputer. Yes, it is possible. Furthermore, the low power consumption reduces heat generation from the circuit, thus reducing heat generation. This minimizes the impact on the circuit itself, surrounding circuits, and modules.

[0440] Figures 20E and 20F illustrate a supercomputer as an example of a large-scale computer. However, a large computer to which a GPU or chip according to one aspect of the present invention is applied has Not limited to, as a large computer to which a GPU or chip according to one aspect of the present invention is applied. For example, a computer (server) that provides a service, a large general-purpose computer (mechanism) Examples include (in-frame).

[0441] [Mobile] A GPU or chip according to one aspect of the present invention is used in a mobile vehicle and in the driver's seat of the vehicle. It can be applied to the surrounding area.

[0442] Figure 20G shows the area around the windshield inside an automobile, which is an example of a moving object. Yes. In Figure 20G, the display panel 5701 is mounted on the dashboard. In addition to 5702 and display panel 5703, the diagram shows a display panel 5704 mounted on the pillar. They are doing it.

[0443] Display panels 5701 to 5703 display the speedometer, tachometer, and By displaying the distance traveled, fuel gauge, gear status, air conditioning settings, and other various information, It can be provided. Also, the display items and layout displayed on the display panel are customizable. It can be customized to suit the user's preferences, allowing for enhanced design. Display panels 5701 to 5703 can also be used as lighting devices. .

[0444] The display panel 5704 shows images from an imaging device (not shown) installed in the automobile. By projecting the image, it is possible to compensate for the blind spots (views obstructed by the pillars). By displaying images from an imaging device installed on the outside of the vehicle, blind spots can be compensated for. This can enhance safety. Furthermore, by displaying images that complement the unseen areas... This allows for a more natural and unobtrusive safety check. The display panel 5704 is a lighting device. It can also be used as such.

[0445] A GPU or chip according to one aspect of the present invention can be applied as a component of artificial intelligence, for example For example, the chip can be used in an autonomous driving system for automobiles. It can be used in systems that provide road guidance, predict hazards, etc. Display panel 5701 The display panel 5704 may be configured to display information such as road guidance and hazard predictions. .

[0446] In the above, an automobile was described as an example of a moving object, but the moving object is an automobile. It is not limited to these. For example, examples of moving objects include trains, monorails, ships, and aircraft (helicopters). Other examples include unmanned aerial vehicles (drones), airplanes, and rockets, and these can be moved Applying a chip according to one aspect of the present invention to a moving object to provide it with a system utilizing artificial intelligence. It is possible.

[0447] [electric appliances] Figure 20H shows an example of an electrical appliance, the electric refrigerator-freezer 5800. The storage unit 5800 includes a casing 5801, a door for the refrigerator compartment 5802, a door for the freezer compartment 5803, and the like.

[0448] By applying a chip according to one aspect of the present invention to an electric refrigerator 5800, artificial intelligence An electric refrigerator-freezer 5800 with the following features can be realized. By utilizing artificial intelligence... The electric refrigerator-freezer 5800 is used to store food items, and the food It has a function that automatically generates menus based on the expiration dates of ingredients, and the menus are stored in the 5800 electric refrigerator / freezer. It can have features such as automatically adjusting the temperature to suit the ingredients being used.

[0449] I explained electric refrigerators as an example of electrical appliances, but other electrical appliances include For example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, and water heaters. Heating and cooling appliances including air conditioners, washing machines, dryers, and audio equipment. Examples include visual equipment.

[0450] The electronic device described in this embodiment, its functions, examples of artificial intelligence applications, and their effects. These can be combined as appropriate with descriptions of other electronic devices.

[0451] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and examples. It is possible to do so. [Examples]

[0452] In this embodiment, a transistor 200 having an oxide semiconductor as shown in Figures 1A to 1D is used. Multiple transistors were fabricated using the same process, their characteristics were measured, and the variation in transistor characteristics was analyzed. I evaluated it.

[0453] The semiconductor device having the transistor 200 shown in Figures 1A to 1D will be referred to as sample 1A. Furthermore, the semiconductor device prepared as a sample consisted of 161 transistors fabricated using the same process. It has a sta. Note that in sample 1A, the design values ​​for channel length and channel width are as follows. Each was set to 60nm.

[0454] Sample 1A is described below.

[0455] In sample 1A, oxide 230a has an atomic ratio of In:Ga:Zn=1:3:4. Using an oxide target, an In-Ga-Zn oxide film was deposited by sputtering. The oxide 230b was formed with an oxidation state of In:Ga:Zn=4:2:4.1 [atomic ratio]. Using a material target, an InGa-Zn oxide film is deposited by sputtering, forming a shape. It was achieved. Furthermore, the film that becomes oxide 230a and the film that becomes oxide 230b were formed by continuous deposition. It was formed.

[0456] Furthermore, oxide 230c is an oxide with an atomic ratio of In:Ga:Zn=4:2:4.1. Using a GET, an In-Ga-Zn oxide film was deposited by sputtering, and In:G Using an oxide target with an atomic ratio of a:Zn=1:3:4, the sputtering method is used. It was formed by a layered structure of a deposited In-Ga-Zn oxide film.

[0457] The conductor 242 was formed using a tantalum nitride film. The insulator 250 was formed using oxidative nitride. It was formed using a silicon film.

[0458] Conductor 260a was formed using a titanium nitride film. Conductor 260b was made of tungsten. It was formed using a stainless steel film. The film that becomes the conductor 260a and the film that becomes the conductor 260b The film was formed by continuous deposition.

[0459] <Electrical characteristics of the transistor in sample 1A> First, sample 1A was subjected to a heat treatment at 400°C for 4 hours under a nitrogen atmosphere. The electrical characteristics of the 161 transistors in sample 1A were measured. Then, the drain voltage Vd is set to 1.2V, and the gate voltage Vg is varied from -4V to +4V. The Id-Vg characteristics were measured.

[0460] Here, in the Id-Vg transistor characteristics, the drain current Id = 1.0 × 10⁻⁶ -1 2 The gate voltage Vg value at A was defined as the Shift value (Vsh).

[0461] Figure 21 shows the normal probability projection of the electrical characteristics of the 161 transistors in sample 1A. A diagram is shown. In Figure 21, the horizontal axis is the Shift value (Vsh) [V], and the vertical axis is the shift value. It is a constant cumulative probability [%].

[0462] Furthermore, the median ranking method is used to calculate the estimated cumulative probability (also called the cumulative relative frequency). These include the mean rank method, the symmetric sample cumulative distribution method, and the Kaplan-Meier method, which can be selected as appropriate. This is sufficient. In this example, the estimated cumulative probability was calculated using the median rank method.

[0463] From Figure 21, the mean value of the Shift value for sample 1A was -0.231V, and the standard deviation was σ was 0.056V.

[0464] As described above, the transistor 200 using the present invention has variations in the electrical characteristics of the transistor. It was found to be small.

[0465] The configurations, methods, etc., shown in this embodiment are at least partially described in other embodiments described herein. It can be implemented in combination with the appropriate form of implementation. [Examples]

[0466] In this embodiment, the semiconductor device shown in Figures 12A to 12D was fabricated, and transistor 200 This section describes the results of a reliability evaluation and investigation into the stress-time dependence. This was done on four transistors, Sample A through Sample D, from a single substrate. The substrate having sample A to sample D is prepared as oxide 243 by sputtering. Using a target with an atomic ratio of In:Ga:Zn=1:3:4, at a substrate temperature of 200°C A film thickness of 2 nm was formed. The substrate was then subjected to a nitrogen atmosphere at 400°C for 8 hours. Heat treatment was performed. Reliability was evaluated using +GBT (Gate Bia) at a stress temperature of 150°C. The stress test was conducted using a temperature-based stress test. The set temperature was 150°C. The rain potential Vd, source potential Vs, and bottom gate potential Vbg are set to 0V, and the top The gate potential Vg was set to +3.63V. Note that the transistors in samples A through D are as follows: The size of all components is based on design specifications, with a channel length of 60nm and a channel width of 60nm. In the Tress test, the stress time when ΔVsh exceeds ±100mV is measured. The lifespan of the device is defined as follows. Furthermore, the variations in Ion, S value, and μFE due to stress time are also evaluated. It was worth it.

[0467] Figure 22 shows the results of the +GBT stress test. In Figure 22, the horizontal axis represents stress time. The graph shows the time (hr), and the vertical axis shows ΔVsh (mV). As shown in Figure 22, sample A has a lifetime. Sample B had a lifetime of 1410 hours, Sample C had a lifetime of 1240 hours, Sample B Sample D had a lifetime of 1230 hours. In all four samples, the lifetime was less than 1200 hours. The above favorable results were obtained.

[0468] The set temperature of 150°C for the +GBT stress test evaluated in this embodiment is for the +GBT stress test Compared to the experimental setting temperature of 125°C, it is estimated that the degradation is accelerated by approximately 24 times. Therefore, the lifespan at a stress temperature of 125°C can be estimated to be over 28,000 hours. Cut.

[0469] Figure 23A shows the variation of Ion in samples A to D with respect to stress time. Figure 2 Figure 3B shows the variation in S values ​​of samples A to D with respect to stress time. Figure 23C shows the variation in S values. This shows the variation in μFE of Samples A through D with respect to stress time.

[0470] Note that Ion(A) is the value of Id when Vd = +1.2V and Vg = +3.3V. The S value (mV / dec) is set to Vd = +1.2V, and in the subthreshold region... This is the value of Vg required for Id to change by one order of magnitude. μFE(cm 2 / Vs) is Graju This value was calculated from the linear region equation of the A-channel approximation.

[0471] As shown in Figures 23A to 23C, in Samples A to D, Ion, S We confirmed that both the value and μFE showed little variation with stress time.

[0472] Based on the above results, the transistor 200, which is one aspect of the present invention, has high reliability. I confirmed that this was the case.

[0473] This embodiment can be appropriately combined with the configurations, structures, methods, etc., shown in other embodiments and examples. They can be used together. [Examples]

[0474] In this embodiment, a semiconductor device having the transistor 200 shown in Figures 12A to 12D is used. The transistors were fabricated, their characteristics were measured, and the variability in those characteristics was evaluated.

[0475] Furthermore, the semiconductor device having the fabricated transistor 200 was fabricated using the same process as 21 It has 5 transistors. Note that the design values ​​for channel length and channel width are as follows: It was set to 60nm.

[0476] <Electrical characteristics of transistors> First, the fabricated semiconductor device was subjected to a heat treatment at 400°C for 8 hours under a nitrogen atmosphere. Subsequently, the electrical characteristics of the 215 transistors in the semiconductor device were measured. As a characteristic, Vd is set to 0.1V or 1.2V, and Vg is set from -4V to +4V respectively. The parameters were varied, and the Id-Vg characteristics were measured.

[0477] Figure 24 shows a graph of the Id-Vg characteristics of the 215 transistors in the semiconductor device. In Figure 24, the horizontal axis represents Vg(V) and the vertical axis represents Id(A).

[0478] Furthermore, Figure 25A shows a normal probability plot of Vsh. In Figure 25A, the horizontal axis is Vs The formula is h(V), and the vertical axis represents the estimated cumulative probability (%). Figure 25B shows the normal probability of Ion. The plot diagram is shown. In Figure 25B, the horizontal axis is Ion (μA), and the vertical axis is the estimated cumulative probability. This is the percentage. Also, Figure 25C shows the Vbg dependence of Vsh for 9 transistors. show.

[0479] Furthermore, the median ranking method is used to calculate the estimated cumulative probability (also called the cumulative relative frequency). There are various methods, including the mean rank method, the symmetric sample cumulative distribution method, and the Kaplan-Meier method, but you can choose the appropriate one. Good. In this example, the estimated cumulative probability was calculated using the median rank method.

[0480] Figure 24 shows the Id-Vg characteristics of each of the 215 transistors superimposed on each other.

[0481] From Figure 25A, the standard deviation σ of Vsh for the 215 transistors was approximately 64mV. .

[0482] From Figure 25B, the average Ion of the 215 transistors is approximately 7.78 μA, with a standard deviation. The difference σ was approximately 6.71 μA.

[0483] From the above, the transistor 200 using one aspect of the present invention has good electrical characteristics, and We confirmed that the variation is small. Furthermore, Vbg allows control of Vsh. I confirmed that.

[0484] The configurations, methods, etc., shown in this embodiment are at least partially described in other embodiments described herein. The method of implementation can be carried out in appropriate combination with other embodiments. [Examples]

[0485] In this embodiment, two transistors of the semiconductor device having transistor 200 used in Example 2 The reliability of the inverters (element A and element B) was evaluated.

[0486] Transistor reliability Reliability was evaluated by a +GBT stress test. In the test, the set temperature was 150°C, Vd=Vs=Vbg=0V, and Vg=+3.63 Let V be the drain potential. Vs is the drain potential and Vbg is the bottom gate potential.

[0487] +During the GBT stress test, Id-Vg measurements were taken at regular intervals. In the transistor, with Vd=1.2V, Vs=0V, and Vbg=0V, Vg is - The measurement was performed by sweeping from 3.3V to +3.3V. Note that a keyer was used for the Id-Vg measurement. A semiconductor parameter analyzer manufactured by Ito Technology was used. Additionally, a +GBT stress test was performed. In the experiment, the change in Vsh from the start of measurement was used as an indicator of the amount of variation in the electrical characteristics of the transistor. We used ΔVsh to represent the quantity. We also evaluated the variation of the S value with respect to stress time.

[0488] Figure 26A shows the results of the +GBT stress test on element A and element B. The horizontal axis represents stress time (hr), and the vertical axis represents ΔVsh (mV).

[0489] As shown in Figure 26A, elements A and B are subjected to the above stress at 490 Even after time had passed, the change in shift voltage ΔVsh remained below 100mV. For details, see the basics. Child A's ΔVsh after 490 hours is -16mV, and element B's after 490 hours... The subsequent ΔVsh was -23mV.

[0490] Furthermore, Figure 26B shows the variation in S values ​​during the +GBT stress test for element A and element B. In Figure 26B, the horizontal axis represents stress time (hr), and the vertical axis represents the S value (mV / dec). ) indicates.

[0491] As shown in Figure 26B, elements A and B are subjected to the above stress at 490 Even as time passes, the fluctuation in the S value exceeds the range of 100mV / dec to 140mV / dec. It wasn't there.

[0492] From the above results, the transistor 200 using one aspect of the present invention has high reliability. I confirmed that.

[0493] The configurations, methods, etc., shown in this embodiment are at least partially described in other embodiments described herein. The method of implementation can be carried out in appropriate combination with other embodiments. [Explanation of Symbols]

[0494] 100: Capacitive element, 110: Conductor, 112: Conductor, 120: Conductor, 130: Insulator Body, 150: Insulator, 200: Transistor, 200_1: Transistor, 200_2: Transistor, 200_n: Transistor, 205: Conductor, 205a: Conductor, 205 b: Conductor, 210: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 21 7: Insulator, 218: Conductor, 222: Insulator, 224: Insulator, 230: Oxide, 23 0a: Oxide, 230A: Oxide film, 230b: Oxide, 230B: Oxide film, 230c: Acid compound, 230c1: oxide, 230c2: oxide, 230C: oxide film, 231: region, 2 31a: area, 231b: area, 234: area, 240: conductor, 240a: conductor, 2 40b: Conductor, 241: Insulator, 241a: Insulator, 241b: Insulator, 242: Conductor body, 242a: conductor, 242A: conductive film, 242b: conductor, 242B: conductive layer, 24 3: Oxide, 243a: Oxide, 243b: Oxide, 246: Conductor, 246a: Conductor , 246b: Conductor, 250: Insulator, 250A: Insulator, 254: Insulator, 254a: Insulator, 254A: Insulator, 254b: Insulator, 260: Conductor, 260a: Conductor, 2 60A: Conductive film, 260b: Conductor, 260B: Conductive film, 265: Sealing part, 265a: Sealing Stopper part, 265b: sealing part, 274: insulator, 280: insulator, 281: insulator, 282: Insulator, 283: Insulator, 300: Transistor, 311: Substrate, 313: Semiconductor area, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 32 0: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 33 0: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 40 0: Transistor, 405: Conductor, 430c: Oxide, 431a: Oxide, 431b: Oxide, 432a: Oxide, 432b: Oxide, 440: Conductor, 440a: Conductor, 4 40b: Conductor, 441: Insulator, 441a: Insulator, 441b: Insulator, 442a: Conductor Electrical material, 442b: Conductor, 450: Insulator, 460: Conductor, 460a: Conductor, 460 b: Conductor, 1001: Wiring, 1002: Wiring, 1003: Wiring, 1004: Wiring, 10 05: Wiring, 1006: Wiring, 1007: Wiring, 1008: Wiring, 1009: Wiring, 10 10: Wiring, 1100: USB memory, 1101: Enclosure, 1102: Cap, 1103 :USB connector, 1104: circuit board, 1105: memory chip, 1106: controller Chip, 1110: SD card, 1111: Housing, 1112: Connector, 1113: Circuit board ,1114: Memory chip, 1115: Controller chip, 1150: SSD, 115 1: Enclosure, 1152: Connector, 1153: Circuit board, 1154: Memory chip, 1155: Memory chip, 1156: controller chip, 1200: chip, 1201: PCB, 1202: Bump, 1203: Motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: Analog processing unit, 1214: Memory controller , 1215: Interface, 1216: Network circuit, 1221: DRAM, 1 222: Flash memory, 1400: Storage device, 1411: Peripheral circuit, 1420: Linear circuit Path, 1430: Column circuit, 1440: Output circuit, 1460: Control logic circuit, 1 470: Memory cell array, 1471: Memory cell, 1472: Memory cell, 1473: Memory cell, 1474: Memory cell, 1475: Memory cell, 1476: Memory cell, 1 477: Memory cell, 1478: Memory cell, 5100: Information terminal, 5101: Enclosure, 5 102: Display unit, 5200: Notebook-type information terminal, 5201: Main unit, 5202: Display unit, 5 203: Keyboard, 5300: Portable game console, 5301: Cabinet, 5302: Cabinet, 53 03: Enclosure, 5304: Display unit, 5305: Connection unit, 5306: Operation keys, 5400: Stand E: Stationary game console, 5402: Controller, 5500: Supercomputer, 550 1: Rack, 5502: Calculator, 5504: Circuit board, 5701: Display panel, 5702: Front Display panel, 5703: Display panel, 5704: Display panel, 5800: Electric refrigerator / freezer, 5801: Enclosure, 5802: Door for refrigerator compartment, 5803: Door for freezer compartment

Claims

[Claim 1] A semiconductor device having a transistor, The aforementioned transistor is A first insulator and The first oxide on the first insulator and, A first conductor, a second conductor, on the first oxide, The second insulator on the first oxide, The present invention comprises a third conductor on the second insulator, The upper surface of the first oxide in the region overlapping with the third conductor is lower than the upper surface of the first oxide in the region overlapping with the first conductor. In the region where the first oxide and the third conductor overlap, In a cross-sectional view of the transistor in the channel width direction, the first oxide has a curved surface, Let W be the length of the region on the upper surface of the first oxide that does not have a curved surface. When La is the difference between the height of the upper surface of the first oxide that does not have a curved surface and the height of the lower end of the region of the first oxide that has a curved surface, with respect to the lower surface of the first insulator, then La < W / 2. Semiconductor equipment.

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