Method for manufacturing semiconductor devices

Abstract

The present invention provides a semiconductor device with minimal variation in transistor characteristics and a method for manufacturing the same. [Solution] A method for manufacturing a semiconductor device includes: forming silicon nitride insulators 212 and 214 on a substrate; forming an insulator 216 on insulator 214; forming an opening on the insulator 214 thereon; forming conductors 205a and 205b; removing a portion of the conductor to expose insulator 216; forming an insulator 222 on insulator 216 and conductor 205; forming an insulator 224 thereon; forming an insulator 224 thereon; forming oxide 230a, oxide 230b, oxide layer 241B, conductor 240b, and insulator 271b using a lithography method; and forming an insulating film that will become an insulator 280 thereon.

Description

Technical Field

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a semiconductor device. Another aspect of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor devices include semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices, which are one aspect of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc. may be said to have semiconductor devices in some cases.

[0003] One aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

Background Art

[0004] Techniques for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface have attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.

[0005] In oxide semiconductors, CAAC (c-axis ali) is neither single crystal nor amorphous. gned crystalline) structure and nc (nanocrystalline) structure A structure has been found (see Non-Patent Documents 1 and 2).

[0006] Non-patent documents 1 and 2 describe using an oxide semiconductor having a CAAC structure. The technology for manufacturing a lunger has been disclosed. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] One aspect of the present invention provides a semiconductor device with less variation in transistor characteristics. This is one of the challenges. Furthermore, one aspect of the present invention provides a semiconductor device with good reliability. This is one of the challenges. Furthermore, one aspect of the present invention provides a semiconductor device having good electrical characteristics. One of the challenges is to achieve this. Furthermore, one aspect of the present invention relates to a semiconductor device with a large on-current. One of the objectives is to provide this. Furthermore, one aspect of the present invention enables miniaturization or high integration. One of the objectives is to provide a semiconductor device that can perform well. Furthermore, one aspect of the present invention is to provide a low-power consumption semiconductor device. One of our objectives is to provide semiconductor devices that can withstand high power.

[0009] Furthermore, the description of these problems does not preclude the existence of other problems. One approach does not require that all of these issues be resolved. The title will become clear from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the drawings, claims, etc. [Means for solving the problem]

[0010] One aspect of the present invention involves forming a first insulator film, and on the first insulator, a first oxide, a second An island-like laminate is formed by sequentially stacking an oxide and a first conductor, and a first insulator and a stack A second insulator is formed on the layer, and an opening is formed in the second insulator to expose the laminate. By removing the region exposed within the opening of the first conductor, the upper surface of the second oxide is exposed. After forming a second conductor and a third conductor, which are arranged on the second oxide, After cleaning, the side surface of the first oxide and the top surface of the second oxide are exposed inside the opening. And a first oxide film is formed in contact with the side surface, and a second oxide and After adding oxygen near the interface of the first oxide film, heat treatment is performed, and the first acid After forming a first insulating film and a first conductive film on the film, the first film is subjected to chemical polishing. By removing the conductive film, the first insulating film, the first oxide film, and a portion of the second insulator, The second insulator is exposed, and a fourth conductor and a third conductor are placed in an opening provided in the second insulator. It forms an insulator and a third oxide.

[0011] One aspect of the present invention involves forming a first insulator film, and on the first insulator, a first oxide, a second An island-like laminate is formed by sequentially stacking an oxide and a first conductor, and a first insulator and a stack A second insulator is formed on the layer, and an opening is formed in the second insulator to expose the laminate. By removing the region exposed within the opening of the first conductor, the upper surface of the second oxide is exposed. After forming a second conductor and a third conductor, which are arranged on the second oxide, After cleaning, the side surface of the first oxide and the top surface of the second oxide are exposed inside the opening. And a first oxide film is formed in contact with the side surface, and a second oxide and The process involves adding oxygen near the interface of the first oxide film, thereby creating a second oxide film on the first oxide film. A film is formed, and heat treatment is performed to create a first insulating film and a first conductive film on the second oxide film. After film formation, chemical polishing treatment is performed to remove the first conductive film, the second oxide film, the first insulating film, and the first By removing the oxide film and a portion of the second insulator, the second insulator is exposed, and the In the opening provided in the insulator 2, a fourth conductor, a third insulator, a third oxide, and a third It forms an oxide of 4.

[0012] In the above, it is preferable to use ion implantation for the oxygenation treatment.

[0013] In the above, in claim 1 or claim 2, in the ion implantation method, the second oxidation In the direction of the shorter side of the object, the oxygen ion is at an angle θ with respect to the tangent to the upper surface of the second oxide. It is preferable for the incident light to be incident at (45° < θ < 135°).

[0014] In the above, it is preferable to perform the heat treatment at a temperature of 350°C to 400°C.

[0015] In the above, the heat treatment is performed in an atmosphere containing 1% or more, or 10% or more, of an oxidizing gas. It is preferable to do so.

[0016] In the above, the first oxide and the third oxide have a wider oxygen content than the second oxide. It is preferable to suppress dispersion. [Effects of the Invention]

[0017] According to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics is provided. This can be achieved. Furthermore, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. It is possible. Furthermore, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. This is possible. Furthermore, according to one aspect of the present invention, a semiconductor device with a large on-current is provided. This is possible. Furthermore, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated is provided. It can be provided. Furthermore, according to one aspect of the present invention, a low-power semiconductor device can be provided. It is possible.

[0018] Furthermore, the description of these effects does not preclude the existence of other effects. One embodiment does not need to have all of these effects. Other effects are described in the specification. This will become clear from the description in the drawings, claims, etc., and the specification, drawings, claims From descriptions such as these, it is possible to extract other effects. [Brief explanation of the drawing]

[0019] [Figure 1] Figure 1A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 1B and 1C are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 2]Figure 2A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 2B and 2C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 3] Figure 3A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 3B and 3C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 4] Figure 4A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 4B and 4C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 5] Figure 5A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 5B and 5C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 6] Figure 6A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 6B and 6C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 7] Figure 7A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 7B and 7C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 8] Figure 8A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 8B and 8C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 9] Figure 9A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 9B and 9C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 10] Figure 10A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 10B and 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 11] Figure 11A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 11B and 11C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 12] Figures 12A, 12B, and 12C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 13] Figure 13A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 13B and 13C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 14] Figure 14A illustrates the classification of IGZO crystal structures. Figure 14B illustrates the XRD spectrum of quartz glass. Figure 14C illustrates the XRD spectrum of crystalline IGZO. Figure 14D illustrates the micro-electron diffraction pattern of crystalline IGZO. [Figure 15] Figure 15A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 15B and 15C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 16] Figures 16A and 16B are cross-sectional views of a semiconductor device according to one aspect of the present invention. [Figure 17] Figure 17A is a top view of a semiconductor device according to one embodiment of the present invention. Figures 17B and 17C are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 18] Figure 18A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 18B and 18C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 19] Figure 19A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 19B and 19C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 20] Figure 20A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 20B and 20C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 21] Figure 21A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 21B and 21C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 22]Figure 22A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 22B and 22C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 23] Figure 23A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 23B and 23C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 24] Figure 24A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 24B and 24C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 25] Figure 25A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 25B and 25C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 26] Figures 26A, 26B, and 26C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 27] Figure 27A is a top view showing a method for manufacturing a semiconductor device according to one aspect of the present invention. Figures 27B and 27C are cross-sectional views showing a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 28] Figures 28A and 28B are cross-sectional views of a semiconductor device according to one aspect of the present invention. [Figure 29] Figure 29 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. [Figure 30] Figure 30 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. [Figure 31] Figure 31 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. [Figure 32] Figure 32 is a cross-sectional view showing the configuration of a storage device according to one aspect of the present invention. [Figure 33] Figure 33 is a top view illustrating an apparatus for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 34] Figures 34A and 34B are a block diagram and a perspective view showing an example configuration of a storage device according to one aspect of the present invention. [Figure 35] Figures 35A to 35H are circuit diagrams showing an example of the configuration of a storage device according to one aspect of the present invention. [Figure 36] Figure 36 is a diagram showing various types of storage devices in a hierarchical structure. [Figure 37] Figures 37A and 37B are schematic diagrams of a semiconductor device according to one aspect of the present invention. [Figure 38] Figures 38A and 38B illustrate an example of an electronic component. [Figure 39] Figures 39A to 39E are schematic diagrams of a storage device according to one aspect of the present invention. [Figure 40] Figures 40A to 40H show an electronic device according to one aspect of the present invention. [Modes for carrying out the invention]

[0020] The embodiments will be described below with reference to the drawings. However, many embodiments are described. It can be implemented in different ways, without deviating from its purpose and scope. It will be readily apparent to those skilled in the art that the form and details can be varied in various ways. Therefore, the present invention shall not be construed as being limited to the contents described in the following embodiments.

[0021] Furthermore, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. This may be the case. Therefore, it is not necessarily limited to that scale. Note that the drawings are of the present invention. This is a schematic representation of one aspect and is not limited to the shapes or values ​​shown in the drawings. However, in the actual manufacturing process, processes such as etching can cause layers and resist masks to be removed. While some figures may decrease without being shown in the diagram, this is sometimes omitted to facilitate understanding. Furthermore, in drawings, the same reference numeral is used for identical parts or parts having similar functions, but different numerals are used for different parts. It is used in common across different surfaces, and explanations of its repetition may be omitted. Also, similar functions may be indicated. In such cases, the hatch pattern may be the same, and no specific designation may be assigned.

[0022] Furthermore, the invention is made easier to understand, especially in top views (also called "plan views") and perspective views. Therefore, the description of some components may be omitted. Also, some hidden lines and other markings may be omitted. The word "included" may be omitted in some cases.

[0023] Furthermore, the ordinal numbers used in this specification, etc., as "1st," "2nd," etc., are used for convenience only. It does not indicate the order of processes or stacking order. Therefore, for example, "the first" should be written as "the second". This can be explained by appropriately replacing it with "of" or "the third of," etc. The ordinal numbers described herein do not correspond to the ordinal numbers used to specify one aspect of the present invention. There are cases where this is the case.

[0024] Furthermore, in this specification, phrases indicating placement such as "above" and "below" refer to the relative positions of the components. The positional relationships are used for convenience in explaining them by referring to the diagram. Also, the positions of the components are shown. The relationships change as appropriate depending on the direction in which each component is described. Therefore, in the specification... The terms explained are not limited to those used in the text; they can be appropriately rephrased depending on the context.

[0025] For example, in this specification, it is explicitly stated that X and Y are connected. In this case, X and Y are electrically connected, and X and Y are functionally connected. The cases disclosed in this specification, etc., include cases where X and Y are directly connected. Therefore, it is limited to predetermined connection relationships, for example, connection relationships shown in a diagram or text. Furthermore, connections other than those shown in the diagram or text are also disclosed in the diagram or text. Let X and Y be the objects (e.g., devices, elements, circuits, wiring, electrodes, terminals). (Conductive film, layer, etc.)

[0026] Furthermore, in this specification, the term "transistor" includes a gate, a drain, and a source. It is an element having at least three terminals. And, drain (drain terminal, drain Between the drain region (or drain electrode) and the source (source terminal, source region, or source electrode) It has a region where channels are formed (hereinafter also called the channel-forming region), This design allows current to flow between the source and drain through a flannel-formed region. In this specification, the channel-forming region refers to the region through which electric current primarily flows.

[0027] Furthermore, the source and drain functions may differ when using transistors with different polarities, or when the circuit The direction of the current may change during operation, which can cause the current to switch positions. In detailed documents, the terms "source" and "drain" may be used interchangeably. ru.

[0028] Note that channel length refers to, for example, the length of the semiconductor (or transistor) in a top view of a transistor. When the inverter is ON, the part of the semiconductor through which current flows and the gate electrode overlap each other. In the region or channel-forming region, the source (source region or source electrode) and This refers to the distance between the drain (drain region or drain electrode) and the other terminal. In a zista, the channel length is not necessarily the same across all regions. That is, one The channel length of the transistor may not be fixed to a single value. Therefore, this specification So, the channel length is any one value, maximum value, minimum value, or This will be the average value.

[0029] Channel width refers to, for example, the top view of a transistor in a semiconductor (or transistor) The region where the gate electrode and the part of the semiconductor through which current flows when the gate electrode is ON overlap each other. Channels in a region or channel-forming region, perpendicular to the channel length direction. This refers to the length of the formation region. Note that in a single transistor, the channel width encompasses the entire region. They do not necessarily take the same value. In other words, the channel width of a single transistor is a single value. It may not be fixed. Therefore, in this specification, the channel width is defined as the channel formation region. This is one of the values, the maximum value, the minimum value, or the average value.

[0030] In this specification, depending on the transistor structure, channel formation may actually occur. The channel width in the region (hereinafter also referred to as the "effective channel width") and the transition The channel width shown in the top view of the stylus (hereinafter also referred to as the "apparent channel width") is as follows. ) and may differ. For example, when the gate electrode covers the side of the semiconductor, the effective ch When the channel width becomes larger than the apparent channel width, and its effect can no longer be ignored. For example, in a transistor that is very small and whose gate electrode covers the side of the semiconductor, the semiconductor In some cases, the proportion of channel-forming regions formed on the sides may increase. In such cases, the apparent The effective channel width will be larger than the channel width shown above.

[0031] In such cases, it can be difficult to estimate the effective channel width through actual measurements. For example, in order to estimate the effective channel width from the design value, the shape of the semiconductor is known. A certain assumption is necessary. Therefore, if the shape of the semiconductor is not precisely known, the effective It is difficult to accurately measure channel width.

[0032] In this specification, when simply referred to as "channel width," it refers to the apparent channel width. There is. Or, in this specification, when simply referred to as channel width, it means effective channel It can refer to width. Note that it can also refer to channel length, channel width, effective channel width, or apparent width. Channel width and other parameters can be determined by analyzing cross-sectional TEM images, etc. can.

[0033] Furthermore, semiconductor impurities refer to components other than the main components that make up the semiconductor, for example, concentrated Elements with a concentration of less than 0.1 atomic percent are considered impurities. The presence of impurities can, for example, lead to... In some cases, this can lead to an increase in the defect level density of semiconductors or a decrease in crystallinity. If the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, oxide semiconductors Other components besides the main component include transition metals, such as hydrogen, lithium, sodium, silicon, These include boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen vacancies (V) in oxide semiconductors. O :oxygen va In some cases, cancy (also known as cancy) may form.

[0034] In this specification, silicon oxidnitride is defined as having a composition that contains more oxygen than nitrogen. It has a high content of [something]. Also, silicon nitride oxide, in terms of its composition, has more oxygen than [something]. It has a high nitrogen content.

[0035] Furthermore, in this specification, the term "insulator" shall be replaced with "insulating film" or "insulating layer." It is possible to replace the term "conductor" with "conductive film" or "conductive layer." This is possible. Also, the term "semiconductor" can be replaced with "semiconductor film" or "semiconductor layer." can.

[0036] Furthermore, in this specification, "parallel" means that two straight lines have an angle of -10 degrees or more and 10 degrees or less. This refers to a state where objects are arranged in degrees. Therefore, it also includes cases where the angle is between -5 degrees and 5 degrees. Furthermore, "approximately parallel" means that two straight lines are positioned at an angle of -30 degrees or more and 30 degrees or less. It refers to a state or position. Also, "perpendicular" means that two straight lines are positioned at an angle of 80 degrees or more and 100 degrees or less. This refers to a state in which the temperature is between 85 and 95 degrees. Therefore, it also includes cases between 85 and 95 degrees. "Perpendicular" refers to a state where two straight lines are positioned at an angle between 60 degrees and 120 degrees.

[0037] In this specification, metal oxide refers to metal in a broad sense. It is an oxide. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). . ), oxide semiconductor (also called Oxide Semiconductor or simply OS) They are classified into categories such as . ) For example, when a metal oxide is used in the semiconductor layer of a transistor, The metal oxide in question is sometimes referred to as an oxide semiconductor. Therefore, it is sometimes described as an OS transistor. In such cases, it can be rephrased as a transistor having a metal oxide or oxide semiconductor. It is possible.

[0038] Furthermore, in this specification, normally off means not applying a potential to the gate, or When the gate is given a ground potential, the amount of drain flowing through the transistor per 1 μm of channel width is The current is 1 × 10 at room temperature. -20 A or less, 1 × 10 at 85℃ -18 Below A , or 1 × 10 at 125℃ -16 This means being less than or equal to A.

[0039] (Embodiment 1) In this embodiment, using Figures 1 to 12, a transistor 20 according to one aspect of the present invention An example of a semiconductor device having a value of 0, and a method for manufacturing the same, will be described.

[0040] <Example 1 of semiconductor device configuration> The configuration of a semiconductor device having transistor 200 will be explained using Figure 1. Figure 1C is a top view and a cross-sectional view of a semiconductor device having transistor 200. Figure 1A Figure 1B to Figure 1C are cross-sections of the semiconductor device. This is a diagram. Here, Figure 1B is a cross-sectional view of the area shown by the dashed line A1-A2 in Figure 1A. This is also a cross-sectional view of transistor 200 in the channel length direction. Furthermore, Figure 1C is a cross-sectional view of Figure 1A. This is a cross-sectional view of the area indicated by the dashed line in 3-A4, showing the channel width direction of transistor 200. This is also a cross-sectional view. Note that in the top view of Figure 1A, some elements have been omitted for clarity. ru.

[0041] A semiconductor device according to one aspect of the present invention comprises an insulator 212 on a substrate (not shown) and an insulator 212 The insulator 214 above, the transistor 200 on the insulator 214, and the transistor 200 above Insulator 280, insulator 282 on insulator 280, insulator 283 on insulator 282, It has: Insulator 212, Insulator 214, Insulator 280, Insulator 282, and Insulator 2 83 functions as an interlaminar membrane.

[0042] Furthermore, the conductor 246 (conductor) is electrically connected to the transistor 200 and functions as a plug. It has an electric body 246a and a conductor 246b). Note that the conductor 2 functions as a plug. An insulator 276 (insulator 276a and insulator 276b) is provided in contact with the side surface of 46. Furthermore, on the insulator 283 and on the conductor 246, there are electrically connected components. A conductor 248 (conductor 248a and conductor 248b) that functions as wiring is provided. Furthermore, an insulator 286 is provided on the conductor 248 and on the insulator 283.

[0043] Specifically, in contact with the inner walls of the openings of insulators 280, 282, and 283 An insulator 276a is provided, and the first conductive material of the conductor 246a is in contact with the side surface of the insulator 276a. A body is provided, and further inside, a second conductive material 246a is provided. The insulator 276b is in contact with the inner wall of the opening of the edge 280, insulator 282, and insulator 283. A first conductor of the conductor 246b is provided in contact with the side surface of the insulator 276b, Furthermore, a second conductor, conductor 246b, is provided on the inside.

[0044] Here, as shown in Figure 1B, the height of the upper surface of the conductor 246 and the region that overlaps with the conductor 248. The height of the top surface of the insulator 283 can be made to be approximately the same. Furthermore, in transistor 200, Regarding a configuration in which the first conductor and the second conductor of the conductor 246 are laminated: As shown, the present invention is not limited thereto. For example, the conductor 246 may be a single layer, Alternatively, it may be configured as a laminated structure of three or more layers. In some cases, ordinal numbers are assigned to distinguish them based on their formation order.

[0045] [Transistor 200] As shown in Figures 1A to 1C, the transistor 200 is located on the insulator 214. 6 and a conductor 205 (conductor 205a, o) arranged to be embedded in the insulator 216. The conductor 205b), the insulator 222 on the insulator 216, and the insulator 222 on the conductor 205, An insulator 224 on the edge body 222, an oxide 230a on the insulator 224, and an oxide 230a Oxide 230b, and oxide 241(oxide 241a, and oxide 241a) on oxide 230b, and oxide Material 241b) and oxide 230c, conductor 240a on oxide 241a, and conductor 2 The insulator 271a on 40a, the conductor 240b on the oxide 241b, and the conductor 240b The insulator 271b, the insulator 250 on the oxide 230c, and the acid located on the insulator 250. The conductor 260 (conductor 260a and conductor 260b) overlaps with a portion of the compound 230c. , has . Also, oxide 230c has sides of oxide 241a, sides of oxide 241b, The sides of the conductor 240a, the sides of the conductor 240b, the sides of the insulator 271a, and the insulating Each of them is in contact with the side surface of the edge body 271b.

[0046] Here, as shown in Figures 1B and 1C, the upper surface of the conductor 260 is above the insulator 250. The surface and the upper surface of oxide 230c are positioned in approximate agreement. In addition, the insulator 282 is a conductor The upper surfaces of the electrode 260, the insulator 250, the oxide 230c, and the insulator 280 are in contact with each other. do.

[0047] In the following, insulators 271a and 271b will be collectively referred to as insulator 271. There are cases where this is the case.

[0048] The insulator 280 is provided with an opening that reaches the oxide 230b. 230c, an insulator 250, and a conductor 260 are arranged. Also, transistor 2 In the channel length direction of 00, the conductor 240a and oxide 241a, and the conductor 240 Between b and oxide 241b, there is a conductor 260, an insulator 250, and oxide 230c. It is provided. The insulator 250 has a region that is in contact with the side surface of the conductor 260 and the conductor 260 It has a region that is in contact with the bottom surface. In addition, in the region that overlaps with oxide 230b, oxide 2 30c has a region in contact with the oxide 230b and a side surface of the conductor 260 via the insulator 250. It has an overlapping region and a region that overlaps with the bottom surface of the conductor 260 via the insulator 250.

[0049] Oxide 230 consists of oxide 230a placed on the insulator 224 and oxide 230a The oxide 230b is placed on top, and the oxide 230b is placed on top of the oxide 230b, and at least a portion of it is acid It is preferable to have an oxide 230c in contact with the oxide 230b.

[0050] Furthermore, the transistor 200 is made of oxide 230 (oxide 230a) which includes a channel formation region. , oxide 230b, and oxide 230c) are used to create metal oxides that function as semiconductors (hereinafter It is preferable to use an oxide semiconductor (also known as an oxide semiconductor).

[0051] Transistors using oxide semiconductors in the channel formation region exhibit extremely high conductivity in the non-conductive state. Because of its low leakage current, it can provide a semiconductor device with low power consumption. On the other hand, oxide semiconductors The transistor used had its electrical properties affected by impurities and oxygen vacancies in the oxide semiconductor. It fluctuates, and has normally-on characteristics (the channel exists even when no voltage is applied to the gate electrode). This is a characteristic that makes it easy for current to flow through a transistor.

[0052] Therefore, the oxide semiconductor used in the channel formation region of the transistor contains impurities and oxygen It is preferable to use a high-purity, intrinsic oxide semiconductor with reduced defects. In this context, a low impurity concentration and low defect level density indicate high purity intrinsic or substantially high purity. It is called "degree of authenticity."

[0053] However, in a transistor using an oxide semiconductor, the transistor is constructed In conductive materials, or in conductive materials used in plugs and wiring that connect to transistors, oxide semiconductors As the body gradually absorbs oxygen, oxygen deficiency can occur as one of the changes over time.

[0054] Therefore, after making oxide 230b substantially high-purity intrinsic, the channel of oxide 230b The region formed is formed by oxide 230a, which suppresses oxygen diffusion more than oxide 230b, and It is preferable to cover it with 230c oxide.

[0055] Specifically, as shown in the figure, oxide 230a is placed below oxide 230b. Therefore, the extraction of oxygen from oxide 230b can be suppressed. Oxygen and fumes from the structure formed below material 230a to oxide 230b It can suppress the diffusion of pure substances.

[0056] Furthermore, by placing oxide 230c on top of oxide 230b, This can suppress the extraction of oxygen. Also, above oxide 230c The diffusion of impurities from the formed structure to oxide 230b can be suppressed. .

[0057] Furthermore, the metal oxide that functions as a semiconductor has a band gap of 2 eV or more, preferably It is preferable to use gold with a band gap of 2.5 eV or higher. By using a specific oxide, the off-current of the transistor can be reduced.

[0058] For example, In-M-Zn, which has indium, element M, and zinc as oxide 230. Oxides (elements M include aluminum, gallium, yttrium, tin, copper, vanadium, and beryllium) Rium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, ra Tantalum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium It is preferable to use one or more metal oxides selected from among others. For 230, In-Ga oxide, In-Zn oxide, or indium oxide may be used. .

[0059] Here, oxide 230 has a layered structure of multiple oxide layers with different chemical compositions. Preferably. Specifically, the metal oxide used in oxide 230b is the original In for element M. The number of atoms is relative to the element M of the metal oxide used in oxide 230a or oxide 230c. It is preferable that the ratio is greater than the atomic ratio of In.

[0060] In other words, in the metal oxides used in oxide 230a and oxide 230c, the main component The atomic ratio of element M to other metal elements is such that the metal oxide used in oxide 230b It is preferable that the atomic ratio of element M to the main component metal element is greater than the atomic ratio of element M. Furthermore, in the metal oxide used in oxide 230a, the atomic ratio of element M to In is, The atomic ratio of element M to In in the metal oxide used in oxide 230b is greater than It is preferable that the metal oxide used in oxide 230b has a ratio of I to element M. The atomic ratio of n is such that in the metal oxides used for oxide 230a and oxide 230c, It is preferable that the atomic ratio of In to element M is greater than that of In.

[0061] Oxide 230a and oxide 230c have a common element other than oxygen (as the main component) By doing so, the interfaces of oxide 230a, oxide 230b, and oxide 230c The defect level density in this can be reduced. In this case, the main carrier pathway is oxidation. This becomes the interface between material 230b or its vicinity, for example, between oxide 230b and oxide 230c. The defect level density at the interface between oxide 230b and oxide 230c can be reduced. Therefore, the influence of interfacial scattering on carrier conduction is small, and a high on-current can be obtained.

[0062] For example, as oxide 230b, specifically, In:M:Zn = 4:2:3 [atomic ratio] ] or a composition in its vicinity, In:M:Zn=5:1:3 [atomic ratio] or its vicinity Gold with the following composition, or In:M:Zn=10:1:3 [atomic ratio] or a composition close to that. It is advisable to use group oxides, indium oxide, etc.

[0063] Furthermore, it is preferable that oxide 230b has crystalline properties. In particular, oxide 230b has , CAAC-OS(c-axis aligned crystalline oxide It is preferable to use an e-semiconductor.

[0064] CAAC-OS has c-axis orientation and multiple nanocrystals are linked in the ab-plane direction. It has a crystalline structure that is linked and distorted. Note that distortion refers to the linkage between multiple nanocrystals. Within a region, between a region with a aligned grid arrangement and another region with a aligned grid arrangement, the grid arrangement This refers to the point where the orientation has changed.

[0065] Nanocrystals are based on a hexagonal shape, but they are not necessarily regular hexagons; they can also be non-regular hexagonal. There are also cases where the distortion has a grid arrangement such as pentagons and heptagons. Furthermore, in CAAC-OS, even near strain, clear grain boundaries (grain bows) are present. It is difficult to confirm that it is also called a lattice. That is, due to the distortion of the lattice arrangement, It can be seen that the formation of grain boundaries is suppressed. This is because CAAC-OS is in the ab plane direction. In this case, the arrangement of oxygen atoms is not dense, and the substitution of metal elements increases the interatomic bond distance. This is because distortion can be tolerated due to changes in the distance between the elements.

[0066] Furthermore, crystal structures in which clear grain boundaries can be observed are known as multi-grain structures. It is called a polycrystal. The grain boundaries become recombination centers and carriers. This can lead to a decrease in the transistor's on-current or a decrease in its field-effect mobility. The possibility is high. Therefore, CAAC-OS, in which no clear grain boundaries can be confirmed, is a transistor. It is one of the crystalline oxides having a crystal structure suitable for semiconductor layers. (Note: CAAC-OS) A configuration having Zn is preferred for the structure. For example, In-Zn oxide and In- Ga-Zn oxide is preferred because it can suppress the generation of grain boundaries more effectively than In oxide.

[0067] Furthermore, CAAC-OS consists of a layer containing indium and oxygen (hereinafter referred to as the In layer), and A layered crystal in which layers containing element M, zinc, and oxygen (hereinafter referred to as (M,Zn) layers) are stacked. It tends to have a structure (also called a layered structure). Note that indium and element M are relative to each other. It is interchangeable, and if element M in the (M,Zn) layer is replaced with indium, then (In,M,Zn It can also be represented as a layer. Furthermore, if the indium in the In layer is replaced by element M, (In, It can also be represented as layer M.

[0068] As described above, CAAC-OS has a highly crystalline, dense structure, and is free from impurities and It is a metal oxide with few defects (such as oxygen deficiencies Vo). In particular, after the formation of the metal oxide, gold Heat treatment at a temperature that does not cause polycrystalline formation of the group oxides (for example, between 400°C and 600°C). This allows CAAC-OS to have a more crystalline and dense structure. In this way, the density of CAAC-OS is increased, thereby reducing the impurities in the CAAC-OS. Alternatively, it can further reduce oxygen diffusion.

[0069] On the other hand, CAAC-OS is difficult to identify clear grain boundaries, so it is difficult to identify grain boundaries. It can be said that a decrease in electron mobility due to CAAC-OS is less likely to occur. Metal oxides have stable physical properties. Therefore, metal oxides containing CAAC-OS are It is heat-resistant and highly reliable.

[0070] Furthermore, the region where the oxide 230b channel is formed is the source region of oxide 230b, Alternatively, the cross-sectional area in the width direction may be smaller than the area that functions as a drain region. Furthermore, in the processing step of creating an opening in the insulator 280, or in the cleaning step after the processing step, A portion of the surface of oxide 230b exposed at the bottom of the opening is removed, and grooves are formed in oxide 230b. A recess (hereinafter also referred to as a counterbore) may be formed.

[0071] Furthermore, in oxide 230b, it is preferable to embed oxide 230c in the groove portion. At this time, the oxide 230c is arranged to cover the inner wall (side wall and bottom surface) of the groove. It is placed there. Furthermore, the film thickness of oxide 230c may be approximately the same as the depth of the groove.

[0072] With the above configuration, when forming an opening for embedding the conductor 260, Even if a damaged area is formed on the surface of oxide 230b at the bottom of the mouth, the damaged area is repaired. This makes it possible to eliminate electrical defects in transistor 200 caused by the damaged area. It can suppress the positive effects.

[0073] In Figure 1B, the side of the opening into which the conductor 260 is embedded is also the groove portion of the oxide 230b. Including this, it is roughly perpendicular to the surface on which oxide 230b is formed, but in this embodiment This is not limited to the above. For example, a U-shaped opening with a gently curved bottom. It may take on a specific shape. Also, for example, the side surface of the opening may be relative to the surface to which oxide 230b is formed. It may be sloped.

[0074] Furthermore, as shown in Figure 1C, in a cross-sectional view of transistor 200 in the channel width direction, A curved surface may be present between the side surface of oxide 230b and the top surface of oxide 230b. The edges of the side surface and the edges of the top surface may be curved (hereinafter also referred to as rounded). .

[0075] The radius of curvature on the above curved surface is greater than 0 nm, and the oxide 2 in the region overlapping with the conductor 240. The length of the region of oxide 230b that is smaller than the film thickness of 30b, or the region that does not have the curved surface described above. It is preferable that it be less than half. Specifically, the radius of curvature of the curved surface is greater than 0 nm. Preferably 20 nm or less, 1 nm to 15 nm, and more preferably 2 nm or more. The size should be less than 0 nm. By creating this shape, the insulator 250 formed in a later process will be smaller. Furthermore, the coverage of the conductor 260 in the groove can be improved. This prevents a decrease in the length of the region without the region, and suppresses a decrease in the on-current and mobility of transistor 200. Therefore, it is possible to provide a semiconductor device with good electrical characteristics. .

[0076] Conductor 260 functions as the first gate (also called the top gate) electrode, and conductor 205 functions as the second gate (also called the back gate) electrode. It is also an insulator. 250 functions as the first gate insulator, and insulator 224 functions as the second gate insulator. It functions as such. Also, the conductor 240a functions as either the source electrode or the drain electrode. Furthermore, the conductor 240b functions as either the source electrode or the other of the drain electrode. Also, acid At least a portion of the region of the compound 230 that overlaps with the conductor 260 is used as a channel-forming region. To be able to.

[0077] Furthermore, the conductor 260 and the insulator 250 are shared between adjacent transistors 200. It may be used throughout. That is, the conductor 260 of transistor 200 The conductor 260 of the transistor 200 adjacent to the st 200 is provided in a continuous region with respect to the conductor 260 of the transistor 200. In addition, the insulator 250 of transistor 200 is adjacent to the transistor 200. It has a region that is provided in continuous with the insulator 250 of the transistor 200.

[0078] Insulator 212, insulator 214, insulator 271, insulator 282, insulator 283, and insulator The edge body 286 is susceptible to impurities such as water and hydrogen from the substrate side or on top of the transistor 200. It is preferable that it functions as a barrier insulating film that suppresses diffusion from one side to the transistor 200. It seems so.

[0079] In this specification, a barrier insulating film refers to an insulating film that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (low permeability). (Also known as) capturing and fixing the corresponding substance (also known as gettering) (u) To be a function.

[0080] Therefore, insulator 212, insulator 214, insulator 271, insulator 282, insulator 283, And insulator 286 contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxides. It has the function of suppressing the diffusion of impurities such as ions (N2O, NO, NO2, etc.) and copper atoms. It is preferable to use an insulating material that does not easily allow the above-mentioned impurities to permeate. Alternatively, oxygen (for example) , has the function of suppressing the diffusion of at least one of the oxygen atoms, oxygen molecules, etc. (the above oxygen It is preferable to use an insulating material (that is not easily permeable).

[0081] For example, silicon nitride may be used as the insulator 212, insulator 283, and insulator 286. Using aluminum oxide as the insulator 214, insulator 271, and insulator 282, It is preferable to use such a material. This allows impurities such as water and hydrogen to be absorbed into the insulator 212, The diffusion from the substrate side to the transistor 200 side via the insulator 214 is suppressed. Yes, it is possible. Alternatively, the oxygen contained in insulator 224, etc., can be absorbed by insulator 212 and insulator 214. This can suppress diffusion to the substrate side via this. Also, impurities such as water and hydrogen This suppresses diffusion from the insulator 280, conductor 248, etc., to the oxide 230. In this way, transistor 200 suppresses the diffusion of impurities such as water and hydrogen, as well as oxygen. Insulators 212, 214, 271, 282, and an insulating element having the function of insulating It is preferable to have a structure that surrounds it with a rim 283.

[0082] Furthermore, it is preferable to lower the resistivity of insulators 212, 283, and 286. There are cases where this is difficult. For example, the resistivity of insulators 212, 283, and 286. Approximately 1 × 10 13 By setting it to Ωcm, processing using plasma, etc. in semiconductor device manufacturing processes. In this, insulator 212, insulator 283, and insulator 286 are conductor 205, conductor A field in which the charge up of 240, conductor 260, or conductor 248 can be mitigated. There is a match. The resistivity of insulators 212, 283, and 286 is preferably, 1 x 10 10 Ωcm or more, 1 × 10 15 The density should be less than or equal to Ωcm.

[0083] Furthermore, insulators 216 and 280 have a lower dielectric constant than insulator 214. This is preferable. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings is reduced. For example, silicon oxide, oxide, silicon oxide can be used as insulator 216 and insulator 280. Silicon nitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon Silicon oxide with added carbon and nitrogen, silicon oxide with added carbon and nitrogen, porous silicon oxide You can use reconnaissance or similar methods as appropriate.

[0084] Furthermore, insulators 212, 214, and 216 were manufactured using the sputtering method. It is preferable to form the film by sputtering. Insulator 212, insulator formed by sputtering It is preferable that the hydrogen concentration in the film is low for 214 and the insulator 216. 12. The deposition of the insulators 214 and 216 is carried out continuously without exposure to the atmospheric environment. It is preferable to do so. By forming the film without exposing it to the atmospheric environment, the insulator 212, insulator 214, Furthermore, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulator 216. The interface between insulator 212 and insulator 214 and the vicinity of the interface, and the interface between insulator 214 and insulator 216 This is preferable because it allows the interface and the vicinity of the interface to be kept clean.

[0085] Conductor 205 may function as a second gate electrode. In that case, conductor 20 The potential applied to 5 is changed independently of the potential applied to the conductor 260, without being linked to it. This allows us to control the threshold voltage (Vth) of transistor 200. In particular, By applying a negative potential to the conductor 205, the Vth of transistor 200 can be increased. Therefore, it becomes possible to reduce the off-current. Thus, a negative potential is applied to the conductor 205. When applied, the voltage applied to the conductor 260 is greater than when not applied. The inductive current can be reduced.

[0086] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. The conductor 205 is preferably provided embedded in the insulator 214 or insulator 216. stomach.

[0087] Furthermore, as shown in Figure 1A, the conductor 205 is made of oxide 230a and oxide 230b If the area is made larger than the area that does not overlap with conductors 240a and 240b, Good. In particular, as shown in Figure 1C, the conductor 205 is oxide 230a and oxide 230 It is preferable that the region extends beyond the end of b that intersects with the channel width direction. In other words, the outer surface of the sides of oxide 230a and oxide 230b in the channel width direction On this side, it is preferable that the conductor 205 and the conductor 260 are superimposed with an insulator in between. It is so. With this configuration, the electric field of the conductor 260 which functions as the first gate electrode Then, the electric field of the conductor 205, which functions as a second gate electrode, causes the oxide 230 to charge. The flannel formation region can be electrically surrounded. In this specification, the first gate, and The electric field of the second gate electrically surrounds the channel formation region of the transistor. This structure is called a surrounded channel (S-channel) structure.

[0088] In this specification, etc., an S-channel transistor refers to a pair of gates. The electric fields of one and the other electrodes electrically surround the channel formation region. This represents the structure of the sta. Furthermore, the S-channel structure disclosed in this specification is a Fin-type structure. It differs from conventional and planar structures. By adopting an S-channel structure, short channels A transistor that is less susceptible to the Nell effect, or in other words, a transistor that is less prone to short-channel effects. It is possible.

[0089] Furthermore, as shown in Figure 1C, the conductor 205 is extended to function as wiring. However, this is not limited to the case where a conductor that functions as wiring is placed beneath the conductor 205. It is also possible to configure it in such a way. Furthermore, the conductor 205 is not necessarily provided one per transistor. There is no need to do so. For example, you can configure it so that the conductor 205 is shared by multiple transistors. stomach.

[0090] In transistor 200, the conductor 205 consists of conductor 205a and conductor 205b. The present invention describes a configuration in which layers are stacked, but is not limited thereto. For example, The conductor 205 may be provided as a single layer or as a laminated structure of three or more layers. When a body has a layered structure, ordinal numbers may be assigned to distinguish it based on the order of its formation.

[0091] Here, the conductor 205a consists of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and oxidation. It has the function of suppressing the diffusion of impurities such as nitrogen molecules (N2O, NO, NO2, etc.) and copper atoms. It is preferable to use a conductive material. Alternatively, oxygen (for example, oxygen atoms, oxygen molecules) It is preferable to use a conductive material that has the function of suppressing the diffusion of at least one of the following.

[0092] By using a conductive material that has the function of suppressing oxygen diffusion in the conductor 205a, This can suppress the oxidation of the conductor 205b and the resulting decrease in conductivity. Oxygen diffusion Examples of conductive materials that have the function of suppressing this include tantalum, tantalum nitride, and ruthenium. It is preferable to use um, ruthenium oxide, etc. Therefore, as conductor 205a The conductive material can be in a single layer or a laminate. For example, the conductor 205a is tanta Ruthenium, tantalum nitride, ruthenium, or ruthenium oxide, and titanium or titanium nitride. It may also be constructed as a laminate.

[0093] Furthermore, the conductor 205b is a conductive material mainly composed of tungsten, copper, or aluminum. It is preferable to use a material with properties. Although the conductor 205b is shown as a single layer, a laminated structure is also possible. This may also be done, for example, by laminating titanium or titanium nitride with the conductive material. .

[0094] Insulators 222 and 224 function as gate insulators.

[0095] The insulator 222 suppresses the diffusion of hydrogen (for example, at least one such as a hydrogen atom or hydrogen molecule). It is preferable that it has a function to control oxygen. Also, the insulator 222 is oxygen (for example, oxygen atoms, It is preferable that the function suppresses the diffusion of at least one of the following: oxygen molecules. For example, Insulator 222 suppresses the diffusion of hydrogen and / or oxygen more effectively than insulator 224. It is preferable that it has a function.

[0096] The insulator 222 is made of either or both aluminum and hafnium, which are insulating materials. It is preferable to use an insulator containing an oxide. Suitable insulators include aluminum oxide and hafni oxide. Using oxides containing um, aluminum, and hafnium (hafnium aluminate), etc. It is preferable that such a material is used to form the insulator 222. 2 is the release of oxygen from the oxide 230 to the substrate side, and oxidation from the periphery of the transistor 200. It functions as a layer that suppresses the diffusion of impurities such as hydrogen into material 230. Therefore, insulator 222 By providing this feature, the diffusion of impurities such as hydrogen into the inside of transistor 200 is suppressed. This can suppress the formation of oxygen vacancies in the oxide 230. Also, the conductor 205 is an absolute This suppresses the reaction between the surrounding material 224 and the oxygen present in the oxide 230.

[0097] Alternatively, the above insulator may contain, for example, aluminum oxide, bismuth oxide, or germanium oxide. Niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, oxide Zirconium may be added. Alternatively, these insulators may be nitrided. Also, Insulator 222 is made of silicon oxide, silicon oxide nitride, or silicon nitride. They may be used in stacked form.

[0098] Furthermore, the insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrT) (Io3), (Ba,Sr)TiO3 (BST), and other so-called high-k materials are included in the aqueous solution. The edge material may be used in a single layer or in a stacked configuration. As transistors become smaller and more integrated... Thinning the gate insulator can sometimes lead to problems such as leakage current. By using a high-k material as an insulator that functions as a body, the physical film thickness is maintained while... This allows for a reduction in the gate voltage during transistor operation.

[0099] Also, the insulator 224 preferably has a lower dielectric constant than the insulator 222. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 216 and the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, etc. may be appropriately used.

[0100] Note that the insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be

[0101] The oxide 241 (oxide 241a and oxide 241b) may be provided on the oxide 230b.

[0102] The oxide 241 (oxide 241a and oxide 241b) preferably has a function of suppressing oxygen permeation. By disposing the oxide 241 having a function of suppressing oxygen permeation between the conductor 240 that functions as a source electrode or a drain electrode and the oxide 230b, the electrical resistance between the conductor 240 and the oxide 230b is reduced, which is preferable. By adopting such a configuration, the electrical characteristics and reliability of the transistor 200 can be improved. Note that when the electrical resistance between the conductor 240 and the oxide 230b can be sufficiently reduced, the oxide 241 may not be provided.

[0103] As oxide 241, a metal oxide containing element M may be used. In particular, element M is A Luminium, gallium, yttrium, or tin may be used. Oxide 241 is an oxide. It is preferable that the concentration of element M is higher than that of substance 230b. Also, as oxide 241, Gallium may be used. Also, as oxide 241, a metallic acid such as In-M-Zn oxide may be used. A compound may also be used. Specifically, in the metal oxide used in oxide 241, with respect to In The atomic ratio of element M in oxide 230b is the element relative to In in the metal oxide used in oxide 230b. It is preferable that the atomic ratio is greater than that of element M. Also, the film thickness of oxide 241 is 0.5 nm or less. Preferably, the wavelength is 5 nm or less, more preferably 1 nm to 3 nm, and even more preferably 1 nm. The wavelength is between m and 2 nm. Furthermore, it is preferable that oxide 241 is crystalline. If 41 is crystalline, the release of oxygen from the oxide 230 can be effectively suppressed. For example, if oxide 241 has a crystalline structure such as hexagonal, then the acid in oxide 230 In some cases, it may be possible to suppress the release of primary substances.

[0104] Note that the oxide film that becomes oxide 230a, the oxide film that becomes oxide 230b, and oxide 24 It is preferable to continuously deposit the oxide film resulting in 1 without exposing it to the atmospheric environment. By forming the film without opening it, an oxide film that becomes oxide 230a and an oxide film that becomes oxide 230b are formed. , and impurities or moisture from the atmospheric environment adhering to the oxide film that becomes oxide 241. This can prevent the interface between the oxide film that becomes oxide 230a and the oxide film that becomes oxide 230b. and near the interface, the interface between the oxide film that becomes oxide 230b and the oxide film that becomes oxide 241 This is preferable because it allows for keeping the vicinity of the interface clean. This will be described later.

[0105] The conductor 240a is provided on the oxide 241a, and the conductor 240b is provided on the oxide 241b. The conductor 240a and the conductor 240b each function as a source electrode or a drain electrode of the transistor 200.

[0106] As the conductor 240 (the conductor 240a and the conductor 240b), for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. In one aspect of the present invention, nitrides containing tantalum are particularly preferred. Further, for example, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may be used. These materials are preferred because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen.

[0107] When the oxide 241 is not provided, the conductor 240 contacts the oxide 230b or the oxide 230c, and oxygen in the oxide 230b or the oxide 230c may diffuse into the conductor 240, causing the conductor 240 to oxidize. When the conductor 240 oxidizes, the probability of the conductivity of the conductor 240 decreasing is high. Note that the diffusion of oxygen in the oxide 230b or the oxide 230c into the conductor 240 can be rephrased as the conductor 240 absorbing oxygen in the oxide 230b or the oxide 230c.

[0108] ​Furthermore, oxygen in oxide 230b or oxide 230c is present in conductor 240a and conductor 2 By diffusing into 40b, the conductor 240a and oxide 230b, and the conductor 24 Between 0b and oxide 230b, or between conductor 240a and oxide 230c, and A layer may be formed between the conductor 240b and the oxide 230c. This layer is conductive. Because it contains more oxygen than body 240a or conductor 240b, the layer has insulating properties. It is estimated that at this time, the conductor 240a or conductor 240b, the layer, and the oxide 23 The three-layer structure with 0b or oxide 230c is considered to be a three-layer structure consisting of metal-insulator-semiconductor. It is possible to do this, MIS (Metal-Insulator-Semiconductor r) It can be seen as a diode junction structure mainly consisting of a structure or an MIS structure.

[0109] Furthermore, hydrogen contained in oxide 230b, oxide 230c, etc., is present in conductor 240a or It may diffuse into conductor 240b. In particular, into conductor 240a and conductor 240b, By using a nitride containing tantalum, the oxides contained in oxide 230b, oxide 230c, etc. Hydrogen readily diffuses into conductor 240a or conductor 240b, and the diffused hydrogen then enters the conductor. It may combine with nitrogen present in 240a or conductor 240b. In other words, oxide 23 Hydrogen contained in 0b, oxide 230c, etc., is absorbed by conductor 240a or conductor 240b. It may be stolen.

[0110] Furthermore, there may be a curved surface between the side surface of the conductor 240 and the top surface of the conductor 240. In other words, the edges of the sides and the edges of the top surface may be curved. Curved surfaces are, for example, guide At the end of the electric body 240, the radius of curvature is 3 nm or more and 10 nm or less, preferably 5 nm. The above is 6 nm or less. By not having corners at the edges, the film coverage in subsequent film deposition processes is improved. It will improve.

[0111] The insulator 271 is provided in contact with the upper surface of the conductor 240, and is at least resistant to oxygen. It is preferable that the insulator 271 also functions as a barrier insulating film. It is preferable that the insulator 271 has a function to suppress dispersion. For example, the insulator 271 is better than the insulator 280. It is preferable that the insulator also has the function of suppressing oxygen diffusion. For example, the insulator 271 is It is preferable to deposit an insulator containing an oxide of either or both aluminum and hafnium. Furthermore, as the insulator 271, for example, an insulator containing silicon nitride may be used.

[0112] Also, oxide 230a, oxide 230b, oxide 241, conductor 240, insulator 271 An insulator may be provided to cover the sides. This insulator provides at least a barrier against oxygen. It is preferable that it functions as an insulating film. In other words, the insulator is a device that suppresses the diffusion of oxygen. It is preferable that the insulator has the ability to suppress oxygen diffusion more effectively than insulator 280. It is preferable that the insulator has a controlling function. Examples of such insulators include aluminum and It is preferable to deposit an insulator containing one or both oxides of hafnium.

[0113] In particular, the insulator 271 is made of aluminum oxide by sputtering in an oxygen-containing atmosphere. It is preferable to deposit a film of nium or hafnium oxide. The sputtering method is performed in a hydrogen atmosphere. Because it does not contain ambient air, it can suppress the inclusion of hydrogen, which is an impurity.

[0114] By providing the insulator 271, oxide 230a, oxide 230b, oxide 241, and The conductor 240 can be separated from the insulator 280. Therefore, oxide 230a, Oxygen is directly distributed from the insulator 280 to oxide 230b, oxide 241, and conductor 240. Dispersion can be suppressed. Therefore, the source region and drain region of oxide 230 An excess of oxygen is supplied to the region, reducing the carrier density in both the source and drain regions. This can prevent this. Also, if the conductor 240 is excessively oxidized, the resistivity will increase, and the ON-EV This can suppress the reduction in flow.

[0115] Insulator 250 functions as a gate insulator. Insulator 250 is on top of oxide 230c It is preferable to arrange them in contact with the surface. The insulator 250 is silicon oxide, silicon oxide and nitride. silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, carbon-added acid Silicon oxide, silicon oxide with added carbon and nitrogen, porous silicon oxide, etc. It can be used. In particular, silicon oxide and silicon oxide-nitride are stable to heat. Therefore, it is preferable.

[0116] Insulator 250, like insulator 224, uses an insulator that releases oxygen when heated. It is preferable to form an insulator that releases oxygen upon heating, as insulator 250. By providing it in contact with the upper surface of oxide 230c, the channel formation region of oxide 230b This effectively supplies oxygen and reduces oxygen deficiency in the channel formation region of oxide 230b. Yes, it is possible. Therefore, it suppresses fluctuations in electrical characteristics and has stable electrical characteristics, and reliable It is possible to provide a transistor with improved reliability. Also, similar to insulator 224, It is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. The film thickness of 50 is preferably between 1 nm and 20 nm.

[0117] Note that in Figures 1B and 1C, the insulator 250 is shown as a single layer, but a laminated structure of two or more layers is also shown. It may also be constructed as follows. When the insulator 250 has a two-layer laminated structure, the lower layer of the insulator 250 is added It is formed using an insulator that releases oxygen due to heat, and the upper layer of the insulator 250 allows for oxygen diffusion. It is preferable to form it using an insulator that has a suppressive function. This suppresses the diffusion of oxygen contained in the lower layer of the insulator 250 into the conductor 260. This is possible. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to oxide 230. This makes it possible to suppress the oxidation of the conductor 260 by oxygen contained in the lower layer of the insulator 250. For example, the lower layer of the insulator 250 may be made of a material that can be used for the insulator 250 as described above. The upper layer of the insulator 250 can be provided using the same material as the insulator 222. ru.

[0118] Furthermore, when silicon oxide or silicon oxide nitride is used as the lower layer of the insulator 250, The upper layer of body 250 may be made of an insulating material, which is a high-k material with a high dielectric constant. The gate insulator is constructed with a laminated structure consisting of a lower layer of insulator 250 and an upper layer of insulator 250. A layered structure that is stable against heat and has a high dielectric constant can be created. Therefore, the gate The gate voltage applied during transistor operation can be reduced while maintaining the physical thickness of the insulator. This becomes possible. Also, a thin film of equivalent oxide film thickness (EOT) of an insulator that functions as a gate insulator. This makes transformation possible.

[0119] Specifically, the upper layer of insulator 250 is made of hafnium, aluminum, gallium, and Thorium, zirconium, tungsten, titanium, tantalum, nickel, germanium, A metal oxide containing one or more metals selected from magnesium, or an acid Metal oxides that can be used as oxide 230 can be used. In particular, aluminum It is preferable to use an insulator containing oxides of um and / or hafnium.

[0120] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The material preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 is reduced. Dispersion is suppressed. In other words, the decrease in the amount of oxygen supplied to oxide 230 can be suppressed. Furthermore, the oxidation of the conductor 260 by oxygen in the insulator 250 can be suppressed.

[0121] Furthermore, it is preferable that the above metal oxide functions as part of the first gate electrode. For example, a metal oxide that can be used as oxide 230 is the above metal oxide. It can be used in this way. In that case, the conductive material 260a is deposited by sputtering. The electrical resistance of the above metal oxide can be reduced to make it a conductor. This is called OC(O It can be called an xide conductor electrode.

[0122] Having the above metal oxide, the influence of the electric field from the conductor 260 is not weakened. The on-current of the transistor 200 can be improved. Also, the insulator 250 and the above metal The physical thickness of the group oxide maintains the distance between the conductor 260 and the oxide 230. This makes it possible to suppress leakage current between the conductor 260 and the oxide 230. Also, By providing a laminated structure with the edge body 250 and the metal oxide, the conductor 260 and the oxide are formed. The physical distance between 230 and the conductor 260, and the electric field strength from the conductor 260 to the oxide 230. It can be easily adjusted as needed.

[0123] Conductor 260 functions as the first gate electrode of transistor 200. Conductor 26 0 comprises a conductor 260a and a conductor 260b disposed on top of the conductor 260a. Preferably, the conductor 260a encloses the bottom and sides of the conductor 260b. It is preferable to arrange them in this manner. Also, as shown in Figures 1B and 1C, the conductor 260 The upper surface of the oxide 230c is approximately the same as the upper surface of the insulator 250 and the upper surface of the oxide 230c. In Figures 1B and 1C, the conductor 260 has a two-layer structure consisting of conductor 260a and conductor 260b. As shown, it may be a single-layer structure or a laminated structure of three or more layers.

[0124] Conductor 260a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules. It is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms. Alternatively, a device that inhibits the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule). It is preferable to use a conductive material that has conductivity.

[0125] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, the insulator 250 The oxygen contained in the material suppresses the oxidation of the conductor 260b, which reduces its conductivity. Yes, it is possible. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum and nitrogen. It is preferable to use tantalum oxide, ruthenium oxide, or the like.

[0126] Furthermore, since the conductor 260 also functions as wiring, a highly conductive conductor 260b is used. It is preferable to use an electrostatic material. For example, the conductor 260b may be tungsten, copper, or A conductive material mainly composed of luminium can be used. In addition, the conductor 260b is multiplicative A layered structure is also acceptable, for example, a laminated structure of titanium or titanium nitride and the above-mentioned conductive material. That is also acceptable.

[0127] Furthermore, in transistor 200, the conductor 260 is formed on an insulator 280 or the like. The conductor 260 is formed in a self-aligning manner to fill the opening. Therefore, the conductor 260 is positioned in the region between the conductor 240a and the conductor 240b. It can be positioned reliably without any problems.

[0128] Furthermore, as shown in Figure 1C, in the channel width direction of transistor 200, insulator 2 When the bottom surface of 22 is used as a reference, the conductor 260 and the oxide 230b overlap. Preferably, the height of the bottom surface of the region that does not undergo this process is less than or equal to the height of the bottom surface of oxide 230b. The conductor 260, which functions as a gate electrode, is connected to oxide 230b via an insulator 250, etc. By configuring the channel formation region to cover the sides and top surfaces, the electric field of the conductor 260 is acidic This makes it easier to apply the substance 230b to the entire channel formation region. Therefore, transistor 20 The ON current of 0 can be increased, improving the frequency characteristics. The bottom surface of the insulator 222 When used as a reference, if oxides 230a and 230b and conductor 260 overlap, The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in the region without conductors is , 0 nm to 100 nm, preferably 3 nm to 50 nm, more preferably, The wavelength should be between 5nm and 20nm.

[0129] The insulator 280 is on the insulator 224, oxide 230, conductor 240, and insulator 271. It is provided therein. The upper surface of the insulator 280 may also be flattened.

[0130] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. By using the material as an interlayer film, parasitic capacitance occurring between wiring can be reduced. Insulator 28 It is preferable that 0 be provided using a material similar to that of the insulator 216, for example. In particular, oxide Silicon oxide and silicon nitride are preferred because they are thermally stable. In particular, silicon oxide Materials such as silicon oxidnitride and silicon oxide with voids release oxygen upon heating. This is preferable because it allows for the easy formation of a region containing [the specified element].

[0131] Furthermore, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. Furthermore, the insulator 280 may also have a structure in which the above-mentioned materials are laminated, for example, sputtering Silicon oxide film deposited by the chemimetric method, and chemical vapor deposition (CVD) layered on top of it. Laminated structure of silicon oxide nitride deposited by the (Cal Vapor Deposition) method This can be done by constructing it this way. Alternatively, silicon nitride may be laminated on top of it.

[0132] Insulator 282 or insulator 283 is susceptible to impurities such as water and hydrogen from above. It is preferable that it functions as a barrier insulating film that suppresses diffusion. Also, insulator 28 2 or insulator 283 is preferred to function as a barrier insulating film that suppresses oxygen permeation. For example, insulators 282 and 283 may be aluminum oxide, silica nitride, etc. An insulator such as silicon nitride can be used. For example, as insulator 282, acid Aluminum oxide, which has high blocking properties against the element, is used as the insulator 283, and hydrogen Alternatively, silicon nitride, which has high blocking properties, can be used.

[0133] Conductors 246a and 246b are primarily composed of tungsten, copper, or aluminum. It is preferable to use conductive materials as components. Also, conductor 246a and conductor 24 6b may be a laminated structure.

[0134] Furthermore, when the conductor 246 is made into a laminated structure, the insulator 284, insulator 283, insulator 28 2. The conductor in contact with the insulator 280 and the insulator 271 is permeable to impurities such as water and hydrogen. It is preferable to use a conductive material that has a function to suppress overheating. For example, tantalum, nitride It is preferable to use tantalum, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Furthermore, conductive materials that have the function of suppressing the permeation of impurities such as water and hydrogen are single-layer or It may be used in a laminated form. Also, impurities such as water and hydrogen contained in the layer above the insulator 284 This suppresses the mixing of conductors 246a and 246b into the oxide 230. It is possible.

[0135] Examples of insulators 276a and 276b include silicon nitride and aluminum oxide. Insulators such as um and silicon nitride can be used. Insulator 276a and Insulator 27 Since 6b is provided in contact with the insulator 271a, water and hydrogen contained in the insulator 280, etc. These impurities are introduced into the oxide 230 through the conductors 246a and 246b. This can suppress the process. In particular, silicon nitride has high blocking properties for hydrogen. Therefore, it is suitable. Also, the oxygen contained in the insulator 280 is suitable for conductor 246a and conductor 24 This prevents absorption by 6b.

[0136] Furthermore, it functions as wiring in contact with the upper surface of the conductor 246a and the upper surface of the conductor 246b. Conductors 248 (conductors 248a and conductors 248b) may be arranged. 48 uses a conductive material whose main component is tungsten, copper, or aluminum. This is preferable. The conductor may also have a laminated structure, for example, titanium or nitride. The titanium and the conductive material may be laminated. The conductor is provided on the insulator. It may be formed to be embedded in the opening.

[0137] The insulator 286 is provided on the conductor 248 and on the insulator 283. This allows, The upper surface and the side surface of the conductor 248 are in contact with the insulator 286, and the conductor 248 The lower surface is in contact with the insulator 283. In other words, the conductor 248 is in contact with the insulator 283 and the insulating It can be configured to be enclosed by body 286. With such a configuration, acid from the outside This suppresses the transmission of the element and prevents oxidation of the conductor 248. Furthermore, it is preferable because it can prevent impurities such as water and hydrogen from diffusing to the outside.

[0138] <<Metal Oxides>> As oxide 230, a metal oxide (oxide semiconductor) that functions as a semiconductor is used. This is preferable. Below, metal oxides applicable to the oxide 230 according to the present invention will be described. do.

[0139] The metal oxide preferably contains at least indium or zinc. In particular, indium Preferably, it contains aluminum and zinc. In addition, aluminum and gallium It is preferable that it contains yttrium, tin, etc. Also, boron, titanium, iron, nitrile Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Ha One or more elements selected from phnium, tantalum, tungsten, magnesium, etc. It may include

[0140] Here, the metal oxide is In-M-Zn oxide, which has indium, element M, and zinc. Let's consider the case where it is a substance. Note that element M is aluminum, gallium, yttrium, and Let M be tin. Other elements that can be used for element M include boron, titanium, iron, and nickel. Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium Examples include um, tantalum, tungsten, and magnesium. However, as for element M, as mentioned above... In some cases, it is acceptable to combine multiple elements.

[0141] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). They are sometimes collectively referred to as metal oxynitrides (metal oxides). Also, metal oxides containing nitrogen are sometimes called metal oxynitrides (metal oxides). It may also be called tal oxynitride.

[0142] [Structure of metal oxides] Oxide semiconductors (metal oxides) include single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. It can be divided into conductors and conductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS, multi-phase crystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous (us-like oxide semiconductors), and amorphous oxide semiconductors It has a body, etc.

[0143] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially regions larger than 1 nm). It has periodicity in the atomic arrangement in the region of 3 nm or less. Also, nc-OS has different na No regularity is observed in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analytical method, nc-OS may be a-like OS or amorphous oxide semiconductor. It can sometimes be indistinguishable from the body.

[0144] Furthermore, In- is a type of metal oxide containing indium, gallium, and zinc. Ga-Zn oxide (hereinafter referred to as IGZO) adopts a stable structure when formed into the nanocrystals described above. In some cases, IGZO tends to have difficulty growing crystals in the atmosphere, so large bonds may form. Crystals smaller than crystals (here, crystals of several millimeters or several centimeters) (for example, as mentioned above) In some cases, forming the material into nanocrystals can result in a more structurally stable material.

[0145] a-like OS is a metallic acid having a structure between nc-OS and amorphous oxide semiconductors. It is a monster. a-like OS has porous or low-density regions. That is, a-li ke OS has lower crystallinity compared to nc-OS and CAAC-OS.

[0146] Oxide semiconductors (metal oxides) can take on diverse structures, each possessing different properties. An oxide semiconductor according to one aspect of the present invention is an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, and a-li It may have two or more of the following: ke OS, nc-OS, and CAAC-OS.

[0147] In addition to the oxide semiconductors mentioned above, there is also CAC (Cloud-Aligned Com Posite-OS may be used.

[0148] CAC-OS refers to a material that possesses both conductive and insulating properties in some parts. It possesses the properties of a semiconductor as a whole. Note that CAC-OS or CAC-m When ethanol oxide is used in the active layer of a transistor, its conductive function is due to the carrier The function of A is to allow electrons (or holes) to flow, and the insulating function is to allow the carrier electrons to flow. It has a function that prevents the flow of current. The conductive function and the insulating function work complementaryly with each other. By doing so, the switching function (the function to turn on / off) is controlled by CAC-OS or CA It can be imparted to C-metal oxide. CAC-OS or CAC-met In aluminum oxides, separating each function maximizes the performance of both. It can be improved.

[0149] Furthermore, CAC-OS or CAC-metal oxide has conductive and insulating properties. It has regions. The conductive region has the conductive function described above, and the insulating region has the insulating function described above. It has the function of [this]. Furthermore, within the material, the conductive region and the insulating region are at the nanoparticle level. In some cases, they are separated by a rib. Also, conductive regions and insulating regions are located within the material. They may be unevenly distributed. Furthermore, the conductive regions appear blurred around the edges and connected in a cloud-like pattern. There are cases where this occurs.

[0150] Furthermore, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region The marginal region is defined as being between 0.5 nm and 10 nm, preferably between 0.5 nm and 3 nm. These particles may be dispersed in the material at the following sizes.

[0151] Furthermore, CAC-OS or CAC-metal oxide have different band gaps. It is composed of the following components. For example, CAC-OS or CAC-metal oxid e. Components with a wide gap due to the insulating region and a narrow gap due to the conductive region It is composed of a component having a gap. In this configuration, when the carrier is flowed, In components with a low gap, the carrier mainly flows. Also, in components with a narrow gap The component acts complementaryly with the component having a wide gap, and the component having a narrow gap Carriers also flow to components with a wide gap in conjunction with the minutes. Therefore, the above CAC - OS or CAC-metal oxide is used in the channel formation region of the transistor. In this case, the transistor has a high current driving force in the ON state, i.e., a large ON current, and high A field effect mobility can be obtained.

[0152] In other words, CAC-OS or CAC-metal oxide is a matrix composite material. (matrix composite), or metal matrix composite (metal It can also be called a matrix composite.

[0153] Furthermore, when focusing on the crystal structure, oxide semiconductors may be classified differently from those mentioned above. Here, we will explain the classification of crystal structures in oxide semiconductors using Figure 14A. To proceed. Figure 14A shows an oxide semiconductor, typically IGZO (containing In, Ga, and Zn). This is a diagram illustrating the classification of the crystal structures of metal oxides.

[0154] As shown in Figure 14A, IGZO can be broadly divided into Amorphous and, They are classified into Crystalline and Crystal. Amorphous includes completely amorphous molecules. Furthermore, within Crystalline, there is CAAC (c-axis aligned). crystalline), nc (nanocrystalline), and CAC (C This includes loud-Aligned Composite. The classification of INE includes single crystal, polycrystal, and c Completely amorphous elements are excluded. Also, within Crystal, This includes single crystals and polycrystals.

[0155] The structures within the thick frame shown in Figure 14A are Amorphous and Crystal. It is an intermediate state between al (crystal) and a new boundary region (New crystallin This structure belongs to the e phase. This structure is Amorphous and Cryst It lies in the boundary region between al and Amor. In other words, this structure is energetically unstable. To put it another way, it's a structure that is completely different from phous (amorphous) or crystal (crystalline). It is possible.

[0156] The crystal structure of the film or substrate can be determined by X-ray diffraction (XRD). It can be evaluated using an ion image. Here, quartz glass and Crystal XRD of IGZO (also called crystalline IGZO) having a crystal structure classified as ine The vectors are shown in Figures 14B and 14C. Figure 14B shows quartz glass, and Figure 14C shows crystalline glass. This is the XRD spectrum of IGZO. Note that the composition of crystalline IGZO shown in Figure 14C is I The ratio of n:Ga:Zn is approximately 4:2:3 [atomic ratio]. Also, the crystalline IG shown in Figure 14C The thickness of ZO is 500 nm.

[0157] As shown by the arrow in Figure 14B, the shape of the peak in the XRD spectrum of quartz glass is approximately It is symmetrical. On the other hand, as shown by the arrow in Figure 14C, crystalline IGZO has XRD spectrum The peak shape of the clef is asymmetrical. The peak shape of the XRD spectrum is asymmetrical. The fact that it is named indicates the presence of a crystal. In other words, the peak of the XRD spectrum A shape cannot be considered amorphous unless it is symmetrical. Note that Figure 14C shows , 2θ=31° or near that, IGZO crystal phase It is clearly stated. The reason why the peaks in the XRD spectrum are asymmetrical is as follows. This is presumed to be due to the crystalline phase (microcrystals).

[0158] Specifically, in the XRD spectrum of crystalline IGZO shown in Figure 14C, 2θ=3 It has a peak at 4° or nearby. Also, the microcrystals have a peak at 2θ=31° or nearby. It has a peak. When evaluating an oxide semiconductor film using X-ray diffraction patterns, as shown in Figure 14C... In other words, the spectral width is wider at angles lower than the peak at 2θ=34° or its vicinity. This is because the oxide semiconductor film contains microcrystals having a peak at or near 2θ = 31°. This suggests that it is inherent.

[0159] Furthermore, the crystalline structure of the film is determined by nano-beam electron diffraction (NBED). Diffraction patterns observed by tron ​​diffraction (micro-electron diffraction) It can be evaluated using the pattern (also called a pattern). IGZ film deposited at room temperature. The diffraction pattern of the O film is shown in Figure 14D. Note that the IGZO film shown in Figure 14D is In:Ga Using an oxide target with an atomic ratio of Zn=1:1:1, the sputtering method is applied to Therefore, a film is formed. In addition, in the ultra-micro electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm. It was carried out.

[0160] As shown in Figure 14C, the diffraction pattern of the IGZO film deposited at room temperature shows a halo, rather than A spot-like pattern is observed. Therefore, the IGZO film deposited at room temperature is in a crystalline state. It is neither an amorphous state nor a non-amorphous state; it is an intermediate state, and it cannot be concluded that it is an amorphous state. It is presumed that it will not be possible.

[0161] [impurities] Here, we will explain the effects of various impurities in metal oxides.

[0162] When impurities are introduced into oxide semiconductors, defect levels or oxygen vacancies may be formed. Therefore, when impurities are mixed into the channel formation region of the oxide semiconductor, the oxide semiconductor is affected. The electrical characteristics of the transistors used can be prone to fluctuations, which can lead to poor reliability. If the channel formation region contains oxygen deficiency, the transistor tends to have normally-on characteristics (characteristics in which a channel exists without applying a voltage to the gate electrode and current flows through the transistor). and become more likely to occur.

[0163] In a transistor using a metal oxide, due to impurities and oxygen deficiency in the metal oxide, its electrical characteristics fluctuate and it tends to have normally-on characteristics. Also, when the transistor is driven in a state where the metal oxide has an excessive amount of oxygen exceeding an appropriate value, the valence of the excessive oxygen atoms changes, and the electrical characteristics of the transistor fluctuate, which may result in poor reliability.

[0164] Therefore, it is preferable to use a metal oxide with a low carrier concentration in the channel formation region of the transistor. When reducing the carrier concentration of the metal oxide, the impurity concentration in the metal oxide may be reduced and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high purity intrinsic or substantially high purity intrinsic. In this specification and the like, when the carrier concentration of the metal oxide in the channel formation region is 1×10 16 cm -3 or less, it is defined as substantially high purity intrinsic.

[0165] Also, the carrier concentration of the metal oxide in the channel formation region is preferably 1×10 18 cm -3 or less, more preferably 1×10 17 cm -3 or less, even more preferably 1×10 1 6 cm -3 or less, and still more preferably 1×10 13 cm -3 ​​​Being less than More preferably, 1 × 10 12 cm -3 It is even more preferable that it be less than [a certain value]. There are no particular limitations on the lower limit of the carrier concentration of the metal oxide in the formation region, but for example, 1 x 10 -9 cm -3 It can be done this way.

[0166] Examples of impurities in metal oxides include hydrogen, nitrogen, alkali metals, and alkalis. Examples include earth metals, iron, nickel, and silicon. In particular, hydrogen contained in metal oxides is a metal. Because it reacts with oxygen that bonds to atoms to form water, it can sometimes form oxygen vacancies in metal oxides. Yes. If the channel-forming region in the metal oxide contains oxygen vacancies, the transistor will be no - Marione properties may occur. Furthermore, when hydrogen enters the oxygen vacancy in the metal oxide... In combination, oxygen-deficient atoms and hydrogen combine to form V O Sometimes H is formed. A vacancy where hydrogen is placed in an oxygen vacancy. (V O H) can function as a donor, and electrons, which are carriers, may be generated. When some of the hydrogen combines with oxygen that is bonded to a metal atom, it generates electrons, which are carriers. Therefore, transistors using metal oxides that contain a lot of hydrogen are normally It tends to exhibit ionic properties. Also, hydrogen in metal oxides is affected by stress such as heat and electric fields. Because it moves easily, if metal oxides contain a lot of hydrogen, the reliability of transistors deteriorates. There is a risk that this may happen.

[0167] In one embodiment of the present invention, V in oxide 230 O Reduce H as much as possible, high purity intrinsic Alternatively, it is preferable to make it substantially high-purity intrinsic. Thus, V O H was sufficiently reduced. To obtain metal oxides, impurities such as water and hydrogen must be removed from the metal oxide (dehydration). (This is sometimes referred to as dehydrogenation treatment.) This involves supplying oxygen to the metal oxide to compensate for the oxygen deficiency. It is important to do this (sometimes referred to as oxygenation treatment). V O Impurities such as H By using a sufficiently reduced metal oxide in the channel formation region of the transistor, stability is achieved. It is possible to impart specific electrical characteristics.

[0168] A defect in which hydrogen is inserted into an oxygen vacancy (V O H) can function as a donor for metal oxides. However, it is difficult to quantitatively evaluate the defect in metal oxides. In some cases, the evaluation is based on the carrier concentration rather than the donor concentration. Therefore, this specification, etc. So, as a parameter for metal oxides, instead of donor concentration, let's consider the state where no electric field is applied. In some cases, the assumed carrier concentration may be used. That is, the "carrier concentration" described in this specification, etc. " can sometimes be rephrased as "donor concentration." Also, as described in this specification, etc. "Carrier concentration" can be rephrased as "carrier density."

[0169] Therefore, it is preferable that the hydrogen content in the metal oxide be reduced as much as possible. Specifically, In metal oxides, secondary ion mass spectrometry (SIMS) is used. The hydrogen concentration obtained by mass spectrometry is 1 × 10⁻⁶ 20 at oms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than, more 5 x 10 18 atoms / cm 3 Less than 1 × 1018 atoms / cm 3 It shall be less than. Metal oxides with sufficiently reduced impurities such as hydrogen are used as transistor channels. By using it in the region where the material is formed, stable electrical properties can be imparted.

[0170] Furthermore, the above defect levels may include trap levels. (Metal oxide traps) Charges trapped in energy levels take a long time to disappear, almost like fixed charges. This behavior can occur. Therefore, metal oxides with a high trap level density can form channels in the channel formation region. Transistors in this context may exhibit unstable electrical characteristics.

[0171] Furthermore, if impurities are present in the channel formation region of an oxide semiconductor, the channel formation region will Crystallinity may be low, and the crystallinity of the oxide provided in contact with the channel formation region The value may be low. If the crystallinity of the channel formation region is low, the stability of the transistor may also be affected. This tends to worsen reliability. Also, the oxide formation adjacent to the channel formation region If the crystallinity is low, interface states may form, which can worsen the stability or reliability of the transistor. There is.

[0172] Therefore, in order to improve the stability or reliability of transistors, oxide semiconductor chips Reducing the impurity concentration in the channel formation region and its vicinity is effective. These include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and others.

[0173] Specifically, in the channel formation region of the oxide semiconductor and its vicinity, SIMS The concentration of the impurities obtained by this method is 1 × 10 18 atoms / cm 3 The following, preferably 2 x 10 16 atoms / cm 3 Do the following: Or, channel formation of the oxide semiconductor. The concentration of the above impurities obtained by elemental analysis using EDX in the region and its vicinity. This should be reduced to 1.0 atomic% or less. Note that the oxide semiconductor in question is an oxide containing element M. When using the material, in the channel formation region of the oxide semiconductor and its vicinity, element M The concentration ratio of the above impurities to is set to less than 0.10, preferably less than 0.05. The concentration of element M used when calculating the above concentration ratio is the same as the concentration of the impurity in the region from which the above impurity concentration was calculated. The concentration may be in the same region, or it may be the concentration in the oxide semiconductor in question.

[0174] Furthermore, metal oxides with reduced impurity concentrations have a lower defect level density, thus reducing the trap level density. The degree may also decrease.

[0175] Furthermore, in transistors using oxide semiconductors, the channel formation region in the oxide semiconductor is incomplete. The presence of pure materials and oxygen vacancies can cause the oxide semiconductor to exhibit low resistance. Electrical characteristics can be prone to fluctuations, which can lead to poor reliability.

[0176] For example, silicon has a greater bonding energy with oxygen than indium and zinc. For example, when using In-M-Zn oxide as an oxide semiconductor, the oxide semiconductor When silicon is mixed in, the oxygen contained in the oxide semiconductor is taken away by the silicon. In some cases, oxygen deficiencies may form near indium or zinc.

[0177] In a transistor using an oxide semiconductor for the channel formation region, the channel formation region When a low-resistance region is formed, the source electrode and drain electrode of the transistor are connected in that low-resistance region. Leakage current (parasitic channel) is likely to occur between the poles. Also, due to this parasitic channel... This involves the normally-on state of the transistor, increased leakage current, and threshold due to stress application. Voltage fluctuations (shifts) and other transistor characteristic defects are more likely to occur. If the processing precision of the transistor is low, the parasitic channel will vary from transistor to transistor, This can lead to variations in the characteristics of the transistors.

[0178] Therefore, in the channel formation region of the oxide semiconductor and its vicinity, the impurity It is preferable that oxygen deficiency be minimized as much as possible.

[0179] <Method for fabricating semiconductor devices> Next, a method for manufacturing a semiconductor device, which is one embodiment of the present invention, as shown in Figures 1A to 1C, is shown in Figure 2. Figures A to 11A, 2B to 11B, 2C to 11C, and 12A to 12 Let's explain using C.

[0180] Figures 2A to 11A show top views. Figures 2B to 11B show top views. This is a cross-sectional view corresponding to the area shown by the dashed line A1-A2 in A, and transistor 200 These are also cross-sectional views in the channel length direction. Figures 2C to 11C are also cross-sectional views in the channel length direction. The cross-sectional view corresponds to the area indicated by the dashed line A3-A4, and shows the chain of transistor 200. This is also a cross-sectional view in the width direction of the panel. Note that in the top views of Figures 2A to 11A, for clarity of the diagram... Some elements have been omitted for this reason.

[0181] First, a substrate (not shown) is prepared, and an insulator 212 is deposited on the substrate. The deposition of 212 can be done by sputtering, CVD, or molecular beam epitaxy (MBE). cular beam epitaxy (PLD) method, pulsed laser deposition (PLD) Atomic Layer Deposition (ALD) This can be done using methods such as the (ER Deposition) method.

[0182] Furthermore, the CVD method is a type of plasma CVD (PECVD) that utilizes plasma. Enhanced CVD (Enhanced CVD), Thermal CVD (TCVD: Thermal CCVD) which utilizes heat. It can be classified into methods such as the VD method and the photoCVD method which utilizes light. Depending on the source gas used, the process can be metal CVD (MCVD) or organometallic CVD. It can be divided into (MOCVD: Metal Organic CVD) methods.

[0183] Plasma CVD can produce high-quality films at relatively low temperatures. Thermal CVD, on the other hand, is a method that can produce high-quality films at low temperatures. A film deposition method that does not use Zuma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) included in semiconductor devices. ) and others can be charged up by receiving an electric charge from the plasma. In cases where the accumulated charge destroys the wiring, electrodes, and elements contained in the semiconductor device. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage occurs. Therefore, the yield of semiconductor devices can be increased. Also, in the thermal CVD method, Because plasma damage does not occur within the film, a film with fewer defects can be obtained.

[0184] Furthermore, in the ALD method, the reaction between the precursor and reactant is carried out using only thermal energy. Thermal ALD (Thermal Altode Discharge) method, using plasma-excited reactants. Methods such as EALD (Plasma Enhanced Alopecia) can be used.

[0185] Furthermore, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer. Because it is possible to deposit ultra-thin films, it is possible to deposit films on structures with a high aspect ratio, pinhole It enables film formation with fewer defects such as blemishes, enables film formation with excellent coverage, and enables film formation at low temperatures. What are the effects? In the PEALD (Plasma Enhanced ALD) method, Using Zuma can enable film deposition at lower temperatures, which is preferable in some cases. Some precursors used in the D method contain impurities such as carbon. Therefore, the ALD method... The film formed by this method contains more impurities such as carbon compared to films formed by other film formation methods. It may contain [unclear]. Furthermore, the quantitative determination of impurities is performed by X-ray photoelectron spectroscopy (XPS). This can be done using hotoelectron Spectroscopy.

[0186] CVD and ALD are film deposition methods in which particles emitted from a target or other source are deposited. Unlike other methods, this is a film-forming method in which a film is formed by a reaction on the surface of the object being treated. This film-forming method is less affected by the shape of the workpiece and has good step-level coverage. Furthermore, the ALD method has excellent step coverage and excellent thickness uniformity, thus aspect ratio This method is suitable for coating the surface of high-aperture openings, etc. However, the ALD method is relatively suitable for film formation. Because of its slow rate, it should be used in combination with other film deposition methods that have a faster deposition rate, such as CVD. In some cases, this may be preferable.

[0187] The CVD and ALD methods control the composition of the resulting film by adjusting the flow rate ratio of the source gases. This is possible. For example, in the CVD method and ALD method, the flow rate ratio of the raw material gas can be adjusted as needed. A film with the following composition can be formed. Furthermore, for example, in the CVD method and ALD method, film formation can be performed. By changing the flow rate ratio of the raw material gas while simultaneously depositing a film with a continuously changing composition. This is possible. When forming a film while changing the flow rate ratio of the raw material gas, multiple deposition chambers can be used. Compared to the method of film deposition using a conveyor belt, it eliminates the time required for transport and pressure adjustment, thus reducing the time required for film deposition. The interval can be shortened. Therefore, the productivity of semiconductor devices can be increased. There is.

[0188] In this embodiment, silicon nitride is formed as the insulator 212 by sputtering. To form a membrane.

[0189] Thus, as the insulator 212, an insulator that is impermeable to copper, such as silicon nitride, is used. By doing so, easily diffusible metals such as copper can be introduced into the conductor layer (not shown) below the insulator 212. Even when using this method, it is possible to suppress the upward diffusion of the metal through the insulator 212. Furthermore, using an insulator that is resistant to the permeability of impurities such as water and hydrogen, such as silicon nitride. This suppresses the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212. can.

[0190] Next, an insulator 214 is deposited on the insulator 212. The insulator 214 is deposited by sputtering. This can be performed using methods such as the kerning method, CVD method, MBE method, PLD method, and ALD method. In this application, aluminum oxide is deposited as the insulator 214 by sputtering. do.

[0191] The hydrogen concentration of insulator 214 is preferably lower than the hydrogen concentration of insulator 212. By depositing silicon nitride film as 212 using the sputtering method, the hydrogen concentration is low. Silicon nitride can be formed. Also, by using aluminum oxide for the insulator 214... Therefore, the hydrogen concentration can be lower than that of insulator 212.

[0192] In the following step, a transistor 200 is formed on the insulator 214, For membranes close to 200, it is preferable to have a relatively low hydrogen concentration, and for membranes with a relatively high hydrogen concentration... It is preferable to position it remotely from transistor 200.

[0193] Next, an insulator 216 is deposited on the insulator 214. The insulator 216 is deposited by sputtering. This can be performed using methods such as the kerning method, CVD method, MBE method, PLD method, and ALD method. In the application method, the insulator 216 is made of silicon oxide or oxide by sputtering. A silicon nitride film is deposited.

[0194] Furthermore, insulators 212, 214, and 216 are subjected to reduced pressure without being exposed to the atmospheric environment. It is preferable to continuously deposit the film under the following conditions. By depositing the film without exposure to the atmospheric environment, an insulator is formed. Impurities or moisture from the atmospheric environment adhere to insulators 212, 214, and 216. This prevents the interface between insulator 212 and insulator 214 and the vicinity of the interface from becoming insulated. This is preferable because it allows the interface between the body 214 and the insulator 216, and the vicinity of the interface, to be kept clean. Continuous film deposition can be performed, for example, by using a multi-chamber type deposition apparatus. This makes it possible to shorten the manufacturing process time for semiconductor devices, which is desirable.

[0195] Next, an opening is formed in the insulator 216 that reaches the insulator 214. The opening is, for example, a groove or This also includes slits, etc. Furthermore, the term "opening" can sometimes refer to the area where an opening has been formed. The opening can be formed using wet etching, but dry etching is preferable. This is preferable for microfabrication. In addition, the insulator 214 forms grooves by etching the insulator 216. It is preferable to select an insulator that functions as an etching stopper film during the etching process. When silicon oxide or silicon oxide nitride is used for the insulator 216 that forms the groove, The edge material 214 may be silicon nitride, aluminum oxide, or hafnium oxide.

[0196] As a dry etching apparatus, a capacitively coupled plasma (CCP) system with parallel plate electrodes is used. (Capacitively Coupled Plasma) Etching apparatus is used. Capacitively coupled plasma etching apparatus having parallel plate electrodes can be used. Alternatively, a high-frequency voltage may be applied to one electrode of the type electrode. Or, one of the parallel plate type electrodes. Alternatively, a configuration in which multiple different high-frequency voltages are applied to the electrodes may be used. Or a parallel plate type electrode Alternatively, a configuration in which the same high-frequency voltage is applied to each of them is also possible. Alternatively, a configuration in which high-frequency voltages of different frequencies are applied may be used. Or, a high-density plasma source may be used. A dry etching apparatus can be used. Dry etching with a high-density plasma source. The device is, for example, an inductively coupled plasma (ICP) device. Etching equipment such as an ed Plasma etching device can be used.

[0197] After the opening is formed, a conductive film that will become the conductor 205a is formed. The conductive film allows oxygen to permeate. It is desirable to include a conductor that has a suppressive function. For example, tantalum nitride, tan nitride Gusten, titanium nitride, etc. can be used. Alternatively, a function to suppress oxygen permeation can be used. Conductors possessing tantalum, tungsten, titanium, molybdenum, aluminum, copper, and It can be formed as a laminated film with a rib-den tungsten alloy. The conductive film is deposited by sputtering. This can be performed using methods such as the ring method, CVD method, MBE method, PLD method, and ALD method.

[0198] In this embodiment, the conductive film that becomes the conductor 205a has a multilayer structure. First, sputtering A tantalum nitride film is formed by a tangent molding process, and titanium nitride is then laminated on top of the tantalum nitride film. By using such a metal nitride as the lower layer of the conductor 205b, the conductor 20 described later Even if a diffusible metal such as copper is used as the conductive film for 5b, if the metal is conductor 205 This can prevent diffusion from a to the outside.

[0199] Next, a conductive film that will become the conductor 205b is formed. The formation of this conductive film is done by plating, spalling, etc. This can be done using methods such as Taring, CVD, MBE, PLD, and ALD. In this embodiment, a low-resistance conductive material such as copper is used as the conductive film that becomes the conductor 205b. To form a membrane.

[0200] Next, by performing chemical mechanical polishing (CMP) treatment, the conductive film that becomes the conductor 205a, and A portion of the conductive film that becomes the conductor 205b is removed, exposing the insulator 216. Conductors 205a and 205b remain only at the opening. As a result, the top surface is flat. Furthermore, a conductive material 205 can be formed (see Figures 2A to 2C). The P treatment may remove a portion of the insulator 216.

[0201] In the above, the conductor 205 was formed to be embedded in the opening of the insulator 216. However, this embodiment is not limited to this. For example, a conductor 20 on an insulator 214 Form 5, deposit an insulator 216 on the conductor 205, and perform CMP treatment on the insulator 216. This means that a portion of the insulator 216 can be removed, exposing the surface of the conductor 205.

[0202] Next, an insulator 222 is formed on the insulator 216 and the conductor 205. As such, an insulating film containing an oxide of aluminum and / or hafnium is formed. It is desirable to do so. Furthermore, an insulator containing an oxide of either aluminum or hafnium or both. Examples include aluminum oxide, hafnium oxide, and aluminum and hafnium oxides. It is preferable to use materials such as aluminum and hafnium aluminate. Insulators containing oxides of one or both of the elements provide a barrier against oxygen, hydrogen, and water. It holds.

[0203] The insulator 222 has barrier properties against hydrogen and water, so transistor 200 Hydrogen and water contained in the structure provided around it transition through the insulator 222 Diffusion into the interior of sta 200 is suppressed, and the formation of oxygen vacancies in oxide 230 is suppressed. It is possible.

[0204] The insulator 222 was deposited using sputtering, CVD, MBE, PLD, and ALD methods. This can be done using methods such as [mention specific methods].

[0205] Next, it is preferable to perform a heat treatment. The heat treatment is preferably performed at a temperature of 250°C to 650°C. It is preferable to carry it out at a temperature of 300°C to 500°C, and more preferably at 320°C to 450°C. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or with an oxidizing gas for 10 minutes. The procedure should be carried out in an atmosphere containing ppm or more, 1% or more, or 10% or more. For example, nitrogen gas and oxygen. When performing heat treatment in a gas mixture atmosphere, it is sufficient to use about 20% oxygen gas. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out under nitrogen gas or an inert gas. After heat treatment in an atmosphere, an oxidizing gas of 10 ppm or more is added to replenish the desorbed oxygen. Heat treatment may be carried out in an atmosphere containing % or more, or 10% or more.

[0206] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, The amount of moisture contained in the gas used in the heat treatment described above is 1 ppb or less, preferably 0.1 ppb or less. More preferably, the level should be 0.05 ppb or less. Heat treatment using highly purified gas. By performing this process, it is possible to prevent moisture and other substances from being absorbed into the insulator 222, etc., as much as possible. can.

[0207] In this embodiment, as a heat treatment, after the film formation of the insulator 222, nitrogen gas and oxygen gas are used. The treatment is performed at a temperature of 400°C for 1 hour with a flow rate ratio of 4 slm: 1 slm. This method allows for the removal of impurities such as water and hydrogen contained in the insulator 222. Furthermore, when using an oxide containing hafnium as the insulator 222, the heat treatment will This can improve the crystallinity of the insulator 222. Also, the heat treatment improves the insulator 22 This can also be done at a later stage, such as after film deposition (step 4).

[0208] Next, an insulator 224 is deposited on the insulator 222. The insulator 224 is deposited by sputtering. This can be performed using methods such as the kerning method, CVD method, MBE method, PLD method, and ALD method. In the application method, silicon oxide or silicon oxiditride is used as the insulator 224 by the ALD method. A film is formed. The insulator 224 is formed using a gas in which hydrogen atoms have been reduced or removed. It is preferable to form the film using this method. This reduces the hydrogen concentration of the insulator 224. Yes, it is possible. The insulator 224 will be the insulator 224 that comes into contact with the oxide 230a in a later process. It is preferable that the hydrogen concentration is reduced in this manner.

[0209] Alternatively, the insulator 224 may be subjected to plasma treatment containing oxygen under reduced pressure. By appropriately selecting the processing conditions, impurities such as water and hydrogen contained in the insulator 224 can be removed. It can be removed.

[0210] Here, aluminum oxide is applied to the insulator 224, for example, by sputtering. After film formation, CMP treatment may be performed until the insulator 224 is reached. This process allows for the planarization and smoothing of the surface of the insulator 224. By placing nium on the insulator 224 and performing CMP processing, the endpoint detection of the CMP processing can be easily performed. It becomes easy. Also, due to the CMP treatment, a part of the insulator 224 is polished, and the insulator 224 The film thickness may become thin, but this can be corrected by adjusting the film thickness during the deposition of the insulator 224. 224 Planarizing and smoothing the surface prevents deterioration of the coverage of the oxide film that will be deposited later. This can sometimes prevent a decrease in the yield of semiconductor devices.

[0211] Next, oxide films 230A and 230B are sequentially deposited on the insulator 224 (Figure 2A). See Figure 2C. ).

[0212] The oxide films 230A and 230B were deposited by sputtering, CVD, and MBE. This can be done using methods such as the PLD method and the ALD method.

[0213] For example, oxide film 230A and oxide film 230B are deposited by sputtering. In this case, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. Furthermore, when the above oxide film is deposited by sputtering, the above In-M-Zn acid Monster targets and the like can be used.

[0214] In this embodiment, the oxide film 230A is formed by sputtering, using the In:Ga: The film is deposited using an oxide target with a Zn = 1:3:4 [atomic ratio]. Also, oxide film 23 As 0B, by sputtering, In:Ga:Zn=4:2:4.1 [atomic ratio] The film is deposited using the oxide target of ]. Note that each oxide film is formed under different deposition conditions and atomic ratios. By selecting appropriately, the desired properties for oxide 230a and oxide 230b can be determined. It is good to form it.

[0215] Next, an oxide film 241A is formed on the oxide film 230B (see Figures 2A to 2C). Film 241A was deposited using sputtering, CVD, MBE, PLD, ALD, etc. It can be done using the following method. Oxide film 241A has an atomic ratio of Ga to In, which is the same as oxide film 2 It is preferable that the atomic ratio of Ga to In in 30B is greater than that of In. In this embodiment, acid As coating film 241A, In:Ga:Zn=1:3:4[atoms The film is deposited using an oxide target in a numerical ratio.

[0216] Furthermore, oxide films 230A, 230B, and 241A are not exposed to the atmospheric environment. It is preferable to deposit the film continuously under reduced pressure. By depositing the film without exposure to the atmospheric environment, oxidation is prevented. Impurities or water from the atmospheric environment are present on film 230A, oxide film 230B, and oxide film 241A. This prevents the adhesion of particles, and the interface and boundary between oxide film 230A and oxide film 230B. The vicinity of the surface, the interface between oxide film 230B and oxide film 241A, and the vicinity of the interface can be kept clean. This is preferable. For example, a multi-chamber type film deposition apparatus can be used. Continuous film deposition This is preferable because it makes it possible to shorten the manufacturing process time for semiconductor devices.

[0217] Next, it is preferable to perform a heat treatment. The heat treatment is performed on oxide film 230A and oxide film 230B. The process should be carried out within a temperature range in which the oxide film 241A does not undergo polycrystallization, which is between 250°C and 650°C. The following steps should preferably be performed at a temperature of 400°C to 600°C. Note that the heat treatment is performed using nitrogen gas. Alternatively, an inert gas atmosphere, or an oxidizing gas at 10 ppm or more, 1% or more, The process should be carried out in an atmosphere containing 10% or more of the substance. For example, heat treatment should be performed in a mixed atmosphere of nitrogen and oxygen gas. In this case, the oxygen gas concentration should be around 20%. Also, the heat treatment can be performed under reduced pressure. Alternatively, the heat treatment may involve heating in a nitrogen or inert gas atmosphere followed by desorption. An atmosphere containing oxidizing gas at a concentration of 10 ppm or more, 1% or more, or 10% or more to replenish the oxygen. Heat treatment may be performed in an open atmosphere.

[0218] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, The amount of moisture contained in the gas used in the heat treatment described above is 1 ppb or less, preferably 0.1 ppb or less. More preferably, the level should be 0.05 ppb or less. Heat treatment using highly purified gas. By performing this process, moisture, etc., is removed from oxide film 230A, oxide film 230B, and oxide film 241A. This can prevent it from being absorbed as much as possible.

[0219] In this embodiment, the heat treatment is performed at a temperature of 550°C for 1 hour in a nitrogen atmosphere. After this, the process is carried out continuously in an oxygen atmosphere at a temperature of 550°C for 1 hour. According to the principle, water, hydrogen, etc. in oxide film 230A, oxide film 230B, and oxide film 241A This allows for the removal of impurities, etc. Furthermore, this heat treatment results in the oxide film 230B This improves the crystallinity and creates a denser, more compact structure. The diffusion of oxygen or impurities within the film 230B can be reduced.

[0220] Next, a conductive film 240A is deposited on the oxide film 241A (see Figures 2A to 2C). The 240A film can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. This can be done using the following method. For example, as conductive film 240A, using the sputtering method A tantalum nitride film can be deposited. Note that even if heat treatment is performed before depositing the conductive film 240A, Good. The heat treatment is carried out under reduced pressure and without exposure to the atmosphere, continuously applying the conductive film 240 A may be formed into the film. By performing such a process, the surface of the oxide film 241A, etc. The adsorbed moisture and hydrogen are removed, and further oxide film 230A, oxide film 230B, and The water and hydrogen concentrations in the oxide film 241A can be reduced. Heat treatment temperature The temperature is preferably between 100°C and 400°C. In this embodiment, the heat treatment temperature is set to 200°C. Let's use °C.

[0221] Next, an insulating film 271A is deposited on the conductive film 240A (see Figures 2A to 2C). The edge film 271A is deposited using sputtering, CVD, MBE, PLD, or ALD. This can be done using methods such as the law. The insulating film 271A has the function of suppressing oxygen permeation. It is preferable to use an insulating film. For example, as insulating film 271A, sputtering method Alternatively, aluminum oxide, hafnium oxide, or silicon nitride can be produced by the ALD method. You just need to deposit a film.

[0222] Next, a conductive film 291A is deposited on the insulating film 271A (see Figures 2A to 2C). Film 291A was deposited using sputtering, CVD, MBE, PLD, or ALD. This can be done using methods such as the above. The conductive film 291A is, for example, similar to the conductive film 240A. Using an electrochemical film would suffice.

[0223] In this embodiment, the conductive film 240A, insulating film 271A, and conductive film 291A are as follows: By sputtering, conductive film 240A is tantalum nitride, and insulating film 271A is oxidized Aluminum and conductive film 291A are each coated with tantalum nitride.

[0224] Furthermore, the conductive film 240A, insulating film 271A, and conductive film 291A are not exposed to the atmospheric environment. It is preferable to deposit the film continuously under reduced pressure. By depositing the film without exposure to the atmospheric environment, Impurities from the atmospheric environment are removed from the conductive film 240A, insulating film 271A, and conductive film 291A. This prevents moisture from adhering, and the interface between the conductive film 240A and the insulating film 271A The interface and the vicinity of the interface, the interface between the insulating film 271A and the conductive film 291A, and the vicinity of the interface are kept clean. This is preferable because it allows for continuous deposition. For example, a multi-chamber type film deposition apparatus can be used. Depositing a film allows for a reduction in the manufacturing process time of semiconductor devices, which is desirable.

[0225] Next, using lithography, oxide film 230A, oxide film 230B, and oxide film 241A were obtained. The conductive film 240A, insulating film 271A, and conductive film 291A are processed into island shapes, and oxide 2 30a, oxide 230b, oxide layer 241B, conductive layer 240B, insulating layer 271B, and A conductive layer 291B is formed (see Figures 3A to 3C). This process is performed using dry etching. Dry etching can be used. Suitable for microfabrication. Also, oxide film 230A, oxide film 230B, oxide film 241A, conductive The processing of film 240A, insulating film 271A, and conductive film 291A was carried out under different conditions. The process may be carried out in a manner that does not overlap with the oxide 230a of the insulator 224. The film thickness in that area may become thinner.

[0226] In lithography, the resist is first exposed through a mask. Next, exposure... The selected area is removed or left intact using a developer to form a resist mask. Next, By etching through the resist mask, conductors, semiconductors, or insulators can be etched. These can be processed into desired shapes. For example, KrF excimer laser light, ArF excimer laser light Using sima laser light, EUV (Extreme Ultraviolet) light, etc., A resist mask can be formed by exposing the dyst. Also, the relationship between the substrate and the projection lens An immersion technique may be used, in which a liquid (e.g., water) is filled in between and then exposed. Alternatively, the aforementioned light Alternatively, electron beams or ion beams may be used. When using this method, a mask is not required. Note that a resist mask is used in processes such as ashing. After performing dry etching, wet etching, and dry etching Perform wet etching, or dry etching after wet etching. It can be removed by performing the necessary procedures.

[0227] Furthermore, a hard mask made of an insulator or conductor may be used beneath the resist mask. When using a hard mask, an insulating film or conductive film that will serve as the hard mask material is placed on the conductive film 240A. By forming a hard mask, then forming a resist mask on top of it, and etching the hard mask material... A hard mask of the desired shape can be formed. Etching of conductive film 240A, etc. You can either remove the resist mask before proceeding, or you can proceed with the resist mask still in place. Good. In the latter case, the resist mask may disappear during etching. Conductive film 240 After etching A, the hard mask may be removed by etching. If the mask material does not affect subsequent processes, or can be used in subsequent processes, then it is not necessarily hard. There is no need to remove the mask. In this embodiment, the insulating layer 271B and the conductive layer 291 Use B as the hard mask.

[0228] Also, oxide 230a, oxide 230b, oxide layer 241B, conductive layer 240B, insulating layer 271B and the conductive layer 291B are formed such that at least a portion of them overlaps with the conductor 205. It also includes oxide 230a, oxide 230b, oxide layer 241B, conductive layer 240B, and an insulating layer. The edges of the margin layer 271B and the conductive layer 291B are approximately perpendicular to the upper surface of the insulator 222. It is preferable that there be oxide 230a, oxide 230b, oxide layer 241B, conductive layer 24 The sides of 0B, the insulating layer 271B, and the conductive layer 291B are roughly relative to the upper surface of the insulator 222. Being nearly vertical allows for miniaturization and high density when installing multiple transistors 200. It becomes possible. Alternatively, oxide 230a, oxide 230b, oxide layer 241B, conductive layer 240 The angle between the sides of B, the insulating layer 271B, and the conductive layer 291B and the upper surface of the insulator 222 is A configuration with a lower angle is also acceptable. In that case, oxide 230a, oxide 230b, oxide The sides of layer 241B, conductive layer 240B, insulating layer 271B, and conductive layer 291B, and the insulator The angle between the top surface of 222 and the surface is preferably 60 degrees or more and less than 70 degrees. In subsequent processes, the coating properties of insulating film 280A and other materials are improved, reducing defects such as porosity. It can be reduced.

[0229] Next, the conductive layer 291B is removed. The conductive layer 291B is removed using a dry etching method. (See Figures 4A to 4C.)

[0230] Next, insulator 224, oxide 230a, oxide 230b, oxide layer 241B, conductive layer 2 An insulating film, which will become an insulator 280, is formed on 40B and the insulating layer 271B. Film deposition is performed using methods such as sputtering, CVD, MBE, PLD, and ALD. It is possible to do so.

[0231] For example, as the insulating film, a silicon oxide film is formed using the sputtering method, A silicon oxide film can then be deposited on top using the PEALD method or the thermal ALD method. The insulating film is preferably deposited using a film deposition method that utilizes a gas in which hydrogen atoms have been reduced or removed. This makes it possible to reduce the hydrogen concentration of the insulator 280. Heat treatment may be performed before film formation. The heat treatment should be carried out under reduced pressure and not exposed to air. The insulating film may be deposited continuously. By performing such a process, The edge body 224 removes moisture and hydrogen adsorbed on the surface of the film to be deposited, and further removes oxides. The moisture concentration in 230a, oxide 230b, oxide layer 241B, and insulator 224 and The hydrogen concentration can be reduced. The heat treatment conditions described above are used for this heat treatment. It is possible.

[0232] Next, the insulating film is subjected to CMP treatment to form an insulator 280 with a flat top surface (Figure 5A). (See Figure 5C.) Furthermore, similar to the insulator 224, for example, spats can be placed on the insulator 280. Aluminum oxide is deposited by the Tarling method, and the aluminum oxide is then applied to the insulator 280. CMP processing may be performed until the target is reached.

[0233] Microwave treatment may be performed here. Microwave treatment is performed in an oxygen-containing atmosphere. It is preferable to carry out the process under reduced pressure. After microwave treatment, heating is performed while maintaining the reduced pressure. Processing may be performed. The heat treatment temperature should be between 300°C and 500°C. preferable.

[0234] Furthermore, by performing microwave treatment, the film quality of the insulator 280 is modified, thus improving insulation. This can suppress the diffusion of hydrogen, water, and impurities from body 280 to oxide 230. Therefore, in subsequent processes after the formation of the insulator 280, or through heat treatment, etc., the insulator 280 is used. This suppresses the diffusion of hydrogen, water, impurities, etc., into the oxide 230. In this embodiment, the microwave processing is performed on the insulator 280. The examples given are not limited to these. For example, in addition to microwave processing, plasma processing, Microwave-excited plasma treatment may also be performed.

[0235] Next, a portion of the insulator 280, a portion of the insulating layer 271B, a portion of the conductive layer 240B, and an oxide layer A portion of 241B and a portion of oxide 230b are processed to form an opening that reaches oxide 230b. The opening is preferably formed to overlap with the conductor 205. The composition consists of insulator 271a, insulator 271b, conductor 240a, conductor 240b, and oxide. This forms substance 241a and oxide 241b (see Figures 6A to 6C).

[0236] In the process of forming the above-mentioned opening, the upper part of the oxide 230b may be removed. By removing a portion of the oxide 230b, grooves are formed in the oxide 230b.

[0237] Note that a portion of the insulator 280, a portion of the insulating layer 271B, a portion of the conductive layer 240B, and the oxide layer Processing of part of 241B and part of oxide 230b is performed by dry etching or Dry etching can be used. Dry etching is suitable for microfabrication. Suitable. Furthermore, the processing may be carried out under different conditions. For example, an insulator. Part of 280 was processed by dry etching, and part of the insulating layer 271B was wet etched. Processed using the 2000 method, a portion of the oxide layer 241B, a portion of the conductive layer 240B, and oxide 230b A portion of it may be processed by dry etching. Also, a portion of the oxide layer 241B and the conductive Even if the processing of a portion of the electrode layer 240B and the processing of a portion of the oxide 230b are carried out under different conditions good.

[0238] Furthermore, a portion of oxide 230b is removed using a dry etching method to form grooves. When doing so, it is preferable to process with a high bias power. For example, the bias power The density is 0.02 W / cm³. 2 The above should suffice, resulting in 0.03 W / cm². 2 It is preferable to do the above. Furthermore, 0.06 W / cm² 2 It is preferable to do the above. Also, during dry etching The spacing should be set appropriately according to the depth of the groove.

[0239] Here, in the above opening process, impurities are introduced into the opening, or damage is introduced to the surface of oxide 230b. Damaged areas may occur. These impurities and damaged areas are removed by the cleaning process. It is preferable to do so.

[0240] These impurities are found, for example, in the insulator 280, a portion of the insulating layer 271B, and the conductive layer 240B. Components contained in, and components used in the apparatus used to form the above-mentioned opening. This could be due to the components of the material, or components contained in the gas or liquid used for etching. Specifically, the impurities in question include, for example, aluminum, silicon, tantalum, and f Examples include fluorine and chlorine.

[0241] In particular, impurities such as aluminum or silicon may form oxides in later processes. This may hinder the CAAC-OS conversion of 0c.

[0242] In metal oxides, impurities such as aluminum or silicon cause CAAC-O S-formation is inhibited, resulting in a pseudo-amorphous oxide semiconductor (a-like OS: amorphous- The region that has become a (like oxide semiconductor) is a non-CAAC region. It is sometimes called this. In the non-CAAC region, the density of the crystal structure is reduced, so V O H A large amount is formed, making it easier for the transistor to become normally-on. Therefore, oxide 23 The non-CAAC regions of 0b and oxide 230c are preferably reduced or removed. It's nice.

[0243] Therefore, the aluminum adhering to the surfaces of oxide 230a and oxide 230b, Impurity elements that inhibit CAAC-OS formation, such as silicon, are reduced or removed. It is preferable to do so. For example, at the interface between oxide 230b and oxide 230c, and in the vicinity thereof. The concentration of aluminum atoms should be 5.0 atomic percent or less, and 2.0 atomic percent or less. Preferably, 1.5 atomic% or less is more preferable, 1.0 atomic% or less is even more preferable, and 0 Less than 0.3 atomic percent is even more preferable.

[0244] Furthermore, oxides 230b and 230c have a layered CAAC structure. This is preferable. In particular, CAAC is applied to the lower end of the drain of oxide 230b and oxide 230c. It is preferable that the structure is formed. Here, in transistor 200, conductor 240 a or conductor 240b, and its vicinity, function as drains. That is, conductor 2 Near the lower end of 40a (conductor 240b), oxide 230b and oxide 230c It is preferable that one or both of the drains have a CAAC structure. Even at the drain end, which significantly affects pressure resistance, the damaged area of ​​oxide 230b is removed. The CAAC structure further suppresses fluctuations in the electrical characteristics of transistor 200. This can be done. Furthermore, the reliability of transistor 200 can be improved.

[0245] Cleaning processes include wet cleaning using cleaning solutions, plasma treatment using plasma, and This includes cleaning by heat treatment, and the above cleaning treatments may be combined as appropriate. The cleaning process may cause the grooves to deepen.

[0246] For wet cleaning, use ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, etc., with carbonated water. Alternatively, the cleaning process may be carried out using an aqueous solution diluted with pure water, pure water, carbonated water, etc. Ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. These washing methods may be combined as appropriate.

[0247] In this specification, etc., an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water is referred to as diluted hydrofluoric acid. It is called an acid, and a solution obtained by diluting commercially available ammonia water with pure water is sometimes called diluted ammonia water. Yes. Furthermore, the concentration and temperature of the aqueous solution depend on the impurities to be removed and the semiconductor device being cleaned. The composition should be adjusted as appropriate. The ammonia concentration of the diluted ammonia solution should be 0.0 The concentration should be between 1% and 5%, preferably between 0.1% and 0.5%. The hydrogen fluoride concentration of the hydrochloric acid is 0.01 ppm to 100 ppm, preferably 0.1 ppm. It should be between 10 ppm and above.

[0248] For ultrasonic cleaning, a frequency of 200 kHz or higher, preferably 900 kHz or higher, is used. It is preferable to have this. By using this frequency, damage to oxides such as 230b is reduced. It can be reduced.

[0249] Furthermore, the above cleaning process may be performed multiple times, and the cleaning solution may be changed each time the cleaning process is performed. Example For example, the first cleaning treatment involves using diluted hydrofluoric acid or diluted ammonia water. In addition, a second washing treatment using pure water or carbonated water may be performed.

[0250] In this embodiment, as the above cleaning process, wet cleaning is performed using diluted hydrofluoric acid. Next, wet cleaning is performed using purified water or carbonated water. Removes impurities such as oxide 230a and oxide 230b that are attached to the surface or diffused into the interior. Furthermore, the crystallinity of the oxide 230c formed on the oxide 230b can be improved. It is possible to do so.

[0251] Furthermore, the above-mentioned processing such as dry etching, or the above-mentioned cleaning treatment, will cause the above-mentioned opening and overlap The thickness of the insulator 224 in the region that does not overlap with oxide 230b is equal to the thickness of oxide 230b In the overlapping region, the thickness may be thinner than that of the insulator 224.

[0252] Furthermore, heat treatment may be performed after etching or cleaning as described above. The process should be carried out at a temperature between 100°C and 450°C, preferably between 350°C and 400°C. Heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or with an oxidizing gas at a concentration of 10 ppm or higher. The procedure should be carried out in an atmosphere containing 1% or more, or 10% or more. For example, heat treatment should be carried out in an oxygen atmosphere. This is preferable. This supplies oxygen to oxide 230a and oxide 230b. This can help reduce oxygen deficiency. Furthermore, the heat treatment may be carried out under reduced pressure. This involves heat treatment in an oxygen atmosphere, followed by continuous heat treatment in a nitrogen atmosphere without exposure to the atmosphere. You may go.

[0253] Next, the oxide film 230C is deposited (see Figures 7A to 7C). Before deposition of oxide film 230C Heat treatment may be performed, and this heat treatment shall be carried out under reduced pressure and without exposure to the atmosphere. It is preferable to continuously form an oxide film 230C. Furthermore, this heat treatment contains oxygen. It is preferable to perform this process in an atmospheric environment. By performing this process, the surface of oxide 230b It removes moisture and hydrogen adsorbed on surfaces, and further removes oxide 230a and oxide 23 The water and hydrogen concentrations in 0b can be reduced. The heat treatment temperature is 100°C. A temperature of 400°C or higher is preferred. In this embodiment, the heat treatment temperature is set to 200°C.

[0254] Here, the oxide film 230C is formed on the inner wall of the groove in the oxide 230b, A portion of the side surface of object 241, a portion of the side surface of conductor 240, a portion of the side surface of insulator 271, and It is preferable that it be provided so as to be in contact with a part of the side surface of the insulator 280. The conductor 240 is Surrounded by oxide 241, insulator 271, and oxide film 230C, in subsequent processes This makes it possible to suppress the decrease in conductivity due to oxidation of the conductor 240.

[0255] The 230C oxide film can be deposited using sputtering, CVD, MBE, PLD, or ALD methods. This can be done using methods such as those described above. Oxide film 230C is formed using the same film formation method as oxide film 230A. It is possible to use this to form a film. In this embodiment, the oxide film 230C is formed by sputtering. Therefore, film deposition is performed using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. do.

[0256] Here, the oxygen vacancies in oxide 230b and oxide film 230C are reduced, and oxide 2 To make 30b substantially high-purity intrinsic, oxide 230b and oxide film 230C are used. The process involves adding oxygen (hereinafter also referred to as oxygen ion implantation or oxygen doping). This is done (see Figures 8A to 8C and Figure 12A. Note that Figure 12A is an enlarged version of a part of Figure 8C). This is the diagram I showed.

[0257] Oxygen is added to the channel-forming region of oxide 230b via the oxide film 230C. This suppresses the diffusion of impurities or the formation of damaged areas on the surface of the channel-forming region. This is possible. In particular, since the oxide film 230C is composed of the same elements as the oxide 230b, Even if a portion of the oxide film 230C diffuses into the oxide 230b due to the treatment, impurities may still cause... No problems will arise.

[0258] As shown in Figures 8B, 8C, and 12A, the oxide film 23 is formed by oxygen injection treatment. Oxygen is present on the surface of oxide 230b, the surface of insulator 280, and the surface of insulator 224. Region 292 is formed by the addition of [substance name]. In particular, region 292 is formed by the oxide film 230C and the oxide film. It is preferable to provide it near the interface of 230b. Oxygen is added to the surface of oxide 230b. This allows for efficient reduction of oxygen deficiency in oxide 230b during subsequent heat treatment.

[0259] Specifically, oxygen implantation treatments include ion implantation, ion doping, and plasma injection. By using methods such as Merjohn ion implantation, the oxide film 230C and oxide 230b can be formed. Oxygen can be added. Furthermore, the gas used in the oxygen addition process is: 16 O2 or 18 Oxygen gases such as O2, nitrous oxide gas, ozone gas, and other oxygen-containing gases These can be listed. Furthermore, the process of adding oxygen may be carried out while heating the substrate.

[0260] For example, the acceleration voltage in ion doping is between 0.5kV and 100kV. Preferably 1kV to 50kV, more preferably 1kV to 30kV, even more preferably The voltage should be between 1kV and 10kV. The ion implantation concentration should be 1 × 10⁻⁶. 15 at oms / cm 2 Preferably 2 × 10 15 atoms / cm 2 More preferably, is 5 x 10 15 atoms / cm 2 In summary, 1 × 10 16 atoms / cm 2 The above is fua2×10 16 atoms / cm 2 That concludes this section.

[0261] Furthermore, the addition of ions by ion doping should be performed approximately perpendicular to the sample surface. This is also good. In addition, the addition of ions by ion doping treatment has an angle with respect to the sample surface. It's fine if you do that.

[0262] Here, in Figures 8B and 8C, arrow 290 schematically represents the direction of oxygen ion movement. As shown by arrow 290, in the channel width direction of oxide 230b, 1 Two ions are at an angle θ (45° < θ < 135°) with respect to the tangent to the upper surface of oxide 230b. It is preferable to incident at a temperature of °. Also, in the L-length direction of oxide 230b, one It is preferable that the ions are incident on the upper surface of oxide 230b at an angle θ. By adjusting this appropriately, a film is formed on the side surface of oxide 230b and on the side surface of oxide 230b. Oxygen can also be added to the oxide film 230C.

[0263] Furthermore, an oxygen-adding treatment may be performed before forming the oxide film 230C. Oxide film 2 When oxygen is added before the 30C film is formed, as shown in Figure 13, the oxide layer 241B is formed. It is preferable that it remains within the opening. In this case, the oxide layer 241B and the oxide film 230C are made of the same material and have the same atomic ratio. It is preferable that this be the case.

[0264] Oxygen doping treatment is performed on the channel formation region of oxide 230b via oxide layer 241B. This suppresses the diffusion of impurities or the formation of damaged areas on the surface of the channel-forming region. This is possible. In particular, the oxide layer 241B is composed of the same elements as the oxide 230b. Even if a portion of the oxide layer 241B diffuses into the oxide layer 230b due to the additive treatment, impurities remain. No causal problems arise.

[0265] Next, heat treatment is performed (see Figures 9A to 9C, 12B, and 12C). Figures 12B and 12C are enlarged views of a portion of Figure 9C.

[0266] It is preferable to carry out the heat treatment in an oxygen atmosphere. This allows oxygen to be released into the oxide 230b. By supplying oxygen, it is possible to reduce oxygen deficiency. Furthermore, the heat treatment can be performed under reduced pressure. Good. Alternatively, heat treatment in an oxygen atmosphere followed by continuous treatment in a nitrogen atmosphere without exposure to air. Heat treatment may be performed.

[0267] Specifically, the heat treatment is performed at a temperature of 100°C to 450°C, preferably 350°C to 400°C. The following procedure is recommended. Note that the heat treatment should be performed using an oxidizing gas of 10 ppm or more, 1% or more. It is best to perform this in an atmosphere containing 10% or more of the substance.

[0268] The effects of this heat treatment will be explained using Figure 12. As shown in Figure 12B, the heat treatment Due to heat, the oxygen added to region 292 by oxygen injection treatment is oxide 230b It diffuses into the interior, into the interior of insulator 224, and into the interior of insulator 280. Also, simultaneously, Figure 12C As shown, the diffused oxygen, upon heating, forms the oxide film 230C and oxide 230 It is supplied to the oxygen-deficient Vo in b, and by compensating for the oxygen deficiency, the oxide film 230C and It becomes part of oxide 230b. Meanwhile, oxygen diffused into insulators 224 and 280 The excess oxygen remains in insulators 224 and 280.

[0269] By reducing defect levels or oxygen vacancies in the channel formation region, variations in electrical properties are minimized. Furthermore, it can provide highly reliable transistors with normally-off characteristics. We can provide a Rangista.

[0270] On the other hand, when the metal oxide contains an excess of oxygen exceeding the appropriate amount, the transistor is When driven, the valence state of excess oxygen atoms changes, causing the electrical characteristics of the transistor to fluctuate. This can sometimes lead to a decrease in reliability.

[0271] Therefore, the channel formation region of oxide 230b is made of oxide 230a, which has barrier properties, By covering with an oxide 230c that has barrier properties, the excess oxygen present in the insulator 224 is removed. However, this can suppress the excessive supply to oxide 230b.

[0272] Next, the insulating film 250A is deposited (see Figures 10A to 10C). Deposition of insulating film 250A A heat treatment may be performed beforehand. After the heat treatment is performed under reduced pressure, exposure to the atmosphere is not permitted. Furthermore, it is preferable to continuously deposit the insulating film 250A. In addition, this heat treatment is performed using oxygen. It is preferable to carry out the process in an atmosphere containing the substance. By performing this process, the oxide film 230C is formed. It removes moisture and hydrogen adsorbed on the surface, and further removes oxide 230a and oxide 23 This allows for the reduction of moisture and hydrogen concentrations in 0b and the oxide film 230C. The heat treatment temperature is preferably between 100°C and 400°C.

[0273] Insulating film 250A can be produced using methods such as sputtering, CVD, MBE, PLD, and ALD. It can be formed using [a specific method]. In addition, the insulating film 250A has reduced or removed hydrogen atoms. It is preferable to deposit the film using a film deposition method that utilizes a gas. This allows the water in the insulating film 250A to be deposited. The elemental concentration can be reduced. The insulating film 250A comes into contact with the oxide 230c in a later process. Since it becomes an insulator 250, it is preferable that the hydrogen concentration is reduced in this way.

[0274] Furthermore, when the insulator 250 has a two-layer laminated structure, the insulating film that is the lower layer of the insulator 250 The insulating film that forms the upper layer of the insulator 250 can be continuously deposited without exposure to the atmospheric environment. Preferably. By forming the film without opening to the atmosphere, an insulating film that becomes the lower layer of the insulator 250, and an insulating film. This prevents impurities or moisture from the atmospheric environment from adhering to the insulating film that forms the upper layer of the edge body 250. This allows for the insulating film that forms the lower layer of the insulator 250 and the insulating film that forms the upper layer of the insulator 250 to be separated. The vicinity of the interface can be kept clean.

[0275] Here, after the insulating film 250A is formed, the microphone is subjected to an oxygen-containing atmosphere and under reduced pressure. Microwave treatment may be performed. Furthermore, after microwave treatment, heat treatment may be performed while maintaining a reduced pressure state. This may be done. By performing microwave treatment, the film quality of insulating film 250A and other materials can be modified. This suppresses the diffusion of hydrogen, water, impurities, etc. Therefore, the conductor 260 and Through subsequent processes such as deposition of a conductive film or post-treatment such as heat treatment, the insulator 250 is used This suppresses the diffusion of hydrogen, water, impurities, etc., into oxide 230b, oxide 230a, etc. It is possible.

[0276] Next, conductive film 260A and conductive film 260B are deposited in sequence (see Figures 10A to 10C). The conductive films 260A and 260B were deposited using sputtering, CVD, and MB. This can be done using methods such as the E method, PLD method, and ALD method. In this embodiment, the ALD method is used. Using this method, a conductive film 260A was deposited, and the CVD method was continuously applied under reduced pressure without releasing it to the atmosphere. Then, a conductive film 260B is deposited.

[0277] Next, by CMP treatment, oxide film 230C, insulating film 250A, conductive film 260A, and By polishing the conductive film 260B until the insulator 280 is exposed, the oxide 230c , forming an insulator 250 and a conductor 260 (conductor 260a and conductor 260b) (See Figures 11A to 11C.)

[0278] The above CMP process may remove a portion of the insulator 280, including region 292. By removing the region, the amount of excess oxygen present in the insulator 280 can be reduced.

[0279] As a result of the above processing, oxide 230c has openings that reach oxide 230b and oxide 230 It is positioned to cover the inner wall (side wall and bottom surface) of the groove of b. In addition, the insulator 250 is It is arranged to cover the inner walls of the opening and the groove via oxide 230c. The conductor 260, via the oxide 230c and the insulator 250, the opening and the It is positioned to fill the groove.

[0280] Next, a heat treatment may be performed under the same conditions as the heat treatment described above. In this embodiment, nitrogen The process is carried out at a temperature of 400°C for 1 hour in a plain atmosphere. This heat treatment causes the insulator 250 Furthermore, the moisture and hydrogen concentrations in the insulator 280 can be reduced. After heat treatment, the insulator 282 may be deposited continuously without exposure to the atmosphere.

[0281] Next, on oxide 230b, on oxide 230c, on insulator 250, on conductor 260, and An insulator 282 is formed on the insulator 280. The insulator 282 is deposited by sputtering. This can be done using methods such as CVD, MBE, PLD, and ALD. Insulator 2 For example, in 82, aluminum oxide can be deposited by sputtering. It is preferable. Furthermore, it is preferable to deposit the insulator 282 while heating the substrate. By forming an insulator 282 in contact with the upper surface of the conductor 260, the subsequent heat treatment... This prevents the oxygen contained in the insulator 280 from being absorbed by the conductor 260. Therefore, it is preferable.

[0282] Next, an insulator 283 is formed on the insulator 282. The insulator 283 is deposited by sputtering. This can be done using methods such as the ring method, CVD method, MBE method, PLD method, or ALD method. In this embodiment, silicon nitride is deposited using the sputtering method.

[0283] Next, the conductor 2 Form an opening that reaches 40. This opening can be formed using lithography. Note that although the shape of the opening in Figure 1A is shown as circular in a top view, it is not limited to this. It is not the case that the opening, when viewed from above, is a roughly circular shape such as an ellipse, or a rectangle. Any polygonal shape is acceptable, including quadrilaterals and other polygons with rounded corners.

[0284] Next, an insulating film to become an insulator 276 is formed, and the insulating film is anisotropically etched to form an insulator. Forms insulator 276 (insulator 276a and insulator 276b). Film deposition can be performed using methods such as sputtering, CVD, MBE, PLD, or ALD. This can be done using an insulating film that suppresses oxygen permeability. It is preferable to use an insulating film with properties. For example, using the ALD method, aluminum oxide It is preferable to deposit a film of 'mu'. Alternatively, silicon nitride can be deposited using the PEALD method. This is preferable. Silicon nitride is preferred because of its high blocking properties for hydrogen.

[0285] Furthermore, as an anisotropic etching of the insulating film that becomes the insulator 276, for example, dry etching Methods such as the G method can be used. By providing an insulator 276 on the side wall of the opening, oxygen from the outside can be blocked. This suppresses the transmission of the material and prevents oxidation of the conductors 246a and 246b that are formed next. This can be done. Also, impurities such as water and hydrogen can be removed from conductors 246a and 246b. It can prevent it from spreading to the outside.

[0286] Next, conductive films that will become conductors 246a and 246b are formed. Conductor 246a The conductive film that forms the conductor 246b has the function of suppressing the permeation of impurities such as water and hydrogen. It is desirable to have a laminated structure that includes a conductive material. For example, tantalum nitride, titanium nitride, etc. It can be made into a laminate of materials such as tungsten, molybdenum, and copper. Conductor 24 The conductive film for 6 can be deposited using sputtering, CVD, MBE, PLD, or AL. This can be done using methods such as the D method.

[0287] Next, by performing CMP treatment, the conductive films that become conductors 246a and 246b are formed. Remove a portion to expose the upper surfaces of insulators 283 and 276. As a result, only the opening remains. The remaining conductive film forms conductors 246a and 246b with flat upper surfaces. This can be achieved. Furthermore, this CMP treatment removes part of the upper surface of the insulator 283 and the insulation A portion of the upper surface of the edge 276 may be removed.

[0288] Next, a conductive film that will become the conductor 248 is formed. The formation of the conductive film that will become the conductor 248 is performed by This can be done using methods such as puttering, CVD, MBE, PLD, or ALD. can.

[0289] Next, the conductive film that will become the conductor 248 is processed by lithography, and the conductor 246a is produced. The conductor 248a that is in contact with the upper surface of the conductor 246b, and the conductor 248b that is in contact with the upper surface of the conductor 246b Formed. At this time, although not shown in the figure, conductor 248a and conductor 248b and insulator 28 A portion of the insulator 283 in the region that does not overlap with 3 may be removed.

[0290] Next, an insulating film 286 is formed on the conductive material 248 and the insulating material 283 (Figure 1A). (See Figure 1C.) The insulator 286 was deposited by sputtering, CVD, MBE, and P This can be done using methods such as the LD method or ALD method. In addition, the insulator 286 is multilayered. For example, silicon nitride may be deposited using a sputtering method, and the silicon nitride A silicon nitride film may be deposited on the surface using the CVD method.

[0291] Based on the above, a semiconductor device having the transistor 200 shown in Figures 1A to 1C is fabricated. It is possible.

[0292] <Example 1 of a semiconductor device> In the following, using Figures 15A to 15C, an example of a semiconductor device according to one aspect of the present invention will be shown. I will explain about this.

[0293] Figure 15A shows a top view of the semiconductor device. Figure 15B shows the A1-A2 shown in Figure 15A. This is a cross-sectional view corresponding to the area indicated by the dashed line in Figure 15A. Figure 15C is a cross-sectional view corresponding to the area A3-A in Figure 15A. This is a cross-sectional view corresponding to the area indicated by the dashed line in 4. In the top view of Figure 15A, the diagram is clarified. Some elements have been omitted for this reason.

[0294] In addition, in the semiconductor device shown in Figures 15A to 15C, <Example of semiconductor device configuration 1> Structures having the same function as the semiconductor device shown will be denoted by the same reference numeral. In this section as well, the constituent materials of semiconductor devices are described in detail in <Example of Semiconductor Device Configuration 1>. The materials described can be used.

[0295] The semiconductor device shown in Figures 15A to 15C is a modified version of the semiconductor device shown in Figures 1A to 1C. This is an example. The semiconductor device shown in Figures 15A to 15C is the same as the semiconductor device shown in Figures 1A to 1C. The body device differs in the shape of the insulators 214, 282, and 283. Having 284 is different.

[0296] In the semiconductor device shown in Figures 15A to 15C, insulator 214, insulator 216, insulator 2 Insulators 222, 280, and 282 are patterned. Furthermore, insulator 283 is insulator 214, insulator 216, insulator 222, insulator 224, insulator The structure covers the body 280 and the insulator 282. In other words, the insulator 283 is an insulating material. The top and side surfaces of the body 282 and the top surface of the insulator 212 are in contact. This allows the oxide 230 Insulators 214, 216, 222, 224, and 280, among others. , and insulator 282 is isolated from the outside by insulator 283 and insulator 212. In other words, transistor 200 is sealed with insulator 283 and insulator 212. It will be located within the region.

[0297] For example, the insulators 214 and 282 have the function of capturing hydrogen and fixing hydrogen. Formed using a material having the properties of, insulator 212 and insulator 283 are opposed to hydrogen and oxygen. It is preferable to form it using a material that has the function of suppressing diffusion. Typically, an insulator Aluminum oxide can be used as 214 and the insulator 282. Typically, silicon nitride is used as the insulator 212 and insulator 283. can.

[0298] With the above configuration, hydrogen contained outside the sealed region will enter the sealed region This can prevent contamination inside the container.

[0299] Furthermore, in the transistor 200 shown in Figures 15A to 15C, the insulator 212 and the insulator The present invention is shown in which the edge 283 is provided as a single layer, but the present invention is not limited to this. No. For example, the insulator 212 and the insulator 283 are each made up of two or more layers. It may also be configured as a structural element.

[0300] Insulator 284 functions as an interlayer film. Insulator 284 has a higher dielectric constant than insulator 214. A low dielectric constant is preferable. By using a material with a low dielectric constant as the interlayer film, parasitic volumes that form between wiring are reduced. The amount can be reduced. The insulator 284 can be made of the same material as the insulator 280, for example. It can be established.

[0301] <Application Example 1 of Semiconductor Devices> In the following, using Figures 16A and 16B, we will explain the above <Semiconductor Device Configuration Example 1> and the previous A transistor according to one aspect of the present invention, which differs from the one shown in <Modification 1 of the semiconductor device> An example of a semiconductor device having a 200 is described below. Note that Figures 16A and 16B are shown below. In the semiconductor device shown, the semiconductor device shown in <Modified Example of Semiconductor Device 1> (Figures 1A to 1A) See 1C. Structures having the same function as the structures that constitute ( ) shall be denoted with the same reference numeral. Regarding the constituent materials of transistor 200, see <Example of semiconductor device configuration 1> and The materials described in detail in <Modification Example 1 of Semiconductor Device> can be used.

[0302] Figures 16A and 16B show multiple transistors 200_1 to 200_ The configuration in which n is enclosed and sealed by insulators 283 and 212 is shown. Note: Figure 1 In 6A and Figure 16B, transistors 200_1 to 200_n are, They appear to be aligned along the channel length, but this is not the only arrangement. Transition The transistors 200_1 through 200_n may be arranged in the channel width direction, They may be arranged in a matrix. Alternatively, they may be arranged without any regularity, depending on the design. It's fine if you do that.

[0303] As shown in Figure 16A, multiple transistors 200_1 to 200_n On the outside, the portion where the insulator 283 and the insulator 212 are in contact (hereinafter referred to as the sealing portion 265) There is a combination.) is formed. The sealing portion 265 is formed by multiple transistors 200_1 to It is formed to surround the transistor 200_n. By using this structure, multiple The transistors 200_1 through 200_n are connected by insulators 283 and 212. It can be enclosed. Therefore, multiple transistor groups surrounded by the sealing portion 265 can be placed on the substrate. It will be established.

[0304] Also, a dicing line (scribe line, division line, or A cutting line may be provided. The above substrate is divided at the dicing line. Because it is disconnected, the group of transistors surrounded by the sealing portion 265 can be extracted as a single chip. It will become that.

[0305] Furthermore, in Figure 16A, multiple transistors 200_1 to 200_n are connected. An example of surrounding with two sealing portions 265 has been shown, but it is not limited to this. Figure 16B shows As shown, multiple transistors 200_1 to 200_n are connected to multiple sealing parts It may also be configured to enclose it. In Figure 16B, multiple transistors 200_1 or to The structure is such that the 200_n is surrounded by the sealing part 265a, and further surrounded by the outer sealing part 265b. Yes, they are.

[0306] In this way, multiple transistors 200_1 to transistor 200_ are enclosed in multiple sealing portions. By creating a configuration that surrounds n, the area where insulator 283 and insulator 212 are in contact increases, thus providing an insulating The adhesion between the edge body 283 and the insulator 212 can be further improved. This makes it more reliable. In fact, multiple transistors 200_1 through 200_n can be sealed. .

[0307] In this case, even if a dicing line is provided overlapping the sealing portion 265a or the sealing portion 265b Alternatively, a dicing line may be provided between the sealing portion 265a and the sealing portion 265b.

[0308] According to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics is provided. This can be achieved. Furthermore, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. It is possible. Furthermore, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. This is possible. Furthermore, according to one aspect of the present invention, a semiconductor device with a large on-current is provided. This is possible. Furthermore, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated is provided. It can be provided. Furthermore, according to one aspect of the present invention, a low-power semiconductor device can be provided. It is possible.

[0309] The configurations and methods described in this embodiment are similar to those described in other embodiments or examples. It can be used in appropriate combination with other methods, etc.

[0310] (Embodiment 2) In this embodiment, using Figures 17 to 26, a transistor 2 according to one aspect of the present invention is shown. An example of a semiconductor device having 00 and a method for manufacturing the same will be described.

[0311] Furthermore, structures having the same functions as the semiconductor device shown in the previous embodiment are denoted by the same reference numerals. Therefore, with respect to the structures designated with the same reference numeral, the above embodiment should be considered. It is possible.

[0312] <Example of semiconductor device configuration 2> The configuration of a semiconductor device having transistor 200 will be explained using Figure 17. Figure 17A Figures 17C are a top view and a cross-sectional view of a semiconductor device having a transistor 200. Figure 17A is a top view of the semiconductor device. Figures 17B to 17C show the semiconductor device. This is a cross-sectional view of the body apparatus. Here, Figure 17B shows the part indicated by the dashed line A1-A2 in Figure 17A. This is a cross-sectional view of the position, and also a cross-sectional view of transistor 200 in the channel length direction. Also, Figure 1 7C is a cross-sectional view of the area shown by the dashed line A3-A4 in Figure 17A, and transistor 20 This is also a cross-sectional view in the channel width direction of 0. Note that in the top view of Figure 17A, for clarity of the diagram Some elements have been omitted.

[0313] A semiconductor device according to one aspect of the present invention comprises an insulator 212 on a substrate (not shown) and an insulator 212 The insulator 214 above, the transistor 200 on the insulator 214, and the transistor 200 above Insulator 274, insulator 280 on insulator 274, insulator 282 on insulator 280, It has an insulator 283 on an insulator 282, an insulator 212, an insulator 214, and an insulator 27 4. Insulators 280, 282, and 283 function as interlayer films.

[0314] Furthermore, the conductor 246 (conductor) is electrically connected to the transistor 200 and functions as a plug. It has an electric body 246a and a conductor 246b). Note that the conductor 2 functions as a plug. An insulator 276 (insulator 276a and insulator 276b) is provided in contact with the side surface of 46. Furthermore, on the insulator 283 and on the conductor 246, there are electrically connected components. A conductor 248 (conductor 248a and conductor 248b) that functions as wiring is provided. Furthermore, an insulator 286 is provided on the conductor 248 and on the insulator 284.

[0315] Specifically, the openings of insulator 274, insulator 280, insulator 282, and insulator 283 An insulator 276a is provided in contact with the inner wall of the insulator 276a, and a conductor 246 is provided in contact with the side surface of the insulator 276a. A first conductor a is provided, and a second conductor 246a is provided further inside. It is also in contact with the inner wall of the opening of insulator 280, insulator 282, and insulator 283. An edge member 276b is provided, and the first conductor of the conductor 246b is in contact with the side surface of the insulator 276b. A second conductor, conductor 246b, is provided on the inside.

[0316] Here, as shown in Figure 17B, the height of the upper surface of the conductor 246 and the area overlapping with the conductor 248 The height of the upper surface of the insulator 283 in this region can be made to be approximately the same. Note that in transistor 200 Regarding the configuration in which the first conductor and the second conductor of the conductor 246 are laminated: Although shown, the present invention is not limited thereto. For example, the conductor 246 may be a single layer, Alternatively, it may be configured as a laminated structure of three or more layers. In some cases, ordinal numbers are assigned to distinguish between elements based on their order of formation.

[0317] [Transistor 200] As shown in Figures 17A to 17C, the transistor 200 is on the insulator 214 216 and a conductor 20 arranged to be embedded in the insulator 214 or insulator 216 5 (conductors 205a and 205b), on the insulator 216, and conductor 205 The upper insulator 222, the insulator 224 on the insulator 222, and the oxide 230 on the insulator 224 a, oxide 230b on oxide 230a, and oxide 241 (oxidation) on oxide 230b. Substance 241a, and oxide 241b) and oxide 230c, and oxidation on oxide 230c Material 230d, conductor 240a on oxide 241a, and insulator 271 on conductor 240a a, conductor 240b on oxide 241b, insulator 271b on conductor 240b, acid An insulator 250 on oxide 230d, and an oxide 230c located on the insulator 250, and an acid The conductor 260 (conductor 260a and conductor 260b) overlaps with a portion of the compound 230d. , has . Also, oxide 230c has sides of oxide 241a, sides of oxide 241b, The sides of the conductor 240a, the sides of the conductor 240b, the sides of the insulator 271a, and the insulating Each of them is in contact with the side surface of the edge body 271b.

[0318] Here, as shown in Figures 17B and 17C, the upper surface of the conductor 260 is the insulator 250 It is positioned so as to substantially coincide with the upper surface of oxide 230c and the upper surface of oxide 230d. Insulator 282 consists of conductor 260, insulator 250, oxide 230c, oxide 230d, and It is in contact with the upper surfaces of the insulator 280.

[0319] In the following, insulators 271a and 271b will be collectively referred to as insulator 271. There are cases where this is the case.

[0320] The insulator 280 is provided with an opening that reaches the oxide 230b. 230c, oxide 230d, insulator 250, and conductor 260 are arranged. In the channel length direction of transistor 200, conductor 240a and oxide 241a And between the conductor 240b and oxide 241b, there is a conductor 260, an insulator 250, and an oxide Material 230d and oxide 230c are provided. The insulator 250 is a conductor 260 It has a region in contact with the side surface and a region in contact with the bottom surface of the conductor 260. Oxide 230d, It is provided between the oxide 230c and the insulator 250. Also, the oxide 230b and heavy In the region, oxide 230c has a region in contact with oxide 230b and oxide 230d , and the region that overlaps with the side surface of the conductor 260 via the insulator 250, and via the insulator 250 It has a region that overlaps with the bottom surface of the conductor 260.

[0321] Oxide 230 consists of oxide 230a placed on the insulator 224 and oxide 230a The oxide 230b is placed on top, and the oxide 230b is placed on top of the oxide 230b, and at least a portion of it is acid Oxide 230c in contact with oxide 230b, oxide 230d disposed on oxide 230c and It is preferable that it has ,

[0322] Furthermore, the transistor 200 is made of oxide 230 (oxide 230a) which includes a channel formation region. , oxide 230b, oxide 230c, and oxide 230d) function as semiconductors. It is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor).

[0323] Transistors using oxide semiconductors in the channel formation region exhibit extremely high conductivity in the non-conductive state. Because of its low leakage current, it can provide a semiconductor device with low power consumption. On the other hand, oxide semiconductors The transistor used had its electrical properties affected by impurities and oxygen vacancies in the oxide semiconductor. It fluctuates, and has normally-on characteristics (the channel exists even when no voltage is applied to the gate electrode). This is a characteristic that makes it easy for current to flow through a transistor.

[0324] Therefore, the oxide semiconductor used in the channel formation region of the transistor contains impurities and oxygen It is preferable to use a high-purity, intrinsic oxide semiconductor with reduced defects. In this context, a low impurity concentration and low defect level density indicate high purity intrinsic or substantially high purity. It is called "degree of authenticity."

[0325] However, in a transistor using an oxide semiconductor, the transistor is constructed In conductive materials, or in conductive materials used in plugs and wiring that connect to transistors, oxide semiconductors As the body gradually absorbs oxygen, oxygen deficiency can occur as one of the changes over time.

[0326] Therefore, it is preferable to make oxide 230b substantially high-purity intrinsic. To make it highly pure and genuine, the oxide 230b is subjected to a treatment in which oxygen is added (hereinafter referred to as oxygen It is recommended to perform an impregnation treatment (also called oxygen doping treatment). Specifically, oxygen impregnation treatment Theories include ion implantation, ion doping, and plasma immersion ion implantation. You can use it.

[0327] On the other hand, when performing a treatment that adds oxygen using methods such as ion implantation, the table of oxide 230b Physical damage may occur on the surface. Therefore, through the oxide film 230C, oxide 2 It is preferable to add oxygen to 30b. Therefore, the oxide film 230C is oxidized. It is best to use the same material as item 230b.

[0328] Oxygen is added to the channel-forming region of oxide 230b via oxide 230c. This suppresses the diffusion of impurities or the formation of damaged areas on the surface of the channel-forming region. This is possible. Also, since the same material is used for oxide 230b and oxide 230c Even if a portion of the oxide film 230C diffuses into the oxide 230b due to the additive treatment, impurities may still form. The problem of cause does not arise.

[0329] Furthermore, after making oxide 230b substantially high-purity intrinsic, the channels of oxide 230b form The region formed is made of oxide 230a, which suppresses oxygen diffusion more than oxide 230b, and It is preferable to cover it with oxide 230d.

[0330] Specifically, as shown in the figure, oxide 230a is placed below oxide 230b. Therefore, the extraction of oxygen from oxide 230b can be suppressed. Oxygen and fumes from the structure formed below material 230a to oxide 230b It can suppress the diffusion of pure substances.

[0331] Furthermore, oxide 230d is placed on top of oxide 230b and oxide 230c. Therefore, the extraction of oxygen from oxide 230b and oxide 230c is suppressed. This is possible. Also, oxide 230 from structures formed above oxide 230d This can suppress the diffusion of impurities to b.

[0332] Furthermore, the metal oxide that functions as a semiconductor has a band gap of 2 eV or more, preferably It is preferable to use gold with a band gap of 2.5 eV or higher. By using a specific oxide, the off-current of the transistor can be reduced.

[0333] For example, In-M-Zn, which has indium, element M, and zinc as oxide 230. Oxides (elements M include aluminum, gallium, yttrium, tin, copper, vanadium, and beryllium) Rium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, ra Tantalum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium It is preferable to use one or more metal oxides selected from among others. For 230, In-Ga oxide, In-Zn oxide, or indium oxide may be used. .

[0334] Here, oxide 230 has a layered structure consisting of multiple oxide layers with different chemical compositions. Preferably, the metal oxide used for oxide 230b is I relative to element M. The atomic ratio of n is such that it is equal to the element M of the metal oxide used in oxide 230a or oxide 230d. It is preferable that this ratio is greater than the atomic ratio of In.

[0335] In other words, in the metal oxides used in oxide 230a and oxide 230d, the main component The atomic ratio of element M to the metal element is such that in the metal oxide used in oxide 230b Furthermore, it is preferable that the atomic ratio of element M to the main component metal element is greater than that. In the metal oxide used in oxide 230a, the atomic ratio of element M to In is, The atomic ratio of element M to In in the metal oxide used in material 230b is greater than that of In. This is preferable. Also, in the metal oxide used for oxide 230b, the ratio of In to element M The atomic ratio of the elements in the metal oxides used in oxide 230a and oxide 230d. It is preferable that the atomic ratio of In to M is greater than that of M.

[0336] Oxide 230a and oxide 230d have a common element other than oxygen (as the main component) By doing so, the interfaces of oxide 230a, oxide 230b, and oxide 230d The defect level density in this can be reduced. In this case, the main carrier pathway is oxidation. This becomes the interface between material 230b or its vicinity, for example, between oxide 230b and oxide 230c. The defect level density at the interface between oxide 230b and oxide 230c can be reduced. Therefore, the influence of interfacial scattering on carrier conduction is small, and a high on-current can be obtained.

[0337] For example, as oxide 230b and oxide 230c, specifically In:M:Zn =4:2:3 [atomic ratio] or a composition close to that, In:M:Zn=5:1:3 [atomic ratio] [Atomic ratio] or a composition in the vicinity thereof, or In:M:Zn=10:1:3 [Atomic ratio] if For example, metal oxides with a similar composition, such as indium oxide, may be used.

[0338] Furthermore, it is preferable that oxide 230b and oxide 230c have crystalline properties. Furthermore, oxide 230b contains CAAC-OS (c-axis aligned crystal It is preferable to use an alline oxide semiconductor.

[0339] Furthermore, in one embodiment of the present invention, for example, insulator 212, insulator 282, insulator 283 Silicon nitride and the like are used as insulators 274 and 286, and insulator 214, And it is preferable to use aluminum oxide or the like as the insulator 271. Impurities such as water and hydrogen enter through insulators 212 and 214, and travel from the substrate side. This can suppress diffusion towards the inverter 200 side. Alternatively, it can be contained in the insulator 224, etc. This suppresses the diffusion of oxygen into the substrate side via insulators 212 and 214. It is possible to remove impurities such as water and hydrogen from the insulator 280, conductor 248, etc. This can suppress diffusion into oxide 230. In this way, transistor 200, Insulator 212 having the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen, insulator Structure surrounded by 214, insulator 271, insulator 274, insulator 282, and insulator 283 It is preferable to use this construction method.

[0340] For example, oxide 230a, oxide 230b, oxide 241, conductor 240, insulator 27 An insulator 274 is provided to cover the side of 1. The insulator 274 is less than the insulator 280. Preferably, the insulator functions as a barrier insulating film against oxygen. In other words, the insulator Preferably, the insulator has the function of suppressing the diffusion of oxygen. For example, the insulator 274 is an insulator It is preferable that it has a function that suppresses oxygen diffusion more effectively than 280.

[0341] Furthermore, the insulator 274 can be formed in an oxygen-free atmosphere, especially an inert atmosphere. This is preferable. When forming a film in an oxygen-containing atmosphere, oxygen may be added to the film-forming surface. When oxygen is added to the insulator 224, the oxygen is channeled through the oxide 230c. There is a high probability that it will diffuse into the channel formation region. If excess oxygen diffuses into the channel formation region, This can sometimes contribute to the deterioration of the transistor's electrical characteristics. Therefore, as for insulator 274, For example, it is good to deposit a film of a nitride such as silicon nitride.

[0342] In particular, the insulator 274 is preferably formed by sputtering. The Tarling method does not involve a hydrogen atmosphere, thus suppressing the inclusion of hydrogen, which can be an impurity. Cut.

[0343] By providing insulators 271 and 274, oxide 230a and oxide 230b The oxide 241 and the conductor 240 can be separated from the insulator 280. Then, oxide 230a, oxide 230b, oxide 241, and conductor 240, insulator 2 Direct diffusion of oxygen from 80 can be suppressed. Therefore, the source of oxide 230 Excess oxygen is supplied to the source region and drain region, causing the source region and drain region to become saturated. This prevents a reduction in carrier density. Also, it prevents the conductor 240 from being excessively oxidized. This can suppress the increase in resistance and the decrease in on-current.

[0344] Furthermore, when the conductor 246 is made into a laminated structure, the insulator 284, insulator 283, insulator 28 2. The conductor in contact with the insulator 280 and the insulator 271 is permeable to impurities such as water and hydrogen. It is preferable to use a conductive material that has a function to suppress overheating. For example, tantalum, nitride It is preferable to use tantalum, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Furthermore, conductive materials that have the function of suppressing the permeation of impurities such as water and hydrogen are single-layer or It may be used in a laminated form. Also, impurities such as water and hydrogen contained in the layer above the insulator 284 This suppresses the mixing of conductors 246a and 246b into the oxide 230. It is possible.

[0345] In particular, insulator 282, like insulator 274, is in an oxygen-free atmosphere and inert. It is preferable to deposit the film under an atmosphere. When depositing a film in an oxygen-containing atmosphere, oxygen is present on the film-deposited surface. Oxygen may be added. If oxygen is added to the insulator 280, the oxygen will be oxide 23. It is highly probable that oxygen diffuses into the channel-forming region via 0c. Excess oxygen leads to channel formation. If it diffuses into the region, it can contribute to the degradation of the transistor's electrical characteristics. Therefore For the insulator 282, for example, a nitride such as silicon nitride may be deposited as a film.

[0346] Furthermore, if you wish to use an oxide film with high barrier properties, such as aluminum oxide, for the insulator 282... It is preferable to deposit the film under conditions where oxygen is not injected into the film-forming surface.

[0347] Furthermore, it is preferable to deposit the insulator 282 by sputtering. The Tarling method does not involve a hydrogen atmosphere, thus suppressing the inclusion of hydrogen, which can be an impurity. Cut.

[0348] <Method for fabricating semiconductor devices> Next, a method for manufacturing a semiconductor device, which is one embodiment of the present invention, is shown in Figures 17A to 17C. Figures 18A to 25A, 18B to 25B, 18C to 25C, and 26A Next, we will explain using Figure 26C.

[0349] Figures 18A to 25A show top views. Figures 18B to 25B show top views. This is a cross-sectional view corresponding to the area shown by the dashed line A1-A2 in Figure 25A, which is a transistor. This is also a cross-sectional view of the channel in the direction of the channel length of 200. Furthermore, Figures 18C to 25C are the same as Figure 18A. Figure 25A shows a cross-sectional view corresponding to the area indicated by the dashed line A3-A4, and transistor 2 This is also a cross-sectional view of the channel width direction of 00. Note that in the top views of Figures 18A to 25A, Some elements have been omitted for clarity.

[0350] First, in this embodiment, the preparation method described using Figures 2 to 4 of the previous embodiment The law can be taken into consideration.

[0351] Next, insulator 224, oxide 230a, oxide 230b, oxide layer 241B, conductive layer 2 An insulator 274 is formed on 40B and the insulating layer 271B.

[0352] The insulator 274 is formed in an atmosphere that does not contain oxygen at least. For example, a noble gas, nitrogen It is preferable to form the film under an inert atmosphere such as an element. Specifically, as the insulator 274 It is preferable to deposit a film of a nitride such as silicon nitride.

[0353] When forming a film in an oxygen-containing atmosphere, oxygen may be added to the film-forming surface. Insulator 2 When oxygen is added to 24, the oxygen enters the channel-forming region via oxide 230c. There is a high probability that it will diffuse. If excess oxygen diffuses into the channel formation region, the transient This can sometimes be a cause of deterioration in the electrical properties of the device.

[0354] Next, an insulating film, which will become an insulating film 280, is formed on the insulating film 274. This is done using sputtering, CVD, MBE, PLD, ALD, etc. It is possible.

[0355] Next, the insulating film is subjected to CMP treatment to form an insulator 280 with a flat top surface (Figure 18). See Figures A to 18C. Note that, similar to the insulator 224, for example, a s Aluminum oxide is formed by the puttering method, and the aluminum oxide is used as an insulator 28 CMP processing may be performed until the value reaches 0.

[0356] Microwave treatment may be performed here. Microwave treatment is performed in an oxygen-containing atmosphere. It is preferable to carry out the process under reduced pressure. After microwave treatment, heating is performed while maintaining the reduced pressure. Processing may be performed. The heat treatment temperature should be between 300°C and 500°C. preferable.

[0357] Furthermore, by performing microwave treatment, the film quality of the insulator 280 is modified, and hydrogen Therefore, the diffusion of water, impurities, etc. can be suppressed after the formation of the insulator 280. Subsequent processes, such as heat treatment, allow hydrogen, water, and impurities to enter through the insulator 280, which can lead to acid This can suppress diffusion to the compound 230. In this embodiment, While an example of a configuration in which microwave processing is performed from the edge body 280 has been given, the invention is not limited to this. For example, in addition to microwave processing, plasma processing or microwave-excited plasma processing, etc. You may go.

[0358] Next, a portion of the insulator 280, a portion of the insulator 274, a portion of the insulating layer 271B, and the conductive layer 24 Part of 0B, part of oxide layer 241B, and part of oxide 230b are processed to obtain oxide 230 An opening is formed that reaches b. It is preferable that this opening be formed so as to overlap with the conductor 205. It is clear that the formation of the opening allows the insulator 271a, insulator 271b, and conductor 240a to be formed. Conductor 240b, oxide 241a, and oxide 241b are formed (Figures 19A to 19A). See 9C. ).

[0359] In the process of forming the above-mentioned opening, the upper part of the oxide 230b may be removed. By removing a portion of the oxide 230b, grooves are formed in the oxide 230b.

[0360] Furthermore, a portion of the insulator 280, a portion of the insulator 274, a portion of the insulating layer 271B, and the conductive layer 24 Processing of part of 0B, part of oxide layer 241B, and part of oxide 230b is performed by dryer The etching method or the wet etching method can be used. This type of machining is suitable for micro-machining. Furthermore, this machining can be performed under different conditions. Good. For example, a portion of the insulator 280 and a portion of the insulator 274 can be etched by dry etching. After processing, a portion of the insulating layer 271B is processed by the wet etching method, and a portion of the oxide layer 241B is processed. The part, a portion of the conductive layer 240B, and a portion of the oxide 230b were processed by dry etching. It is also possible to process a portion of the oxide layer 241B and a portion of the conductive layer 240B, and the oxide Some of the processing described in 230b may be carried out under different conditions.

[0361] Furthermore, a portion of oxide 230b is removed using a dry etching method to form grooves. When doing so, it is preferable to process with a strong bias power. For example, the bias power The density is 0.02 W / cm³. 2 The above should suffice, resulting in 0.03 W / cm². 2 It is preferable to do the above. Furthermore, 0.06 W / cm² 2 It is preferable to do the above. Also, during dry etching The spacing should be set appropriately according to the depth of the groove.

[0362] Here, in the above opening process, impurities are introduced into the opening, or damage is introduced to the surface of oxide 230b. Damaged areas may occur. These impurities and damaged areas are removed by the cleaning process. It is preferable to do so.

[0363] Next, an oxide film 230C is formed (see Figures 20A to 20C). A heat treatment may be performed before film formation, and this heat treatment should be carried out under reduced pressure and without exposure to the atmosphere. Furthermore, it is preferable to continuously form an oxide film 230C. In addition, this heat treatment is performed using oxygen. It is preferable to carry out the process in an atmosphere containing oxide 230b. It removes moisture and hydrogen adsorbed on the surface, and further removes oxide 230a and oxide The water and hydrogen concentrations in 230b can be reduced. The heat treatment temperature is 1 A temperature of 00°C to 400°C is preferred. In this embodiment, the heat treatment temperature is set to 200°C. ru.

[0364] Here, the oxide film 230C is formed on the inner wall of the groove in the oxide 230b, A portion of the side surface of object 241, a portion of the side surface of conductor 240, a portion of the side surface of insulator 271, and It is preferable that it be provided so as to be in contact with a part of the side surface of the insulator 280. The conductor 240 is Surrounded by oxide 241, insulator 271, and oxide film 230C, in subsequent processes This makes it possible to suppress the decrease in conductivity due to oxidation of the conductor 240.

[0365] The 230C oxide film can be deposited using sputtering, CVD, MBE, PLD, or ALD methods. This can be done using methods such as those described above. Oxide film 230C is formed using the same film formation method as oxide film 230A. It is possible to use this to form a film. In this embodiment, the oxide film 230C is formed by sputtering. Therefore, film deposition is performed using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. do.

[0366] Here, the oxygen vacancies in oxide 230b and oxide film 230C are reduced, and oxide 2 To make 30b substantially high-purity intrinsic, oxide 230b and oxide film 230C are used. Then, an oxygen-adding treatment (hereinafter also called oxygen injection treatment or oxygen doping treatment) is performed. (See Figures 21A to 21C and Figure 26A. Note that Figure 26A is a part of Figure 21C.) This is a magnified view of the image.

[0367] Oxygen is added to the channel-forming region of oxide 230b via the oxide film 230C. This suppresses the diffusion of impurities or the formation of damaged areas on the surface of the channel-forming region. This is possible. In particular, the oxide film 230C uses the same material as the oxide film 230b. Even if a portion of the oxide film 230C diffuses into the oxide 230b due to the additive treatment, impurities may still form. The problem of cause does not arise.

[0368] As shown in Figures 21B, 21C, and 26A, the oxide film is formed by oxygen injection treatment. On the surface of 230C, oxide 230b, insulator 280, and insulator 224, Oxygen is added to form region 292. In particular, region 292 is an oxide film 230C and acid It is preferable to provide it near the interface of oxide 230b. Oxygen is added to the surface of oxide 230b. This allows for efficient reduction of oxygen deficiency in oxide 230b during subsequent heat treatment. ru.

[0369] Specifically, oxygen implantation treatments include ion implantation, ion doping, and plasma injection. By using methods such as Merjohn ion implantation, the oxide film 230C and oxide 230b can be formed. Oxygen can be added. Furthermore, the gas used in the oxygen addition process is: 16 O2 or 18 Oxygen gases such as O2, nitrous oxide gas, ozone gas, and other oxygen-containing gases These can be listed. Furthermore, the process of adding oxygen may be carried out while heating the substrate.

[0370] For example, the acceleration voltage in ion doping is between 0.5kV and 100kV. Preferably 1kV to 50kV, more preferably 1kV to 30kV, even more preferably The voltage should be between 1kV and 10kV. The ion implantation concentration should be 1 × 10⁻⁶. 15 at oms / cm 2 Preferably 2 × 10 15 atoms / cm 2 More preferably, is 5 x 10 15 atoms / cm 2 In summary, 1 × 10 16 atoms / cm 2 The above is fua2×1016 atoms / cm 2 That concludes this section.

[0371] Furthermore, the addition of ions by ion doping should be performed approximately perpendicular to the sample surface. This is also good. In addition, the addition of ions by ion doping treatment has an angle with respect to the sample surface. It's fine if you do that.

[0372] In Figures 21B and 21C, arrow 290 represents the direction of oxygen ion movement. This is shown formulaically. As indicated by arrow 290, in the channel width direction of oxide 230b One ion is at an angle θ (45° < θ < 1) with respect to the tangent to the upper surface of oxide 230b. It is preferable to incident the light at 35°. Also, in the L-length direction of oxide 230b, It is preferable that the ions are incident on the upper surface of oxide 230b at an angle approximately perpendicular to it. By appropriately adjusting the angle θ, a film can be formed on the side surface of oxide 230b and on the side surface of oxide 230b. Oxygen can also be added to the oxide film 230C that has been formed.

[0373] Next, an oxide film 230D is deposited on the oxide film 230C (see Figures 22A to 22C). The oxide film 230D contains more oxygen and impurities than oxide film 230b and oxide film 230C. It is preferable that it has barrier properties against objects.

[0374] By placing oxide film 230D on top of oxide 230b and oxide film 230C, acid This suppresses the abstraction of oxygen from the oxide 230b and oxide film 230C. It can. Also, the oxide 230b from the structure formed above the oxide film 230D This can suppress the diffusion of impurities.

[0375] Next, heat treatment is performed (see Figures 23A to 23C, Figure 26B, and Figure 26C). Figures 26B and 26C are enlarged versions of parts of Figure 23C.

[0376] It is preferable to carry out the heat treatment in an oxygen atmosphere. This allows oxygen to be released into the oxide 230b. By supplying oxygen, it is possible to reduce oxygen deficiency. Furthermore, the heat treatment can be performed under reduced pressure. Good. Alternatively, heat treatment in an oxygen atmosphere followed by continuous treatment in a nitrogen atmosphere without exposure to air. Heat treatment may be performed.

[0377] Specifically, the heat treatment is performed at a temperature of 100°C to 450°C, preferably 350°C to 400°C. The following procedure is recommended. Note that the heat treatment should be performed using an oxidizing gas of 10 ppm or more, 1% or more. It is best to perform this in an atmosphere containing 10% or more of the substance.

[0378] The effects of this heat treatment will be explained using Figure 26. As shown in Figure 26B, the Due to heat, the oxygen added to region 292 by oxygen injection treatment is oxide 230b It diffuses into the interior, into the interior of insulator 224, and into the interior of insulator 280. Also, simultaneously, Figure 26C As shown, the diffused oxygen, upon heating, forms the oxide film 230C and oxide 230 It is supplied to the oxygen-deficient Vo in b, and by compensating for the oxygen deficiency, the oxide film 230C and It becomes part of oxide 230b. Meanwhile, oxygen diffused into insulators 224 and 280 The excess oxygen remains in insulators 224 and 280.

[0379] By reducing defect levels or oxygen vacancies in the channel formation region, variations in electrical properties are minimized. Furthermore, it is possible to provide highly reliable transistors. Also, transistors are normally - A transistor with off-mode characteristics can be provided.

[0380] On the other hand, when the metal oxide contains an excess of oxygen exceeding the appropriate amount, the transistor is When driven, the valence state of excess oxygen atoms changes, causing the electrical characteristics of the transistor to fluctuate. This can sometimes lead to a decrease in reliability.

[0381] Therefore, the channel formation region of oxide 230b is made of oxide 230a, which has barrier properties, By covering with the oxide 230d which has barrier properties, the excess oxygen present in the insulator 224 However, this can suppress the excessive supply to oxide 230b.

[0382] Next, the insulating film 250A is deposited (see Figures 24A to 24C). Deposition of insulating film 250A A heat treatment may be performed beforehand. After the heat treatment is performed under reduced pressure, exposure to the atmosphere is not permitted. Furthermore, it is preferable to continuously deposit the insulating film 250A. In addition, this heat treatment is performed using oxygen. It is preferable to carry out the process in an atmosphere containing the substance. By performing this process, the oxide film 230D It removes moisture and hydrogen adsorbed on the surface, and further removes oxide 230a and oxide 23 The water and hydrogen concentrations in 0b and oxide film 230D can be reduced. The heat treatment temperature is preferably between 100°C and 400°C.

[0383] Next, conductive film 260A and conductive film 260B are deposited in sequence (see Figures 24A to 24C). The conductive films 260A and 260B were deposited using sputtering, CVD, and MB. This can be done using methods such as the E method, PLD method, and ALD method. In this embodiment, the ALD method is used. Using this method, a conductive film 260A was deposited, and the CVD method was continuously applied under reduced pressure without releasing it to the atmosphere. Then, a conductive film 260B is deposited.

[0384] Next, CMP treatment is performed to create oxide film 230C, oxide film 230D, insulating film 250A, and conductive film. By polishing film 260A and conductive film 260B until the insulator 280 is exposed , oxide 230c, oxide 230d, insulator 250, and conductor 260 (conductor 260 a) and conductor 260b) are formed (see Figures 25A to 25C).

[0385] The above CMP process may remove a portion of the insulator 280, including region 292. By removing the region, the amount of excess oxygen present in the insulator 280 can be reduced.

[0386] As a result of the above processing, oxide 230c has openings that reach oxide 230b and oxide 230 It is positioned to cover the inner wall (side wall and bottom surface) of the groove of b. In addition, the insulator 250 is It is arranged to cover the inner walls of the opening and the groove via oxide 230c. The conductor 260, via the oxide 230c and the insulator 250, the opening and the It is positioned to fill the groove.

[0387] Next, a heat treatment may be performed under the same conditions as the heat treatment described above. In this embodiment, nitrogen The process is carried out at a temperature of 400°C for 1 hour in a plain atmosphere. This heat treatment causes the insulator 250 Furthermore, the moisture and hydrogen concentrations in the insulator 280 can be reduced. After heat treatment, the insulator 282 may be deposited continuously without exposure to the atmosphere.

[0388] Next, on oxide 230d, on oxide 230c, on insulator 250, on conductor 260, and An insulator 282 is formed on the insulator 280. The insulator 282 is deposited by sputtering. This can be done using methods such as CVD, MBE, PLD, and ALD.

[0389] The insulator 282 is formed in an atmosphere that does not contain at least oxygen. For example, a noble gas, nitrogen It is preferable to form the film under an inert atmosphere such as an element. Specifically, as the insulator 282 It is preferable to deposit a film of a nitride such as silicon nitride.

[0390] When forming a film in an oxygen-containing atmosphere, oxygen may be added to the film-forming surface. Insulator 2 When oxygen is added to 80, the oxygen enters the channel-forming region via oxide 230c. There is a high probability that it will diffuse. If excess oxygen diffuses into the channel formation region, the transient This can sometimes be a cause of deterioration in the electrical properties of the device.

[0391] Next, an insulator 283 is formed on the insulator 282.

[0392] Next, the conductor 2 It forms an opening that reaches 40.

[0393] Next, an insulating film to become an insulator 276 is formed, and the insulating film is anisotropically etched to form an insulator. Forms 276 (insulators 276a and 276b).

[0394] Next, conductive films that will become conductors 246a and 246b are formed. Conductor 246a The conductive film that forms the conductor 246b has the function of suppressing the permeation of impurities such as water and hydrogen. It is desirable to have a laminated structure that includes a conductor.

[0395] Next, by performing CMP treatment, the conductive films that become conductors 246a and 246b are formed. Remove a portion to expose the upper surfaces of insulators 283 and 276. As a result, only the opening remains. The remaining conductive film forms conductors 246a and 246b with flat upper surfaces. This can be achieved. Furthermore, this CMP treatment removes part of the upper surface of the insulator 283 and the insulation A portion of the upper surface of the edge 276 may be removed.

[0396] Next, a conductive film that will become the conductor 248 is deposited.

[0397] Next, the conductive film that will become the conductor 248 is processed by lithography, and the conductor 246a is produced. The conductor 248a that is in contact with the upper surface of the conductor 246b, and the conductor 248b that is in contact with the upper surface of the conductor 246b To form.

[0398] Next, an insulating film 286 is formed on the conductive material 248 and the insulating material 283 (Figure 17A). (See Figure 17C.)

[0399] Based on the above, a semiconductor device having the transistor 200 shown in Figures 17A to 17C can be constructed. It can be manufactured.

[0400] <Modified example of a semiconductor device 2> In the following, using Figures 27A to 27C, an example of a semiconductor device that is one aspect of the present invention will be shown. I will explain about this.

[0401] Figure 27A shows a top view of the semiconductor device. Figure 27B shows the same A1-A2 as in Figure 27A. This is a cross-sectional view corresponding to the area indicated by the dashed line in Figure 27A. Also, Figure 27C is a cross-sectional view corresponding to A3-A in Figure 27A. This is a cross-sectional view corresponding to the area indicated by the dashed line in 4. In the top view of Figure 27A, the diagram is clarified. Some elements have been omitted for this reason.

[0402] In addition, in the semiconductor device shown in Figures 27A to 27C, <Example of semiconductor device configuration 2> Structures having the same function as the semiconductor device shown will be denoted by the same reference numeral. In this section as well, the constituent materials of semiconductor devices are described in detail in <Example of Semiconductor Device Configuration 2>. The materials described can be used.

[0403] The semiconductor device shown in Figures 27A to 27C is the same as the semiconductor device shown in Figures 17A to 17C. This is a modified version. The semiconductor device shown in Figures 27A to 27C is shown in Figures 17A to 17C. The semiconductor device described above has different shapes for insulators 214, 282, and 283. The difference is that it has an insulator 284.

[0404] In the semiconductor device shown in Figures 27A to 27C, insulator 214, insulator 216, insulator 2 Insulators 222, 280, and 282 are patterned. Furthermore, insulator 283 is insulator 214, insulator 216, insulator 222, insulator 224, insulator The structure covers the body 280 and the insulator 282. In other words, the insulator 283 is an insulating material. The top and side surfaces of the body 282 and the top surface of the insulator 212 are in contact. This allows the oxide 230 Insulators 214, 216, 222, 224, and 280, among others. , and insulator 282 is isolated from the outside by insulator 283 and insulator 212. In other words, transistor 200 is sealed with insulator 283 and insulator 212. It will be located within the region.

[0405] For example, the insulator 214 is made of a material having the function of capturing and fixing hydrogen. Forms and expands the insulators 212, 282, and 283 to hydrogen and oxygen. It is preferable to form it using a material that has a function of suppressing dispersion. Typically, insulator 214 Aluminum oxide can be used as an example. Also, typically, insulator 212, Silicon nitride can be used as the insulator 282 and the insulator 283.

[0406] With the above configuration, hydrogen contained outside the sealed region will enter the sealed region This can prevent contamination inside the container.

[0407] Furthermore, in the transistor 200 shown in Figures 27A to 27C, the insulator 212 and the insulator The present invention is shown in which the edge 283 is provided as a single layer, but the present invention is not limited to this. No. For example, the insulator 212 and the insulator 283 are each made up of two or more layers. It may also be configured as a structural element.

[0408] Insulator 284 functions as an interlayer film. Insulator 284 has a higher dielectric constant than insulator 214. A low dielectric constant is preferable. By using a material with a low dielectric constant as the interlayer film, parasitic volumes that form between wiring are reduced. The amount can be reduced. The insulator 284 can be made of the same material as the insulator 280, for example. It can be established.

[0409] <Application example of semiconductor device 2> In the following, using Figures 28A and 28B, we will explain the <Semiconductor Device Configuration Example 2> and the previous A transistor according to one aspect of the present invention, which differs from the one shown in <Modification Example 2 of Semiconductor Device> An example of a semiconductor device having a 200 is described below. Note that Figures 28A and 28B are shown below. In the semiconductor device shown, the semiconductor device shown in <Modified Example of Semiconductor Device 2> (Figures 17A to See Figure 17C. Structures having the same function as the structures that constitute the ) are denoted by the same reference numeral. In this section, the constituent materials of transistor 200 are as shown in <Example of Semiconductor Device Configuration 2>. The materials described in detail in <Modification of Semiconductor Device 2> can be used.

[0410] Figures 28A and 28B show multiple transistors 200_1 to 200_ The configuration in which n is enclosed and sealed by insulators 283 and 212 is shown. Note: Figure 2 In 8A and Figure 28B, transistors 200_1 to 200_n are, They appear to be aligned along the channel length, but this is not the only arrangement. Transition The transistors 200_1 through 200_n may be arranged in the channel width direction, They may be arranged in a matrix. Alternatively, they may be arranged without any regularity, depending on the design. It's fine if you do that.

[0411] As shown in Figure 28A, multiple transistors 200_1 to 200_n On the outside, the portion where the insulator 283 and the insulator 212 are in contact (hereinafter referred to as the sealing portion 265) There is a combination.) is formed. The sealing portion 265 is formed by multiple transistors 200_1 to It is formed to surround the transistor 200_n. By using this structure, multiple The transistors 200_1 through 200_n are connected by insulators 283 and 212. It can be enclosed. Therefore, multiple transistor groups surrounded by the sealing portion 265 can be placed on the substrate. It will be established.

[0412] Also, a dicing line (scribe line, division line, or A cutting line may be provided. The above substrate is divided at the dicing line. Because it is disconnected, the group of transistors surrounded by the sealing portion 265 can be extracted as a single chip. It will become that.

[0413] Furthermore, in Figure 28A, multiple transistors 200_1 to 200_n are connected. An example of surrounding with two sealing portions 265 has been shown, but it is not limited to this. Figure 28B shows As shown, multiple transistors 200_1 to 200_n are connected to multiple sealing parts It may also be configured to enclose it. In Figure 28B, multiple transistors 200_1 or to The structure is such that the 200_n is surrounded by the sealing part 265a, and further surrounded by the outer sealing part 265b. Yes, they are.

[0414] In this way, multiple transistors 200_1 to transistor 200_ are enclosed in multiple sealing portions. By creating a configuration that surrounds n, the area where insulator 283 and insulator 212 are in contact increases, thus providing an insulating The adhesion between the edge body 283 and the insulator 212 can be further improved. This makes it more reliable. In fact, multiple transistors 200_1 through 200_n can be sealed. .

[0415] In this case, even if a dicing line is provided overlapping the sealing portion 265a or the sealing portion 265b Alternatively, a dicing line may be provided between the sealing portion 265a and the sealing portion 265b.

[0416] According to one aspect of the present invention, a semiconductor device with less variation in transistor characteristics is provided. This can be achieved. Furthermore, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. It is possible. Furthermore, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. This is possible. Furthermore, according to one aspect of the present invention, a semiconductor device with a large on-current is provided. This is possible. Furthermore, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated is provided. It can be provided. Furthermore, according to one aspect of the present invention, a low-power semiconductor device can be provided. It is possible.

[0417] The configurations and methods described in this embodiment are similar to those described in other embodiments or examples. It can be used in appropriate combination with other methods, etc.

[0418] (Embodiment 3) In this embodiment, one form of a semiconductor device will be described using Figures 29 to 32.

[0419] [Storage device 1] An example of a semiconductor device (memory device) according to one aspect of the present invention is shown in Figures 29 and 30. A semiconductor device according to one aspect of the present invention comprises a transistor 200, a transistor 300, and a capacitor. It has element 100. Transistor 200 is provided above transistor 300, and capacitance Element 100 is located above transistors 300 and 200. Furthermore, the transistor 200 used is the same transistor 200 described in the previous embodiment. It is possible.

[0420] Transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. It is a transistor. Transistor 200 is used in memory devices because it has a low off-current. This makes it possible to retain memory content for a long period of time. In other words, refresh Because it does not require any operation, or because the refresh operation is performed very infrequently, the memory Power consumption can be significantly reduced.

[0421] In the semiconductor device shown in Figures 29 and 30, wiring 1001 is transistor 300 The source is electrically connected, and wiring 1002 is electrically connected to the drain of transistor 300. They are connected. Also, wiring 1003 is one of the source and drain of transistor 200. The wiring 1004 is electrically connected to the first gate of transistor 200. The wiring 1006 is then electrically connected to the second gate of transistor 200. And the gate of transistor 300, and the source and slave of transistor 200. The other end of the wire is electrically connected to one of the electrodes of the capacitive element 100, and the wiring 1005 is connected to the capacitive element It is electrically connected to the other of the 100 electrodes.

[0422] Furthermore, the memory devices shown in Figures 29 and 30 are arranged in a matrix, allowing for memo storage. A recell array can be constructed.

[0423] <Transistor 300> The transistor 300 is provided on the substrate 311 and has a conductor 316 that functions as a gate. , an insulator 315 that functions as a gate insulator, and a semiconductor region 31 which is part of the substrate 311 3, and a low-resistance region 314a that functions as a source region or drain region, and low It has a resistive region 314b. Transistor 300 is either a p-channel or n-channel type. Any type is acceptable.

[0424] Here, the transistor 300 shown in Figures 29 and 30 is a semiconductor in which a channel is formed. The body region 313 (part of the substrate 311) has a convex shape. Also, the side surface of the semiconductor region 313 The upper surface is covered by a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 Because it utilizes the protrusions on the semiconductor substrate, it is also called a FIN-type transistor. Even if there is an insulator that is in contact with the upper part of the protrusion and functions as a mask for forming the protrusion, Good. Also, although we have shown here the case where a protrusion is formed by processing a part of the semiconductor substrate, SO A semiconductor film having a convex shape may be formed by processing the substrate.

[0425] Note that the transistor 300 shown in Figures 29 and 30 is just one example and is not limited to its structure. It is not necessary to use a specific transistor; instead, an appropriate transistor should be used depending on the circuit configuration and driving method.

[0426] <Capacitive element 100> The capacitive element 100 is located above the transistor 200. The capacitive element 100 is the first A conductor 110 that functions as an electrode, a conductor 120 that functions as a second electrode, and It has an insulator 130 that functions as a dielectric. Here, the insulator 130 is in the form described above. It is preferable to use an insulator that can be used as the insulator 286 shown in the diagram.

[0427] Furthermore, for example, the conductor 112 and the conductor 110 provided on the conductor 246 are formed simultaneously. This is possible. Furthermore, the conductor 112 is connected to the capacitive element 100, the transistor 200, and It functions as a plug or wire that electrically connects to transistor 300.

[0428] In Figures 29 and 30, the conductors 112 and 110 showed a single-layer structure. However, the configuration is not limited to this, and a laminated structure of two or more layers is also acceptable. For example, a conductive barrier. A conductor with barrier properties and a highly conductive conductor are placed between the body and the highly conductive conductor. A conductive material with high adhesion to it may be formed.

[0429] Furthermore, the insulator 130 may be, for example, silicon oxide, silicon oxide nitride, or silicon oxide nitride. Silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, nitrile Aluminum oxide, hafnium oxide, hafnium oxide nitride, hafnium oxide nitride, hafnium nitride It can be made using materials such as nium, and can be constructed in layers or as a single layer.

[0430] For example, the insulator 130 may contain a material with high dielectric strength, such as silicon oxynitride, and a high dielectric strength material. It is preferable to use a laminated structure with a high-k material. With this configuration, the capacity element Child 100 has a high dielectric constant (high-k) insulator, which ensures sufficient capacitance. By having an insulator with high dielectric strength, the dielectric strength is improved, and the electrostatic discharge of the capacitive element 100 is reduced. It can suppress damage.

[0431] Furthermore, as an insulator of high-dielectric constant (high-k) materials (materials with a high relative permittivity), Having gallium, hafnium oxide, zirconium oxide, aluminum and hafnium Oxides, aluminum and hafnium-containing oxides and nitrides, silicon and hafnium Oxides having silicon and hafnium, or silicon and ha Examples include nitrides containing humium.

[0432] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide and nitrogen oxide. Silicon oxide, silicon nitride, silicon nitride, silicon oxide with added fluorine, carbon Silicon oxide with added carbon and nitrogen, silicon oxide with voids It may be made of concrete or resin.

[0433] <Wiring layer> Between each structure, there is a wiring layer containing interlayer membranes, wiring, and plugs. This is also possible. Furthermore, multiple wiring layers can be provided depending on the design. Here, the plug In the case of a conductor that functions as wiring, where multiple structures are grouped together and assigned the same code, There is a possibility of this occurring. Furthermore, in this specification, etc., the wiring and the plug that electrically connects to the wiring are integrated. It may also be an object. That is, when a part of the conductor functions as wiring, and the conductor Some parts may function as plugs.

[0434] For example, on transistor 300, there are insulators 320, 322, and an insulator as interlayer films. The edge body 324 and the insulator 326 are arranged in order in stacked layers. Also, the insulator 320, Insulators 322, 324, and 326 contain capacitive elements 100 or transients Conductors 328 and 330, etc., which are electrically connected to the sta 200, are embedded within. Furthermore, conductors 328 and 330 function as plugs or wiring.

[0435] Furthermore, the insulator, which functions as an interlayer film, acts as a planarizing film that covers the uneven shape beneath it. It may function. For example, the upper surface of the insulator 322 may be chemically and mechanically polished to improve flatness. The surface may be flattened by a flattening treatment such as the CMP method.

[0436] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, Figure 29, In Figure 30, insulators 350, 352, and 354 are stacked in order. It is also provided with a conductor 35 insulator 350, insulator 352, and insulator 354. 6 is formed. The conductor 356 functions as a plug or wiring.

[0437] Similarly, insulators 210, 212, 214, and 216 are conductive Body 218 and the conductor (conductor 205) that constitutes the transistor 200 are embedded. It is present. Furthermore, the conductor 218 is electrically connected to the capacitive element 100 or the transistor 300. It functions as a connecting plug or wiring. Furthermore, the conductor 120 and the insulator An insulator 150 is provided above 130.

[0438] Here, similar to the insulator 271 shown in the above embodiment, a conductor 2 that functions as a plug An insulator 217 is provided in contact with the side surface of 18. The insulator 217 is in contact with the insulator 210, insulator In contact with the inner wall of the opening formed in insulators 211, 212, 214, and 216. It is provided in this manner. In other words, the insulator 217 is made up of a conductor 218, an insulator 210, and an insulator It is provided between insulator 211, insulator 212, insulator 214, and insulator 216. Furthermore, since the conductor 205 can be formed in parallel with the conductor 218, the conductor 205 In some cases, an insulator 217 may be formed in contact with the side surface.

[0439] Examples of insulators 217 include silicon nitride, aluminum oxide, or silicon nitride oxide. An insulator such as Ricon can be used. Insulator 217 is an insulator, insulator 211, insulator 212, Since it is provided in contact with the edge 214 and the insulator 222, the insulator 210 or the insulator 2 Impurities such as water or hydrogen from 16 etc. are mixed into the oxide 230 through the conductor 218. This can suppress hydrogen formation. In particular, silicon nitride has high blocking properties for hydrogen. Therefore, it is suitable. Also, the oxygen contained in the insulator 210 or insulator 216 is conductor 218 This can prevent it from being absorbed.

[0440] The insulator 217 can be formed in the same manner as the insulator 271. For example, PEA A silicon nitride film is deposited using the LD method, and the conductive material 356 is reached using anisotropic etching. You just need to form an opening.

[0441] Insulators that can be used as interlayer films include insulating oxides, nitrides, and acids. Examples include nitrides, nitride oxides, metal oxides, metal oxide nitrides, and metal nitride oxides.

[0442] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, wiring The parasitic capacitance that occurs between them can be reduced. Therefore, depending on the function of the insulator, the material You should choose this option.

[0443] For example, insulators 150, 210, 352, and 354 have a ratio It is preferable to have an insulator with a low dielectric constant. For example, the insulator may be silicon nitride. , nitride silicon, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and silicon oxide with nitrogen added, silicon oxide having voids, or resins, etc. This is preferable. Alternatively, the insulator may be silicon oxide, silicon oxide nitride, or silicon oxide nitride Cone, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, carbon Lamination of silicon oxide with added elements and nitrogen or porous silicon oxide with resin It is preferable that it has a structure. Silicon oxide and silicon oxide-nitride are thermally stable. Therefore, by combining it with resin, a thermally stable laminated structure with a low dielectric constant is achieved. This can be done. Examples of resins include polyester, polyolefin, and polyamide (nylon Examples include ramid, polyimide, polycarbonate, or acrylic.

[0444] Furthermore, transistors using oxide semiconductors suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has a controlling function, the electrical characteristics of the transistor are stabilized. Therefore, hydrogen, etc. can be contained in insulators 214, 212 and 350, etc. An insulator that has the function of suppressing the permeation of impurities and oxygen should be used.

[0445] Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include, Boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, salt Element, argon, gallium, germanium, yttrium, zirconium, lanthanum, neo An insulator containing zym, hafnium, or tantalum may be used in a single layer or in a multilayer configuration. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide Umium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tan oxide Metal oxides such as tar, silicon nitride, or silicon nitride can be used. .

[0446] Conductors that can be used in wiring and plugs include aluminum, chromium, copper, and silver. Gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanilla Dium, niobium, manganese, magnesium, zirconium, beryllium, indium, Materials containing one or more metallic elements selected from thenium and others can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like nitrates, Silicides such as nickel silicide may also be used.

[0447] For example, conductor 328, conductor 330, conductor 356, conductor 218, and conductor 1 12, etc., are metal materials, alloy materials, metal nitride materials, or formed from the above materials. Conductive materials such as metal oxide materials can be used in a single layer or in a laminated form. Heat resistance and It is preferable to use high-melting-point materials such as tungsten or molybdenum that can achieve both conductivity and electrical conductivity. Tungsten is preferable. Alternatively, a low-resistance conductive material such as aluminum or copper may be used. It is preferable to form it with a material. By using a low-resistance conductive material, the wiring resistance can be reduced. It is possible.

[0448] <Wiring or plugs in layers containing oxide semiconductors> Furthermore, when an oxide semiconductor is used for transistor 200, excess near the oxide semiconductor An insulator having an oxygen region may be provided. In that case, the insulator having the excess oxygen region A barrier-type insulator is provided between the insulator having the excess oxygen region and the conductor. It is preferable to provide one.

[0449] For example, in Figures 29 and 30, insulators 224 and 28 have excess oxygen. It is preferable to provide an insulator 271 between 0 and the conductor 246. Insulator 271 and insulator 2 22, the insulator 282 and the insulator 283 are provided in contact with each other, so that the insulator 224, The transistor 200 is to be sealed with a barrier-type insulator. It is possible.

[0450] In other words, by providing the insulator 271, the excess insulation of the insulators 224 and 280 is eliminated. The absorption of oxygen by the conductor 246 can be suppressed. Also, the insulator 271 By having this, the impurity hydrogen diffuses to the transistor 200 via the conductor 246. This can suppress the action.

[0451] Furthermore, the insulator 271 is designed to suppress the diffusion of impurities such as water or hydrogen, and oxygen. It is preferable to use an insulating material that has the function of [doing something]. For example, silicon nitride, silicon nitride oxide, It is preferable to use aluminum oxide or hafnium oxide. In particular, silica nitride N is preferred because it has high blocking properties for hydrogen. In addition, other options include, for example, magnesium oxide. Nesium, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, acid Metal oxides such as lanthanum oxide, neodymium oxide, or tantalum oxide can be used. ru.

[0452] Furthermore, similar to the above embodiment, the transistor 200 is insulator 212, insulator 214 It is preferable that the insulators 282 and 283 are sealed. As a result, hydrogen contained in insulators 284 and 150 mixes with insulator 280 and the like. This can reduce the likelihood of this happening.

[0453] Here, the insulator 283 and insulator 282 have a conductor 246, and the insulator 214 has an insulating The conductor 218 penetrates the body 212 and the insulator 211, but as described above, the insulator The 271 is provided in contact with the conductor 246, and the insulator 217 is provided in contact with the conductor 218. This allows the insulator 212 and the insulator to pass through the conductor 246 and the conductor 218. This reduces the amount of hydrogen that can be mixed inside insulators 214, 282, and 283. In this way, insulator 212, insulator 214, insulator 282, insulator 283, insulation The body 271 and the insulator 217 more securely seal the transistor 200, and the insulator 284 This can reduce the intrusion of impurities such as hydrogen contained in the material from the outside.

[0454] Also, insulators 216, 224, 280, 250, and 28 4 is a film deposition using a gas in which hydrogen atoms have been reduced or removed, as shown in the previous embodiment. It is preferable to form them by this method. This results in insulator 216, insulator 224, insulator 2 The hydrogen concentrations of 80, insulator 250, and insulator 284 can be reduced.

[0455] In this way, the hydrogen concentration of the silicon-based insulating film near transistor 200 is reduced, and acid The hydrogen concentration of compound 230 can be reduced.

[0456] <Dicing line> In the following, by dividing a large-area substrate into semiconductor elements, multiple semiconductor devices are created. Dicing lines (scribe lines, division lines) are provided when extracting chips. This explains the cutting line (which may also be called the cutting line). For example, the method of division is... First, grooves (dicing lines) are formed in the substrate to divide the semiconductor elements, In some cases, the semiconductor device may be cut during grinding, resulting in its division into multiple semiconductor devices.

[0457] Here, for example, as shown in Figures 29 and 30, there is an insulator 283 and an insulator 212 It is preferable to design the area where the two touch to overlap with the dicing line. This is a dicing line provided on the outer edge of a memory cell having 200 transistors. Near the region, insulator 282, insulator 280, insulator 224, insulator 222, insulator Openings are provided in 216 and the insulator 214.

[0458] In other words, the above insulators 282, 280, 224, 222, and 21 6, and in the opening provided in the insulator 214, the insulator 212 and the insulator 283 are in contact. The insulators 212 and 283 are provided using the same material and method, ensuring close contact. The properties can be improved. For example, it is preferable to use silicon nitride.

[0459] With this structure, insulators 212, 214, 282, and 283 , can enclose transistor 200. Insulator 212, insulator 214, insulator 2 82, and at least one of the insulators 283, have the function of suppressing the diffusion of oxygen, hydrogen, and water. Because it has, for each circuit region where the semiconductor element shown in this embodiment is formed, the substrate By dividing the substrate, even if it is processed into multiple chips, hydrogen or This prevents impurities such as water from contaminating the transistor 200 and diffusing into it.

[0460] Furthermore, this structure allows excess oxygen from the insulators 280 and 224 to diffuse to the outside. This can be prevented. Therefore, excess oxygen in insulator 280 and insulator 224 The acid is efficiently supplied to the oxide that forms the channel in transistor 200. This reduces oxygen vacancies in the oxide that form the channel in transistor 200. This allows the channel in transistor 200 to be formed in the oxide. This allows for the creation of an oxide semiconductor with a low defect level density and stable properties. In other words, This suppresses fluctuations in the electrical characteristics of transistor 200 and improves its reliability. ru.

[0461] In the memory devices shown in Figures 29 and 30, the shape of the capacitive element 100 is planar type. However, the storage devices shown in this embodiment are not limited to these. For example, Figure 3 As shown in Figure 1 and Figure 32, the shape of the capacitive element 100 may be cylindrical. The memory device shown in Figure 32 has the same configuration below the insulator 150 as the semiconductor device shown in Figure 31. It appears that way.

[0462] The capacitive element 100 shown in Figures 31 and 32 is connected to the insulator 150 on the insulator 130, and The insulator 142 on the edge 150 and the openings formed in the insulator 150 and the insulator 142 A conductor 115 is arranged on the conductor 115 and an insulator 145 on the insulator 142, and A conductor 125 on the edge 145, and an insulator 152 on the conductor 125 and the insulator 145, It has an opening formed in the insulator 150 and the insulator 142 into which the conductor 11 5. At least a portion of the insulator 145 and the conductor 125 are arranged.

[0463] The conductor 115 functions as the lower electrode of the capacitive element 100, and the conductor 125 functions as the lower electrode of the capacitive element 10 The insulator 145 functions as the upper electrode of 0 and as the dielectric of the capacitive element 100. The capacitive element 100 has openings in the insulators 150 and 142, not only on the bottom surface, On the side, the upper electrode and the lower electrode are arranged facing each other with a dielectric in between, The capacitance per unit area can be increased. Therefore, increasing the depth of the opening will increase the capacitance per unit area. This allows the capacitance of the capacitive element 100 to be increased. By increasing the capacitance per unit area, it is possible to miniaturize or highly integrate semiconductor devices. This can be used to advance it.

[0464] Insulator 152 may be any insulator that can be used for insulator 280. The edge 142 functions as an etching stopper when forming an opening in the insulator 150. Preferably, any insulator that can be used for the insulator 214 may be used.

[0465] The shape of the openings formed in the insulators 150 and 142, when viewed from above, is rectangular. It may be a polygon other than a quadrilateral, or a polygon with curved corners. It may be a shape, or it may be a circular shape including an ellipse. Here, in a top view, the opening It is preferable to have a large overlapping area between the port and transistor 200. This reduces the occupied area of ​​the semiconductor device having the capacitive element 100 and the transistor 200. It is possible.

[0466] The conductor 115 is positioned in contact with the openings formed in the insulator 142 and the insulator 150. The upper surface of the conductor 115 is preferably substantially the same as the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through an opening in the insulator 130. 5 is preferably formed using the ALD method or CVD method, for example, conductor 2 Any conductive material suitable for 05 should be used.

[0467] The insulator 145 is positioned to cover the conductor 115 and the insulator 142. For example, It is preferable to deposit the insulator 145 using the ALD method or CVD method. 45 is, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, Zirconium oxide, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, Aluminum nitride, hafnium oxide, hafnium oxide nitride, hafnium oxide nitride, hafnium nitride A material such as humic acid can be used, and it can be provided in a laminated or single layer. For example, insulator 1 As shown in 45, the layers are stacked in the order of zirconium oxide, aluminum oxide, and zirconium oxide. An insulating film can be used.

[0468] Furthermore, the insulator 145 may be a material with high dielectric strength, such as silicon oxynitride, or a high dielectric strength material. It is preferable to use a high-k material. Alternatively, a material with high dielectric strength and high A laminated structure of high-k dielectric materials may also be used.

[0469] Furthermore, as an insulator of high-dielectric constant (high-k) materials (materials with a high relative permittivity), Having gallium, hafnium oxide, zirconium oxide, aluminum and hafnium Oxides, aluminum and hafnium-containing oxides and nitrides, silicon and hafnium Oxides having silicon and hafnium, oxidized nitrides having silicon and hafnium Examples include nitrides containing um. By using such high-k materials, an insulator 1 Even if the thickness of 45 is increased, sufficient capacitance of the capacitive element 100 can be secured. Insulator 145 By increasing the thickness, the leakage current between the conductor 115 and the conductor 125 is suppressed. It is possible.

[0470] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxide nitride, and silicon oxide nitride. Silicon oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, Examples include silicon oxide with added carbon and nitrogen, silicon oxide with voids, and resins. For example, silicon nitride (SiN) deposited using the ALD method x ), using the PEALD method Silicon oxide film (SiO x ), silicon nitride (SiN) deposited using the ALD method x ) An insulating film can be used that is stacked in the order of these. By using this method, the dielectric strength is improved, and electrostatic discharge breakdown of the capacitive element 100 can be suppressed. .

[0471] The conductor 125 is positioned to fill the openings formed in the insulators 142 and 150. It is placed. Also, the conductor 125 is connected to the wiring 10 via the conductor 140 and the conductor 153. It is electrically connected to 05. Conductor 125 is formed using methods such as ALD or CVD. It is preferable to form a film, for example, by using a conductor that can be used for the conductor 205. stomach.

[0472] Furthermore, the conductor 153 is provided on the insulator 154 and is covered by the insulator 156. The conductor 153 can be any conductor that can be used for the conductor 112, and the insulator 156 can be any insulator that can be used for insulator 152. Here, conductor 1 53 is in contact with the upper surface of the conductor 140, and the capacitive element 100, the transistor 200, or It functions as a terminal for transistor 300.

[0473] The configurations and methods shown in this embodiment are similar to the configurations and structures shown in other embodiments or examples. It can be used in appropriate combination with other methods, etc.

[0474] (Embodiment 4) In this embodiment, a device that can be used when manufacturing a semiconductor device according to one aspect of the present invention is provided. The placement will be explained with reference to Figure 33.

[0475] When fabricating a semiconductor device according to one aspect of the present invention, multiple different film types can be continuously deposited. It is preferable to use a so-called multi-chamber apparatus having processing chambers. In each processing chamber, Each can perform thin-film deposition processes such as sputtering, CVD, and ALD. For example, if one processing chamber is used as a sputtering chamber, the sputtering chamber will have a gas supply. The supply device, the gas purification device connected to the gas supply device, the vacuum pump, the target, etc. It can be continued.

[0476] In addition, each processing room performs substrate cleaning, plasma treatment, and reverse sputtering. Etching, ashing, and heat treatment may also be performed. In each treatment chamber, By performing different processes as appropriate, insulators, conductors, and semiconductor films can be processed without exposure to the atmosphere. It can be used to form a thin film.

[0477] A typical example of a semiconductor film used in one aspect of the present invention is an oxide semiconductor film. In particular, oxide semiconductor films with low impurity concentrations and low defect level densities (few oxygen vacancies) Transistors with excellent electrical properties can be fabricated. Here, the impurity concentration is A low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic.

[0478] High-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films have fewer carrier sources. Therefore, the carrier density can be lowered. Consequently, the oxide semiconductor film has channel-shaped A transistor in which a region is formed exhibits electrical characteristics where the threshold voltage is negative (normally It is also called -on.) It rarely becomes. Also, it is high-purity intrinsic or substantially high-purity intrinsic. In some oxide semiconductor films, the low defect level density can result in a low trap level density. Furthermore, oxide semiconductor films that are high-purity intrinsic or substantially high-purity intrinsic have a significant off-current. It is very small, with a channel width of 1 x 10 6 Even if the element has a channel length L of 10 μm, When the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, The off-current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1 × 10⁻⁶ -13 After A It can acquire the characteristic of being downwards.

[0479] Typical impurities in oxide semiconductor films include water and hydrogen. Furthermore, in this specification, etc., reducing or removing water and hydrogen from oxide semiconductor films. This is sometimes expressed as dehydration or dehydrogenation. Furthermore, the process of adding oxygen to an oxide semiconductor film is also referred to as dehydration or dehydrogenation. This is sometimes expressed as oxygenation, and refers to a state where oxygenation has occurred and the oxygen content is in excess of the stoichiometric composition. This state is sometimes referred to as an excess oxygen state.

[0480] Here, an oxide semiconductor, an insulator or conductor located beneath the oxide semiconductor, and an acid A different film is used to separate an insulator or conductor located on the upper layer of a semiconductor without opening it to the atmosphere. By continuously depositing seeds into a film, the concentration of impurities (especially hydrogen and water) is reduced, resulting in a substantially high-purity product. It is possible to deposit highly intrinsic oxide semiconductor films.

[0481] First, an example of the configuration of an apparatus that can be used when manufacturing a semiconductor device according to one aspect of the present invention. Details will be explained using Figure 33. By using the apparatus shown in Figure 33, a semiconductor film and an insulator or conductor located in the lower layer of the semiconductor film, and an insulator located in the upper layer of the semiconductor film. It can be used to continuously form a film with a conductor or other material. Therefore, impurities that can penetrate into the semiconductor film can be deposited. It can suppress substances (especially hydrogen and water).

[0482] Figure 33 schematically shows a top view of the single-wafer multi-chamber apparatus 4000.

[0483] The apparatus 4000 includes an atmospheric substrate supply chamber 4010, and from the atmospheric substrate supply chamber 4010, The atmospheric side substrate transport chamber 4012 transports the substrates, and the chamber is used for loading the substrates and maintaining the pressure inside the chamber at atmospheric pressure. A load lock chamber 4020a for reducing pressure, or switching from reduced pressure to atmospheric pressure, and for unloading the substrate. This involves unloading the room by switching the pressure from reduced pressure to atmospheric pressure, or from atmospheric pressure to reduced pressure. Locking chamber 4020b, transport chamber 4029 for transporting substrates in a vacuum, and transport chamber 403 9, and a transfer room 4030a connecting the transport room 4029 and the transport room 4039, and a transfer room 4 030b and processing chambers 4024a, 4024b, and 4024b, where film deposition or heating is performed. 34a, processing room 4034b, processing room 4034c, processing room 4034d, and processing room 403 It has 4e and .

[0484] Furthermore, each of the multiple processing rooms can perform different processes in parallel. Therefore, A layered structure of different film types can be easily fabricated. Parallel processing is possible in up to [number of processing chambers]. It can be performed as many times as there are units. For example, the apparatus 4000 shown in Figure 33 has seven processing chambers. This is a device that does so. Therefore, using one device (also referred to as in-situ in this specification), The seven film deposition processes can be performed continuously without exposure to the atmosphere.

[0485] On the other hand, in a laminated structure, the number of layers that can be fabricated without opening to the atmosphere is not necessarily equal to the number of processing chambers. They will not be the same. For example, if the desired laminated structure has multiple layers of the same material, Since this layer can be provided in a single processing chamber, the number of layers can be greater than the number of processing chambers installed. A layered structure can be created using multiple layers.

[0486] Furthermore, the atmospheric substrate supply chamber 4010 includes a cassette port 4014 for housing the substrate, and the substrate It is equipped with an alignment port 4016 for performing alignment, and a cassette port. 4014 may be configured to have multiple units (for example, three in Figure 33).

[0487] Furthermore, the atmospheric substrate transport chamber 4012 is connected to the load lock chamber 4020a and the unload lock chamber. It is connected to the loading room 4020b. The transport room 4029 is connected to the load lock room 4020a and the unloading room. Dropping room 4020b, transfer room 4030a, transfer room 4030b, processing room 4024a, and It is connected to processing room 4024b. Transfer room 4030a and transfer room 4030b are transport It is connected to room 4029 and transport room 4039. Also, transport room 4039 is connected to transfer room 40 30a, transfer room 4030b, processing room 4034a, processing room 4034b, processing room 4034c, It is connected to processing rooms 4034d and 4034e.

[0488] Furthermore, a gate valve 4028 or gate valve 4038 is provided at the connection point of each room. With the exception of the atmospheric substrate supply chamber 4010 and the atmospheric substrate transport chamber 4012, each chamber is independent. It can be maintained in a vacuum state. In addition, the atmospheric substrate transport chamber 4012 is a transport robot It has a to 4018. The transport room 4029 has a transport robot 4026, and the transport room 4039 It has a transport robot 4036. Transport robot 4018, transport robot 4026, The transport robot 4036 has multiple movable parts and an arm that holds the substrate, and each room It can transport substrates to the destination.

[0489] The transport room, processing room, load lock room, unload lock room, and transfer room are as described above. The number is not limited to a specific number; the optimal number can be set as needed, depending on the installation space and process conditions. can.

[0490] In particular, when there are multiple transport rooms, there must be two or more transports between one transport room and another transport room. It is preferable to have a transport room. For example, as shown in Figure 33, a transport room 4029 and transport If there is a transport room 4039, a transfer room 4030 is located between the transport room 4029 and the transport room 4039. It is preferable that a and the transfer chamber 4030b are arranged in parallel.

[0491] By arranging transfer chambers 4030a and 4030b in parallel, for example, a transporter The process involves bot 4026 loading the substrate into transfer chamber 4030a, and the transfer robot 4036 moving The process of loading the substrate into the transport room 4030b can be performed simultaneously. The process involves the transport robot 4036 unloading the substrate from the transport chamber 4030b, and the transport robot 4036 then transporting it. The process of unloading substrates from chamber 4030a can be performed simultaneously. By simultaneously driving the feeding robots, production efficiency is improved.

[0492] Furthermore, Figure 33 shows that one transport room has one transport robot and is connected to multiple processes. The following examples have been shown, but the structure is not limited to this one. It may have.

[0493] In addition, one or both of the transport chambers 4029 and 4039 are accessible via a valve. It is connected to a vacuum pump and a cryopump. Therefore, the transport chamber 4029 and transport Chamber 4039 uses a vacuum pump to change the pressure from atmospheric pressure to low or medium vacuum (several hundred Pas or less). After exhausting to approximately 0.1 Pa, switch the valve and use a cryopump to control the center From empty to high vacuum or ultra-high vacuum (0.1 Pa to 1 × 10⁻¹⁶ -7 Exhaust to approximately Pa. It is possible.

[0494] Furthermore, for example, two or more cryopumps may be connected in parallel to a single transport chamber. i. Having multiple cryopumps allows one cryopump to regenerate while However, it is also possible to exhaust using other cryopumps. Note that regeneration refers to the cryopump. This process involves releasing molecules (or atoms) accumulated within an io-pump. (Cryopump) Because accumulating too many molecules (or atoms) reduces exhaust capacity, regular refrigeration is necessary. It would be good to perform energy work.

[0495] Processing room 4024a, processing room 4024b, processing room 4034a, processing room 4034b, processing room Rooms 4034c, 4034d, and 4034e each carry out different processes in parallel. This can be done in a row. In other words, for each processing room, the substrate installed can be subjected to the sputtering method, C Film deposition treatment, heat treatment, or plastic film deposition treatment by methods such as VD, MBE, PLD, and ALD. Plasma treatment can be performed. In addition, heat treatment or plasma treatment can be performed in the treatment chamber. After this, a film deposition process may be performed.

[0496] The apparatus 4000 has multiple processing chambers, which allows the substrate to be exposed to the atmosphere between processing steps. Because it can be transported without any issues, the adsorption of impurities onto the substrate can be suppressed. Each processing chamber can perform different types of film deposition, heat treatment, or plasma treatment. Therefore, the sequence of processes such as film deposition and heat treatment can be freely constructed.

[0497] Each processing chamber may be connected to a vacuum pump via a valve. For example, a dry pump and a mechanical booster pump can be used.

[0498] Furthermore, each processing chamber may be connected to a power supply capable of generating plasma. For power sources, you can provide DC power, AC power, and high-frequency (RF, microwave, etc.) power supplies. Alternatively, a pulse generator may be connected to the DC power supply.

[0499] Furthermore, the processing chamber may be connected to the gas purification device via a gas supply device. The supply and gas purification devices should be provided in quantities equal to the number of gas types.

[0500] For example, when performing film deposition by sputtering in a processing room, the processing room is a target And, a backing plate connected to the target, and via the backing plate, The device may also include a cathode positioned opposite the get, a protective plate, and a circuit board stage. Furthermore, for example, the substrate stage includes a substrate holding mechanism to hold the substrate, and a mechanism to heat the substrate from the back side. It may also be equipped with a heater on the back.

[0501] The substrate stage is held in a position approximately perpendicular to the floor during film deposition, and is used for substrate transfer. Sometimes it is held in a roughly horizontal position relative to the floor. Here, the substrate stage is held in a roughly horizontal position relative to the floor. By making it nearly vertical, the probability of dust or particles that may be introduced during film formation adhering to the substrate is reduced. This can be suppressed more effectively than maintaining a horizontal position. However, if the substrate stage is not relative to the floor surface... If held in a vertical (90°) position, the substrate may fall, therefore, the substrate stage The angle with respect to the floor surface is preferably 80° or more and less than 90°.

[0502] Note that the configuration of the substrate stage is not limited to the above configuration. For example, the substrate stage The configuration may be such that it is roughly horizontal to the floor surface. In this configuration, the board stage is The target should be placed below, and the circuit board should be placed between the target and the board stage. Furthermore, the board stage includes a jig to secure the board so that it does not fall, or a mechanism to secure the board. It may also be equipped with a mechanism for determining this.

[0503] Furthermore, by equipping the processing chamber with an anti-adhesion plate, particles sputtered from the target are prevented from being... It can suppress the accumulation of spatter in critical areas. In addition, the anti-adhesion plate prevents the accumulation of spatter. It is desirable to process the material in a way that prevents the ring particles from peeling off. For example, increasing the surface roughness The surface of the protective plate may be subjected to blast treatment or have irregularities created on it.

[0504] The backing plate has the function of holding the target, and the cathode is connected to the target. It has the function of applying voltage (for example, negative voltage).

[0505] The target can be a conductor, an insulator, or a semiconductor. For example, When the target is an oxide semiconductor such as a metal oxide, the oxide semiconductor film is deposited in a processing chamber. This is possible. Also, even when the target is a metal oxide, nitrogen can be used as the film-forming gas. Using elementary gases, it is also possible to form oxididine nitride semiconductor films.

[0506] Furthermore, each processing chamber may be connected to a gas supply device via a gas heating mechanism. The structure is connected to the gas purification device via a gas supply device. The gas introduced into the processing chamber has a dew point. The temperature is -80°C or lower, preferably -100°C or lower, and more preferably -120°C or lower. Gases such as oxygen, nitrogen, and noble gases (argon, etc.) can be used. ) can be used. In addition, the gas heating mechanism raises the temperature of the gas introduced into the processing chamber to 40°C. It can be heated to a temperature of 400°C or lower, preferably between 50°C and 200°C. The gas heating mechanism, gas supply device, and gas purification device should be provided in equal numbers to the number of gas types.

[0507] Furthermore, each processing chamber may be connected to a turbomolecular pump and a vacuum pump via valves. Furthermore, a cryotrap may be installed in each processing room.

[0508] Furthermore, cryotraps adsorb molecules (or atoms) with relatively high melting points, such as water. It is a mechanism that can do this. Turbomolecular pumps stabilize large molecules (or atoms). It exhausts gases and requires infrequent maintenance, resulting in excellent productivity, but also producing hydrogen and water emissions. Its capacity is low. Therefore, a cryotrap is used to improve the exhaust capacity for water and other liquids. This is possible. The temperature of the cryotrap's refrigerator should be 100K or less, preferably 80K or less. In addition, if the cryotrap has multiple refrigerators, the temperature can be changed for each refrigerator. This is preferable because it allows for efficient exhaust. For example, the temperature of the first stage refrigerator The temperature of the first stage refrigerator should be set to 100K or less, and the temperature of the second stage refrigerator should be set to 20K or less.

[0509] Furthermore, the exhaust method for the processing chamber is not limited to this, and the exhaust method shown for the connected transport chamber (kura The exhaust method for the ion pump and vacuum pump may be the same as the configuration used. The method may be configured similarly to that of the processing chamber (exhaust method using a turbomolecular pump and a vacuum pump). .

[0510] In particular, as an exhaust method for the processing chamber in which oxide semiconductor films are deposited, a vacuum pump and cryo It may also be configured in combination with wrap. It is provided in a processing chamber for forming oxide semiconductor films. The exhaust method is preferably one that has the function of adsorbing at least water molecules. .

[0511] Furthermore, the processing chamber for depositing oxide semiconductor films has a partial pressure of hydrogen molecules of 1 × 10⁻⁶. -2 Below Pa Yes, and the partial pressure of water molecules is 1 × 10⁻⁶ -4 It is preferable that the pressure is Pa or less. The pressure in the standby state of the processing chamber for forming body membranes is 8.0 × 10⁻⁶ -5 Pa or less, preferably less than or equal to Pa. 5.0×10 -5 Pa or less, more preferably 1.0 × 10 -5 It is less than or equal to Pa. The partial pressure values ​​for hydrogen molecules and water molecules mentioned above are based on the sputtering process. These are the values ​​for both when the laboratory is in standby mode and when it is in the deposition state (plasma discharge state). ru.

[0512] The total pressure and partial pressure of the processing chamber can be measured using a mass spectrometer. For example, Qulee, a quadrupole mass spectrometer (also known as Q-mass) manufactured by ULVAC, Inc. You should use CGM-051.

[0513] The partial pressure of hydrogen molecules, the partial pressure of water molecules, and the pressure in the standby state of the processing chamber are within the above range. This makes it possible to lower the concentration of impurities in the oxide semiconductor film that is formed. .

[0514] In particular, by using each processing chamber for film deposition by sputtering, the aforementioned practical A part of the configuration of transistor 200 shown in the example is formed by continuous in-situ deposition of a film. It can be fabricated using a layered structure.

[0515] In the method for fabricating transistor 200, insulator 212, insulator 214, and insulating Body 216 is continuously deposited using apparatus 4000. Also, oxide film 230A, oxide film 230 B and oxide film 243A are continuously deposited using apparatus 4000. Also, conductive film 242 A, insulating film 271A, and conductive film 248A are continuously deposited using apparatus 4000.

[0516] In other words, the insulators 212, 214, and 216 are connected without being exposed to the atmosphere. The films can be formed in succession. Also, oxide film 230A, oxide film 230B, and oxide film 2 43A can be continuously deposited without venting to the atmosphere. Also, conductive film 242A, The insulating film 271A and the conductive film 248A can be deposited continuously without exposure to the atmosphere. can.

[0517] By adopting the above configuration, impurities (typically water, hydrogen, etc.) are thoroughly eliminated from the layered structure. It becomes possible to form a film. Furthermore, since each interface of the above-mentioned laminated film is not exposed to the atmosphere, The concentration of impurities is reduced.

[0518] Furthermore, for example, when heat treatment is performed in a processing chamber, the processing chamber can accommodate the substrate. It may be equipped with multiple heating stages. The heating stages may also be configured in a multi-stage configuration. By increasing the number of heating stages, multiple substrates can be heated simultaneously, thus improving productivity. It can be improved.

[0519] Heating mechanisms that can be used in the processing chamber include, for example, heating using a resistance heating element. This may be used as a heating mechanism. Alternatively, heat conduction or heat radiation from a heated medium such as a gas may be used. A heating mechanism that heats by injection may also be used. For example, GRTA (Gas Rapid Thermal Anneal), LRTA(Lamp Rapid Thermal Using RTA (Rapid Thermal Anneal) such as Anneal LRTA can do this. LRTA can handle halogen lamps, metal halide lamps, and xenon arc lamps. Lamps such as carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps emit light. The object to be processed is heated by the radiation of light (electromagnetic waves). GRTA uses high-temperature gas Heat treatment is performed. An inert gas is used as the heat treatment gas.

[0520] The load lock chamber 4020a is a substrate transfer stage and a back surface heating chamber for substrates. It may be equipped with a heater or the like. The load lock chamber 4020a is a reduced pressure chamber that goes from a reduced pressure state to atmospheric pressure. The force is increased, and when the pressure in the load lock chamber 4020a becomes atmospheric pressure, the substrate is transported to the atmosphere side. The board transfer stage receives the board from the transport robot 4018 located in room 4012. Remove. Then, the load lock chamber 4020a is evacuated and reduced in pressure, and then the transport chamber The transport robot 4026 located at 4029 receives the circuit board from the circuit board transfer stage. take.

[0521] Furthermore, the load lock chamber 4020a is connected to a vacuum pump and a cryo-pump via a valve. It is connected to the load lock chamber 4020. The same configuration as in (a) should be used.

[0522] The atmospheric substrate transport chamber 4012 has a transport robot 4018, therefore the transport robot 40 18 allows for the transfer of the circuit board between the cassette port 4014 and the load lock chamber 4020a. This can be done. Also, the atmospheric substrate transport chamber 4012 and the atmospheric substrate supply chamber 4010 A HEPA filter (High Efficiency Particulate Filter) is located above it. Mechanisms to suppress the ingress of dust or particles, such as an air filter. It may be provided. Furthermore, the cassette port 4014 can accommodate multiple circuit boards.

[0523] Using the above apparatus 4000, insulating films, semiconductor films, and conductive films are processed without exposure to the atmosphere. By continuously depositing the film, the incorporation of impurities into the semiconductor film can be effectively suppressed.

[0524] As described above, by using the apparatus according to one aspect of the present invention, a laminated structure having a semiconductor film can be continuously formed. It can be fabricated by film. Therefore, hydrogen, water, and other impurities incorporated into the semiconductor film are not incorporated. This method allows for the fabrication of semiconductor films that suppress pure substances and have a low defect level density.

[0525] The configurations and methods shown in this embodiment are not the same as those shown in other embodiments or examples. It can be used in appropriate combinations with the above.

[0526] (Embodiment 5) In this embodiment, the present invention is described using Figures 34A, 34B, and 35A to 35H. A transistor using an oxide as a semiconductor, according to one aspect of this invention (hereinafter referred to as an OS transistor) In some cases, ), and storage devices to which capacitive elements are applied (hereinafter referred to as OS memory devices) This may be the case.) The OS memory device has at least a capacitive element and a capacitive element This is a memory device that has an OS transistor that controls the charging and discharging of the device. Because the current is extremely small, the OS memory device has excellent retention characteristics and is a non-volatile memory. It can be made to function.

[0527] <Example of a storage device configuration> Figure 34A shows an example of the configuration of the OS memory device. The storage device 1400 is connected to peripheral circuit 141 1, and a memory cell array 1470. Peripheral circuit 1411 is a row circuit 1420, It has a column circuit 1430, an output circuit 1440, and a control logic circuit 1460. .

[0528] The column circuit 1430 includes, for example, a column decoder, a pre-charge circuit, a sense amplifier, and a programming circuit. It has circuits, etc. The precharge circuit has the function of precharging the wiring. The amplifier has the function of amplifying the data signal read from the memory cell. The lines are wiring connected to memory cells in the memory cell array 1470, and more details The details will be explained later. The amplified data signal is sent via the output circuit 1440 to the data signal RDA. It is output to the outside of the storage device 1400 as TA. Also, the row circuit 1420 is, for example, row It has a decoder, a word line driver circuit, etc., and can select the row to access.

[0529] The storage device 1400 receives a low power supply voltage (VSS) from an external source as the power supply voltage, and peripheral circuits 14 The high power supply voltage (VDD) for 11 and the high power supply voltage (VIL) for the memory cell array 1470 are It is supplied. In addition, the storage device 1400 contains control signals (CE, WE, RE) and address signals. The address signal ADDR and the data signal WDATA are input from an external source. The address signal ADDR is the line The data signal WDATA is input to the decoder and column decoder, and then input to the writing circuit. ru.

[0530] The control logic circuit 1460 receives externally input control signals (CE, WE, R Process E) to generate control signals for the row decoder and column decoder. The control signal CE is a chip The write enable signal is the control signal R E is the read enable signal. The signal processed by the control logic circuit 1460 The signal is not limited to this; other control signals can be input as needed.

[0531] The memory cell array 1470 consists of multiple memory cells MC arranged in a matrix, and multiple It has the wiring. Note that the wiring connecting the memory cell array 1470 and the row circuit 1420 The number of lines is determined by the configuration of the memory cell MC, the number of memory cell MCs in a single row, and other factors. Also, the number of wires connecting the memory cell array 1470 and the column circuit 1430 is noted. This is determined by factors such as the configuration of the recell MC and the number of memory cell MCs in each row.

[0532] In Figure 34A, the peripheral circuit 1411 and the memory cell array 1470 are on the same plane. Although examples of how to form it have been shown, this embodiment is not limited to this. For example, As shown in Figure 34B, the memory cell array 1470 is superimposed on a portion of the peripheral circuit 1411. It may be provided in such a way. For example, so as to overlap below the memory cell array 1470, A configuration that includes a sense amplifier is also possible.

[0533] Figures 35A to 35H show examples of memory cell configurations applicable to the above-mentioned memory cell MC. I will explain.

[0534] [DOSRAM] Figures 35A to 35C show examples of the circuit configuration of a DRAM memory cell. And, DRAM using a 1OS transistor 1 capacitance element type memory cell is called DOSRAM. (Dynamic Oxide Semiconductor Random Acce. It is sometimes called ss Memory. As shown in Figure 35A, memory cell 1471 is a tra It has a transistor M1 and a capacitive element CA. Note that the transistor M1 has a gate (top It has a front gate (sometimes called a back gate) and a back gate.

[0535] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, and transistor M The second terminal of 1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. Next, the back gate of transistor M1 is connected to wiring BGL. Capacitive element C The second terminal of A is connected to wiring CAL.

[0536] Wiring BIL functions as a bit line, and wiring WOL functions as a word line. CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. During data writing and reading, a low-level potential is applied to the wiring CAL. It is preferable to do so. Wiring BGL is used to apply potential to the back gate of transistor M1. It functions as wiring. By applying an arbitrary potential to wiring BGL, the transistor The threshold voltage of M1 can be increased or decreased.

[0537] Furthermore, the memory cell MC is not limited to memory cell 1471, and the circuit configuration can be changed. This is possible. For example, a memory cell MC can be a memory cell 1472 as shown in Figure 35B. The back gate of transistor M1 is connected to the WOL wiring instead of the BGL wiring. It is also possible to do so. For example, the memory cell MC is like the memory cell 1473 shown in Figure 35C. In addition, a single-gate transistor, that is, a transistor without a back gate, M It may also be a memory cell composed of 1.

[0538] When the semiconductor device shown in the above embodiment is used as a memory cell 1471, etc., a transistor Transistor 200 is used as M1, and capacitive element 100 is used as capacitive element CA. This can be done. By using an OS transistor as transistor M1, the transistor The leakage current of the M1 can be made very small. In other words, the written data can be transmitted via Because it can be retained for a long time by the M1 converter, the frequency of memory cell refresh is reduced. The degree can be reduced. Also, it eliminates the need for memory cell refresh operations. Yes, it is possible. Also, because the leakage current is very small, memory cell 1471 and memory cell 147 2. The memory cell 1473 can hold multi-level data or analog data. ru.

[0539] Furthermore, in DOSRAM, as described above, overlaps below the memory cell array 1470 As shown, by using a configuration that includes a sense amplifier, the bit line can be shortened. This reduces the bit line capacitance and thus the memory cell retention capacity.

[0540] [NOSRAM] Figures 35D to 35G show the rotation of a gain cell type memory cell with two transistors and one capacitance element. An example of a circuit configuration is shown. As shown in Figure 35D, the memory cell 1474 is connected to transistor M2 and It has a transistor M3 and a capacitive element CB. Note that transistor M2 is the top gate ( It is sometimes simply called a gate, and has a back gate. In this specification, etc., A memory device having a gain cell type memory cell using an OS transistor in the transistor M2. , NOSRAM(Nonvolatile Oxide Semiconductor It is sometimes referred to as RAM.

[0541] The first terminal of transistor M2 is connected to the first terminal of the capacitive element CB, and transistor M The second terminal of 2 is connected to the wiring WBL, and the gate of transistor M2 is connected to the wiring WOL. Next, the back gate of transistor M2 is connected to wiring BGL. Capacitive element C The second terminal of B is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring R. The second terminal of transistor M3 is connected to BL, and the wiring SL is connected to transistor M The gate of 3 is connected to the first terminal of the capacitive element CB.

[0542] Wiring WBL functions as the write bit line, and wiring RBL functions as the read bit line. The wiring WOL functions as a word line. The wiring CAL is the second of the capacitive element CB. It functions as wiring to apply a predetermined potential to the terminal. When writing data, data retention During the process, when reading data, a low-level potential is applied to the wiring CAL. Preferred. Wiring BGL is wiring for applying potential to the back gate of transistor M2. It functions as follows: By applying an arbitrary potential to the wiring BGL, the transistor M2 The threshold voltage can be increased or decreased.

[0543] Here, the memory cell 1474 shown in Figure 35D corresponds to the storage device shown in Figure 37. In other words, transistor M2 becomes transistor 200, and capacitive element CB becomes capacitive element 100. Transistor M3 is connected to transistor 300, wiring WBL is connected to wiring 1003, wiring WOL Wire BGL goes to wire 1006, wire CAL goes to wire 1005, wire R BL corresponds to wiring 1002, and wiring SL corresponds to wiring 1001.

[0544] Furthermore, the memory cell MC is not limited to memory cell 1474, and the circuit configuration can be changed as appropriate. This is possible. For example, the memory cell MC is like the memory cell 1475 shown in Figure 35E. In this configuration, the back gate of transistor M2 is connected to the WOL wiring instead of the BGL wiring. It may also be made into a memory cell MC, as shown in Figure 35F, memory cell 1476 As shown above, a single-gate transistor, that is, a transistor without a back gate A memory cell composed of sta M2 may also be used. Furthermore, for example, the memory cell MC is shown in Figure 3. As shown in memory cell 1477 in 5G, the wiring WBL and wiring RBL are combined into a single wiring BIL. It would also be acceptable to use a structure that summarizes the information in this way.

[0545] When the semiconductor device shown in the above embodiment is used as a memory cell 1474, etc., a transistor Transistor 200 is used as M2, and transistor 300 is used as transistor M3. Capacitive element 100 can be used as the capacitive element CB. Transistor M2 By using an OS transistor, the leakage current of transistor M2 is made very small. This allows the written data to be stored for a long time by transistor M2. Because it can maintain this, the frequency of refreshing the memory cells can be reduced. Furthermore, it eliminates the need for memory cell refresh operations. Also, leakage current is non Because it is always small, the memory cell 1474 can store multi-level data or analog data. This is possible. The same applies to memory cells 1475 to 1477.

[0546] Note that transistor M3 is a transistor having silicon in the channel formation region (hereinafter (Sometimes called Si transistors) The conductivity type of Si transistor is It may be an n-channel type or a p-channel type. Si transistors are OS transistors In some cases, the field-effect mobility is higher than that of a transistor. Therefore, readout transistor A Si transistor may be used as transistor M3, which functions as a transistor. By using a Si transistor for transistor M3, a transistor can be stacked on top of transistor M3. Because a converter M2 can be installed, the occupied area of ​​the memory cell is reduced, and the storage device is high It is possible to integrate the resources.

[0547] Also, transistor M3 may be an OS transistor. Transistor M2 and When an OS transistor is used for transistor M3, the memory cell array 1470 is an n-type A circuit can be constructed using only transistors.

[0548] Figure 35H also shows an example of a gain cell type memory cell with 3 transistors and 1 capacitance element. The memory cell 1478 shown in Figure 35H consists of transistors M4 to M6, and It has a capacitive element CC. The capacitive element CC is provided as appropriate. The memory cell 1478 is wired Electrically connected to BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. The wiring GNDL is a wiring that provides a low level potential. Note that memory cell 1478 Alternatively, instead of wiring BIL, electrical connections may be made to wiring RBL and wiring WBL.

[0549] Transistor M4 is an OS transistor with a back gate, and the back gate is It is electrically connected to wiring BGL. Note that the back gate and gate of transistor M4 They may be electrically connected to each other. Alternatively, transistor M4 may have a back gate. It's not necessary.

[0550] Note that transistors M5 and M6 are n-channel type Si transistors. A t-channel or p-channel Si transistor may also be used. Alternatively, transistor M4 or a trans-transistor may be used. The ZISTA M6 can also be an OS transistor. In this case, the memory cell array 1470 is an n-type transistor. A circuit can be constructed using only transistors.

[0551] When the semiconductor device shown in the above embodiment is used as the memory cell 1478, transistor M Transistor 200 is used as 4, and transistors M5 and M6 are trans Using the ZISTA 300, the capacitive element 100 can be used as the capacitive element CC. By using an OS transistor as transistor M4, the leakage current of transistor M4 is reduced. The flow can be made very small.

[0552] The configuration of the peripheral circuit 1411, memory cell array 1470, etc., as shown in this embodiment is , but not limited to, these circuits, and the wiring connected to them. The arrangement or function of path elements, etc., may be changed, deleted, or added as necessary.

[0553] Generally, semiconductor devices such as computers use various types of storage devices (memory) depending on the application. This is used. Figure 36 shows various storage devices in order of hierarchy. Storage devices located in the upper layers are Extremely fast access speeds are required, and lower-level memory devices have larger storage capacities and higher recording capabilities. The density can be determined. In Figure 36, starting from the top layer, the arithmetic processing units such as the CPU have registers. Memory that is mixed in as such, SRAM (Static Random Access Memory) mory), DRAM (Dynamic Random Access Memory) This indicates 3D NAND memory.

[0554] Memory embedded as registers in processing units such as CPUs is used for temporary storage of calculation results. Because it is used in such applications, it is frequently accessed by the processing unit. Therefore, rather than memory capacity... Fast operating speed is required. Also, registers hold configuration information for the arithmetic processing unit. It also has functions.

[0555] SRAM is used, for example, as a cache. The cache is held in main memory. It has the function of duplicating and storing some of the information it holds. Frequently used data is cached. By creating a copy, you can increase the speed of data access.

[0556] DRAM is used, for example, in main memory. Main memory reads from storage. It has the function of retaining the programs and data that are released. The recording density of DRAM is approximately 0.1~0.3Gbit / mm 2 That is the case.

[0557] 3D NAND memory is used, for example, in storage. Storage is for long-term storage. It has the function of holding necessary data and various programs used by the processing unit. Therefore, storage requires a large storage capacity and high recording density rather than just high operating speed. The recording density of storage devices used for storage is approximately 0.6 to 6.0 Gbit / m². m 2 That is the case.

[0558] A storage device according to one aspect of the present invention has a high operating speed and can retain data for a long period of time. A storage device according to one aspect of the invention has a hierarchy in which the cache is located and a hierarchy in which the main memory is located. It can be suitably used as a storage device located in the boundary region 901 which includes both. A storage device according to one aspect of the present invention comprises a hierarchical layer in which the main memory is located and a hierarchical layer in which the storage is located. It can be suitably used as a storage device located in the boundary region 902 which includes both of the above.

[0559] The configuration shown in this embodiment can be appropriately combined with the configurations shown in other embodiments or examples. It can be used.

[0560] (Embodiment 6) In this embodiment, the semiconductor device of the present invention is mounted using Figures 37A and 37B. An example of chip 1200 is shown. Multiple circuits (systems) are mounted on chip 1200. This technology, which integrates multiple circuits (systems) onto a single chip, is called sys. It is sometimes called a System on Chip (SoC).

[0561] As shown in Figure 37A, the chip 1200 consists of a CPU 1211, a GPU 1212, and It consists of multiple analog processing units 1213, one or more memory controllers 1214, and It has multiple interfaces 12...

Claims

[Claim 1] A first insulator is formed into a film, An island-shaped laminate is formed on the first insulator by sequentially stacking a first oxide, a second oxide, and a first conductor. A second insulator is formed on the first insulator and the laminate. An opening is formed in the second insulator to expose the laminate, By removing the region exposed within the opening of the first conductor, the upper surface of the second oxide is exposed, and after forming the second conductor and the third conductor disposed on the second oxide, a cleaning process is performed. A first oxide film is formed in contact with the side surface of the first oxide and the upper and side surfaces of the second oxide, which are exposed within the opening. After adding oxygen to the vicinity of the interface between the second oxide and the first oxide film via the first oxide film, a heat treatment is performed. A method for manufacturing a semiconductor device, comprising: forming a first insulating film and a first conductive film on the first oxide film; then removing a portion of the first conductive film, the first insulating film, the first oxide film, and the second insulator by chemical polishing to expose the second insulator; and forming a fourth conductor, a third insulator, and a third oxide within an opening provided in the second insulator.

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