Memory device

Abstract

This provides a memory device that enables stable read operations across multiple planes. [Solution] The memory device 100 has multiple address signals and multiple frequency divider clock signals CKD <n:1>Based on this, multiple instruction codes RINST <n:1>An instruction memory 600 is configured to output signals with a predetermined time difference, and multiple memory regions are linked to each other, and multiple frequency divider clock signals CKD <n:1>Based on each of these, each of the multiple address signals is provided to the instruction memory 600, and multiple instruction codes RINST <n:1>This may include a plurality of microcontrol units MCU1 to MCUn, each configured to perform an action according to the instruction code corresponding to itself.< / n:1>

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a memory device capable of sharing an instruction memory.

Background Art

[0002] A general memory device includes a plurality of memory regions, for example, a plurality of planes, a micro control unit for controlling the plurality of planes, and an instruction memory for storing instruction codes related to control operations. The memory device supports a Plane Interleave Read (PIR) mode for interleaved read operations on the plurality of planes.

[0003] However, due to high integration, a general memory device has spatial constraints due to the layout and wiring for connection between the plurality of planes, the micro control unit, and the instruction memory, and there is a problem that the peak current increases due to the plane interleave read mode. In addition, there is a problem that the area increases due to a large number of instruction memories, and the probability of occurrence of defects proportional to the number of instruction memories increases, resulting in a decrease in yield.

Summary of the Invention

Problems to be Solved by the Invention

[0004] An embodiment of the present invention aims to provide a memory device that reduces the circuit area and enables stable read operations on a plurality of planes at the same time.

Means for Solving the Problems

[0005] Embodiments of the present invention may include an instruction memory configured such that a plurality of instruction codes are output with a predetermined time difference based on a plurality of address signals and a plurality of frequency divider clock signals, and a plurality of microcontrol units, each connected to a plurality of memory areas, which are configured to provide each of the plurality of address signals to the instruction memory based on each of the plurality of frequency divider clock signals and to perform an operation according to the instruction code corresponding to themselves among the plurality of instruction codes.

[0006] Embodiments of the present invention may include a plurality of planes, an input / output pad section including a plurality of pads, a data input / output circuit connected to the input / output pad section, an instruction memory configured to output a plurality of instruction codes with a predetermined time difference based on a plurality of address signals and a plurality of frequency divider clock signals, and a plurality of memory operation control related circuits that are commonly connected to the data input / output circuit, connected one-to-one with the plurality of planes, and configured to provide each of the plurality of address signals to the instruction memory based on each of the plurality of frequency divider clock signals, and to perform an operation according to the instruction code corresponding to itself among the plurality of instruction codes. [Effects of the Invention]

[0007] This technology can reduce circuit area and current consumption, thereby improving system efficiency and reliability. [Brief explanation of the drawing]

[0008] [Figure 1] This figure shows the configuration of a data storage device according to an embodiment of the present invention. [Figure 2] This figure shows the configuration of a memory device according to an embodiment of the present invention. [Figure 3] This diagram shows the configuration of the first plane and peripheral circuits in Figure 2. [Figure 4] This diagram shows the configuration of the memory operation control-related circuitry. [Figure 5] This figure shows the operation of a memory device according to an embodiment of the present invention. [Figure 6]This figure shows the configuration of a memory device according to another embodiment of the present invention. [Figure 7] This diagram shows the configuration of the memory operation control-related circuitry. [Figure 8] This diagram shows the configuration of the frequency divider circuit shown in Figure 6. [Figure 9] This diagram shows the operation of the frequency divider circuit shown in Figure 8. [Figure 10] This diagram shows the operation of the frequency divider circuit shown in Figure 8. [Figure 11] This diagram shows the configuration of the instruction memory shown in Figure 6. [Figure 12] This diagram shows the configuration of the memory core shown in Figure 11. [Figure 13] This figure shows the configuration of the output control circuit shown in Figure 11. [Figure 14] This diagram shows the configuration of the instruction output circuit shown in Figure 11. [Figure 15] This diagram shows the configuration of the control signal generation circuit shown in Figure 11. [Figure 16] This diagram shows the operation of the control clock generation circuit in Figure 15. [Figure 17] This diagram shows the operation of the control clock generation circuit in Figure 15. [Figure 18] This diagram shows the operation of the control signal generation unit in Figure 15. [Figure 19] This diagram shows the operation of the control signal generation unit in Figure 15. [Figure 20] This figure shows the operation of a memory device according to another embodiment of the present invention. [Modes for carrying out the invention]

[0009] The embodiments of the present invention will be described in more detail below with reference to the attached drawings.

[0010] Figure 1 shows the configuration of a data storage device 1 according to an embodiment of the present invention.

[0011] Referring to FIG. 1, the data storage device 1 can be connected to the host 2. The data storage device 1 can perform transmission / reception of data (DATA) to / from the host 2 according to an instruction (CMDe) provided from the host 2. The data storage device 1 can include a memory device 1-1 and a controller 1-2.

[0012] The memory device 1-1 can include a plurality of logic units (LU0 to LUn). A logic unit (LU) can be a unit for dividing and managing all memory areas of the data storage device 1. Each of the plurality of logic units (LU0 to LUn) can include at least one memory chip.

[0013] The controller 1-2 can generate a plurality of control signals (CTRLs) and an instruction (CMDi) according to an instruction (CMDe) and provide them to the memory device 1-1. The controller 1-2 can perform transmission / reception of data (DATA) to / from the memory device 1-1 through read and write operations. The plurality of control signals (CTRLs) can include a clock signal, signals related to activation of the memory chip, read, and write operations.

[0014] FIG. 2 is a diagram showing the configuration of a memory device 10 according to an embodiment of the present invention.

[0015] Referring to FIG. 2, the memory device 10 can include a plurality of memory areas, for example, a plurality of planes (PL1 to PLn), a plurality of memory operation control related circuits 11-1 to 11-n, an input / output pad section 12, and a data input / output circuit 13.

[0016] Each of the plurality of planes (PL1 to PLn) includes a memory cell array, and the plurality of memory cells constituting the memory cell array can include non-volatile memory cells.

[0017] The input / output pad section 12 can include a plurality of pads 12-1 for receiving an instruction (CMDi), a clock signal (CKL), and an address, and inputting and outputting data (DQ).

[0018] The data input / output circuit 13 is commonly connected between multiple memory operation control-related circuits 11-1 to 11-n and the input / output pad section 12, enabling it to perform data input and output.

[0019] Multiple memory operation control related circuits 11-1 to 11-n can be connected between multiple planes (PL1 to PLn) and data input / output circuits 13. Multiple memory operation control related circuits 11-1 to 11-n can be connected one-to-one with multiple planes (PL1 to PLn). For example, the first memory operation control related circuit 11-1 is connected between the first plane (PL1) and the data input / output circuit 13, the second memory operation control related circuit 11-2 is connected between the second plane (PL2) and the data input / output circuit 13, and the nth memory operation control related circuit 11-n is connected between the nth plane (PLn) and the data input / output circuit 13.

[0020] Multiple memory operation control related circuits 11-1 to 11-n can be configured similarly to one another. For example, the first memory operation control related circuit 11-1 may include an instruction memory (ISTM), a microcontroller (MCU), and peripheral circuits (PER). The instruction memory (ISTM) stores multiple pieces of data (hereinafter referred to as instruction data) related to the operation of the memory device 10, and can output at least one instruction data corresponding to external access from among the stored instruction data as an instruction code. The instruction memory (ISTM) may consist of a ROM (Read-only memory).

[0021] The instruction data includes information for instructing the operation of the memory device 10, that is, the operation of the circuit related to program / erase / read, etc. The instruction data consists of data stored in multiple planes (PL1 to PLn) and independent information.

[0022] The peripheral circuitry (PER) may include data input / output related circuits of the first plane (PL1), i.e., circuit configurations for controlling program, read, and erase operations. The microcontroller (MCU) can control the operation of the peripheral circuitry (PER) based on the result of decoding the instruction code provided from the instruction memory (ISTM).

[0023] Figure 3 shows the configuration of the first plane (PL1) and peripheral circuitry (PER) in Figure 2.

[0024] Referring to Figure 3, the peripheral circuit (PER) may include an address decoder 51, a voltage generator 52, and a read and write circuit 53. The read and write circuit 53 may include a plurality of page buffers (PB1 to PBm). The peripheral circuit (PER) is connected to the first plane (PL1) and can drive the first plane (PL1) to perform program, read, and erase operations.

[0025] The first plane (PL1) includes a memory cell array and can be connected to an address decoder 51 via a word line (WL) and to read and write circuits 53 via multiple bit lines (BL1~BLm). The first plane (PL1) can include multiple memory blocks (BLK1~BLKz). The multiple memory blocks (BLK1~BLKz) can be connected to the address decoder 51 via a word line (WL). The multiple memory blocks (BLK1~BLKz) can be connected to read and write circuits 53 via multiple bit lines (BL1~BLm). Each of the multiple memory blocks (BLK1~BLKz) contains multiple memory cells. The multiple memory cells may be non-volatile memory cells. The multiple memory blocks (BLK1~BLKz) can include multiple pages. Among the multiple memory cells, memory cells connected to the same word line can be defined as a single page.

[0026] The address decoder 51 can be connected to the first plane (PL1) via a word line (WL). Based on the result of decoding an address provided from outside the memory device 10, the address decoder 51 can select at least one memory block from a plurality of memory blocks (BLK1 to BLKz). The address decoder 51 can select at least one word line (WL) of the selected memory block by applying a voltage provided by the voltage generation unit 52 to at least one word line (WL) of the selected memory block. The address decoder 51 can perform a program operation by applying a program voltage to the selected word line and a path voltage lower than the program voltage to the word lines that are not selected. The address decoder 51 can perform a read operation by applying a read voltage to the selected word line and a path voltage higher than the read voltage to the word lines that are not selected. The address decoder 51 can perform an erase operation by applying a ground voltage to the word line connected to the selected memory block and an erase voltage to the bulk area where the selected memory block is formed.

[0027] The voltage generation unit 52 can generate various voltages necessary for the operation of the memory device 10, such as read voltage, pass voltage, program voltage, and erase voltage, and provide them to the address decoder 51.

[0028] Multiple page buffers (PB1 to PBm) can be connected to the first plane (PL1) via the first to mth bit lines (BL1 to BLm). Multiple page buffers (PB1 to PBm) can perform data communication with the data input / output circuit 13.

[0029] Figure 4 shows the configuration of the memory operation control-related circuits 11-1 to 11-n in Figure 2.

[0030] Referring to Figure 4, the first memory operation control related circuit 11-1 connected to the first plane (PL1) may include an instruction memory (ISTM) 20-1, a microcontroller (MCU) 30-1, and a peripheral circuit (PER) 40-1.

[0031] The peripheral circuit 40-1 may include the configuration described based on Figure 3. The peripheral circuit 40-1 may further include logic circuits for controlling the operation of the configuration described based on Figure 3.

[0032] The instruction memory 20-1 receives the clock signal (CKL) and the address signal (RMADD1 <n-1:0>It can receive input (RINST1) and output instruction code (RINST1). Instruction memory 20-1 can store instruction data related to various functions of peripheral circuit 40-1. Based on the clock signal (CKL), instruction memory 20-1 selects from among multiple instruction data, the address signal (RMADD1 <n-1:0>The instruction data corresponding to ) can be output as an instruction code (RINST1).

[0033] The microcontrol unit 30-1 can control the peripheral circuit 40-1 based on the clock signal (CKL) and instruction code (RINST1). The microcontrol unit 30-1 may include a fetch register (FTR) 31-1, a decoder (DEC) 32-1, an execution register (EXR) 33-1, a program counter (PGMCNT) 34-1, an address register (ADDR) 35-1, and an instruction processing logic (CPL) 36-1.

[0034] The fetch register 31-1 can store the instruction code (RINST1) based on the clock signal (CKL). The decoder 32-1 can output the result of decoding the instruction code (RINST1) stored in the fetch register 31-1. The execution register 33-1 can store the output of the decoder 32-1 based on the clock signal (CKL) and provide it to the peripheral circuit 40-1. The output of the execution register 33-1 can selectively control the logic circuit of the peripheral circuit 40-1. The program counter 34-1 can change the value of the internal address (ADD-INT1) based on the output of the decoder 32-1. The address register 35-1 can receive the internal address (ADD-INT1) changed by the program counter 34-1 and output the address signal (RMADD1) based on the clock signal (CKL). <n-1:0>It can be saved as a value and provided to the instruction memory 20-1. The instruction processing logic 36-1 can control the program counter 34-1 by instruction (CMDi).

[0035] The nth memory operation control related circuit 11-n, which is connected to the nth plane (PLn), may include an instruction memory 20-n, a microcontroller unit (MCU) 30-n, and a peripheral circuit (PER) 40-n.

[0036] Peripheral circuit 40-n can be configured in the same way as peripheral circuit 40-1.

[0037] The instruction memory 20-n receives the clock signal (CKL) and the address signal (RMADDn <n-1:0>It can receive input from ) and output an instruction code (RINSTn). Instruction memory 20-n stores instruction data similar to instruction memory 20-1 and, based on the clock signal (CKL), outputs an address signal (RMADDn <n-1:0>The instruction data corresponding to ) can be output as an instruction code (RINSTn). Instruction memory 20-n can be configured in the same way as instruction memory 20-1.

[0038] The microcontrol unit 30-n can control the peripheral circuit 40-n based on the clock signal (CKL) and instruction code (RINSTn). The microcontrol unit 30-n can be configured in the same way as the microcontrol unit 30-1.

[0039] Figure 4 shows only a portion of the memory operation control-related circuits 11-1 to 11-n, and the memory operation control-related circuits 11-1 to 11-n can be configured similarly to each other.

[0040] Figure 5 shows the operation of the memory device 10 according to an embodiment of the present invention.

[0041] The memory device 10 supports Plane Interleave Read (PIR) mode. Plane interleave read mode is an operating mode in which multiple planes perform read operations at predetermined timing intervals.

[0042] For the sake of explanation, we will assume that there are three planes (PL1 to PLn) (n=3) and describe the plane interleave bleed operation of the memory device 10.

[0043] Of the first to third planes (PL1 to PL3), the first plane (PL1) is sequentially supplied with address signals (RMADD1) of different values, based on the rising edge of the clock signal (CKL).

[0044] Based on address signals (RMADD1) with different values, instruction codes (RINST1) with different values ​​are sequentially generated.

[0045] At intervals of 1tCK in response to the input timing of the address signal (RMADD1), instruction codes (RINST1) with different values ​​are stored in the fetch register (FTR). 1tCK represents the time of one cycle of the clock signal (CKL).

[0046] The decoder (DEC) sequentially decodes instruction codes (RINST1) with different values.

[0047] At a 1tCK interval relative to the input timing of the fetch register (FTR), the output of the decoder (DEC) is stored in the execution register 33-1 and simultaneously provided to the peripheral circuit 40-1.

[0048] The third plane (PL3) can perform the same operations as the first plane (PL1), but with a 1tCK interval relative to the first plane (PL1).

[0049] The second plane (PL2) can perform the same operations as the third plane (PL3), but with a 2tCK interval relative to the third plane (PL3).

[0050] The sequence of operations and / or timing intervals between each plane are merely examples and may vary depending on the design and operating method.

[0051] Figure 6 shows the configuration of a memory device 100 according to another embodiment of the present invention.

[0052] Referring to Figure 6, the memory device 100 may include multiple planes (PL1 to PLn), multiple memory operation control related circuits 110-1 to 110-n, input / output pad section 120, data input / output circuit 130, oscillator (OSC) 140, frequency divider circuit (DIV) 500, and instruction memory (ISTM) 600.

[0053] Each of the multiple planes (PL1 to PLn) includes a memory cell array, and the multiple memory cells constituting the memory cell array may include non-volatile memory cells.

[0054] The input / output pad section 120 may include a plurality of pads 120-1 for receiving commands (CMDi) and inputting and outputting data (DQ).

[0055] The data input / output circuit 130 is commonly connected between multiple memory operation control-related circuits 110-1 to 110-n and the input / output pad section 120, enabling it to perform data input and output operations.

[0056] Multiple memory operation control circuits 110-1 to 110-n can be connected between multiple planes (PL1 to PLn) and the data input / output circuit 130. Multiple memory operation control circuits 110-1 to 110-n can control operations related to the input / output of data on multiple planes (PL1 to PLn), that is, to perform operations such as program / read / erase on multiple planes (PL1 to PLn). Multiple memory operation control circuits 110-1 to 110-n are connected one-to-one with multiple planes (PL1 to PLn) and are commonly connected to the data input / output circuit 130. The first memory operation control related circuit 110-1 is connected between the first plane (PL1) and the data input / output circuit 130, the second memory operation control related circuit 110-2 is connected between the second plane (PL2) and the data input / output circuit 130, and the nth memory operation control related circuit 110-n is connected between the nth plane (PLn) and the data input / output circuit 130.

[0057] Multiple memory operation control related circuits 110-1 to 110-n can be configured similarly to one another. The first memory operation control related circuit 110-1 includes only a microcontroller unit (MCU1) and peripheral circuitry (PER1). Peripheral circuitry (PER1) may include data input / output related circuits of the first plane (PL1), i.e., circuit configurations for controlling program, read, and erase operations. The microcontroller unit (MCU1) can control the operation of peripheral circuitry (PER1) based on the result of decoding the instruction code provided from the instruction memory 600. The second memory operation control related circuit 110-2 includes only a microcontroller unit (MCU2) and peripheral circuitry (PER2), and the nth memory operation control related circuit 110-n may include only a microcontroller unit (MCUn) and peripheral circuitry (PERn).

[0058] The frequency divider circuit 500 receives the input of a clock signal (CKH) and a plane interleaved mode setting signal (PIRFLG), and receives multiple divided clock signals (CKD <n:1>The frequency divider circuit 500 divides the clock signal (CKH) to generate multiple divided clock signals (CKD). <n:1>The frequency divider circuit 500 can generate multiple frequency divider clock signals (CKD) based on the plane interleaved mode setting signal (PIRFLG). <n:1>The phase of ) can be adjusted.

[0059] The instruction memory 600 receives multiple divided clock signals (CKD <n:1>The instruction memory 600 can receive inputs such as a plane interleaved mode setting signal (PIRFLG), a timing adjustment signal (TT<2:1>), and multiple address signals, and output multiple instruction codes. The instruction memory 600 can be shared by multiple microcontroller units (MCU1~MCUn). Based on the plane interleaved mode setting signal (PIRFLG), the instruction memory 600 can output multiple frequency divider clock signals (CKD <n:1>Based on this, multiple instruction codes can be output with predetermined time differences.

[0060] Oscillator 140 can generate a clock signal (CKH). ​​Oscillator 140 can generate a clock signal (CKH) having a frequency corresponding to the number of memory operation control-related circuits 110-1 to 110-n, i.e., the number of microcontrollers (MCU1 to MCUn). For example, oscillator 140 can be configured to generate a clock signal (CKH) with three times the frequency of the memory device 100 if it contains three microcontrollers, compared to the case where it contains only one microcontroller. As another example, oscillator 140 can be configured to generate a clock signal (CKH) with four times the frequency of the memory device 100 if it contains four microcontrollers, compared to the case where it contains only one microcontroller. Assuming that the memory device 100 contains only one microcontroller, the frequency of the clock signal (CKH) may be similar to the frequency of the clock signal (CKL) used from the semiconductor device 10 as described with reference to Figure 2. Assuming that the memory device 100 includes three microcontrol units, the frequency of the clock signal (CKH) may be three times the frequency of the clock signal (CKL) used by the semiconductor device 10 as described with reference to Figure 2.

[0061] Figure 7 shows the configuration of the memory operation control-related circuits 110-1 to 110-n in Figure 6.

[0062] Referring to Figure 7, the instruction memory 600 receives multiple divided clock signals (CKD <n:1>), plane interleaved mode setting signal (PIRFLG), timing adjustment signal (TT<2:1>), and multiple address signals (RMADD<3:1>) <n-1:0>) receives input and multiple instruction codes (RINST <n:1>The instruction memory 600 can output ( ). The instruction memory 600 can store instruction data related to the operation of the memory device 100.

[0063] The instruction data includes information for instructing the operation of the memory device 100, that is, the operation of the circuit related to program / erase / read, etc. The instruction data consists of data stored in multiple planes (PL1 to PLn) and independent information.

[0064] The instruction memory 600 stores multiple address signals (RMADD<3:1>) among the stored instruction data. <n-1:0>) Instruction data corresponding to multiple instruction codes (RINST <n:1>It can be output as a multiple divided clock signal (CKD). The instruction memory 600 can output multiple divided clock signals (CKD). <n:1>Based on each of the above, multiple instruction codes (RINST <n:1>Each of these can be provided to each of the multiple microcontrol units (MCU1 to MCUn) with a predetermined time difference.

[0065] The first memory operation control related circuit 110-1, which is connected to the first plane (PL1), may include a microcontroller unit (MCU1) 300-1 and a peripheral circuit (PER1) 400-1.

[0066] The peripheral circuit 400-1 may include the configuration described based on Figure 3. The peripheral circuit 400-1 may further include logic circuits for controlling the operation of the configuration described based on Figure 3.

[0067] The microcontrol unit 300-1 has multiple instruction codes (RINST <n:1>) including the first instruction code (RINST1) and multiple frequency divider clock signals (CKD <n:1>Among them, it receives the input of the first frequency divide clock signal (CKD1) and multiple address signals (RMADD<3:1> <n-1:0>) the first address signal (RMADD1 <n-1:0>It outputs a signal that can control peripheral circuit 400-1.

[0068] The microcontrol unit 300-1 may include a fetch register (FTR) 310-1, a decoder (DEC) 320-1, an execution register (EXR) 330-1, a program counter (PGMCNT) 340-1, an address register (ADDR) 350-1, and an instruction processing logic (CPL) 360-1.

[0069] The fetch register 310-1 can store the first instruction code (RINST1) based on the first divided clock signal (CKD1). The decoder 320-1 can output the result of decoding the first instruction code (RINST1) stored in the fetch register 310-1. The execution register 330-1 can store the output of the decoder 320-1 based on the first divided clock signal (CKD1) and provide it to the peripheral circuit 400-1. The output of the execution register 330-1 can selectively control the logic circuit of the peripheral circuit 400-1. The program counter 340-1 can change the value of the internal address (ADD-INT1) based on the output of the decoder 320-1. The address register 350-1 can take the internal address (ADD-INT1) changed by the program counter 340-1 and, based on the first divided clock signal (CKD1), output the first address signal (RMADD1) <n-1:0>It can be saved as a value and provided to the instruction memory 600. The instruction processing logic 360-1 can control the program counter 340-1 by instruction (CMDi).

[0070] The nth memory operation control related circuit 110-n, which is connected to the nth plane (PLn), may include a microcontrol unit (MCUn) 300-n and peripheral circuits (PERn) 400-n.

[0071] Peripheral circuit 400-n can be configured in the same way as peripheral circuit 400-1.

[0072] The microcontrol unit 300-n has multiple instruction codes (RINST <n:1>) including the nth instruction code (RINSTn) and multiple frequency divider clock signals (CKD <n:1>Among them, it receives the input of the nth divided clock signal (CKDn) and multiple address signals (RMADD<3:1> <n-1:0>) of which the nth address signal (RMADDn <n-1:0>It outputs a signal and can control the peripheral circuit 400-n. The microcontrol unit 300-n can be configured in the same way as the microcontrol unit 300-1.

[0073] Figure 7 shows only a portion of the memory operation control related circuits 110-1 to 110-n, and the memory operation control related circuits 110-1 to 110-n can be configured similarly to each other.

[0074] Figure 8 shows the configuration of the frequency divider circuit 500 in Figure 6, and Figures 9 and 10 show the operation of the frequency divider circuit 500 in Figure 8. Figure 8 is an example in which the memory device 100 consists of three planes (PL1 to PL3) and three memory operation control related circuits 110-1 to 110-3, and the frequency divider circuit 500 is configured to generate first to third frequency divider clock signals (CKD<3:1>).

[0075] The configuration and operation of the frequency divider circuit 500 will be explained below based on Figures 8 to 10.

[0076] In the following explanation, activation / deactivation of a circuit configuration means that the circuit configuration is operational / inoperable, and activation / deactivation of a signal means that the logic level of the signal is high / low or low / high.

[0077] Referring to Figure 8, the frequency divider circuit 500 can include a multiple phase signal generation unit 510, a backup frequency divider clock generation unit 520, an activation control unit 540, and a plurality of multiplexers 531 to 533.

[0078] The multi-phase signal generation unit 510 receives a reset signal (RST) and a clock signal (CKH) as inputs and can output multi-phase signals (CK-PH0 to CK-PH2). The reset signal (RST) is activated at a low level at a predetermined timing during the initial operation of the data storage device 1 and when requested by the host 2, and is deactivated at a high level during other operating intervals.

[0079] The multiple phase signal generation unit 510 may include a first flip-flop 511, a second flip-flop 512, and a logic gate 513. The first flip-flop 511 can output a signal obtained by latching the first phase signal (CK-PH0) to the rising edge of the clock signal (CKH) as the second phase signal (CK-PH1). The second flip-flop 512 can output a signal obtained by latching the second phase signal (CK-PH1) to the rising edge of the clock signal (CKH) as the third phase signal (CK-PH2). The logic gate 513 can output the result of the negation OR of the second phase signal (CK-PH1) and the third phase signal (CK-PH2) as the first phase signal (CK-PH0). The first flip-flop 511 and the second flip-flop 512 can be activated when the reset signal (RST) is high and perform the aforementioned operations, and can initialize their own outputs when the reset signal (RST) is low. Multiple phase signals (CK-PH0~CK-PH2) can be generated with a predetermined phase difference, as shown in Figures 9 and 10.

[0080] The auxiliary frequency divider clock generation unit 520 receives inputs of multiple phase signals (CK-PH0 to CK-PH2) and a clock signal (CKH) and can output multiple auxiliary frequency divider clock signals (CKD-PRE1 to CKD-PRE3). The auxiliary frequency divider clock generation unit 520 may include first to sixth flip-flops 521 to 526 and first to third logic gates 527 to 529. The first flip-flop 521 can output a signal in which the first phase signal (CK-PH0) is latched to the rising edge of the clock signal (CKH). ​​The second flip-flop 522 can output a signal in which the second phase signal (CK-PH1) is latched to the rising edge of the clock signal (CKH). ​​The third flip-flop 523 can output a signal in which the third phase signal (CK-PH2) is latched to the rising edge of the clock signal (CKH). The fourth flip-flop 524 can output a signal obtained by latching the output of the first flip-flop 521 to the falling edge of the clock signal (CKH). ​​The fifth flip-flop 525 can output a signal obtained by latching the output of the second flip-flop 522 to the falling edge of the clock signal (CKH). ​​The sixth flip-flop 526 can output a signal obtained by latching the output of the third flip-flop 523 to the falling edge of the clock signal (CKH). ​​The first logic gate 527 can output the result of the logical OR of the outputs of the first flip-flop 521 and the fourth flip-flop 524 as the first pre-division clock signal (CKD-PRE1). The second logic gate 528 can output the result of the logical OR of the outputs of the second flip-flop 522 and the fifth flip-flop 525 as the second pre-division clock signal (CKD-PRE2). The third logic gate 529 can output the result of the logical OR of the output of the third flip-flop 523 and the output of the sixth flip-flop 526 as a third pre-division clock signal (CKD-PRE3).

[0081] The activation control unit 540 can selectively activate the pre-division clock generation unit 520 based on a reset signal (RST) and a plurality of active signals (ACT-PL<3:1>). The activation control unit 540 can include first to fourth logic gates 541 to 544. The first logic gate 541 can output the reset signal (RST) inverted. The second logic gate 542 can activate the flip-flops 521 and 524 of the pre-division clock generation unit 520 by the result of a negative OR operation of the output of the first logic gate 541 and the inverted first active signal (ACT-PL1). The third logic gate 543 can activate the flip-flops 522 and 525 of the pre-division clock generation unit 520 by the result of a negative OR operation of the output of the first logic gate 541 and the inverted second active signal (ACT-PL2). The fourth logic gate 544 can activate the flip-flops 523 and 526 of the auxiliary frequency divider clock generation unit 520 by the result of the negation OR of the output of the first logic gate 541 and the inverted third active signal (ACT-PL3). Multiple active signals (ACT-PL<3:1>) may be signals that are activated by a read command to the plane in question. The first active signal (ACT-PL1) is a signal that is activated by a read command to the first plane PL1, the second active signal (ACT-PL2) is a signal that is activated by a read command to the second plane PL2, and the third active signal (ACT-PL3) may be a signal that is activated by a read command to the third plane (PL3).

[0082] Multiple multiplexers 531 to 533 can selectively output multiple auxiliary frequency divider clock signals (CKD-PRE1 to CKD-PRE3) as multiple frequency divider clock signals (CKD<3:1>) based on the plane interleave mode setting signal (PIRFLG). The plane interleave mode setting signal (PIRFLG) is activated when the read operation mode of the memory device 100 is set to plane interleave mode, and deactivated otherwise. The first multiplexer 531 can output the first auxiliary frequency divider clock signal (CKD-PRE1) as the first frequency divider clock signal (CKD1) regardless of the plane interleave mode setting signal (PIRFLG). The second multiplexer 532 can output the first auxiliary frequency divider clock signal (CKD-PRE1) as the second frequency divider clock signal (CKD2) when the plane interleave mode setting signal (PIRFLG) is deactivated, and can output the second auxiliary frequency divider clock signal (CKD-PRE2) as the second frequency divider clock signal (CDK2) when the plane interleave mode setting signal (PIRFLG) is activated. The third multiplexer 533 can output the first auxiliary frequency divider clock signal (CKD-PRE1) as the third frequency divider clock signal (CKD3) when the plane interleave mode setting signal (PIRFLG) is deactivated, and can output the third auxiliary frequency divider clock signal (CKD-PRE3) as the third frequency divider clock signal (CKD3) when the plane interleave mode setting signal (PIRFLG) is activated.

[0083] As shown in Figure 9, when the read operation mode of the memory device 100 is set to the plane interleaved mode, and the plane interleaved mode setting signal (PIRFLG) is activated, the frequency divider circuit 500 can generate multiple frequency divider clock signals (CKD<3:1>) having a predetermined phase difference.

[0084] On the other hand, as shown in Figure 10, when the read operation mode of the memory device 100 is set to normal read mode, and the plane interleaved read mode setting signal (PIRFLG) is deactivated, the frequency divider circuit 500 can generate multiple frequency divider clock signals (CDK<3:1>) that have the same phase.

[0085] Figure 11 shows the configuration of the instruction memory 600 in Figure 6.

[0086] Referring to Figure 11, the instruction memory 600 can include a memory core 601, an output control circuit 602, an instruction output circuit 603, and a control signal generation circuit 604.

[0087] The memory core 601 uses the integrated address signal (ADD <n-1:0>) and a word line enable signal (WLEN) are input, and instruction data (IDATA <m-1:0>) can output. When the word line enable signal (WLEN) is activated, the memory core 601 outputs the integrated address signal (ADD) from among the multiple stored instruction data. <n-1:0>) corresponding instruction data (IDATA <m-1:0>It can output ).

[0088] The output control circuit 602 receives multiple address signals (RMADD<3:1> <n-1:0>) and multiple auxiliary word line control signals (RWLEN<3:1>) are input, and the integrated address signal (ADD <n-1:0>It can output a word line enable signal (WLEN) and a word line enable signal.

[0089] The instruction output circuit 603 receives instruction data (IDATA <m-1:0>) and multiple load control signals (RLDEN<3:1>) are input, and multiple instruction codes (RINST<3:1> <m-1:0>It can output ).

[0090] The control signal generation circuit 604 receives inputs of multiple frequency divider clock signals (CKD<3:1>), a plane interleave mode setting signal (PIRFLG), and a timing adjustment signal (TT<2:1>), and can output multiple auxiliary word line control signals (RWLEN<3:1>) and multiple load control signals (RLDEN<3:1>).

[0091] Figure 12 shows the configuration of the memory core 601 in Figure 11.

[0092] Referring to Figure 12, the memory core 601 may include a memory cell array, a word line driver (WLD) 611, a bit line driver (BLD) 612, an address decoder (ADEC) 613, and a sense amplifier array 614.

[0093] A memory cell array may include multiple memory cells (MCs) linked to multiple word lines (WLs) and multiple bit lines (BLs).

[0094] The address decoder 613 receives the integrated address signal (ADD <n-1:0>The result of decoding ) can be output.

[0095] When the word line enable signal (WLEN) is activated, the word line driver 611 can activate the word line (WL) among several word lines that corresponds to the output of the address decoder 613.

[0096] The bit line driver 612 can be connected between multiple bit lines (BLs) and a global line (GBL). The bit line driver 612 can transfer the signal of the bit line (BL) corresponding to the output of the address decoder 613 to the global line (GBL).

[0097] The sense amplifier array 614 may include multiple sense amplifiers (SAs). The sense amplifier array 614 amplifies the result of comparing the level of the signal transferred to the global line (GBL) with the reference signal (RBL) to generate indicator data (IDATA). <m-1:0>It can be output as ).

[0098] Figure 13 shows the configuration of the output control circuit 602 shown in Figure 11.

[0099] Referring to Figure 13, the output control circuit 602 may include a plurality of buffer arrays 621-623, a first logic gate 624, a second logic gate 625, and a pull-down driver 626.

[0100] The first buffer array 621, when the first auxiliary word line control signal (RWLEN1) is activated, receives the first address signal (RMADD1) <n-1:0>) integrated address signal (ADD <n-1:0>The first buffer array 621 can output the first address signal (RMADD1). <n-1:0>It can contain a buffer with a number of bits equal to )

[0101] The second buffer array 622, when the second auxiliary word line control signal (RWLEN2) is activated, receives the second address signal (RMADD2 <n-1:0>) integrated address signal (ADD <n-1:0>The second buffer array 622 can output the second address signal (RMADD2 <n-1:0>It can contain a buffer with a number of bits equal to )

[0102] The third buffer array 623, when the third auxiliary word line control signal (RWLEN3) is activated, receives the third address signal (RMADD3) <n-1:0>) integrated address signal (ADD <n-1:0>The third buffer array 623 can output the third address signal (RMADD3). <n-1:0>It can contain a buffer with a number of bits equal to )

[0103] The first logic gate 624 can output the result of the negation OR of multiple auxiliary word line control signals (RWLEN<3:1>).

[0104] The second logic gate 625 can output a signal obtained by inverting the output of the first logic gate 624 as a word line enable signal (WLEN).

[0105] The first logic gate 624 and the second logic gate 625 can activate the word line enable signal (WLEN) if any one of the multiple auxiliary word line control signals (RWLEN<3:1>) is activated.

[0106] The pull-down driver 626 receives the integrated address signal (ADD) from the output of the first logic gate 624. <n-1:0>The pull-down driver 626 can initialize the integrated address signal (ADD). <n-1:0>It can include drivers with a number of bits equal to the number of bits of the ) Pull-down driver 626 pulls down the output terminals of multiple buffer arrays 621-623 to ground voltage level, thereby enabling the integrated address signal (ADD <n-1:0>) can be initialized.

[0107] The output control circuit 602, when all of the multiple auxiliary word line control signals (RWLEN<3:1>) are deactivated, will activate the integrated address signal (ADD <n-1:0>) initializes, and if any one of the multiple auxiliary word line control signals (RWLEN<3:1>) is activated, multiple address signals (RMADD<3:1>) <n-1:0>Based on this, the integrated address signal (ADD <n-1:0>) can be generated.

[0108] Figure 14 shows the configuration of the instruction output circuit 603 in Figure 11.

[0109] Referring to Figure 14, the instruction output circuit 603 can include multiple buffer arrays 631-633 and multiple latch arrays 634-636.

[0110] The first buffer array 631 receives instruction data (IDATA) when the first load control signal (RLDEN1) is activated. <m-1:0>The first buffer array 631 can invert the instruction data (IDATA) and output it. <m-1:0>It can contain a buffer with a number of bits equal to )

[0111] The second buffer array 632 receives instruction data (IDATA) when the second load control signal (RLDEN2) is activated. <m-1:0>The second buffer array 632 can invert and output the instruction data (IDATA). <m-1:0>It can contain a buffer with a number of bits equal to )

[0112] The third buffer array 633 receives instruction data (IDATA) when the third load control signal (RLDEN3) is activated. <m-1:0>The third buffer array 633 can invert the instruction data (IDATA <m-1:0>It can contain a buffer with a number of bits equal to )

[0113] The first latch array 634 latches the output of the first buffer array 631 to receive the first instruction code (RINST1 <m-1:0>The first latch array 634 can output the first instruction code (RINST1 <m-1:0>It can contain latches with a number of bits equal to the number of bits in the specified value.

[0114] The second latch array 635 latches the output of the second buffer array 632 to receive the second instruction code (RINST2 <m-1:0>The second latch array 635 can output the second instruction code (RINST2). <m-1:0>It can contain latches with a number of bits equal to the number of bits in the specified value.

[0115] The third latch array 636 latches the output of the third buffer array 633 to receive the third instruction code (RINST3 <m-1:0>The output can be as follows: The third latch array 636 outputs the third instruction code (RINST3 <m-1:0>It can contain latches with a number of bits equal to the number of bits in the specified value.

[0116] Figure 15 shows the configuration of the control signal generation circuit 604 in Figure 11, Figures 16 and 17 show the operation of the control clock generation circuit 640 in Figure 15, and Figures 18 and 19 show the operation of the control signal generation unit 650 in Figure 15.

[0117] The configuration and operation of the control signal generation circuit 604 will be explained below based on Figures 15 to 19.

[0118] Referring to Figure 15, the control signal generation circuit 604 can include a control clock generation circuit 640 and a plurality of control signal generation units 650 to 670.

[0119] The control clock generation circuit 640 can receive multiple divided clock signals (CKD<3:1>) and a plane interleaved mode setting signal (PIRFLG) as inputs and output multiple control clock signals (RMCK<3:1>).

[0120] The control clock generation circuit 640 may include a plurality of logic gates 641 to 646. The first logic gate 641 can output the result of a negative AND operation of the first divided clock signal (CKD1) and the first power supply voltage (VCCI). The second logic gate 642 can output the result of a negative AND operation of the second divided clock signal (CKD2) and the plane interleaved mode setting signal (PIRFLG). The third logic gate 643 can output the result of a negative AND operation of the third divided clock signal (CKD3) and the plane interleaved mode setting signal (PIRFLG). The fourth logic gate 644 can output the result of a negative AND operation of the inverted output of the first logic gate 641 and the output of the second logic gate 642 as the first control clock signal (RMCK1). The fifth logic gate 645 can output the result of a logical AND operation between the inverted output of the second logic gate 642 and the output of the third logic gate 643 as the second control clock signal (RMCK2). The sixth logic gate 646 can output the result of a logical AND operation between the inverted output of the third logic gate 643 and the output of the first logic gate 641 as the third control clock signal (RMCK3).

[0121] Referring to Figure 16, the control clock generation circuit 640 outputs the first divided clock signal (CKD1) as the first control clock signal (RMCK1) when in normal read mode, i.e., when the plane interleaved mode setting signal (PIRFLG) is deactivated, and fixes the second control clock signal (RMCK2) and the third control clock signal (RMCK3) to a low level. Therefore, in embodiments of the present invention, when not in plane interleaved mode, unnecessary power consumption can be prevented by fixing the second control clock signal (RMCK2) and the third control clock signal (RMCK3), which are unrelated to the plane interleaved mode, to a low level.

[0122] Referring to Figure 17, when the plane interleaved mode setting signal (PIRFLG) is activated, the control clock generation circuit 640 outputs a signal having a high-level section corresponding to the phase difference between the first divided clock signal (CKD1) and the second divided clock signal (CKD2) as the first control clock signal (RMCK1), a signal having a high-level section corresponding to the phase difference between the second divided clock signal (CKD2) and the third divided clock signal (CDK3) as the second control clock signal (RMCK2), and a signal having a high-level section corresponding to the phase difference between the third divided clock signal (CKD3) and the first divided clock signal (CKD1) as the third control clock signal (RMCK3). When the plane interleaved mode setting signal (PIRFLG) is deactivated, the first control clock signal (RMCK1) will have a high-level section corresponding to 1.5 periods of the clock signal (CKH). When the plane interleaved mode setting signal (PIRFLG) is activated, the first control clock signal (RMCK1) will have a high-level interval corresponding to one period of the clock signal (CKH).

[0123] Referring to Figures 15, 18, and 19, the multiple control signal generation units 650 to 670 can generate multiple auxiliary word line control signals (RWLEN<3:1>) and multiple load control signals (RLDEN<3:1>) by combining signals obtained by delaying each of the multiple control clock signals (RMCK<3:1>).

[0124] The first control signal generation unit 650 receives a first control clock signal (RMCK1) and a timing adjustment signal (TT<2:1>) and can output a first auxiliary word line control signal (RWLEN1) and a first load control signal (RLDEN1).

[0125] The first control signal generation unit 650 may include first to third delay circuits 651 to 653 and first and second logic gates 654 and 655. The first delay circuit 651 can generate a first delay signal (DEL1) by delaying the first control clock signal (RMCK1) by a predetermined time. The second delay circuit 652 can generate a second delay signal (DEL2) by delaying the first delay signal (DEL1) by a time adjusted by a timing adjustment signal (TT1). The third delay circuit 653 can generate a third delay signal (DEL3) by delaying the second delay signal (DEL2) by a time adjusted by a timing adjustment signal (TT2). The first logic gate 654 can output a signal obtained by logically ANDing the second delay signal (DEL2) and the third delay signal (DEL3) as a first auxiliary word line control signal (RWLEN1). The second logic gate 655 can output a signal obtained by logically ANDing the first delay signal (DEL1) and the third delay signal (DEL3) as the first load control signal (RLDEN1).

[0126] The second control signal generation unit 660 receives a second control clock signal (RMCK2) and a timing adjustment signal (TT<2:1>) and can output a second auxiliary word line control signal (RWLEN2) and a second load control signal (RLDEN2). The second control signal generation unit 660 can be configured in the same way as the first control signal generation unit 650.

[0127] The third control signal generation unit 670 receives a third control clock signal (RMCK3) and a timing adjustment signal (TT<2:1>) and can output a third auxiliary word line control signal (RWLEN3) and a third load control signal (RLDEN3). The third control signal generation unit 670 can be configured in the same way as the first control signal generation unit 650.

[0128] Figure 20 shows the operation of a memory device 100 according to another embodiment of the present invention.

[0129] The plane interleaved operation of the memory device 100 will be described below based on Figures 6 to 20. For the sake of explanation, we will assume that there are three planes (PL1 to PLn) (n=3). When the plane interleaved mode is activated, read operations can be performed on the first to third planes (PL1 to PL3) in a predetermined order. One embodiment of the present invention is an example in which, when the plane interleaved mode is activated, read operations are performed in the order of the first plane (PL1), the third plane (PL3), and the second plane (PL2).

[0130] First, as explained with reference to Figure 8, when a read command is input to the first plane PL1, the first active signal (ACT-PL1) is activated, which in turn activates the first frequency divider clock signal (CKD1).

[0131] A microcontrol unit 300-1 connected to the first plane PL1 provides the instruction memory 600 with address signals (RMADD1) having different values ​​from each other, based on each of the rising edges of the first divided clock signal (CKD1).

[0132] The instruction memory 600 sequentially generates instruction codes (RINST1) with different values ​​based on address signals (RMADD1) with different values. The instruction codes (RINST1) with different values ​​can be generated at a time interval of one cycle of the clock signal (CKH) relative to the input timing of the address signal (RMADD1).

[0133] Instruction codes (RINST1) with different values ​​are stored in the fetch register (FTR) at a time interval of one cycle of the first frequency divider clock signal (CKD1) in response to the input timing of the address signal (RMADD1).

[0134] The instruction codes (RINST1) with different values ​​stored in the fetch register (FTR) are decoded by the decoder (DEC).

[0135] The output of the decoder (DEC) is stored in the execution register (EXR) and simultaneously provided to the peripheral circuit (PER1) at a time interval of one cycle of the first frequency divider clock signal (CKD1) in response to the timing when instruction codes (RINST1) with different values ​​are input to the fetch register (FTR).

[0136] The output of the execution register (EXR) controls the operation of the peripheral circuit (PER1), thereby enabling a read operation on the first plane (PL1).

[0137] Next, a read command is input to the third plane (PL3), which activates the third active signal (ACT-PL3), and this activates the third frequency divider clock signal (CKD3).

[0138] A microcontrol unit 300-3, connected to the third plane (PL3), provides the instruction memory 600 with address signals (RMADD3) having different values, based on each of the rising edges of the third frequency divider clock signal (CKD3).

[0139] The instruction memory 600 sequentially generates instruction codes (RINST3) of different values ​​based on address signals (RMADD3) of different values. The instruction codes (RINST3) of different values ​​can be generated at a time interval of one cycle of the clock signal (CKH) relative to the input timing of the address signal (RMADD3).

[0140] Instruction codes (RINST3) with different values ​​are stored in the fetch register (FTR) at a time interval of one cycle of the third frequency divider clock signal (CKD3) in response to the input timing of the address signal (RMADD3).

[0141] The instruction codes (RINST3) with different values ​​stored in the fetch register (FTR) are decoded by the decoder (DEC).

[0142] The output of the decoder (DEC) is stored in the execution register (EXR) and simultaneously provided to the peripheral circuit (PER1) at a time interval of one cycle of the third frequency divider clock signal (CKD3) in response to the timing when instruction codes (RINST3) with different values ​​are input to the fetch register (FTR).

[0143] The output of the execution register (EXR) controls the operation of the peripheral circuit (PER3), thereby enabling read operations on the third plane (PL3).

[0144] Then, when a read command is input to the second plane (PL2), the second active signal (ACT-PL2) is activated, which in turn activates the second frequency divider clock signal (CKD2).

[0145] A microcontrol unit 300-2, connected to the second plane (PL2), provides the instruction memory 600 with address signals (RMADD2) having different values, based on each of the rising edges of the second divided clock signal (CKD2).

[0146] The instruction memory 600 sequentially generates instruction codes (RINST2) with different values ​​based on address signals (RMADD2) with different values. The instruction codes (RINST2) with different values ​​can be generated at a time interval of one cycle of the clock signal (CKH) relative to the input timing of the address signal (RMADD2).

[0147] Two instruction codes (RINST2) with different values ​​are stored in the fetch register (FTR) at a time interval of one cycle of the second frequency divider clock signal (CKD2) relative to the input timing of the address signal (RMADD2).

[0148] The instruction codes (RINST2) with different values ​​stored in the fetch register (FTR) are decoded by the decoder (DEC).

[0149] The output of the decoder (DEC) is stored in the execution register (EXR) and simultaneously provided to the peripheral circuit (PER1) at a time interval of one cycle of the second frequency divider clock signal (CKD2) in response to the timing when instruction codes (RINST2) of different values ​​are input to the fetch register (FTR).

[0150] The output of the execution register (EXR) controls the operation of the peripheral circuit (PER2), which in turn enables the completion of the plane interleaved operation by performing a read operation on the second plane (PL2).

[0151] In the embodiment of the present invention described above, multiple planes (PL1 to PLn) and multiple microcontrol units (MCU1 to MCUn) connected to each of them can share a single instruction memory 600. This reduces the circuit area compared to when multiple instruction memories are used, simplifies signal line wiring, and simplifies circuit design, thereby increasing the layout margin.

[0152] Then, multiple microcontroller units (MCU1~MCUn) receive divided clock signals (CKD) with different phases from each other. <n:1>Since it operates based on one of the above, multiple microcontrollers (MCU1 to MCUn) can freely access the instruction memory 600 without timing overlap and perform plane interleaved operation.

[0153] Furthermore, since there is no overlap in the timing of multiple microcontrollers (MCU1 to MCUn) accessing the instruction memory 600, there is no overlap in peak currents for each plane, which not only reduces current consumption but also ensures the safety of read operations.

[0154] Thus, a person of ordinary skill in the art to which the present invention belongs can understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. Therefore, it must be understood that the examples described above are illustrative in all respects and not limiting. The scope of the present invention is indicated by the claims described below rather than by the detailed description, and it must be understood that all modified or altered forms derived from the meaning and scope of the claims and their equivalent concepts are included within the scope of the present invention. [Explanation of Symbols]

[0155] 1. Data storage device 1-1 Memory device 1-2 Controller 2 hosts 10 Memory devices 11-n Memory operation control related circuits 12 Input / Output Pad Section 13. Data Input / Output Circuit 20-n Indicator Memory (ISTM) 30-n Microcontroller Unit (MCU) 31-1 Fetch Register (FTR) 32-1 Decoder (DEC) 33-1 Execution Register (EXR) 34-1 Program Counter (PGMCNT) 35-1 Address Register (ADDR) 36-1 Instruction Processing Logic (CPL) 40-n Peripheral Circuits (PER) 51 Address Decoder 52 Voltage generation unit 53 Light Circuit 100 memory devices 110-1 First memory operation control related circuit 110-n Memory operation control related circuits 120 Input / Output Pad Section 120-1 Pad 130 Data Input / Output Circuits 140 Oscillators (OSC) 300-n Microcontrol Unit (MCUn) 310-1 Fetch Register (FTR) 320-1 Decoder (DEC) 330-1 Execution Register (EXR) 340-1 Program Counter (PGMCNT) 350-1 Address Register (ADDR) 360-1 Instruction Processing Logic (CPL) 400-n peripheral circuits (PERn) 500 frequency divider circuit (DIV) 510 Multiphase signal generator 520 Auxiliary frequency divider clock generation unit 531 Multiplexer 532 Multiplexer 533 Multiplexer 540 Activation Control Unit 600 Indicator Memory (ISTM) 601 memory cores 602 Output control circuit 603 Instruction Output Circuit 604 Control signal generation circuit

Claims

1. An instruction memory configured such that multiple instruction codes are output with a predetermined time difference based on multiple address signals and multiple frequency divider clock signals, A memory device comprising a plurality of microcontrol units, each connected to a plurality of memory regions, and configured to provide each of the plurality of address signals to the instruction memory based on each of the plurality of frequency divider clock signals, and to perform an operation according to the instruction code corresponding to itself among the plurality of instruction codes.

2. The memory device according to claim 1, further comprising a frequency divider circuit configured to divide a clock signal to generate the plurality of divided clock signals.

3. The memory device according to claim 2, wherein the frequency divider circuit is configured to generate a plurality of frequency divider clock signals having a predetermined phase difference when the plane interleaved mode setting signal is activated, and to generate a plurality of frequency divider clock signals having the same phase when the plane interleaved mode setting signal is deactivated.

4. The aforementioned frequency divider circuit is A multiphase signal generation unit configured to receive the aforementioned clock signal input and output a multiphase signal, A pre-division clock generation unit is configured to receive the multi-phase signal and the clock signal as inputs and output a plurality of pre-division clock signals, An activation control unit is configured to selectively activate the pre-division clock generation unit based on a reset signal and a plurality of active signals corresponding to each of the plurality of memory areas, The memory device according to claim 2, further comprising a plurality of multiplexers configured to selectively output the plurality of pre-division clock signals as the plurality of division clock signals based on the plane interleaved mode setting signal.

5. The memory device according to claim 2, further comprising an oscillator configured to generate the frequency of the clock signal to a frequency corresponding to the number of the plurality of microcontrol units.

6. The instruction memory is When the word line enable signal is activated, a memory core is configured to output the instruction data corresponding to the integrated address signal from among the multiple stored instruction data, An output control circuit configured to receive inputs of multiple auxiliary word line control signals and multiple address signals, and to output the integrated address signal and the word line enable signal, An instruction output circuit configured to receive multiple load control signals and the data, and to output the multiple instruction codes, The memory device according to claim 1, further comprising a control signal generation circuit configured to receive the inputs of the plurality of frequency divider clock signals and the plane interleave mode setting signals, and to output the plurality of auxiliary word line control signals and the plurality of load control signals.

7. The aforementioned memory core is A memory cell array including multiple memory cells connected to multiple word lines and multiple bit lines, An address decoder configured to output the result of decoding the integrated address signal, A word line driver is configured to activate the word line corresponding to the output of the address decoder among the plurality of word lines when the word line enable signal is activated, A bit line driver is connected between the plurality of bit lines and the global line and is configured to transfer the signal of the bit line corresponding to the output of the address decoder to the global line. The memory device according to claim 6, further comprising a sense amplifier array configured to amplify the result of comparing a signal transferred to the global line with a reference signal and output it as instruction data.

8. The output control circuit is, Multiple buffer arrays are configured to output one of the multiple address signals corresponding to the activation of one of the multiple auxiliary word line control signals as the integrated address signal, The memory device according to claim 6, further comprising at least one logic gate configured to activate the word line enable signal when any one of the plurality of auxiliary word line control signals is activated.

9. The aforementioned instruction output circuit is, When one of the aforementioned load control signals is activated, a plurality of buffer arrays are configured to invert and output the instruction data, The memory device according to claim 6, further comprising a plurality of latch arrays configured to output signals latched from the outputs of the plurality of buffer arrays as the plurality of instruction codes.

10. The aforementioned control signal generation circuit is A control clock generation circuit configured to receive the inputs of the plurality of frequency divider clock signals and the plane interleaved mode setting signal, and to output a plurality of control clock signals, The memory device according to claim 6, further comprising a plurality of control signal generation units configured to generate the plurality of auxiliary word line control signals and the plurality of load control signals by combining signals obtained by delaying each of the plurality of control clock signals.

11. The memory device according to claim 10, wherein the control clock generation circuit is configured such that, when the plane interleaved mode setting signal is deactivated, it outputs a first divided clock signal from among the plurality of divided clock signals as a first control clock signal from among the plurality of control clock signals, and fixes the remaining control clock signals, excluding the first control clock signal, to a low level.

12. Multiple planes, An input / output pad section including multiple pads, A data input / output circuit connected to the input / output pad section, An instruction memory configured such that multiple instruction codes are output with a predetermined time difference based on multiple address signals and multiple frequency divider clock signals, A memory device comprising a plurality of memory operation control-related circuits, which are commonly connected to the data input / output circuit and are connected one-to-one with the plurality of planes, and which are configured to provide each of the plurality of address signals to the instruction memory based on each of the plurality of frequency divider clock signals, and to perform an operation according to the instruction code corresponding to the instruction code among the plurality of instruction codes.

13. The instruction memory is When the word line enable signal is activated, a memory core is configured to output instruction data corresponding to the integrated address signal from among the stored instruction data, An output control circuit configured to receive inputs of multiple auxiliary word line control signals and multiple address signals, and to output the integrated address signal and the word line enable signal, An instruction output circuit configured to receive multiple load control signals and the data, and to output the multiple instruction codes, The memory device according to claim 12, further comprising a control signal generation circuit configured to receive the inputs of the plurality of frequency divider clock signals and the plane interleaved mode setting signals, and to output the plurality of auxiliary word line control signals and the plurality of load control signals.

14. The aforementioned memory core is A memory cell array including multiple memory cells connected to multiple word lines and multiple bit lines, An address decoder configured to output the result of decoding the integrated address signal, A word line driver is configured to activate the word line corresponding to the output of the address decoder among the plurality of word lines when the word line enable signal is activated, A bit line driver is connected between the plurality of bit lines and the global line and is configured to transfer the signal of the bit line corresponding to the output of the address decoder to the global line. The memory device according to claim 13, further comprising a sense amplifier array configured to amplify the result of comparing a signal transferred to the global line with a reference signal and output it as instruction data.

15. The output control circuit is, Multiple buffer arrays are configured to output one of the multiple address signals corresponding to the activation of one of the multiple auxiliary word line control signals as the integrated address signal, The memory device according to claim 13, further comprising at least one logic gate configured to activate the word line enable signal when any one of the plurality of auxiliary word line control signals is activated.

16. The aforementioned instruction output circuit is, When one of the aforementioned load control signals is activated, a plurality of buffer arrays are configured to invert and output the instruction data, The memory device according to claim 13, further comprising a plurality of latch arrays configured to output signals latched from the outputs of the plurality of buffer arrays as the plurality of instruction codes.

17. The aforementioned control signal generation circuit is A control clock generation circuit configured to receive the inputs of the plurality of frequency divider clock signals and the plane interleaved mode setting signal, and to output a plurality of control clock signals, The memory device according to claim 13, further comprising a plurality of control signal generation units configured to generate the plurality of auxiliary word line control signals and the plurality of load control signals by combining signals obtained by delaying each of the plurality of control clock signals.

18. The memory device according to claim 17, wherein the control clock generation circuit is configured such that, when the plane interleaved mode setting signal is deactivated, it outputs a first divided clock signal from among the plurality of divided clock signals as a first control clock signal from among the plurality of control clock signals, and fixes the remaining control clock signals, excluding the first control clock signal, to a low level.

19. The memory device according to claim 12, wherein the plurality of memory operation control related circuits are configured to control the program operation and read operation of the plurality of planes.

20. Each of the aforementioned multiple memory operation control related circuits A peripheral circuit configured to control the programmed and read operations of the plane connected to itself among multiple planes, The memory device according to claim 12, further comprising a microcontrol unit configured to provide each of the plurality of address signals to the instruction memory based on each of the plurality of frequency divider clock signals, and to control the operation of the peripheral circuit based on the result of decoding the instruction code corresponding to itself.

21. The memory device according to claim 12, further comprising a frequency divider circuit configured to divide a clock signal to generate the plurality of divided clock signals.

22. The aforementioned frequency divider circuit is The memory device according to claim 21, configured to generate a plurality of divided clock signals having a predetermined phase difference when the plane interleaved mode setting signal is activated, and to generate a plurality of divided clock signals having the same phase when the plane interleaved mode setting signal is deactivated.

23. The aforementioned frequency divider circuit is A multiphase signal generation unit configured to receive the aforementioned clock signal input and output a multiphase signal, A pre-division clock generation unit is configured to receive the multi-phase signal and the clock signal as inputs and output a plurality of pre-division clock signals, An activation control unit is configured to selectively activate the pre-division clock generation unit based on a reset signal and a plurality of active signals corresponding to each of the plurality of memory areas, The memory device according to claim 12, further comprising a plurality of multiplexers configured to selectively output the plurality of pre-divided clock signals as the plurality of divided clock signals based on the plane interleaved mode setting signal.

24. The memory device according to claim 21, further comprising an oscillator configured to generate the frequency of the clock signal to a frequency corresponding to the number of the plurality of memory operation control-related circuits.

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