Wiring boards and display devices

Abstract

Maintain good coverage at the third connection point. [Solution] The wiring board comprises a first conductive portion made of a first conductive film, a first connecting portion connected to the first conductive portion, a first insulating film disposed on the first conductive film, a second conductive portion made of a second conductive film disposed on the first insulating film, a second connecting portion connected to the second conductive portion, a second insulating film disposed on the second conductive film, and a third connecting portion made of a third conductive film disposed on the second insulating film. The second connecting portion 31 is disposed superimposed on the first connecting portion 30, and the second connecting portion is provided with a first opening 31A that superimposes on the first connecting portion. The third connecting portion 32 is disposed superimposed on the second connecting portion and the first opening. The first insulating film 34 is provided with a first contact hole 34A at a position communicating with the first opening, and the second insulating film 36 is provided with a second contact hole 36A at a position communicating with both the first opening and the first contact hole A, and superimposed on both the second connecting portion and the third connecting portion.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a wiring board and a display device.

Background Art

[0002] Conventionally, as an example of a wiring board and a display device including the wiring board, what is described in Patent Document 1 below is known. Patent Document 1 describes an array board which is a wiring board and a liquid crystal display device which is a display device. The liquid crystal display device includes a switching element having a pixel connection portion, a first insulating film in which a first pixel contact hole is formed at a position overlapping at least a part of the pixel connection portion, a common wiring, and an intermediate electrode which is made of the same conductive film as the common wiring and is arranged to overlap the first pixel contact hole and is connected to the pixel connection portion, a common electrode which is not connected to the intermediate electrode but is connected to the common wiring, a second insulating film in which a second pixel contact hole is formed at a position overlapping at least a part of the intermediate electrode, and a pixel electrode arranged so that at least a part thereof overlaps the second pixel contact hole.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The liquid crystal display device described in Patent Document 1 above comprises a lower insulating film disposed on the lower side of the pixel connection portion, lower wiring disposed on the lower side of the lower insulating film, upper wiring made of the same conductive film as the pixel connection portion, and wiring connection portion made of the same conductive film as the pixel electrode and disposed so that at least a part of it overlaps with the lower wiring and the upper wiring. In the first insulating film, a first wiring connection contact hole is formed at a position that overlaps with at least a part of the wiring connection portion, while in the lower insulating film and the second insulating film, a second wiring connection contact hole is formed at a position that overlaps with at least a part of the lower wiring and the first wiring connection contact hole but does not overlap with the upper wiring.

[0005] In the configuration described in Patent Document 1 mentioned above, the outer edge of the upper layer wiring and the opening edge of the second wiring connection contact hole in the second insulating film intersect. Therefore, especially when a configuration is adopted in which there is no planarization film on the lower layer side of the second insulating film, the coverage of the wiring connection portion located on the second insulating film may deteriorate at the intersection of the portion of the second insulating film that overlaps the outer edge of the lower layer wiring and the portion that overlaps the outer edge of the upper layer wiring. When the coverage of the wiring connection portion deteriorates, problems such as moisture easily penetrating the upper layer wiring connected to the wiring connection portion may occur, and as a result, there is a concern that the characteristics of the element connected to the upper layer wiring may deteriorate.

[0006] The technology described herein was developed based on the circumstances described above and aims to maintain good coverage of the third connection. [Means for solving the problem]

[0007] (1) A wiring board relating to the technology described herein comprises a first conductive portion consisting of a part of a first conductive film, a first connecting portion consisting of a part of the first conductive film and connected to the first conductive portion, a first insulating film disposed on the upper side of the first conductive film, a second conductive portion consisting of a part of a second conductive film disposed on the upper side of the first insulating film, a second connecting portion consisting of a part of the second conductive film and connected to the second conductive portion, a second insulating film disposed on the upper side of the second conductive film, and a third connecting portion consisting of a part of a third conductive film disposed on the upper side of the second insulating film, wherein the second connecting portion The connecting portion is arranged overlapping at least a part of the first connecting portion, the second connecting portion is provided with a first opening that overlaps with the first connecting portion, the third connecting portion is arranged overlapping with the second connecting portion and the first opening, the first insulating film is provided with a first contact hole at a position communicating with the first opening, and the second insulating film is provided with a second contact hole at a position communicating with both the first opening and the first contact hole, and overlapping with both the second connecting portion and the third connecting portion.

[0008] (2) In addition to (1) above, the wiring board may also be provided such that the second contact hole is located over a wider area than the first connection portion in the second insulating film.

[0009] (3) In addition to (2) above, the wiring board may be such that the outer edge of the first connection portion overlaps with the opening edge of the first opening in the second connection portion.

[0010] (4) In addition to (3) above, the wiring board may be provided such that the opening edge of the second contact hole overlaps with the outer edge of the second connection portion.

[0011] (5) In addition to (3) or (4) above, the wiring board may have the first conductive portion in the shape of a strip extending in one direction, and the first connecting portion may extend parallel to the first conductive portion and have the same width as the first conductive portion.

[0012] (6) In addition to any of (3) to (5) above, the wiring board may have the same dimensions as the second connection when viewed in plan.

[0013] (7) A display device relating to the technology described herein comprises a wiring board as described in any of (1) to (6) above, and a counter board disposed opposite to the wiring board.

[0014] (8) In addition to (7) above, the display device further includes, on the wiring board, a display area on which an image is displayed and a non-display area on which the image is not displayed, and the non-display area of ​​the wiring board is provided with a display circuit section for displaying the image, and the display circuit section has a first wiring made of a part of the first conductive film and a second wiring made of a part of the second conductive film and connected to the first wiring, and the first wiring may be the first conductive part and the second wiring may be the second conductive part.

[0015] (9) In addition to (7) above, the display device includes, on the wiring board, a display area on which an image is displayed and a non-display area on which the image is not displayed, and the display area of ​​the wiring board is provided with a double-gate transistor, a gate wiring connected to the transistor, a first gate connection electrode connected to the transistor, a second gate connection electrode connected to the gate wiring and the first gate connection electrode, and a pixel electrode connected to the transistor, and the transistor has a first gate electrode made of a part of the first conductive film, a first gate insulating part made of a part of the first insulating film that overlaps with the first gate electrode, a semiconductor part made of a part of the semiconductor film disposed on the upper layer side of the first insulating film and that overlaps with the first gate insulating part, and a third insulating film disposed on the upper layer side of the semiconductor film that overlaps with the semiconductor part The gate comprises a second gate insulating portion consisting of a folded portion, and a second gate electrode consisting of a part of the second conductive film disposed on the upper layer side of the third insulating film and arranged superimposed on the second gate insulating portion, wherein the gate wiring consists of a part of the first conductive film and is connected to the first gate electrode, the first gate connection electrode consists of a part of the second conductive film and is connected to the second gate electrode and arranged superimposed on a part of the gate wiring, the second gate connection electrode consists of a part of the third conductive film and is arranged superimposed on the first gate connection electrode, the first gate electrode is the first conductive portion, the second gate electrode is the second conductive portion, the portion of the gate wiring superimposed on the first gate connection electrode is the first connection portion, the first gate connection electrode is the second connection portion, and the second gate connection electrode may be the third connection portion. [Effects of the Invention]

[0016] According to the technology described herein, good coverage of the third connection can be maintained. [Brief explanation of the drawing]

[0017] [Figure 1] Plan view of the liquid crystal panel, driver, and flexible substrate according to Embodiment 1 [Figure 2]Cross-sectional view of a liquid crystal panel, driver, and flexible substrate according to Embodiment 1 [Figure 3] Planar view showing the pixel arrangement of the liquid crystal panel according to Embodiment 1 [Figure 4] Planar view showing the connection structure of the first wiring and the second wiring included in the gate circuit portion provided in the non-display area of the array substrate constituting the liquid crystal panel according to Embodiment 1 [Figure 5] Cross-sectional view taken along the line v-v of FIG. 4 in the array substrate according to Embodiment 1 [Figure 6] Cross-sectional view taken along the line vi-vi of FIG. 4 in the array substrate according to Embodiment 1 [Figure 7] Cross-sectional view similar to FIG. 5 showing the state in which the first metal film is patterned in the first step included in the manufacturing method of the array substrate according to Embodiment 1 [Figure 8] Cross-sectional view similar to FIG. 5 showing the state in which the first insulating film is formed in the second step included in the manufacturing method of the array substrate according to Embodiment 1 [Figure 9] Cross-sectional view similar to FIG. 5 showing the state in which the second metal film is patterned in the third step included in the manufacturing method of the array substrate according to Embodiment 1 [Figure 10] Cross-sectional view similar to FIG. 5 showing the state in which the second insulating film is formed in the fourth step included in the manufacturing method of the array substrate according to Embodiment 1 [Figure 11] Cross-sectional view similar to FIG. 5 showing the state in which a photoresist film is formed on the first insulating film and then the photoresist film is patterned in the fourth step included in the manufacturing method of the array substrate according to Embodiment 1 [Figure 12] Cross-sectional view similar to FIG. 5 showing the state in which the first insulating film and the second insulating film are etched using the photoresist film as a mask in the fourth step included in the manufacturing method of the array substrate according to Embodiment 1 [Figure 13] Cross-sectional view similar to FIG. 5 showing the state in which the third metal film is patterned in the fifth step included in the manufacturing method of the array substrate according to Embodiment 1 [Figure 14] Planar view showing the vicinity of the TFT provided in the display area of the array substrate according to Embodiment 2 [Figure 15]Cross-sectional view of the array substrate according to Embodiment 2, along the xv-xv line in Figure 14. [Figure 16] Cross-sectional view of the array substrate according to Embodiment 2, along the xvi-xvi line in Figure 14. [Modes for carrying out the invention]

[0018] <Embodiment 1> Embodiment 1 will be explained with reference to Figures 1 to 13. In this embodiment, a liquid crystal display device 10 is illustrated. Note that parts of each figure show the X, Y, and Z axes, and each axis is drawn so that it corresponds to the direction shown in each figure. Also, the upper side of Figures 2, 5 to 13 is considered the front side, and the lower side of the same figure is considered the back side.

[0019] As shown in Figure 1, the liquid crystal display device 10 comprises at least a horizontally elongated rectangular liquid crystal panel (display device, display panel) 11 capable of displaying images, and a backlight device (illumination device) that irradiates the liquid crystal panel 11 with light for display purposes. The backlight device is positioned on the back side (rear side) of the liquid crystal panel 11 and includes a light source that emits white light (e.g., an LED) and an optical component that converts the light from the light source into planar light by applying an optical effect. The central part of the main surface of the liquid crystal panel 11 is designated as a display area AA where images are displayed. In contrast, the frame-like outer peripheral part of the main surface of the liquid crystal panel 11 surrounding the display area AA is designated as a non-display area NAA where images are not displayed.

[0020] As shown in Figure 1, a gate circuit section (display circuit section) 14 is provided in the non-display area NAA of the liquid crystal panel 11. A pair of gate circuit sections 14 are arranged so as to sandwich the display area AA from both sides in the X-axis direction. The gate circuit section 14 is provided in a strip-shaped area extending along the Y-axis direction. The gate circuit section 14 is for supplying scanning signals to the gate wiring 26, which will be described later, and is monolithically provided on the array substrate 21, which will be described later. The gate circuit section 14 is a GDM (Gate Driver Monolithic) circuit.

[0021] The liquid crystal panel 11 will be described with reference to Figure 2 in addition to Figure 1. As shown in Figures 1 and 2, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21 together. Of the pair of substrates 20 and 21, the front side is the opposing substrate 20, and the back side is the array substrate (wiring substrate) 21. Both the opposing substrate 20 and the array substrate 21 are formed by laminating various films on the inner surface of a glass substrate. A liquid crystal layer 22 containing liquid crystal molecules, which are substances whose optical properties change when an electric field is applied, is interposed between the pair of substrates 20 and 21. A sealing portion 23 is provided between the outer edges of the pair of substrates 20 and 21 to seal the liquid crystal layer 22. The sealing portion 23 is formed in the shape of a rectangular frame surrounding the liquid crystal layer 22. Polarizing plates 15 are attached to the outer surfaces of both substrates 20 and 21.

[0022] As shown in Figures 1 and 2, the opposing substrate 20 has a shorter short side dimension than the array substrate 21. The opposing substrate 20 is bonded to the array substrate 21 such that one end in the short side direction (Y-axis direction) is aligned with it. Therefore, the other end of the array substrate 21 in the short side direction is an exposed portion 21A that protrudes laterally from the opposing substrate 20. This exposed portion 21A is entirely a non-display area (NAA), and the driver 12 and flexible substrate 13 for supplying various signals are mounted on it.

[0023] The driver 12 consists of an LSI chip with an internal drive circuit. The driver 12 is mounted on the exposed portion 21A of the array substrate 21 using COG (Chip On Glass) mounting. The driver 12 processes various signals transmitted by the flexible substrate 13. As shown in Figures 1 and 2, the driver 12 is positioned adjacent to one side of the display area AA in the Y-axis direction, sandwiched between the flexible substrate 13 and the display area AA. The driver 12 has a horizontally elongated rectangular shape in its planar form. The driver 12 can supply various signals to source wiring 27 and the like provided on the array substrate 21. The flexible substrate 13 is constructed by forming a large number of wiring patterns on a substrate made of a synthetic resin material (e.g., polyimide resin) that has insulating and flexible properties. One end of the flexible substrate 13 is connected to the exposed portion 21A of the array substrate 21, and the other end is connected to an external circuit board (control board, etc.).

[0024] Next, the configuration of the display area AA on the array substrate 21 will be explained using Figure 3. As shown in Figure 3, at least TFTs (transistors, switching elements) 24 and pixel electrodes 25 are provided on the inner surface of the display area AA on the array substrate 21. Multiple TFTs 24 and pixel electrodes 25 are arranged in a matrix (arrangement) with spacing along the X-axis and Y-axis directions. Around these TFTs 24 and pixel electrodes 25, gate wiring (scanning wiring) 26 and source wiring (image wiring, signal wiring) 27 are arranged orthogonally (intersecting) with each other. Multiple gate wirings 26 extend along the X-axis direction and are arranged with spacing along the Y-axis direction. Multiple source wirings 27 extend along the Y-axis direction and are arranged with spacing along the X-axis direction. The TFT 24 includes a gate electrode 24A connected to the gate wiring 26, a source electrode 24B connected to the source wiring 27, a drain electrode 24C connected to the pixel electrode 25, and a semiconductor portion 24D made of semiconductor material connected to the source electrode 24B and the drain electrode 24C. The TFT 24 is driven based on a scanning signal supplied to the gate electrode 24A by the gate wiring 26. This scanning signal contains a potential higher than the threshold voltage of the TFT 24. As a result, a channel region is created in the semiconductor portion 24D, allowing charge to move between the source electrode 24B and the drain electrode 24C through the channel region. Therefore, the potential related to the image signal (data signal) supplied to the source electrode 24B by the source wiring 27 is supplied to the drain electrode 24C via the semiconductor portion 24D. As a result, the pixel electrode 25 is charged with the potential related to the image signal. The pixel electrode 25 is located in a region surrounded by the gate wiring 26 and the source wiring 27, and its planar shape is, for example, a vertically elongated, approximately rectangular shape.

[0025] Furthermore, the display area AA of the opposing substrate 20 is provided with multiple color filters at positions opposite to each pixel electrode 25 on the array substrate 21. The color filters consist of three colors, R (red), G (green), and B (blue), arranged repeatedly in a predetermined order, and together with the pixel electrodes 25, they constitute pixels of each color (red pixels, green pixels, and blue pixels). The three pixels of red, green, and blue constitute a display pixel capable of displaying a predetermined gradation of color. In addition, a light-shielding portion (black matrix) is formed between each color filter to prevent color mixing. Of both substrates 20 and 21, the innermost surface (uppermost layer) in contact with the liquid crystal layer 22 has an alignment film (not shown) formed on it to orient the liquid crystal molecules contained in the liquid crystal layer 22.

[0026] Next, the connection structure included in the gate circuit section 14 of the array substrate 21 will be explained using Figures 4 to 6. The gate circuit section 14 includes a shift register circuit that outputs a scanning signal at a predetermined timing, a buffer circuit for amplifying the scanning signal, and so on. Figure 4 shows a part of these circuits. As shown in Figure 4, the gate circuit section 14 has a first wiring (first conductive part) 28 and a second wiring (second conductive part) 29 that is located on a different layer from the first wiring 28 and is connected to the first wiring 28. The connection structure for connecting the first wiring 28 and the second wiring 29, which are located on different layers, is configured as follows. That is, this connection structure includes a first connection part 30 connected to the first wiring 28, a second connection part 31 connected to the second wiring 29, and a third connection part 32 connected to the first connection part 30 and the second connection part 31.

[0027] In order to explain the connection structure between the first wiring 28 and the second wiring 29, various films laminated on the glass substrate (substrate) 21GS of the array substrate 21 will be described using Figures 5 and 6. As shown in Figures 5 and 6, at least the following films are laminated on the glass substrate 21GS of the array substrate 21, in order from the bottom layer (glass substrate 21GS side): a first metal film (first conductive film) 33, a first insulating film 34, a second metal film (second conductive film) 35, a second insulating film 36, and a third metal film (third conductive film) 37. Of these, the first metal film 33 is shown in Figure 7, the second metal film 35 is shown in Figure 9, and the third metal film 37 is shown in Figure 13. In addition to the above films, the glass substrate 21GS of the array substrate 21 also has semiconductor films that constitute the semiconductor portion 24D of the TFT 24 and transparent electrode films that constitute the pixel electrodes 25.

[0028] The first metal film 33, the second metal film 35, and the third metal film 37 are all single-layer films made of one type of metal material or multilayer films or alloys made of different types of metal materials, thereby possessing conductivity and light-shielding properties. The first metal film 33 constitutes the gate wiring 26, the gate electrode 24A of the TFT 24, the first wiring 28, the first connection part 30, etc. The second metal film 35 constitutes the source wiring 27, the source electrode 24B and drain electrode 24C of the TFT 24, the second wiring 29, the second connection part 31, etc. The third metal film 37 constitutes the third connection part 32, etc. The first insulating film 34 and the second insulating film 36 are both types of inorganic materials (inorganic resin materials), such as SiO2 (silicon oxide, silicon oxide) and SiN x It consists of materials such as silicon nitride and is used as a single layer or multilayer film.

[0029] The connection structure between the first wiring 28 and the second wiring 29 will now be described in detail. First, the first wiring 28 is made of a part of the first metal film 33 and, as shown in Figure 4, is a strip extending along the Y-axis. The first connection portion 30, like the first wiring 28, is made of a part of the first metal film 33 and is connected to the end of the first wiring 28. The first connection portion 30 extends along the Y-axis parallel to the first wiring 28 and has the same width dimension as the line width of the first wiring 28. The first connection portion 30 has a vertically elongated rectangular shape in plan view.

[0030] The second wiring 29 is made of a part of the second metal film 35 and, as shown in Figure 4, is a strip extending along the X-axis direction. The second connecting portion 31, like the second wiring 29, is made of a part of the second metal film 35 and is connected to the end of the second wiring 29. The second connecting portion 31 has a vertically elongated rectangular shape in plan view and is generally similar in shape to the first connecting portion 30. The second connecting portion 31 is arranged to overlap the first connecting portion 30 when viewed in plan view. The central position of the second connecting portion 31 in the X-axis direction and the Y-axis direction coincides with the central position of the first connecting portion 30. The size of the second connecting portion 31 when viewed in plan view is larger than that of the first connecting portion 30. Therefore, the central portion of the second connecting portion 31 in the X-axis direction and the Y-axis direction overlaps the first connecting portion 30, while the outer peripheral portion surrounding the central portion does not overlap the first connecting portion 30. The outer circumference of the second connecting portion 31 surrounds the first connecting portion 30 around its entire circumference. As shown in Figures 5 and 6, the first insulating film 34 is interposed between the second connecting portion 31 and the superimposed first connecting portion 30.

[0031] The third connecting portion 32 is made up of a part of the third metal film 37, and as shown in Figure 4, its planar shape is a vertically elongated rectangle, and is generally similar in shape to the first connecting portion 30 and the second connecting portion 31. The third connecting portion 32 is arranged superimposed on the second connecting portion 31 when viewed in plane. The central position of the third connecting portion 32 in the X-axis and Y-axis directions coincides with the central position of the second connecting portion 31. The size of the third connecting portion 32 when viewed in plane is approximately the same as that of the second connecting portion 31. Therefore, the second connecting portion 31 and the third connecting portion 32 are arranged in a planar configuration in which they overlap each other almost entirely. The third connecting portion 32 also superimposes on the first connecting portion 30 when viewed in plane, and its positional relationship with the first connecting portion 30 when viewed in plane is the same as the positional relationship between the first connecting portion 30 and the second connecting portion 31 when viewed in plane. As shown in Figures 5 and 6, the third connection portion 32 has a second insulating film 36 interposed between it and the superimposed second connection portion 31.

[0032] As shown in Figures 4 to 6, the second connection portion 31 is provided with a first opening 31A at a position that overlaps with the first connection portion 30. The first opening 31A has a vertically elongated rectangular shape in plan view and is generally similar in shape to the first connection portion 30. The central position of the first opening 31A in the X-axis and Y-axis directions coincides with the central position of the first connection portion 30. The size of the first opening 31A when viewed in plan view is smaller than that of the first connection portion 30. Therefore, the first opening 31A is positioned to overlap with the central portion of the first connection portion 30 in the X-axis and Y-axis directions, and not to overlap with the outer peripheral portion surrounding the central portion. The first opening 31A is positioned to overlap with the central portion of the third connection portion 32 in the X-axis and Y-axis directions, and not to overlap with the outer peripheral portion surrounding the central portion.

[0033] As shown in Figures 5 and 6, the first insulating film 34 is provided with a first contact hole 34A that communicates with the first opening 31A. The first contact hole 34A has the same planar shape and size as viewed from above as the first opening 31A. In other words, the size of the first contact hole 34A as viewed from above is slightly smaller than that of the first connection portion 30. Therefore, the opening edge of the first contact hole 34A of the first insulating film 34 overlaps the outer peripheral edge of the first connection portion 30. Furthermore, the opening edge of the first contact hole 34A of the first insulating film 34 overlaps the opening edge of the first opening 31A in the second connection portion 31 over its entire circumference, and the inner surface of the first contact hole 34A is flush with the inner surface of the first opening 31A over its entire circumference.

[0034] As shown in Figures 4 to 6, the second insulating film 36 is provided with a second contact hole 36A that communicates with both the first opening 31A and the first contact hole 34A described above. The second contact hole 36A is positioned to overlap with the first connection portion 30, the second connection portion 31, and the third connection portion 32. The second contact hole 36A has a vertically elongated rectangular shape in plan view and is generally similar in shape to the first opening 31A and the first contact hole 34A. The central position of the second contact hole 36A in the X-axis and Y-axis directions coincides with the central position of the first opening 31A and the first contact hole 34A. The size of the second contact hole 36A when viewed in plan view is larger than that of the first opening 31A and the first contact hole 34A. The second connection portion 31 located on the lower layer side of the second insulating film 36 includes a portion that is exposed toward the upper layer side through the second contact hole 36A. Therefore, the third connection portion 32, located on the upper side of the second insulating film 36, is connected to the second connection portion 31 through the second contact hole 36A of the second insulating film 36. The third connection portion 32 is then connected to the first connection portion 30 through the first opening 31A, the first contact hole 34A, and the second contact hole 36A, which communicate with each other.

[0035] As described above, the first wiring 28 connected to the first connection portion 30 and the second wiring 29 connected to the second connection portion 31 are electrically connected via the third connection portion 32, as shown in Figures 4 to 6. As mentioned above, the second connection portion 31 is provided with a first opening 31A, so the third connection portion 32 is connected to the portion of the second connection portion 31 that surrounds the first opening 31A. Therefore, unlike in the conventional design, the outer edge of the second connection portion 31 and the opening edge of the second contact hole 36A in the second insulating film 36 do not intersect. This makes it less likely for the coverage of the third connection portion 32 to deteriorate, and thus less likely for the characteristics of the second wiring 29 connected to the second connection portion 31 to deteriorate.

[0036] As shown in Figures 4 to 6, the second insulating film 36 is provided with a second contact hole 36A that is wider than the first connection portion 30. Specifically, the size of the second contact hole 36A, when viewed in plan, is slightly larger than the first connection portion 30 and slightly smaller than the second connection portion 31. Therefore, the opening edge of the second contact hole 36A of the second insulating film 36 overlaps the outer edge of the second connection portion 31 over its entire circumference, whereas the opening edge of the second contact hole 36A does not overlap with the first connection portion 30. In this way, the opening edge of the second contact hole 36A in the second insulating film 36 does not overlap with the first connection portion 30, thus preventing it from riding up onto the outer edge of the first connection portion 30. This makes it possible to improve the coverage of the second insulating film 36 and the third connection portion 32, which are located above the first connection portion 30. Furthermore, since the second insulating film 36 is provided such that the opening edge of the second contact hole 36A overlaps with the outer peripheral edge of the second connection portion 31, the outer peripheral edge of the second connection portion 31 can be well protected by the second insulating film 36.

[0037] Furthermore, in this embodiment, as shown in Figures 4 to 6, the size of the first connection portion 30 is such that its outer peripheral edge overlaps with the opening edge of the first opening 31A in the second connection portion 31. This allows for a large margin (distance) M to be secured between the opening edge of the second contact hole 36A in the second insulating film 36 and the outer peripheral edge of the first connection portion 30. As a result, even if a misalignment occurs in the photomask used when patterning the second insulating film 36 during the manufacturing process, it becomes less likely that the opening edge of the second contact hole 36A in the second insulating film 36 will overlap with a part (outer edge) of the outer peripheral edge of the first connection portion 30.

[0038] Furthermore, in this embodiment, as shown in Figure 4, the first connection portion 30 is the same width as the parallel first wiring 28. Therefore, compared to the case where the first connection portion is wider than the first wiring 28, a larger margin M can be secured between the opening edge of the second contact hole 36A in the second insulating film 36 and the outer peripheral edge of the first connection portion 30.

[0039] Furthermore, in this embodiment, as shown in Figures 4 to 6, the third connecting portion 32 has the same size as the second connecting portion 31 when viewed in a plan view. Therefore, compared to the case where the third connecting portion is larger than the second connecting portion 31 when viewed in a plan view, the connection structure formed by the connection of the first connecting portion 30, the second connecting portion 31, and the third connecting portion 32 can be kept compact.

[0040] The liquid crystal panel 11 according to this embodiment has the structure described above, and its manufacturing method will now be explained. The manufacturing method of the liquid crystal panel 11 includes a counter substrate manufacturing process (CF substrate manufacturing process) for manufacturing the counter substrate 20, an array substrate manufacturing process (substrate manufacturing process) for manufacturing the array substrate 21, and a bonding process for bonding the manufactured counter substrate 20 and the array substrate 21 together. The array substrate manufacturing process will be described below.

[0041] The array substrate manufacturing process includes at least the following steps: a first step of depositing and patterning a first metal film 33; a second step of depositing a first insulating film 34; a third step of depositing and patterning a second metal film 35; a fourth step of depositing and patterning a second insulating film 36; and a fifth step of depositing and patterning a third metal film 37.

[0042] The term "patterning" used above refers to the processing of a film based on a general photolithography method. Specifically, a photoresist film is deposited on the film to be processed, the photoresist film is exposed using an exposure device through a photomask having a predetermined aperture pattern, the photoresist film is developed, and etching is performed through the developed photoresist film to process the film, i.e., pattern the film.

[0043] In the first step, a first metal film 33 is deposited on the glass substrate 21GS of the array substrate 21, as shown by the dashed line in Figure 7. The deposited first metal film 33 is patterned using the general photolithography method described above. Once the first metal film 33 is patterned, the portion of the first metal film 33 that is located in the non-display area NAA is provided with a first wiring 28 and a first connection portion 30, as shown in Figure 7 (see Figure 6). In addition, the portion of the first metal film 33 that is located in the display area AA is provided with a gate electrode 24A and a gate wiring 26 (see Figure 3).

[0044] In the second step, as shown in Figure 8, a first insulating film 34 is deposited on the first metal film 33. Subsequently, in the third step, a second metal film 35 is deposited on the first insulating film 34 as shown by the dashed line in Figure 9. The deposited second metal film 35 is patterned using a general photolithography method. Once the second metal film 35 is patterned, the portion of the second metal film 35 that is located in the non-display area NAA is provided with a second wiring 29 and a second connection portion 31, as shown in Figure 9 (see Figure 4). In addition, the portion of the second metal film 35 that is located in the display area AA is provided with a source electrode 24B, a drain electrode 24C, and a source wiring 27 (see Figure 3).

[0045] In the fourth step, as shown in Figure 10, a second insulating film 36 is deposited on the second metal film 35. The deposited second insulating film 36 is patterned using a general photolithography method. When patterning the second insulating film 36, first, a photoresist film PR made of a photosensitive material is deposited on the second insulating film 36, and then the photoresist film PR is exposed by an exposure apparatus through a photomask having a predetermined aperture pattern (see Figure 11). After exposure, when development is performed, the photosensitive or non-photosensitive portion of the photoresist film PR is dissolved by the developer, and the photoresist film PR is patterned as shown in Figure 11. In the non-visible region NAA, the patterned photoresist film PR has an aperture PR1 that overlaps with the entire area of ​​the first connection portion 30 and the central portion of the second connection portion 31 excluding the outer peripheral portion.

[0046] In the fourth step, the second insulating film 36 is etched through the photoresist film PR having the opening pattern described above, so that the portion of the second insulating film 36 exposed through the opening PR1 is removed, as shown in Figure 12. As a result, a second contact hole 36A is formed in the second insulating film 36 that communicates with the opening PR1 of the photoresist film PR. The second contact hole 36A exposes the second connection portion 31, which is made up of a part of the second metal film 35. Furthermore, in this etching, the portion of the first insulating film 34 located below the second insulating film 36 that overlaps with the first opening 31A of the second connection portion 31 is also removed. In other words, the first insulating film 34 is patterned using the second connection portion 31, which is made up of the second metal film 35, as a mask. As a result, a first contact hole 34A is formed in the first insulating film 34 that communicates with the first opening 31A of the second connection portion 31. The first contact hole 34A communicates with the second contact hole 36A through the first opening 31A, and exposes the first connecting portion 30, which is part of the first metal film 33.

[0047] In the fifth step, which follows the fourth step, a third metal film 37 is deposited on the second insulating film 36 as shown by the dashed line in Figure 13. The deposited third metal film 37 is patterned using a general photolithography method. Once the third metal film 37 is patterned, a third connection portion 32 is provided in the portion of the third metal film 37 that is located in the non-display area NAA, as shown in Figure 13. The third connection portion 32 is connected to the second connection portion 31 through the second contact hole 36A, and is also connected to the first connection portion 30 through the first contact hole 34A, the second contact hole 36A, and the first opening 31A.

[0048] As described above, the array substrate (wiring substrate) 21 of this embodiment comprises a first wiring (first conductive part) 28 made of a part of the first metal film (first conductive film) 33, a first connection part 30 made of a part of the first metal film 33 and connected to the first wiring 28, a first insulating film 34 disposed on the upper side of the first metal film 33, a second wiring (second conductive part) 29 made of a part of the second metal film (second conductive film) 35 disposed on the upper side of the first insulating film 34, a second connection part 31 made of a part of the second metal film 35 and connected to the second wiring 29, a second insulating film 36 disposed on the upper side of the second metal film 35, and a third metal film (third conductive film) 37 disposed on the upper side of the second insulating film 36. The device comprises a third connecting portion 32 consisting of a part, the second connecting portion 31 is arranged overlapping at least a part of the first connecting portion 30, the second connecting portion 31 is provided with a first opening 31A that overlaps with the first connecting portion 30, the third connecting portion 32 is arranged overlapping with the second connecting portion 31 and the first opening 31A, the first insulating film 34 is provided with a first contact hole 34A at a position communicating with the first opening 31A, and the second insulating film 36 is provided with a second contact hole 36A at a position communicating with both the first opening 31A and the first contact hole 34A, and overlapping with both the second connecting portion 31 and the third connecting portion 32.

[0049] The first connection portion 30 is connected to the third connection portion 32 through the first contact hole 34A of the first insulating film 34, the first opening 31A of the second connection portion 31, and the second contact hole 36A of the second insulating film 36. The second connection portion 31 is connected to the third connection portion 32 through the second contact hole 36A of the second insulating film 36. In this way, the first wiring 28 connected to the first connection portion 30 and the second wiring 29 connected to the second connection portion 31 are electrically connected via the third connection portion 32. As described above, since the second connection portion 31 is provided with the first opening 31A, the third connection portion 32 is connected to the portion of the second connection portion 31 that surrounds the first opening 31A. Therefore, unlike in the conventional design, the outer edge of the second connection portion 31 and the opening edge of the second contact hole 36A in the second insulating film 36 do not intersect. This makes it less likely that the coverage of the third connection part 32 will deteriorate, and therefore less likely that the characteristics of the second wiring 29 connected to the second connection part 31 will deteriorate.

[0050] Furthermore, the second insulating film 36 is provided with a second contact hole 36A that is wider than the first connection portion 30. In this way, the opening edge of the second contact hole 36A in the second insulating film 36 is not superimposed on the first connection portion 30 and does not ride up on the outer edge of the first connection portion 30. This makes it possible to improve the coverage of the second insulating film 36 and the third connection portion 32.

[0051] Furthermore, the size of the first connection portion 30 is such that its outer edge overlaps with the opening edge of the first opening 31A in the second connection portion 31. This ensures a large margin between the opening edge of the second contact hole 36A in the second insulating film 36 and the outer edge of the first connection portion 30. As a result, even if a misalignment occurs in the photomask used when patterning the second insulating film 36 during the manufacturing process, it becomes less likely that the opening edge of the second contact hole 36A in the second insulating film 36 will overlap with the outer edge of the first connection portion 30.

[0052] Furthermore, the second insulating film 36 is provided such that the opening edge of the second contact hole 36A overlaps with the outer edge of the second connection portion 31. In this way, the outer edge of the second connection portion 31 can be well protected by the second insulating film 36.

[0053] Furthermore, the first wiring 28 is in the shape of a strip extending in one direction, and the first connection portion 30 extends parallel to the first wiring 28 and has the same width as the first wiring 28. In this way, compared to the case where the first connection portion is wider than the first wiring 28, a larger margin can be secured between the opening edge of the second contact hole 36A in the second insulating film 36 and the outer edge of the first connection portion 30.

[0054] Furthermore, the third connecting portion 32 is made to be the same size as the second connecting portion 31 when viewed in a plan view. Compared to the case where the third connecting portion is larger than the second connecting portion 31 when viewed in a plan view, the connection structure formed by the connection of the first connecting portion 30, the second connecting portion 31, and the third connecting portion 32 can be kept compact.

[0055] Furthermore, the liquid crystal panel (display device) 11 according to this embodiment comprises the array substrate 21 described above and a counter substrate 20 arranged opposite the array substrate 21. With such a liquid crystal panel 11, it is less likely that the coverage of the third connection portion 32 will deteriorate, and it is less likely that the characteristics of the second wiring 29 connected to the second connection portion 31 will deteriorate, making it suitable for maintaining good display quality.

[0056] Furthermore, the array substrate 21 includes a display area AA where an image is displayed and a non-display area NAA where the image is not displayed. The non-display area NAA of the array substrate 21 is provided with a gate circuit section (display circuit section) 14 for displaying an image. The gate circuit section 14 has a first wiring 28 made of a part of the first metal film 33 and a second wiring 29 made of a part of the second metal film 35 and connected to the first wiring 28. The first wiring 28 is the first conductive part, and the second wiring 29 is the second conductive part. The gate circuit section 14 causes an image to be displayed in the display area AA. The first connection section 30, the second connection section 31, and the third connection section 32 are connected to enable conductivity between the first conductive part, the first wiring 28, and the second conductive part, the second wiring 29.

[0057] <Embodiment 2> Embodiment 2 will be described with reference to Figures 14 to 16. This Embodiment 2 shows the connection structure between the TFT 124 and the gate wiring 126. Note that redundant explanations of the structure, operation, and effects similar to those of Embodiment 1 described above will be omitted.

[0058] As shown in Figures 14 and 15, the TFT (transistor) 124 arranged in the display area AA of the array substrate 121 according to this embodiment has a double gate structure. That is, the gate electrode 124A of the TFT 124 includes a first gate electrode (first conductive part) 124A1 arranged on the lower layer side relative to the semiconductor part 124D, and a second gate electrode (second conductive part) 124A2 arranged on the lower layer side relative to the semiconductor part 124D. The first gate electrode 124A1 consists of a part of the first metal film 33 (see Figure 7) and is connected to the gate wiring 126. The second gate electrode 124A2 consists of a part of the second metal film 35 (see Figure 9) and is connected to the gate wiring 126 by a connection structure described later.

[0059] As shown in Figure 15, the films laminated on the glass substrate 121GS of the array substrate 121 according to this embodiment include, in addition to the films described in Embodiment 1, a semiconductor film disposed on the upper side of the first insulating film 134, a third insulating film 38 disposed on the upper side of the semiconductor film and below the second metal film 35 (see Figure 9), a fourth insulating film (planarization film) 39 disposed on the upper side of the second insulating film 136, and a first transparent electrode film disposed on the upper side of the fourth insulating film 39. The semiconductor film is made of an oxide semiconductor material and constitutes the semiconductor portion 124D of the TFT 124, etc. The third insulating film 38 is made of SiO2 or SiN, which are types of inorganic materials, similar to the first insulating film 134 and the second insulating film 136. x It consists of the above and is in the form of a single layer or a multilayer film.

[0060] The fourth insulating film 39 is made of an organic material (organic resin material) such as PMMA (acrylic resin). As shown in Figure 15, the fourth insulating film 39 made of organic material has a greater film thickness than any of the first insulating film 134, second insulating film 136, and third insulating film 38 made of inorganic material. Specifically, while the film thicknesses of the first insulating film 134, second insulating film 136, and third insulating film 38 made of inorganic material are, for example, several tens to several hundred nanometers, the film thickness of the fourth insulating film 39 is, for example, about 1 μm to 3 μm. A pixel contact hole 39A is provided in the fourth insulating film 39 at a position where it overlaps with the drain electrode 124C. The first transparent electrode film is made of a transparent electrode material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The first transparent electrode film constitutes the pixel electrode 125, etc. The pixel electrode 125, which is part of the first transparent electrode film, is partially superimposed on the pixel contact hole 39A and is connected to the drain electrode 124C through the pixel contact hole 39A.

[0061] Furthermore, as shown in Figure 15, a source contact hole 136B is provided in the second insulating film 136 at a position that overlaps with both the source electrode 124B and the semiconductor portion 124D of the TFT 124. The source electrode 124B is connected to the semiconductor portion 124D through the source contact hole 136B of the second insulating film 136. Similarly, a drain contact hole 136C is provided in the second insulating film 136 at a position that overlaps with both the drain electrode 124C and the semiconductor portion 124D of the TFT 124. The drain electrode 124C is connected to the semiconductor portion 124D through the drain contact hole 136C of the second insulating film 136.

[0062] The TFT 124 consists of a portion of the first insulating film 134 and has a first gate insulating portion 40 interposed between the first gate electrode 124A1 and the semiconductor portion 124D. The first gate insulating portion 40 consists of the portion of the first insulating film 134 that overlaps with the first gate electrode 124A1. The TFT 124 also consists of a portion of the third insulating film 38 and has a second gate insulating portion 41 interposed between the semiconductor portion 124D and the second gate electrode 124A2. The second gate insulating portion 41 consists of the portion of the third insulating film 38 that overlaps with the semiconductor portion 124D. The first gate electrode 124A1 and the second gate electrode 124A2 are supplied with a scanning signal containing a potential higher than the threshold voltage of the TFT 124 via the gate wiring 126. As a result, channel regions are generated in the upper and lower parts of the semiconductor portion 124D, which is superimposed on the first gate electrode 124A1 via the first gate insulator 40 and on the second gate electrode 124A2 via the second gate insulator 41. Charge can be moved between the source electrode 124B and the drain electrode 124C through these channel regions in the semiconductor portion 124D, so that the potential based on the image signal supplied from the source wiring 127 to the source electrode 124B is supplied from the drain electrode 124C to the pixel electrode 125. As described above, two channel regions are generated in the semiconductor portion 124D, so the charge mobility is high.

[0063] The connection structure between the second gate electrode 124A2 and the gate wiring 126, which constitute the TFT124, will now be described. As shown in Figures 14 and 16, this connection structure includes a first gate connection electrode (second connection portion) 42 connected to the second gate electrode 124A2 of the TFT124, and a second gate connection electrode (third connection portion) 43 connected to the gate wiring 126 and the first gate connection electrode 42. The first gate connection electrode 42 is made of a part of the second metal film 35 and is connected to the second gate electrode 124A2. Specifically, the dimensions of the first gate connection electrode 42 in the X-axis direction are approximately the same as those of the second gate electrode 124A2, and it extends from the second gate electrode 124A2 toward the gate wiring 126 along the Y-axis direction. The first gate connection electrode 42 is arranged superimposed on a part of the gate wiring 126 (the part adjacent to the first gate electrode 124A1 in the Y-axis direction). In the following, the portion of the gate wiring 126 that overlaps with the first gate connection electrode 42 will be referred to as the electrode overlap portion (first connection portion) 126A.

[0064] As shown in Figures 14 and 16, the second gate connection electrode 43 consists of a part of the third metal film 37 and is positioned on the upper side of the second insulating film 136. More specifically, the dimensions of the second gate connection electrode 43 in the X-axis direction are approximately the same as those of the second gate electrode 124A2 and the first gate connection electrode 42. Although it does not overlap with the second gate electrode 124A2, it overlaps with the first gate connection electrode 42. The central position of the second gate connection electrode 43 in the X-axis and Y-axis directions coincides with the central position of the first gate connection electrode 42. The size of the second gate connection electrode 43 when viewed in a plane is approximately the same as that of the first gate connection electrode 42. Therefore, the first gate connection electrode 42 and the second gate connection electrode 43 are arranged in a planar configuration in which they overlap each other almost entirely. The second gate connection electrode 43 is superimposed on the electrode superposition portion 126A in a planar view, and its positional relationship with the electrode superposition portion 126A in a planar view is the same as the positional relationship between the electrode superposition portion 126A and the first gate connection electrode 42 in a planar view. The second gate connection electrode 43 has a second insulating film 136 interposed between it and the superimposed first gate connection electrode 42.

[0065] As shown in Figures 14 to 16, the first gate connection electrode 42 is provided with a first opening 42A at a position that overlaps with the electrode overlap portion 126A. The first opening 42A has a horizontally elongated rectangular shape in plan view. The size of the first opening 42A when viewed in plan is smaller than that of the electrode overlap portion 126A. The first opening 42A is positioned to overlap the central portion of the electrode overlap portion 126A in the X-axis and Y-axis directions, and not to overlap with the outer peripheral portion surrounding the central portion. The first opening 42A is positioned to overlap the central portion of the second gate connection electrode 43 in the X-axis and Y-axis directions, and not to overlap with the outer peripheral portion surrounding the central portion.

[0066] As shown in Figures 14 and 16, the third insulating film 38 is provided with a third contact hole 38A that communicates with the first opening 42A. The planar shape and size of the third contact hole 38A are the same as those of the first opening 42A. The first insulating film 134 is provided with a first contact hole 134A that communicates with the first opening 42A and the third contact hole 38A. The planar shape and size of the first contact hole 134A are the same as those of the first opening 42A and the third contact hole 38A. The first contact hole 134A and the third contact hole 38A are arranged to overlap with both the electrode overlap portion 126A and the second gate connection electrode 43, similar to the first opening 42A.

[0067] As shown in Figures 14 to 16, the second insulating film 136 is provided with a second contact hole 136A that communicates with the first opening 42A, the first contact hole 134A, and the third contact hole 38A described above. The second contact hole 136A is positioned to overlap with the electrode overlap portion 126A, the first gate connection electrode 42, and the second gate connection electrode 43. The central position of the second contact hole 136A in the X-axis and Y-axis directions coincides with the central position of the first opening 42A, the first contact hole 134A, and the third contact hole 38A. The size of the second contact hole 136A when viewed in plan is larger than that of the first opening 42A, the first contact hole 134A, and the third contact hole 38A. The first gate connection electrode 42 located on the lower side of the second insulating film 136 includes a portion that is exposed toward the upper side through the second contact hole 136A. Therefore, the second gate connection electrode 43, located on the upper side of the second insulating film 136, is connected to the first gate connection electrode 42 through the second contact hole 136A of the second insulating film 36. The second gate connection electrode 43 is then connected to the electrode overlap portion 126A through the first opening 42A, the first contact hole 134A, the second contact hole 136A, and the third contact hole 38A, which are in communication with each other.

[0068] As described above, the gate wiring 126 connected to the electrode superposition portion 126A and the second gate electrode 124A2 connected to the first gate connection electrode 42 are electrically connected via the second gate connection electrode 43, as shown in Figures 14 to 16. As mentioned above, the first gate connection electrode 42 is provided with a first opening 42A, so the second gate connection electrode 43 is connected to the portion of the first gate connection electrode 42 that surrounds the first opening 42A. Therefore, unlike in the conventional design, the outer edge of the first gate connection electrode 42 and the opening edge of the second contact hole 136A in the second insulating film 136 do not intersect. This makes it less likely for the coverage of the second gate connection electrode 43 to deteriorate, and thus less likely for the characteristics of the TFT 124 having the second gate electrode 124A2 connected to the first gate connection electrode 42 to deteriorate.

[0069] As described above, according to the liquid crystal panel 11 of this embodiment, the array substrate 121 includes a display area AA on which an image is displayed and a non-display area NAA on which an image is not displayed. The display area AA of the array substrate 121 is provided with a double-gate type TFT (transistor) 124, gate wiring 126 connected to the TFT 124, a first gate connection electrode 42 connected to the TFT 124, a second gate connection electrode 43 connected to the gate wiring 126 and the first gate connection electrode 42, and a pixel electrode 125 connected to the TFT 124. The TFT 124 consists of a first gate electrode 124A1 made of a part of the first metal film 33, a first gate insulating portion 40 made of a part of the first insulating film 134 that overlaps with the first gate electrode 124A1, a semiconductor portion 124D made of a part of the semiconductor film arranged on the upper side of the first insulating film 134 and arranged overlapping with the first gate insulating portion 40, and a third insulating film 38 arranged on the upper side of the semiconductor film. The first gate has a second gate insulating portion 41 which is superimposed on the semiconductor portion 124D, and a second gate electrode 124A2 which is made of a part of the second metal film 35 which is arranged on the upper side of the third insulating film 38 and is superimposed on the second gate insulating portion 41. The gate wiring 126 is made of a part of the first metal film 33 and is connected to the first gate electrode 124A1, and the first gate connecting electrode 42 is made of a part of the second metal film 35 and is connected to the second gate electrode 124A2. The second gate connection electrode 43 is made of a part of the third metal film 37 and is arranged superimposed on the first gate connection electrode 42. The first gate electrode 124A1 is the first conductive part, the second gate electrode 124A2 is the second conductive part, the electrode superimposed part 126A of the gate wiring 126 that superimposes on the first gate connection electrode 42 is the first connection part, the first gate connection electrode 42 is the second connection part, and the second gate connection electrode 43 is the third connection part. The scanning signal transmitted by the gate wiring 126 is supplied to the first gate electrode 124A1 and also to the second gate electrode 124A2 via the second gate connection electrode 43.As a result, a channel region is created in the semiconductor portion 124D that is superimposed on the first gate electrode 124A1 via the first gate insulating portion 40 and on the second gate electrode 124A2 via the second gate insulating portion 41, thereby enabling the supply of signals to the pixel electrode 125. The electrode superimposition portion 126A, which is the first connection portion, the first gate connection electrode 42, which is the second connection portion, and the second gate connection electrode 43, which is the third connection portion, are connected, thereby enabling conductivity between the first conductive portion, the first gate electrode 124A1, and the second conductive portion, the second gate electrode 124A2.

[0070] <Other Embodiments> The technology disclosed herein is not limited to the embodiments described above in the description and drawings, but also includes, for example, the following embodiments.

[0071] (1) If the array substrates 21, 121 are provided with a switch circuit (SSD (Source Shared Driving) circuit) that distributes the image signal supplied from the driver 12 to a plurality of source wires 27, 127, the connection structure between the first wire 28 and the second wire 29 constituting the switch circuit may include a first connection part 30 connected to the first wire 28, a second connection part 31 connected to the second wire 29, and a third connection part 32 connected to the first connection part 30 and the second connection part 31 (see Figures 4 to 6).

[0072] (2) The connection structure between the first wiring 28 and the second wiring 29 that constitute a circuit other than the switch circuit described in (1) above may include a first connection part 30 connected to the first wiring 28, a second connection part 31 connected to the second wiring 29, and a third connection part 32 connected to the first connection part 30 and the second connection part 31 (see Figures 4 to 6).

[0073] (3) In (1) and (2) above, a gate driver may be mounted on the array substrates 21 and 121 instead of the gate circuit section 14.

[0074] (4) In the configuration described in Embodiment 1, the first wiring 28 may extend along the X-axis direction, or it may extend along a direction oblique to the X-axis direction and the Y-axis direction.

[0075] (5) In the configuration described in Embodiment 1, the second wiring 29 may extend along the Y-axis direction, or it may extend along the X-axis direction and a direction oblique to the Y-axis direction.

[0076] (6) In the configuration described in Embodiment 1, the third connecting portion 32 may be larger or smaller than the second connecting portion 31 when viewed in a plan view.

[0077] (7) In the configuration described in Embodiment 1, the TFT24 may be a bottom-gate type, a top-gate type, or a double-gate type similar to Embodiment 2.

[0078] (8) In the configuration described in Embodiment 2, a portion of the gate wiring 126 may constitute the first gate electrode 124A1, in which case the TFT 124 will be placed on the gate wiring 126. In this case, for example, the electrode overlap portion 126A can be provided by partially widening the gate wiring 126, and the first gate connection electrode 42 and the second gate connection electrode 43 can be placed adjacent to the gate wiring 126 in the Y-axis direction so as to overlap the electrode overlap portion 126A.

[0079] (9) In the configuration described in Embodiment 2, the second gate connection electrode 43 may be larger or smaller in size than the first gate connection electrode 42 when viewed in a planar view.

[0080] (10) The driver 12 may also be mounted on the flexible substrate 13 which is mounted on the array substrates 21 and 121 using the FOG (Film On Glass) method, or it may be mounted using the COF (Chip On Film) method.

[0081] (11) The planar shape of the liquid crystal panel 11 may be a vertically elongated rectangle, square, circle, semicircle, vertically elongated oval, ellipse, trapezoid, etc.

[0082] (12) The semiconductor film material provided on the array substrates 21, 121 may be amorphous silicon material, polycrystalline polysilicon material, etc.

[0083] (13) The display mode of the LCD panel 11 may be any of the following: FFS (Fringe Field Switching) mode, TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, etc.

[0084] (14) The display device may be something other than the liquid crystal panel 11 (such as an organic EL (Electro Luminescence) display panel) or an EPD (microcapsule electrophoretic display panel). [Explanation of Symbols]

[0085] 11...Liquid crystal panel (display device), 14...Gate circuit section (display circuit section), 20...Opposite substrate, 21,121...Array substrate (wiring substrate), 28...First wiring (first conductive part), 29...Second wiring (second conductive part), 30...First connection section, 31...Second connection section, 31A...First opening, 32...Third connection section, 33...First metal film (first conductive film), 34,134...First insulating film, 34A,134A...First contact hole, 35...Second metal film (second conductive film), 36,136...Second insulating film, 36A,136A...Second contact hole 37...Third metal film (third conductive film), 38...Third insulating film, 40...First gate insulating part, 41...Second gate insulating part, 42...First gate connecting electrode (second connecting part), 42A...First opening, 43...Second gate connecting electrode (third connecting part), 124...TFT (transistor), 124A1...First gate electrode (first conductive part), 124A2...Second gate electrode (second conductive part), 124D...Semiconductor part, 125...Pixel electrode, 126...Gate wiring, 126A...Electrode superposition part (first connecting part), AA...Display area, NAA...Non-display area

Claims

1. A first conductive portion consisting of a part of the first conductive film, A first connecting portion, which is made of a part of the first conductive film and connected to the first conductive portion, A first insulating film disposed on the upper layer side of the first conductive film, A second conductive portion consisting of a part of the second conductive film disposed on the upper layer side of the first insulating film, A second connecting portion, which is made of a part of the second conductive film and connected to the second conductive portion, A second insulating film disposed on the upper side of the second conductive film, The device comprises a third connecting portion which is a part of the third conductive film disposed on the upper side of the second insulating film, The second connecting portion is arranged to overlap at least a part of the first connecting portion, The second connecting portion is provided with a first opening that overlaps with the first connecting portion. The third connecting portion is arranged to overlap with the second connecting portion and the first opening, The first insulating film is provided with a first contact hole at a position communicating with the first opening. The wiring board is provided with a second contact hole in the second insulating film that communicates with both the first opening and the first contact hole, and that overlaps with both the second connection portion and the third connection portion.

2. The wiring board according to claim 1, wherein the second insulating film is provided such that the second contact hole is wider than the first connection portion.

3. The wiring board according to claim 2, wherein the first connection portion is sized such that its outer edge overlaps with the opening edge of the first opening in the second connection portion.

4. The wiring board according to claim 3, wherein the second insulating film is provided such that the opening edge of the second contact hole overlaps with the outer edge of the second connection portion.

5. The first conductive portion is in the shape of a strip extending in one direction, The wiring board according to claim 3 or claim 4, wherein the first connecting portion extends parallel to the first conductive portion and has the same width as the first conductive portion.

6. The wiring board according to claim 3 or claim 4, wherein the third connection portion has the same size as the second connection portion when viewed in a plan view.

7. A wiring board according to any one of claims 1 to 4, A display device comprising: a counter board arranged opposite to the aforementioned wiring board;

8. The aforementioned wiring board includes a display area where an image is displayed and a non-display area where the image is hidden. The non-display area of ​​the wiring board is provided with a display circuit section for displaying the image. The display circuit section includes a first wiring made of a part of the first conductive film and a second wiring made of a part of the second conductive film and connected to the first wiring. The first wiring is the first conductive part, The display device according to claim 7, wherein the second wiring is the second conductive part.

9. The aforementioned wiring board includes a display area where an image is displayed and a non-display area where the image is hidden. The display area of ​​the wiring board is provided with a double-gate transistor, gate wiring connected to the transistor, a first gate connection electrode connected to the transistor, a second gate connection electrode connected to the gate wiring and the first gate connection electrode, and a pixel electrode connected to the transistor. The transistor has a first gate electrode made of a part of the first conductive film, a first gate insulating portion made of a portion of the first insulating film that overlaps with the first gate electrode, a semiconductor portion made of a part of a semiconductor film disposed on the upper side of the first insulating film and that overlaps with the first gate insulating portion, a second gate insulating portion made of a portion of a third insulating film disposed on the upper side of the semiconductor film that overlaps with the semiconductor portion, and a second gate electrode made of a part of the second conductive film disposed on the upper side of the third insulating film and that overlaps with the second gate insulating portion. The gate wiring consists of a part of the first conductive film and is connected to the first gate electrode. The first gate connection electrode is made of a part of the second conductive film, connected to the second gate electrode, and arranged superimposed on a part of the gate wiring. The second gate connection electrode is made of a part of the third conductive film and is arranged superimposed on the first gate connection electrode. The first gate electrode is the first conductive part, The second gate electrode is the second conductive part, The portion of the gate wiring that overlaps with the first gate connection electrode is the first connection portion. The first gate connection electrode is the second connection portion, The display device according to claim 7, wherein the second gate connection electrode is the third connection portion.

Images