Manufacturing method for silicon carbide semiconductor devices

Abstract

This suppresses the inclusion of durable, degraded, and occluded MP defects. [Solution] The defect inspection unit 21 irradiates illumination light toward the epitaxial layer 2 and detects reflected light reflected by the epitaxial layer 2 and PL light generated according to defects present in the epitaxial layer 2, forms a reflection image based on the reflected light and a PL image based on the PL light, and determines defects including durable degradation blocked micropipe defects in which micropipe defects contained in the seed substrate 1 are blocked while the epitaxial layer 2 grows, based on the reflection image and the PL image. The characteristic inspection unit performs characteristic inspection on a SiC semiconductor device different from the SiC semiconductor device in which defects including durable degradation blocked micropipe defects are present.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a SiC semiconductor device composed of silicon carbide (hereinafter, also simply referred to as SiC).

Background Art

[0002] Conventionally, when manufacturing a SiC semiconductor device, it has been proposed to manufacture a SiC semiconductor device using a SiC wafer on which an epitaxial layer is grown on a seed substrate. And when manufacturing a SiC semiconductor device, for example, in Patent Document 1, an inspection method for irradiating illumination light to an epitaxial layer to determine defects in the epitaxial layer has been proposed.

[0003] Specifically, in this inspection method, the epitaxial layer is irradiated with first illumination light of visible light and second illumination light of ultraviolet light. And in this inspection method, a reflection image based on the reflected light of the first illumination light reflected by the epitaxial layer is acquired. Also, in this inspection method, a PL image based on photoluminescence (hereinafter, also simply referred to as PL) light generated according to the defects in the epitaxial layer is acquired by irradiating the second illumination light. And in this inspection method, based on the reflection image and the PL image, basal plane defects, carrot defects, through screw dislocation defects, through edge dislocation defects, micropipe (hereinafter, also simply referred to as MP) defects, etc. are determined.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Incidentally, when an epitaxial layer is grown on a seed substrate, if MP defects exist in the seed substrate, the epitaxial layer will have two types of MP defects: inherited MP defects, which are inherited from the seed substrate, and closed MP defects, which grow while closing existing MP defects. The inspection method described above identifies the inherited MP defects as MP defects.

[0006] However, our investigations have confirmed that if blocked MP defects, which were not previously considered a particular problem, are present, the characteristics may deteriorate over time (i.e., durability may deteriorate) due to leakage current, etc. Therefore, when manufacturing SiC semiconductor devices, it is desirable to eliminate blocked MP defects (hereinafter also referred to as durability-degrading blocked MP defects) that may degrade the characteristics.

[0007] In view of the above, the present invention aims to provide a method for manufacturing a SiC semiconductor device that can suppress the inclusion of durable degradation blockage MP defects that may degrade the characteristics of the device. [Means for solving the problem]

[0008] Claim 1 for achieving the above objective is a method for manufacturing a silicon carbide semiconductor device, comprising: preparing a seed substrate (1) made of silicon carbide; forming an epitaxial layer (2) made of silicon carbide on the seed substrate to constitute a silicon carbide wafer (3); and determining defects present in the epitaxial layer. In determining defects, illumination light is shone toward the epitaxial layer, and reflected light reflected by the epitaxial layer and photoluminescence light generated in accordance with defects present in the epitaxial layer are detected; a reflection image based on the reflected light and a photoluminescence image based on the photoluminescence light are formed; and based on the reflection image and the photoluminescence image, defects including durable degradation-blocked micropipe defects (4) in which micropipe defects contained in the seed substrate are blocked while the epitaxial layer grows are determined. In determining defects, if the area of ​​opacity in the photoluminescence image is greater than a predetermined amount, it is determined that durable degradation-blocked micropipe defects are present.

[0009] According to this method, it is possible to easily determine whether or not durable degradation blockage MP defects are present. Furthermore, by including SiC semiconductor devices that have been determined not to have durable degradation blockage MP defects, it is possible to manufacture SiC semiconductor devices in which the presence of durable degradation blockage MP defects is suppressed.

[0010] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]

[0011] [Figure 1] This is a schematic diagram showing the manufacturing system of the SiC manufacturing apparatus in the first embodiment. [Figure 2] This is a schematic diagram showing the configuration of the defect inspection unit. [Figure 3A] This figure shows a binarized visible image illustrating a durable, degraded, occluded MP defect. [Figure 3B]This is a diagram showing a binarized PL image indicating a durability degradation type closed MP defect. [Figure 4] This is a secondary electron image for explaining a durability degradation type closed MP defect. [Figure 5] This is a diagram showing the relationship between the drain voltage and the leakage current. [Figure 6] This is a diagram showing the white turbidity area and the leakage current ratio before and after the reverse bias test. [Figure 7A] This is a diagram showing the relationship between the pit depth and the white turbidity area in the manufacturing method of a conventional SiC semiconductor device and the pass / fail judgment. [Figure 7B] This is a diagram showing the relationship between the pit depth and the white turbidity area in the manufacturing method of the SiC semiconductor device in the first embodiment and the pass / fail judgment. [Figure 8] This is a flowchart showing the manufacturing process of the SiC semiconductor device.

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments of the present invention will be described based on the drawings. In each of the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

[0013] (First Embodiment) The manufacturing system of the SiC semiconductor device according to the first embodiment will be described while referring to FIGS. 1 and 2. As shown in FIG. 1, the manufacturing system of the SiC semiconductor device includes a manufacturing unit 10 and an inspection unit 20.

[0014] The manufacturing unit 10 includes a general configuration used for manufacturing the SiC semiconductor device. In this embodiment, it includes an epitaxial layer growth unit 11, an element formation unit 12, a division unit 13, etc.

[0015] The epitaxial layer growth section 11 is a section that forms the SiC wafer 3 by growing the epitaxial layer 2 on the seed substrate 1. The element formation section 12 is a section that forms a desired semiconductor element for each chip formation region in the SiC wafer 3, and is configured to include an ion implantation device, a heating device, and the like. The dicing section 13 is configured to include a dicing blade and the like, and is a section that dices the SiC wafer 3 along the dicing line between the chip formation regions into SiC semiconductor devices.

[0016] The inspection section 20 is configured to include a defect inspection section 21, a characteristic inspection section 22, and the like. The defect inspection section 21 is a section that determines the defects of the epitaxial layer 2. The characteristic inspection section 22 is a section that inspects the electrical characteristics of the SiC semiconductor device obtained by dicing the SiC wafer 3.

[0017] Here, the inspection of the electrical characteristics refers to the inspection of leakage current characteristics and switching characteristics, and does not include the high-temperature reverse bias test described later. Further, each of the sections 11 to 13 constituting the manufacturing section 10 and each of the sections 21 and 22 constituting the inspection section 20 may be integrated to form one device, or may be provided separately. Furthermore, although not described in detail, the manufacturing section 10 and the inspection section 20 are appropriately provided with a load port, a transfer robot, and the like.

[0018] Hereinafter, the configuration of the defect inspection section 21 of the present embodiment will be described while referring to FIG. 2. Note that the defect inspection section 21 of the present embodiment uses SICA88 manufactured by Lasertec Corporation, and determines defects using a reflection image and a PL image.

[0019] The defect inspection unit 21 is equipped with a light source 201, as shown in Figure 2. The light source 201 in this embodiment is composed of a mercury lamp or the like that can emit illumination light having wavelengths such as a first illumination light of visible light with a wavelength of 546 nm and a second illumination light of ultraviolet light with a wavelength of 313 nm, so that these wavelengths are irradiated onto the epitaxial layer 2. As will be described later, the defect inspection unit 21 uses the first illumination light to generate a reflection image and the second illumination light to generate a PL image. Note that the wavelengths of visible light and ultraviolet light are not limited to those mentioned above; for example, the visible light wavelength is selected from 380 to 830 nm, and the ultraviolet light wavelength is selected from 280 to 380 nm.

[0020] The light source 201 is equipped with a first optical fiber 202 for propagating illumination light. An optical fiber coupler 203 is connected to the output end of the first optical fiber 202, opposite to the light source 201. A second optical fiber 204 and a third optical fiber 205 are connected to the output end of the optical fiber coupler 203. The illumination light emitted from the light source 201 is then split into two by the optical fiber coupler 203: the first illumination light propagates through the second optical fiber 204 and is emitted, and the second illumination light propagates through the third optical fiber 205 and is emitted.

[0021] The first illumination light emitted from the second optical fiber 204 is incident on the first illumination light adjustment unit 206, where it is converted into polarized light and emitted to the half mirror 208. The first illumination light adjustment unit 206 is configured to include a filter that transmits light with a wavelength of 546 nm, a focusing lens, a slit, a polarizer, etc., and converts the first illumination light into linear polarized light before emission.

[0022] The second illumination light emitted from the third optical fiber 205 is incident on the second illumination light adjustment unit 207, where it is P-polarized and irradiated onto the epitaxial layer 2. The second illumination light adjustment unit 207 is configured to include a filter that transmits 313 nm wavelength light, a polarizer, a focusing lens, etc., and its components are arranged so that the P-polarized second illumination light is irradiated onto the epitaxial layer 2 at an incident angle equal to the Brewster angle. As a result, the second illumination light is less likely to be reflected from the surface of the epitaxial layer 2, and most of the second illumination light irradiated onto the epitaxial layer 2 penetrates into the interior of the epitaxial layer 2, making it easier to generate PL light corresponding to defects. Therefore, it is easier to generate high-intensity PL light, making it easier to create clear PL images.

[0023] The first illumination light emitted from the first illumination light adjustment unit 206 is reflected by the half mirror 208 and incident on the vibrating mirror 210, which functions as a scanning device, via the relay lens 209. The first illumination light is then reflected by the vibrating mirror 210 and incident on the differential interference optical system 215 via the relay lens 211, the first dichroic mirror 212, the relay lens 213, and the second dichroic mirror 214.

[0024] The first dichroic mirror 212 is positioned between the relay lens 211 and the relay lens 213, and is configured to reflect light with a wavelength of less than 390 nm and transmit light with a wavelength of 390 nm or more. As will be described later, a portion of the PL light generated in the epitaxial layer 2 is reflected by the first dichroic mirror 212 and incident on the third photodetector 233.

[0025] The second dichroic mirror 214 is positioned between the relay lens 213 and the differential interference optical system 215, and is configured to reflect light with a wavelength of 700 nm or more and transmit light with a wavelength of less than 700 nm. As will be described later, some of the PL light generated in the epitaxial layer 2 is reflected by the second dichroic mirror 214 and incident on the second photodetector 232.

[0026] The differential interference optical system 215, for example, uses a Nomarski prism. When the first illumination light reflected by the vibrating mirror 210 is incident, the incident linear first illumination light is converted into two sub-beams whose vibrating planes are orthogonal to each other. In this case, a phase difference of (2m+1)π / 2 is given between these two sub-beams, where m is a natural number. Therefore, it becomes possible to detect defects with height variations of several nm formed on the surface of the epitaxial layer 2 as a brightness image of light and dark. The shearing amount of the Nomarski prism is set to, for example, 2 μm. The differential interference optical system 215 is also positioned to be insertable and detachable from the optical path and is inserted into the optical path when capturing a confocal differential interference image of the epitaxial layer 2. In other cases, for example, when capturing a three-dimensional confocal image of the epitaxial layer or capturing a surface contour image of the epitaxial layer 2, the differential interference optical system 215 is removed from the optical path.

[0027] Two sub-beams emitted from the differential interference optical system 215 enter the objective lens 216. The objective lens 216 focuses the two incident line-shaped sub-beams and illuminates the epitaxial layer 2 located on the stage 217.

[0028] The stage 217 is on which a SiC wafer 3, on which an epitaxial layer 2 has been grown on a seed substrate 1, is placed. It is connected to a drive unit 218 and is displaceable in the planar direction of the SiC wafer 3 (i.e., the seed substrate 1). When performing defect inspection, the stage 217 is displaced by the drive unit 218 so that the entire surface of the epitaxial layer 2 is scanned by illumination light.

[0029] Furthermore, stage 217 is connected to position sensor 219. Position sensor 219 is connected to signal processing device 240, which will be described later, and transmits position information of stage 217 to signal processing device 240.

[0030] As described above, the epitaxial layer 2 is irradiated with a first visible light illumination and a second ultraviolet light illumination. When the first illumination light, with a wavelength of 536 nm, is irradiated onto the epitaxial layer 2, reflected light corresponding to the surface shape of the epitaxial layer 2 is generated. Specifically, if defects appear on the surface of the epitaxial layer 2 as irregularities of several nanometers to several hundred nanometers, a phase difference corresponding to the change in the height of the defects is introduced between the two sub-lights reflected from the surface of the epitaxial layer 2. As a result, two reflected sub-lights containing phase difference information corresponding to the height of the defects present on the surface of the epitaxial layer 2 are formed.

[0031] Furthermore, when a second illumination light with a wavelength of 313 nm is irradiated onto the epitaxial layer 2, the second illumination light penetrates into the interior of the epitaxial layer 2, generating PL light corresponding to the defects present inside the epitaxial layer 2.

[0032] The reflected light from the epitaxial layer 2 is then focused by the objective lens 216 and incident on the differential interference optical system 215. The differential interference optical system 215 then combines the light to form interference light that includes the height change of the epitaxial layer 2 surface as phase difference information, and this light is incident on the second dichroic mirror 214. For example, if there is a concave or convex defect of a few nanometers on the surface of the epitaxial layer 2, one of the two sub-beams incident on the surface of the epitaxial layer 2 scans over the defect, while the other sub-beam scans the normal surface. As a result, a phase difference corresponding to the height of the defect is introduced between the two sub-beams. Consequently, the defect appearing on the surface of the epitaxial layer 2 is detected as a brightness image.

[0033] Furthermore, the PL light emitted from the epitaxial layer 2 is focused by the objective lens 216, passes through the differential interference optical system 215, and enters the second dichroic mirror 214.

[0034] The second dichroic mirror 214 is configured to transmit light with wavelengths less than 700 nm and reflect light with wavelengths of 700 nm or more. Therefore, the reflected light passes through the second dichroic mirror 214, and the PL light with wavelengths of 700 nm or more is reflected by the second dichroic mirror 214 and incident on the second photodetector 232. The PL light with wavelengths of 700 nm or more refers to PL light generated by basal plane defects, stacking faults, and carrot defects.

[0035] The reflected light and PL light that have passed through the second dichroic mirror 214 are incident on the first dichroic mirror 212. The first dichroic mirror 212 is configured to reflect light with a wavelength of less than 390 nm and transmit light with a wavelength of 390 nm or more. Therefore, the reflected light passes through the first dichroic mirror 212, and the PL light with a wavelength of less than 390 nm is reflected by the first dichroic mirror 212 and incident on the third photodetector 233. Note that the PL light with a wavelength of less than 390 nm is PL light caused by band-edge emission.

[0036] The reflected light that has passed through the second dichroic mirror 214 is reflected by the vibrating mirror 210 and incident on the relay lens 209. In this case, the relay lens 209 acts as an imaging lens for the reflected light. The reflected light that has passed through the relay lens 209 then passes through the half mirror 208 and incident on the first light detection unit 231.

[0037] The first photodetector 231 consists of an analyzer, a positioner, a line sensor as an imaging device, an amplifier, etc., and generates a reflected image based on reflected visible light and outputs it to the signal processing device 240.

[0038] The second light detection unit 232 consists of an imaging lens, a line sensor as an imaging device, an amplifier, etc., and generates a first PL image based on PL light having a wavelength of 700 nm or more and outputs it to the signal processing device 240.

[0039] The third photodetector 233 is configured to include a band filter that transmits light with wavelengths in the range of 380 nm ± 5 nm and a line sensor as an imaging device, and generates a second PL image based on PL light with a wavelength of approximately 380 nm and outputs it to the signal processing device 240.

[0040] The signal processing device 240 is configured to include a CPU (not shown) and various storage units such as ROM, RAM, and non-volatile RAM. The signal processing device 240 performs various control operations by having the CPU read and execute programs from the various storage units. Various data used during program execution (e.g., initial values, lookup tables, maps, etc.) are pre-stored in the various storage units such as ROM. Furthermore, the various storage media such as ROM are non-transitional substantial storage media.

[0041] Specifically, the signal processing device 240 determines defects based on the reflected image and the PL image. In this embodiment, although not limited thereto, the signal processing device 240 converts each image signal input from the first to third photodetectors 231 to 233 into a digital signal to determine defects.

[0042] More specifically, the signal processing device 240 compares the luminance value of each pixel in the reflected image, the first PL image, and the second PL image with a reference luminance value to detect pixels that exhibit luminance values ​​outside the range of the reference luminance value, and maps these pixels to form a defect image. For example, a defect image in the reflected image is formed by mapping pixels that are outside the range of the reference luminance value. A defect image in the PL image is formed by mapping pixels with luminance exceeding the reference luminance value.

[0043] Furthermore, as described above, the signal processing device 240 also receives the position (i.e., address information) where the first illumination light and the second illumination light are irradiated from the position sensor 219. The signal processing device 240 then stores the positions where the first and second illumination lights were irradiated in association with the defect images in the reflected image, the defect images in the first PL image, and the defect images in the second PL image.

[0044] The signal processing device 240 determines defects based on the defect image in the reflected image, the defect image in the first PL image, and the defect image in the second PL image. In this embodiment, if a line-shaped defect image is detected in the first PL image and no defect image is detected in the reflected image, or if a pit-shaped defect image is detected, it is determined that a base plane defect exists. Furthermore, if a line-shaped defect image is detected in both the first PL image and the reflected image, it is determined that a carrot defect exists. In addition, if a light / dark defect image is detected in the reflected image and no defect image is detected in the first PL image, it is determined that a through-spirular dislocation defect or a through-edge dislocation defect exists. Furthermore, if a point-like brightness image (i.e., a concave pit) defect image is detected in the reflected image and a point-like high-brightness image defect image is detected in the second PL image, it is determined that a successor MP defect exists. Furthermore, if a block-shaped high-brightness image defect image, such as a triangle or trapezoid, is detected in the second PL image, it is determined that a stacking fault exists.

[0045] In this embodiment, in addition to the above-mentioned defects, durable degradation-induced blocked MP defects that have grown while blocking MP defects in the seed substrate 1 are also detected. Specifically, as shown in Figure 3A, if a point-like brightness image (i.e., a concave pit) is detected in the reflection image, and as shown in Figure 3B, if a spiderweb-like opacity is detected in the first PL image and the area of ​​the opacity is greater than a predetermined value, it is determined that a durable degradation-induced blocked MP defect 4 exists. Note that Figures 3A and 3B are images at the same magnification, and the area enclosed by the dotted line is the area affected by the durable degradation-induced blocked MP defect 4 (i.e., the opacity area).

[0046] Here, we will explain why we also make a determination regarding the durability degradation blockage MP defect 4, which was not previously considered a particular concern.

[0047] First, the inventors diligently investigated the reason why the durable degradation-causing MP defect 4 appears as a white haze in PL images. As shown in Figure 4, upon examining the cross-section of the area where the durable degradation-causing MP defect 4 is formed, it was confirmed that multiple basal plane dislocations (i.e., intrabasal plane defects) 6 exist in the thickness direction of the epitaxial layer 2. Therefore, as shown in Figure 3B, it is thought that the durable degradation-causing MP defect 4 appears as a spiderweb pattern in PL images due to the influence of each basal plane dislocation 6. Although intrabasal plane defects have been identifiable in the past, they were not recognized as defects that degrade durability.

[0048] Furthermore, the inventors conducted a reverse bias test at a high temperature of approximately 150°C as a durability test, and confirmed that the leakage current increased after the durability test, as shown in Figure 5. This is presumed to be due to the following reasons. Note that Figure 5 shows a cloudy area of ​​1000 μm². 2 The results of a high-temperature reverse bias test performed on a SiC semiconductor device containing the durability degradation blockage MP defect 4 described above are shown. In the case of a MOSFET, the high-temperature reverse bias test is performed by applying a voltage close to the device's breakdown voltage to the drain electrode in the gate-off state.

[0049] In other words, the MP defects in the seed substrate 1 are filled by the epitaxial layer 2, eliminating the void, but as shown in Figure 4, basal plane dislocations 6 are generated to relieve the strain. In this case, multiple basal plane dislocations 6 are formed in the thickness direction of the epitaxial layer 2, while also occurring along the plane direction of the epitaxial layer 2. When basal plane dislocations 6 occur in close proximity along the thickness direction of the epitaxial layer 2, stress is generated in the crystal between them, causing band distortion and creating a region with a locally narrow band gap.

[0050] Therefore, when a high-temperature reverse bias test is performed, depletion occurs in regions where many basal plane dislocations 6 exist, and an electric field is applied. In this case, a small leakage current is generated due to the interaction between the generated electric field and the region with a locally narrow band gap. If this leakage current continues for a long time, the avalanche phenomenon progresses at an accelerating rate while the crystal is destroyed, causing crystal fracture and ultimately device failure. Therefore, in order to improve the reliability of SiC semiconductor devices, it is preferable to also eliminate durable degradation-causing blockage MP defects 4.

[0051] Therefore, in this embodiment, durable degradation-resistant blocked MP defects 4 that have grown while blocking MP defects in the seed substrate 1 are also determined. However, as shown in Figure 6, according to the inventors' studies, even if durable degradation-resistant blocked MP defects 4 are present, if the opacity area shown in the PL image is 1000 μm 2 When the value is less than 1000 μm², it was confirmed that the leakage current does not increase easily even when a high-temperature reverse bias test is performed. In other words, when the opacity area shown in the PL image is 1000 μm² 2 It was confirmed that the reliability of the SiC semiconductor device does not decrease when the opacity area is less than 1000 μm². Therefore, in this embodiment, the opacity area is 1000 μm². 2 Any item meeting the above criteria will be classified as a durable deterioration blockage MP defect 4.

[0052] In other words, in this embodiment, as shown in Figures 7A and 7B, even in areas with shallow pit depth (i.e., depth of surface recesses), which were not a concern in the conventional method, a large area of ​​cloudiness is treated as a defect that reduces reliability. Note that the cloudiness area in Figure 6 is 1000 μm². 2 The above is just one example, and since it varies depending on the characteristics of the semiconductor device being formed, it is preferable to set it for each semiconductor device being formed. Also, the durable degradation-blocking MP defect 4 has a pit depth of less than 67 nm in the reflection image, for example.

[0053] The above describes the manufacturing system for SiC semiconductor devices in this embodiment. Next, a method for manufacturing a SiC semiconductor device using the above-described manufacturing system will be explained with reference to Figure 8. Below, an example of manufacturing a SiC semiconductor device by forming MOSFETs in each chip formation region of the SiC wafer 3 will be described. Furthermore, the handling of durable degradation blockage MP defects 4 will be mainly explained below.

[0054] First, in step S1, a seed substrate 1 made of SiC is prepared. For example, in this embodiment, a 6-inch seed substrate 1 is prepared that has 180 chip formation regions and contains several MP defects in total. Each chip formation region is demarcated by a dicing line.

[0055] Next, in step S2, the epitaxial layer 2 is grown on the seed substrate 1 in the epitaxial layer growth unit 11. In this case, various defects may be generated in the epitaxial layer 2, including inherited MP defects that take over from the MP defects of the seed substrate 1, and durable degradation-blocked MP defects 4 that grow while blocking the MP defects of the seed substrate 1.

[0056] Next, in step S3, the defect inspection unit 21 performs defect detection. In this embodiment, as described above, the defect inspection unit 21 irradiates the epitaxial layer 2 with visible light and ultraviolet light. The defect inspection unit 21 then uses the generated reflection image, first PL image, second PL image, and information on the position where the illumination light was irradiated to determine the defects present in each chip formation region. That is, it determines which SiC semiconductor device contains defects when it is divided into SiC semiconductor devices in step S5, which will be described later. In this embodiment, in addition to the defects that have been identified conventionally, durability degradation blockage MP defects 4 are also detected.

[0057] Next, in step S4, semiconductor elements are formed in each chip formation region in the element formation section 12. For example, in this embodiment, a part of the epitaxial layer 2 is used as a drift layer, and a diffusion layer is formed by ion implantation or the like to form a semiconductor element that functions as a MOSFET.

[0058] Subsequently, in step S5, the SiC wafer 3 is divided along the dicing line in the dividing section 13 to form a SiC semiconductor device.

[0059] Next, in step S6, it is determined whether or not each SiC semiconductor device has a defect. Specifically, since the presence or absence of a defect is determined for each location (i.e., each SiC semiconductor device) in step S3, it is determined whether or not there is a defect based on the result of step S3. In this case, the durable degradation occlusion MP defect 4 is also considered a defect, and SiC semiconductor devices that have a durable degradation occlusion MP defect are also determined to be defective. If it is determined that there is a defect (i.e., step S6: YES), it is discarded in step S7. In other words, SiC semiconductor devices that are determined to have a defect are discarded in step S7 without performing the characteristic inspection described later.

[0060] On the other hand, for SiC semiconductor devices that have been determined to be free of defects (i.e., step S6: NO), a characteristic test is performed in step S8. In other words, in this embodiment, a characteristic test is performed on SiC semiconductor devices that do not have any durable degradation blockage MP defects 4. Note that the characteristic test here is an inspection of leakage current characteristics and switching characteristics, etc., and a high-temperature reverse bias test is not performed.

[0061] In step S9, it is determined whether the SiC semiconductor device is a good product based on the characteristic inspection. If the SiC semiconductor device is determined to be a good product (i.e., step S9: YES), the shipment process is carried out in step S10. If the SiC semiconductor device is determined to be a defective product (i.e., step S9: NO), it is discarded in step S7.

[0062] According to the embodiment described above, characteristic testing is performed on a SiC semiconductor device different from the one containing the durable degradation blockage MP defect 4. Therefore, it is possible to suppress the inclusion of durable degradation blockage MP defect 4 in shipped SiC semiconductor devices, thereby improving the reliability of SiC semiconductor devices. Furthermore, since characteristic testing is not performed on SiC semiconductor devices containing durable degradation blockage MP defects, manufacturing efficiency can be improved.

[0063] (1) In this embodiment, a durable degradation blockage MP defect 4 is defined as a case where the opacity area in the PL image is greater than or equal to a predetermined area. Therefore, durable degradation blockage MP defects 4 can also be identified by the defect inspection unit 21, eliminating the need to prepare separate components and preventing the manufacturing system from becoming more complex. Furthermore, since a durable degradation blockage MP defect 4 is defined as a case where the opacity area in the PL image is greater than or equal to a predetermined area, durable degradation blockage MP defects 4 that do not reduce reliability are less likely to be excluded, thereby improving reliability while preventing a decrease in yield.

[0064] (Other embodiments) This disclosure is described in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and idea of ​​this disclosure.

[0065] For example, in the first embodiment described above, an example was described in which the illumination light from the light source 201 is split into visible light and ultraviolet light. However, in the first embodiment, a light source that emits visible light and a light source that emits ultraviolet light may be provided separately. Furthermore, in the first embodiment, ultraviolet light may be irradiated so that it is reflected by the surface of the epitaxial layer 2 and PL light is generated inside.

[0066] Furthermore, although the first embodiment described above explains an example in which a MOSFET is formed as the semiconductor element, a diode may also be formed as the semiconductor element. Even when a diode is formed, reliability can be improved by discarding the SiC semiconductor device in which the durable degradation blockage MP defect 4 is present.

[0067] Furthermore, in the first embodiment described above, an example was given in which components with a cloudy area of ​​a predetermined size or larger in the PL image were discarded as durable degradation blockage MP defects 4. However, if spiderweb-like cloudiness is observed in the PL image, components may be discarded as durable degradation blockage MP defects 4 regardless of the area. Even when manufacturing SiC semiconductor devices in this way, durable degradation blockage MP defects 4 that may degrade performance can be excluded, thus achieving the same effects as in the first embodiment.

[0068] The control unit (i.e., signal processing unit 240) and its method described herein may be implemented by a dedicated computer provided by configuring a processor and memory programmed to perform one or more functions embodied by a computer program. Alternatively, the control unit (i.e., signal processing unit 240) and its method described herein may be implemented by a dedicated computer provided by configuring a processor by one or more dedicated hardware logic circuits. Alternatively, the control unit (i.e., signal processing unit 240) and its method described herein may be implemented by one or more dedicated computers configured by a combination of a processor and memory programmed to perform one or more functions and a processor configured by one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by the computer on a computer-readable non-transitional tangible recording medium. [Explanation of symbols]

[0069] Type 1 board 2. Epitaxial layer 3 SiC wafers 4. Durable deterioration blockage MP defect 11 Epitaxial layer forming section 12 Element Forming Section 13 Division 21. Defect Inspection Department 22. Characteristics Testing Department

Claims

[Claim 1] A method for manufacturing a silicon carbide semiconductor device, Prepare a seed substrate (1) made of silicon carbide, A silicon carbide wafer (3) is constructed by forming an epitaxial layer (2) made of silicon carbide on the aforementioned seed substrate. The defect present in the epitaxial layer is determined, Determining the defects involves irradiating the epitaxial layer with illumination light and detecting the reflected light reflected by the epitaxial layer and the photoluminescence light generated in response to defects present in the epitaxial layer; forming a reflection image based on the reflected light and a photoluminescence image based on the photoluminescence light; and determining, based on the reflection image and the photoluminescence image, defects including durable degradation-resistant blocked micropipe defects (4) in which the epitaxial layer grows while micropipe defects contained in the seed substrate are blocked. A method for manufacturing a silicon carbide semiconductor device, wherein, by determining the aforementioned defect, it is determined that the durable degradation blockage micropipe defect exists if the area of ​​opacity in the photoluminescence image is greater than or equal to a predetermined value.

Images