Simultaneous bidirectional transmission and reception device and communication system

Abstract

A compact, power-efficient simultaneous bidirectional transceiver is highly anticipated. [Solution] The simultaneous bidirectional transceiver includes a transmit driver DRV connected to the first terminal B1 of the first transmission line TL1, and a receive amplifier RA connected to the first terminal B1. The transmit driver DRV is a differential driver including a first output terminal D1 that outputs a first signal and a second output terminal D2 that outputs a second signal (-BC) that is in opposite phase to the first signal. The receive amplifier RA includes a first input terminal T1 connected to the first terminal B1 and the first output terminal D1, a second input terminal T2 connected to a reference potential Vcm, a third input terminal T3 connected to the second output terminal D2, and a fourth input terminal T4 connected to a reference potential Vcm. The receive amplifier RA outputs a signal obtained by adding the signal input to the first input terminal T1 and the signal input to the third input terminal T3.

Description

[Technical Field]

[0001] This disclosure relates to a simultaneous bidirectional transceiver and communication system. [Background technology]

[0002] In simultaneous bidirectional (SBD) communication, signals are transmitted and received simultaneously in both directions. The transmitting and receiving device employs a configuration such that the receiver does not receive the transmission signal sent from its own transmitter. For example, the transmission signal output by its own transmitter is removed from the received signal entering the receiver. Patent documents 1 to 3 disclose such transmitting and receiving devices. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent No. 10804956 [Patent Document 2] U.S. Patent No. 10484042 [Patent Document 3] U.S. Patent Application Publication No. 2023 / 024661 [Overview of the project] [Problems that the invention aims to solve]

[0004] One possible configuration for removing the transmitted signal from the received signal is to use a differential driver and a common-mode driver. That is, the first signal is transmitted from the differential driver of the first transceiver to the second transceiver, and the second signal is transmitted from the common-mode driver of the second transceiver to the first transceiver. However, this configuration requires the adoption of a complex circuit configuration, such as the provision of dummy circuits, which tends to increase the device area and power consumption.

[0005] A compact, power-efficient simultaneous bidirectional transceiver is highly anticipated. [Means for solving the problem]

[0006] The first simultaneous bidirectional transmitting and receiving device according to this disclosure comprises a transmitting driver connected to a first terminal of a first transmission line and a receiving amplifier connected to the first terminal, wherein the transmitting driver is a differential driver including a first output terminal that outputs a first signal and a second output terminal that outputs a second signal that is in opposite phase to the first signal, and the receiving amplifier includes a first input terminal connected to the first terminal and the first output terminal, a second input terminal connected to a reference potential, a third input terminal connected to the second output terminal and a fourth input terminal connected to a reference potential, wherein the receiving amplifier has an output terminal that outputs a signal that is proportional to (V1-V2)+(V3-V4) when a first voltage V1 is input to the first input terminal, a second voltage V2 is input to the second input terminal, a third voltage V3 is input to the third input terminal and a fourth voltage V4 is input to the fourth input terminal.

[0007] The second simultaneous bidirectional transmitting and receiving device according to this disclosure comprises a transmitting driver connected to a first terminal of a first transmission line and a receiving amplifier connected to the first terminal, wherein the transmitting driver is an in-phase driver including a first output terminal that outputs a first signal and a second output terminal that outputs a second signal which is in phase with the first signal, and the receiving amplifier includes a first input terminal connected to the first terminal and the first output terminal, a second input terminal connected to the second output terminal, a third input terminal connected to a reference potential and a fourth input terminal connected to a reference potential, wherein the receiving amplifier has an output terminal that outputs a signal which is proportional to (V1-V2)-(V3-V4) when a first voltage V1 is input to the first input terminal, a second voltage V2 is input to the second input terminal, a third voltage V3 is input to the third input terminal and a fourth voltage V4 is input to the fourth input terminal.

[0008] The third simultaneous bidirectional transmitting and receiving device according to this disclosure comprises a transmitting driver connected to a first terminal of a first transmission line and a second terminal of a second transmission line, and a receiving amplifier connected to the first terminal and the second terminal, wherein the transmitting driver is a differential driver including a first output terminal that outputs a first signal and a second output terminal that outputs a second signal that is in opposite phase to the first signal, and the receiving amplifier includes a first input terminal connected to the first terminal and the first output terminal, a second input terminal connected to a reference potential, a third input terminal connected to the second terminal and the second output terminal, and a fourth input terminal connected to a reference potential, wherein the receiving amplifier has an output terminal that outputs a signal that is proportional to (V1-V2)+(V3-V4) when a first voltage V1 is input to the first input terminal, a second voltage V2 is input to the second input terminal, a third voltage V3 is input to the third input terminal, and a fourth voltage V4 is input to the fourth input terminal.

[0009] The fourth simultaneous bidirectional transmitting and receiving device according to this disclosure comprises a transmitting driver connected to a first terminal of a first transmission line and a second terminal of a second transmission line, and a receiving amplifier connected to the first terminal and the second terminal, wherein the transmitting driver is an in-phase driver including a first output terminal that outputs a first signal and a second output terminal that outputs a second signal that is in phase with respect to the first signal, and the receiving amplifier includes a first input terminal connected to the first terminal and the first output terminal, a second input terminal connected to the second terminal and the second output terminal, a third input terminal connected to a reference potential, and a fourth input terminal connected to a reference potential, wherein the receiving amplifier has an output terminal that outputs a signal that is proportional to (V1-V2)-(V3-V4) when a first voltage V1 is input to the first input terminal, a second voltage V2 is input to the second input terminal, a third voltage V3 is input to the third input terminal, and a fourth voltage V4 is input to the fourth input terminal.

[0010] The communication system relating to this disclosure comprises a first or second simultaneous bidirectional transceiver and a second simultaneous bidirectional transceiver that communicates with the first simultaneous bidirectional transceiver and a second transceiver that communicates with the first simultaneous bidirectional transceiver and a second transceiver.

[0011] The communication system according to this disclosure comprises a fourth simultaneous bidirectional transceiver and a second simultaneous bidirectional transceiver that communicates with the first simultaneous bidirectional transceiver, wherein the terminal opposite to the first terminal of the first transmission line is designated as the third terminal, and the terminal opposite to the second terminal of the second transmission line is designated as the fourth terminal, and the second simultaneous bidirectional transceiver comprises a second transmit driver connected to the third terminal, and a second receive amplifier connected to the third and fourth terminals, wherein the second transmit driver is a differential driver including a first output terminal that outputs a third signal and a second output terminal that outputs a fourth signal that is inverse phase with respect to the third signal, and the second receive amplifier is The second receiving amplifier includes a first input terminal connected to the third terminal and the first output terminal of the second transmitting driver, a second input terminal connected to a reference potential, a third input terminal connected to the fourth terminal and the second output terminal of the second transmitting driver, and a fourth input terminal connected to a reference potential. The second receiving amplifier has an output terminal that outputs a signal proportional to (V1'-V2')+(V3'-V4') when a first voltage V1' is input to the first input terminal of the second receiving amplifier, a second voltage V2' is input to the second input terminal of the second receiving amplifier, a third voltage V3' is input to the third input terminal of the second receiving amplifier, and a fourth voltage V4' is input to the fourth input terminal of the second receiving amplifier. [Effects of the Invention]

[0012] This allows us to provide a compact, high-power simultaneous bidirectional transceiver. [Brief explanation of the drawing]

[0013] [Figure 1] Figure 1 is a circuit diagram of the first communication system. [Figure 2] Figure 2 is a circuit diagram of the second communication system. [Figure 3] Figure 3 is a circuit diagram of the third communication system. [Figure 4] Figure 4 is a circuit diagram of the fourth communication system. [Figure 5] Figure 5 is a circuit diagram of the fifth communication system. [Figure 6]FIG. 6 is a diagram showing a first type of receiving amplifier. [Figure 7] FIG. 7 is a circuit diagram of the first type of receiving amplifier. [Figure 8] FIG. 8 is a circuit diagram of an improved first type of receiving amplifier. [Figure 9] FIG. 9 is a diagram showing a second type of receiving amplifier. [Figure 10] FIG. 10 is a circuit diagram of the second type of receiving amplifier. [Figure 11] FIG. 11 is a circuit diagram of an improved second type of receiving amplifier. [Figure 12] FIG. 12 is a circuit diagram of a transceiver having a switch group on the input side of the receiving amplifier. [Figure 13] FIG. 13 is a circuit diagram of a transceiver provided with a receiving amplifier having a 1-bit DAC (digital / analog converter). [Figure 14] FIG. 14 is a circuit diagram of the receiving amplifier. [Figure 15] FIG. 15 is a circuit diagram of an improved receiving amplifier. [Figure 16] FIG. 16 is a circuit diagram of a receiving amplifier provided with a plurality of receiving amplifiers. [Figure 17] FIG. 17 is a circuit diagram of a receiving amplifier provided with a plurality of NMOS field effect transistors. [Figure 18] FIG. 18 is a circuit diagram of an improved receiving amplifier. [Figure 19] FIG. 19 is a circuit diagram of a receiving amplifier provided with a plurality of PMOS field effect transistors. [Figure 20] FIG. 20 is a circuit diagram of an improved receiving amplifier. [Figure 21] FIG. 21 is a circuit diagram of an adder amplifier. [Figure 22] FIG. 22 is a circuit diagram of the potential output circuit VCM. [Figure 23] FIG. 23 is a circuit diagram of the transmitter (FIG. 23(A)) and a circuit diagram of the potential output circuit of the receiving amplifier (FIG. 23(B)). [Figure 24]Figure 24 is a circuit diagram of the potential output circuit of the receiving amplifier. [Figure 25] Figure 25 shows the circuit diagram of the transmitter (Figure 25(A)) and the circuit diagram of the potential output circuit in the receiving amplifier (Figure 25(B)). [Figure 26] Figure 26 shows the circuit diagram of the transmitter (Figure 26(A)) and the circuit diagram of the potential output circuit in the receiving amplifier (Figure 26(B)). [Figure 27] Figure 27 shows a differential amplifier that outputs the difference between output signals (Voutp, Voutn). [Modes for carrying out the invention]

[0014] Various exemplary embodiments will be described in detail below with reference to the drawings. In each drawing, the same or corresponding parts will be denoted by the same reference numerals, and redundant explanations will be omitted.

[0015] Figure 1 is a circuit diagram of the first communication system.

[0016] The communication system comprises a first transceiver (TRB) for backward transmission and reception, and a second transceiver (TRF) for forward transmission and reception. Each transceiver is a simultaneous bidirectional (SBD) transceiver. The transceiver (TRB) and the transceiver (TRF) are connected via a first transmission line TL1. The first transmission line TL1 provides a single-ended signaling communication method. In single-ended signaling, the potential of the signal transmitted through the first transmission line TL1 fluctuates relative to a fixed potential such as ground potential.

[0017] Differential signaling is a known communication method that uses two transmission lines. In differential signaling, pairs of signals with complementary components are transmitted over two transmission lines. The signal transmitted from the forward side is FC, and the signal transmitted from the backward side is BC. The signals with opposite phases to these signals are -FC and -BC. The positive and negative phase signals can have opposite positive and negative values ​​with respect to the reference potential. In practice, the signal FC transmitted from the forward side has a common reference potential Vcm superimposed on it, and the signal BC transmitted from the backward side also has a reference potential Vcm superimposed on it. Since the reference potential Vcm is a DC component, the DC component is removed by capacitors (CB1, CF1) provided in the signal transmission path. The reference potential Vcm on the transceiver (TRB) side (potential output circuit VCM) and the reference potential Vcm on the transceiver (TRF) side (potential output circuit VCM) are independent of each other. Therefore, these reference potentials can be controlled independently. If necessary, the reference potential Vcm on the transceiver (TRB) side will be denoted as Vcm_b, and the reference potential Vcm on the transceiver (TRF) side will be denoted as Vcm_f.

[0018] The transceiver (TRB) is equipped with a transmit driver DRV connected to the first terminal B1 of the first transmission line TL1. The transmit driver DRV of the transceiver (TRB) is a differential driver and has a first output terminal D1 that outputs a first signal (+BC+Vcm_b) and a second output terminal D2 that outputs a second signal (-BC+Vcm_b) that is in the opposite phase to the first signal (BC). The transmit driver DRV is equipped with one or two input terminals, and digital signals such as video signals, audio signals, or data signals can be input to these input terminals, but analog signals may also be input.

[0019] The first output terminal D1 of the transmit driver DRV of the transceiver (TRB) is connected to the first terminal B1 via the first capacitor CB1. The second output terminal D2 of the transmit driver DRV of the transceiver (TRB) is connected to the second terminal B2 via the second capacitor CB2. In this example, the second terminal B2 is not connected to the transmission line, but it can be connected to ground potential via the first load resistor RB.

[0020] The transceiver (TRB) includes a receiving amplifier RA connected to the first terminal B1 of the first transmission line TL1. The receiving amplifier RA includes a first input terminal T1, a second input terminal T2, a third input terminal T3, and a fourth input terminal T4.

[0021] The first input terminal T1 of the receiving amplifier RA of the transceiver (TRB) is connected to the first terminal B1 via the first capacitor CB1. The first input terminal T1 of the receiving amplifier RA of the transceiver (TRB) is also connected to the first output terminal D1 of the transmitting driver DRV.

[0022] The second input terminal T2 of the receiving amplifier RA of the transceiver (TRB) is connected to the reference potential Vcm_b.

[0023] The third input terminal T3 of the receiving amplifier RA of the transceiver (TRB) is connected to the second terminal B2 via the second capacitor CB2. The third input terminal T3 of the receiving amplifier RA of the transceiver (TRB) is also connected to the second output terminal D2 of the transmitting driver DRV.

[0024] The fourth input terminal T4 of the receiving amplifier RA of the transceiver (TRB) is connected to the reference potential Vcm_b.

[0025] The receiving amplifier RA has a first input terminal T1, a second input terminal T2, a third input terminal T3, a fourth input terminal T4, a first output terminal (first output signal (Voutn)), and a second output terminal (second output signal (Voutp)). For simplicity, in the following explanation, the amplification factor of the receiving amplifier RA will be assumed to be 1. When the first voltage V1 is input to the first input terminal T1, the second voltage V2 is input to the second input terminal T2, the third voltage V3 is input to the third input terminal T3, and the fourth voltage V4 is input to the fourth input terminal T4, the voltage between the output terminals (Vout) will be a signal proportional to Vout = Voutp - Voutn = [(V1 - V2) + (V3 - V4)], assuming the amplification factor of the receiving amplifier RA is 1. In this example, the first voltage V1 = FC + BC + Vcm_b, the second voltage V2 = Vcm_b, the third voltage V3 = -BC + Vcm_b, and the fourth voltage V4 = Vcm_b.

[0026] Therefore, the voltage between the output terminals (Vout) is a signal proportional to Vout = (FC + BC + Vcm_b) - Vcm_b + (-BC + Vcm_b) - Vcm_b = FC. Figure 27 shows a differential amplifier DA that outputs the difference between the output signals (Voutp, Voutn). Vout can be obtained by inputting the output signals Voutp and Voutn into the differential amplifier DA. In the following explanation as well, the difference between the second output signal (Voutp) and the first output signal (Voutn) can be obtained by using a differential amplifier.

[0027] The reference potential Vcm_b can be generated by the potential output circuit VCM. The second input terminal T2 and the fourth input terminal T4 are connected to the power supply potential Vdd via the potential output circuit VCM. When a termination resistor is provided at the end of the first transmission line TL1, the termination resistor has the function of suppressing reflection of the received signal. The termination resistor has a resistance value equal to the characteristic impedance of the transmission line, and impedance matching can be performed.

[0028] The structure of the transceiver (TRF) is identical to that of the transceiver (TRB).

[0029] The transceiver (TRF) is equipped with a transmit driver DRV connected to the third terminal F1 of the first transmission line TL1. The transmit driver DRV of the transceiver (TRF) is a differential driver and has a first output terminal D1 that outputs a first signal (+FC+Vcm_f) and a second output terminal D2 that outputs a second signal (-FC+Vcm_f) that is in the opposite phase to the first signal (FC+Vcm_f). The transmit driver DRV is equipped with one or two input terminals, and digital signals such as video signals, audio signals, or data signals can be input to these input signals, but analog signals may also be input. The reference potential Vcm_b and the reference potential Vcm_f may be the same reference potential Vcm, or they may be different reference potentials.

[0030] The first output terminal D1 of the transmit driver DRV of the transceiver (TRF) is connected to the third terminal F1 via the third capacitor CF1. The second output terminal D2 of the transmit driver DRV of the transceiver (TRF) is connected to the fourth terminal F2 via the fourth capacitor CF2. In this example, the fourth terminal F2 is not connected to the transmission line, but it can be connected to ground potential via the second load resistor RF.

[0031] The transceiver (TRF) is equipped with a receiving amplifier RA connected to the third terminal F1 of the first transmission line TL1. The receiving amplifier RA of the transceiver (TRF) is also equipped with a first input terminal T1, a second input terminal T2, a third input terminal T3, a fourth input terminal T4, a first output terminal (first output signal (Voutn)), and a second output terminal (second output signal (Voutp)).

[0032] The first input terminal T1 of the receiving amplifier RA of the transceiver (TRF) is connected to the third terminal F1 via the third capacitor CF1. This first input terminal T1 is also connected to the first output terminal D1 of the transmitting driver DRV.

[0033] The second input terminal T2 of the receiving amplifier RA of the transceiver (TRF) is connected to the reference potential Vcm_f.

[0034] The third input terminal T3 of the receiving amplifier RA of the transceiver (TRF) is connected to the fourth terminal F2 via the fourth capacitor CF2. This third input terminal T3 is also connected to the second output terminal D2 of the transmitting driver DRV.

[0035] The fourth input terminal T4 of the transceiver (TRF) is connected to the reference potential Vcm_f.

[0036] The receiving amplifier RA on the left has output terminals that output a first output signal (Voutn) and a second output signal (Voutp). The difference between these output signals is the output signal Vout. When the first voltage V1 is input to the first input terminal T1 of the receiving amplifier RA on the left, the second voltage V2 is input to the second input terminal T2, the third voltage V3 is input to the third input terminal T3, and the fourth voltage V4 is input to the fourth input terminal T4, the voltage between the output terminals (Vout) will be a signal proportional to Vout = Voutp - Voutn = [(V1 - V2) + (V3 - V4)]. In this example, the first voltage V1 = FC + BC + Vcm_f, the second voltage V2 = Vcm_f, the third voltage V3 = -FC + Vcm_f, and the fourth voltage V4 = Vcm_f. Therefore, the voltage across the output terminals (Vout) is a signal proportional to Vout = (FC + BC + Vcm_f) - Vcm_f + (-FC + Vcm_f) - Vcm_f = BC.

[0037] In the transceiver (TRF), the reference potential Vcm_f can also be generated by the potential output circuit VCM. The second input terminal T2 and the fourth input terminal T4 are connected to the power supply potential Vdd via the potential output circuit VCM.

[0038] Note that all receiving amplifiers RA shown in Figure 1 are first-type receiving amplifiers and have the function of an adder that adds the voltage obtained from the first voltage V1 (V1-V2) and the voltage obtained from the third voltage V3 (V3-V4) and outputs the result. When using a receiving amplifier RA with an adder function, differential signals can be output from the transmitting driver, resulting in a simple circuit configuration and a compact, power-saving structure for the transmitting and receiving device. The receiving amplifier RA can also be a second-type receiving amplifier, as described in Figure 2 and later. The second-type receiving amplifier is a DDA (Differential Difference Amplifier) ​​and can function as a subtractor that outputs the difference of a specific signal. When using a receiving amplifier RA with a subtractor function, even if common-mode signals are output from the transmitting driver, these signals can be canceled out, resulting in a simple circuit configuration and a compact, power-saving structure for the transmitting and receiving device.

[0039] Figure 2 is a circuit diagram of the second communication system.

[0040] In the second communication system, compared to the first communication system, the transmit driver DRV in the backward transceiver (TRB) is changed to a common-mode driver, and the receive amplifier RA is changed to a second-type receive amplifier. As a result of this change, the second input terminal T2 of the receive amplifier RA in the transceiver (TRB) is connected to the second output terminal D2 of the transmit driver DRV, and the third input terminal T3 is connected to the reference potential Vcm_b. The other structures of the second communication system are identical to those of the first communication system.

[0041] More specifically, the transceiver (TRB) comprises a transmit driver DRV connected to the first terminal B1 of the first transmission line TL1 via a first capacitor CB1, and a receive amplifier RA connected to the first terminal B1 via the first capacitor CB1. This transmit driver DRV is a common-mode driver including a first output terminal D1 that outputs a first signal (BC + Vcm_b) and a second output terminal D2 that outputs a second signal (BC + Vcm_b) that is in phase with the first signal. The first input terminal T1 of the receive amplifier RA of the transceiver (TRB) is connected to the first terminal B1 and the first output terminal D1. The second input terminal T2 of the receive amplifier RA is connected to the second output terminal D2. The third input terminal T3 of the receive amplifier RA is connected to the reference potential Vcm_b. The fourth input terminal T4 of the receive amplifier RA is connected to the reference potential Vcm_b.

[0042] The receiver amplifier RA on the right has output terminals that output a first output signal (Voutn) and a second output signal (Voutp). The difference between these output signals is the output signal Vout. When the first voltage V1 is input to the first input terminal T1 of the receiver amplifier RA on the right, the second voltage V2 is input to the second input terminal T2, the third voltage V3 is input to the third input terminal T3, and the fourth voltage V4 is input to the fourth input terminal T4, the voltage between the output terminals (Vout) will be a signal proportional to Vout = Voutp - Voutn = [(V1 - V2) - (V3 - V4)]. In this example, the first voltage V1 = FC + BC + Vcm_b, the second voltage V2 = BC + Vcm_b, the third voltage V3 = Vcm_b, and the fourth voltage V4 = Vcm_b. Therefore, the voltage across the output terminals (Vout) is a signal proportional to Vout = ((FC + BC + Vcm_b) - (BC + Vcm_b)) - (Vcm_b - Vcm_b) = FC.

[0043] In the communication system shown in Figure 2, the transceiver (TRB) uses a second-type receiving amplifier RA, while the transceiver (TRF) uses a first-type receiving amplifier RA.

[0044] Figure 3 is a circuit diagram of the third communication system.

[0045] In the third communication system, compared to the second communication system, the forward-side transceiver (TRF) is modified in such a way that the transmit driver DRV is changed to a common-mode driver and the receive amplifier RA is changed to a second-type receive amplifier. As a result of this modification, the second input terminal T2 of the receive amplifier RA of the transceiver (TRF) is connected to the second output terminal D2 of its transmit driver DRV, and the third input terminal T3 is connected to the reference potential Vcm_f. The other structural features of the third communication system are identical to those of the second communication system.

[0046] More specifically, the transceiver (TRB) comprises a transmit driver DRV connected to the first terminal B1 of the first transmission line TL1, and a receive amplifier RA connected to the first terminal B1. This transmit driver DRV is an in-phase driver including a first output terminal D1 that outputs a first signal (BC + Vcm_b) and a second output terminal D2 that outputs a second signal (BC + Vcm_b) that is in phase with the first signal (BC + Vcm_b). The receive amplifier RA of the transceiver (TRB) has a first input terminal T1, a second input terminal T2, a third input terminal T3, and a fourth input terminal T4. The first input terminal T1 of the transceiver (TRB) is connected to the first terminal B1 and the first output terminal D1. The second input terminal T2 is connected to the second output terminal D2. The third input terminal T3 is connected to the reference potential Vcm_b. The fourth input terminal T4 is connected to the reference potential Vcm_b.

[0047] The receiver amplifier RA on the right has output terminals that output a first output signal (Voutn) and a second output signal (Voutp). The difference between these output signals is the output signal Vout. When the first voltage V1 is input to the first input terminal T1 of the receiver amplifier RA on the right, the second voltage V2 is input to the second input terminal T2, the third voltage V3 is input to the third input terminal T3, and the fourth voltage V4 is input to the fourth input terminal T4, the voltage between the output terminals (Vout) will be a signal proportional to Vout = Voutp - Voutn = [(V1 - V2) - (V3 - V4)]. In this example, the first voltage V1 = FC + BC + Vcm_b, the second voltage V2 = BC + Vcm_b, the third voltage V3 = Vcm_b, and the fourth voltage V4 = Vcm_b. Therefore, the voltage across the output terminals (Vout) is a signal proportional to Vout = ((FC + BC + Vcm_b) - (BC + Vcm_b)) - (Vcm_b - Vcm_b) = FC.

[0048] Similarly, the other transceiver (TRF) includes a transmit driver DRV connected to the third terminal F1 of the first transmission line TL1 via a third capacitor CF1, and a receive amplifier RA connected to the third terminal F1 via the third capacitor CF1. This transmit driver DRV is an in-phase driver including a first output terminal D1 that outputs a first signal (FC+Vcm_f) and a second output terminal D2 that outputs a second signal (FC+Vcm_f) that is in phase with the first signal (FC+Vcm). The receive amplifier RA of the transceiver (TRF) has a first input terminal T1, a second input terminal T2, a third input terminal T3, and a fourth input terminal T4. The first input terminal T1 of the transceiver (TRF) is connected to the third terminal F1 and the first output terminal D1. The second input terminal T2 is connected to the second output terminal D2. The third input terminal T3 is connected to a reference potential Vcm_f. The fourth input terminal T4 is connected to a reference potential Vcm_f.

[0049] The receiving amplifier RA on the left has output terminals that output a first output signal (Voutn) and a second output signal (Voutp). The difference between these output signals is the output signal Vout. When the first voltage V1 is input to the first input terminal T1 of the receiving amplifier RA on the left, the second voltage V2 is input to the second input terminal T2, the third voltage V3 is input to the third input terminal T3, and the fourth voltage V4 is input to the fourth input terminal T4, the voltage between the output terminals (Vout) will be a signal proportional to Vout = Voutp - Voutn = [(V1 - V2) - (V3 - V4)]. In this example, the first voltage V1 = FC + BC + Vcm_f, the second voltage V2 = FC + Vcm_f, the third voltage V3 = Vcm_f, and the fourth voltage V4 = Vcm_f. Therefore, the voltage across the output terminals (Vout) is a signal proportional to Vout = ((FC + BC + Vcm_f) - (FC + Vcm_f)) - (Vcm_f - Vcm_f) = BC.

[0050] In the communication system shown in Figure 3, the transceiver (TRB) uses a second-type receiving amplifier RA, and the transceiver (TRF) also uses a second-type receiving amplifier RA.

[0051] Figure 4 is a circuit diagram of the fourth communication system.

[0052] The fourth communication system uses differential signaling with two transmission lines: a first transmission line TL1 and a second transmission line TL2.

[0053] The structure of the transceiver (TRB) of the fourth communication system is the same as that of the third communication system, except that the second terminal B2 is connected to the second transmission line TL2. The structure of the transceiver (TRF) of the fourth communication system is the same as that of the transceiver (TRF) of the first communication system (Figure 1), except that the fourth terminal F2 is connected to the second transmission line TL2.

[0054] More specifically, the transceiver (TRB) comprises a transmit driver DRV connected to the first terminal B1 of the first transmission line TL1 and the second terminal B2 of the second transmission line TL2, and a receive amplifier RA connected to the first terminal B1 and the second terminal B2. The transmit driver DRV of the transceiver (TRB) is an in-phase driver including a first output terminal D1 that outputs a first signal (BC + Vcm_b) and a second output terminal D2 that outputs a second signal (BC + Vcm_b) that is in phase with the first signal. The receive amplifier RA of the transceiver (TRB) has a first input terminal T1, a second input terminal T2, a third input terminal T3, and a fourth input terminal T4. The first input terminal T1 is connected to the first terminal B1 and the first output terminal D1 via a first capacitor CB1. The second input terminal T2 is connected to the second terminal B2 and the second output terminal D2 via a second capacitor CB2. The third input terminal T3 is connected to the reference potential Vcm_b. The fourth input terminal T4 is connected to the reference potential Vcm_b.

[0055] The receiver amplifier RA on the right has output terminals that output a first output signal (Voutn) and a second output signal (Voutp). The difference between these output signals is the output signal Vout. When the first voltage V1 is input to the first input terminal T1 of the receiver amplifier RA on the right, the second voltage V2 is input to the second input terminal T2, the third voltage V3 is input to the third input terminal T3, and the fourth voltage V4 is input to the fourth input terminal T4, the voltage between the output terminals (Vout) will be a signal proportional to Vout = Voutp - Voutn = [(V1 - V2) - (V3 - V4)]. In this example, the first voltage V1 = FC + BC + Vcm_b, the second voltage V2 = -FC + BC + Vcm_b, the third voltage V3 = Vcm_b, and the fourth voltage V4 = Vcm_b. Therefore, the voltage across the output terminals (Vout) is a signal proportional to Vout = ((FC + BC + Vcm_b) - (-FC + BC + Vcm_b)) - (Vcm_b - Vcm_b) = 2FC.

[0056] The terminal opposite to the first terminal B1 of the first transmission line TL1 is the third terminal F1, and the terminal opposite to the second terminal B2 of the second transmission line TL2 is the fourth terminal F2.

[0057] Similarly, the transceiver (TRF) includes a second transmit driver DRV connected to the third terminal F1 of the first transmission line TL1 and the fourth terminal F2 of the second transmission line TL2, and a receive amplifier RA connected to the third terminal F1 and the fourth terminal F2. The transmit driver DRV of the transceiver (TRF) is a differential driver including a first output terminal D1 that outputs a first signal (FC + Vcm_f) and a second output terminal D2 that outputs a second signal (-FC + Vcm_f) that is in opposite phase to the first signal. The receive amplifier RA of the transceiver (TRF) has a first input terminal T1, a second input terminal T2, a third input terminal T3, and a fourth input terminal T4. In the transceiver (TRF), the first input terminal T1 is connected to the third terminal F1 via a third capacitor CF1 and is also connected to the first output terminal D1. The second input terminal T2 is connected to a reference potential Vcm_f. The third input terminal T3 is connected to the fourth terminal F2 via the fourth capacitor CF2, and is also connected to the second output terminal D2. The fourth input terminal T4 is connected to the reference potential Vcm_f.

[0058] The receiving amplifier RA on the left has output terminals that output a first output signal (Voutn) and a second output signal (Voutp). The difference between these output signals is the output signal Vout. When the first voltage V1 is input to the first input terminal T1 of the receiving amplifier RA on the left, the second voltage V2 is input to the second input terminal T2, the third voltage V3 is input to the third input terminal T3, and the fourth voltage V4 is input to the fourth input terminal T4, the voltage between the output terminals (Vout) will be a signal proportional to Vout = Voutp - Voutn = [(V1 - V2) + (V3 - V4)]. In this example, the first voltage V1 = FC + BC + Vcm_f, the second voltage V2 = Vcm_f, the third voltage V3 = -FC + BC + Vcm_f, and the fourth voltage V4 = Vcm_f. Therefore, the voltage across the output terminals (Vout) is a signal proportional to Vout = ((FC + BC + Vcm_f) - Vcm_f) + ((-FC + BC + Vcm_f) - Vcm_f)) = 2BC.

[0059] To distinguish them from the signals in the transceiver (TRB), the first signal (FC+Vcm_b) in the transceiver (TRF) can also be called the third signal, and the second signal (-FC+Vcm_b) can be called the fourth signal. In this case, the transmit driver DRV of the transceiver (TRF) outputs the third signal (FC+Vcm_b) and the fourth signal (-FC+Vcm_b).

[0060] In the communication system shown in Figure 4, the transceiver (TRB) uses a second-type receiving amplifier RA, while the transceiver (TRF) uses a first-type receiving amplifier RA.

[0061] Figure 5 is a circuit diagram of the fifth communication system.

[0062] The fifth communication system, in contrast to the fourth communication system, uses a differential driver for the transmit driver DRV in the transceiver (TRB) and a common-mode driver for the transmit driver DRV in the transceiver (TRF). Accordingly, the first type of receive amplifier RA is used on the transceiver (TRB) side, and the second type of receive amplifier RA is used on the transceiver (TRF) side.

[0063] More specifically, the transceiver (TRB) comprises a transmit driver DRV connected to the first terminal B1 of the first transmission line TL1 and the second terminal B2 of the second transmission line TL2, and a receive amplifier RA connected to the first terminal B1 and the second terminal B2. The transmit driver DRV of the transceiver (TRB) is a differential driver including a first output terminal D1 that outputs a first signal (BC + Vcm_b) and a second output terminal D2 that outputs a second signal (-BC + Vcm_b) that is in opposite phase to the first signal. The receive amplifier RA of the transceiver (TRB) has a first input terminal T1, a second input terminal T2, a third input terminal T3, and a fourth input terminal T4. The first input terminal T1 is connected to the first terminal B1 via a first capacitor CB1 and is also connected to the first output terminal D1. The second input terminal T2 is connected to a reference potential Vcm_b. The third input terminal T3 is connected to the second terminal B2 via the second capacitor CB2, and also to the second output terminal D2. The fourth input terminal T4 is connected to the reference potential Vcm_b.

[0064] The receiver amplifier RA on the right has output terminals that output a first output signal (Voutn) and a second output signal (Voutp). The difference between these output signals is the output signal Vout. When the first voltage V1 is input to the first input terminal T1 of the receiver amplifier RA on the right, the second voltage V2 is input to the second input terminal T2, the third voltage V3 is input to the third input terminal T3, and the fourth voltage V4 is input to the fourth input terminal T4, the voltage between the output terminals (Vout) will be a signal proportional to Vout = Voutp - Voutn = [(V1 - V2) + (V3 - V4)]. In this example, the first voltage V1 = FC + BC + Vcm_b, the second voltage V2 = Vcm_b, the third voltage V3 = FC - BC + Vcm_b, and the fourth voltage V4 = Vcm_b. Therefore, the voltage across the output terminals (Vout) is a signal proportional to Vout = ((FC + BC + Vcm_b) - Vcm_b) + ((FC - BC + Vcm_b) - Vcm_b)) = 2FC.

[0065] Similarly, the transceiver (TRF) includes a second transmit driver DRV connected to the third terminal F1 of the first transmission line TL1 and the fourth terminal F2 of the second transmission line TL2, and a receive amplifier RA connected to the third terminal F1 and the fourth terminal F2. The transmit driver DRV of the transceiver (TRF) is an in-phase driver including a first output terminal D1 that outputs a first signal (FC+Vcm_f) and a second output terminal D2 that outputs a second signal (FC+Vcm_f) that is in phase with the first signal. The receive amplifier RA of the transceiver (TRF) has a first input terminal T1, a second input terminal T2, a third input terminal T3, and a fourth input terminal T4. In the transceiver (TRF), the first input terminal T1 is connected to the third terminal F1 via a third capacitor CF1 and is also connected to the first output terminal D1. The second input terminal T2 is connected to the fourth terminal F2 via a fourth capacitor CF2 and is also connected to the second output terminal D2. The third input terminal T3 is connected to the reference potential Vcm_f. The fourth input terminal T4 is connected to the reference potential Vcm_f.

[0066] The receiver amplifier RA on the left has output terminals that output a first output signal (Voutn) and a second output signal (Voutp). The difference between these output signals is the output signal Vout. When the first voltage V1 is input to the first input terminal T1 of the receiver amplifier RA on the left, the second voltage V2 is input to the second input terminal T2, the third voltage V3 is input to the third input terminal T3, and the fourth voltage V4 is input to the fourth input terminal T4, the voltage between the output terminals (Vout) will be a signal proportional to Vout = Voutp - Voutn = [(V1 - V2) - (V3 - V4)]. In this example, the first voltage V1 = FC + BC + Vcm_f, the second voltage V2 = FC - BC + Vcm_f, the third voltage V3 = Vcm_f, and the fourth voltage V4 = Vcm_f. Therefore, the voltage across the output terminals (Vout) is a signal proportional to Vout = ((FC + BC + Vcm_f) - (FC - BC + Vcm_f)) - (Vcm_f - Vcm_f) = 2BC.

[0067] Next, I will explain the receiving amplifier RA.

[0068] Figure 6 shows the first type of receiving amplifier RA.

[0069] The receiving amplifier RA has a first input terminal T1, a second input terminal T2, a third input terminal T3, and a fourth input terminal T4. The receiving amplifier RA has two output terminals that output signals (Voutn, Voutp), and the voltage between these output terminals can be the output voltage Vout. The receiving amplifier RA may further include an amplifier that outputs the difference between the signals output from the two output terminals.

[0070] The first input terminal T1 can be used as an add input (+), the second input terminal T2 as a subtract input (-), the third input terminal T3 as an add input (+), and the fourth input terminal T4 as a subtract input (-). The first voltage V1 is input to the first input terminal T1, the second voltage V2 is input to the second input terminal T2, the third voltage V3 is input to the third input terminal T3, and the fourth voltage V4 is input to the fourth input terminal T4. In this case, the output voltage Vout can be expressed using a coefficient A as follows: Vout = Voutp - Voutn = A × [(V1 + V3) - (V2 + V4)] = A × [(V1 - V2) + (V3 - V4)]. The coefficient A is the amplification factor, but for simplicity of explanation, A = 1 can be assumed. The first type of receiving amplifier RA also functions as an adder that adds (V1 - V2) and (V3 - V4) and outputs the result.

[0071] Figure 7 is a circuit diagram of the first type receiving amplifier RA.

[0072] The receiving amplifier RA comprises a first transistor Q1 having a first gate G1, a second transistor Q2 having a second gate G2, a third transistor Q3 having a third gate G3, and a fourth transistor Q4 having a fourth gate G4.

[0073] The receiving amplifier RA has a first resistor R interposed between the drains of the first transistor Q1 and the drain of the third transistor Q3 and the power supply potential Vdd. L1 And, a second resistor R is interposed between the drains of the second transistor Q2 and the drain of the fourth transistor Q4 and the power supply potential Vdd. L2 It is equipped with [the following].

[0074] The receiving amplifier RA has a first resistor R L1 A first output terminal (Voutn) is located downstream of the second resistor R L2 It is equipped with a second output terminal (Voutp) located downstream of the transistor and a current source CS. The current source CS is connected between the sources (S) of the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 and the ground potential.

[0075] The first gate G1 of the first transistor Q1 is connected to the first input terminal T1, and the first voltage V1 is input to it. The second gate G2 of the second transistor Q2 is connected to the second input terminal T2, and the second voltage V2 is input to it. The third gate G3 of the third transistor Q3 is connected to the third input terminal T3, and the third voltage V3 is input to it. The fourth gate G4 of the fourth transistor Q4 is connected to the fourth input terminal T4, and the fourth voltage V4 is input to it.

[0076] In the first type of receiving amplifier RA (transceiver (TRB) side) shown in Figure 1, the first voltage V1 input to the first input terminal T1 is (FC + BC + Vcm_b), the second voltage V2 input to the second input terminal T2 is Vcm_b, the third voltage V3 input to the third input terminal T3 is (-BC + Vcm_b), and the fourth voltage V4 input to the fourth input terminal T4 is Vcm_b. In the first type of receiving amplifier RA (transceiver (TRF) side) shown in Figure 1, the first voltage V1 input to the first input terminal T1 is (FC + BC + Vcm_f), the second voltage V2 input to the second input terminal T2 is Vcm_f, the third voltage V3 input to the third input terminal T3 is (-FC + Vcm_f), and the fourth voltage V4 input to the fourth input terminal T4 is Vcm_f.

[0077] In the first type of receiving amplifier RA (transceiver (TRF) side) shown in Figure 2, the first voltage V1 input to the first input terminal T1 is (FC + BC + Vcm_f), the second voltage V2 input to the second input terminal T2 is Vcm_f, the third voltage V3 input to the third input terminal T3 is (-FC + Vcm_f), and the fourth voltage V4 input to the fourth input terminal T4 is Vcm_f.

[0078] In the first type of receiving amplifier RA (transceiver (TRF) side) shown in Figure 4, the first voltage V1 input to the first input terminal T1 is (FC + BC + Vcm_f), the second voltage V2 input to the second input terminal T2 is Vcm_f, the third voltage V3 input to the third input terminal T3 is (-FC + BC + Vcm_f), and the fourth voltage V4 input to the fourth input terminal T4 is Vcm_f.

[0079] In the first type of receiving amplifier RA (transceiver (TRB) side) shown in Figure 5, the first voltage V1 input to the first input terminal T1 is (FC + BC + Vcm_b), the second voltage V2 input to the second input terminal T2 is Vcm_b, the third voltage V3 input to the third input terminal T3 is (FC - BC + Vcm_b), and the fourth voltage V4 input to the fourth input terminal T4 is Vcm_b.

[0080] Figure 8 is a circuit diagram of the improved Type 1 receiving amplifier.

[0081] This receiving amplifier RA is an improved version of the receiving amplifier RA shown in Figure 7.

[0082] The difference between this receiving amplifier RA and the circuit structure shown in Figure 7 is that it has a first current source CS1 and a second current source CS2 instead of the current source CS, but the rest of the structure is the same as the receiving amplifier shown in Figure 7. Specifically, the first current source CS1 is connected between the sources (S) of the first transistor Q1 and the second transistor Q2 and the ground potential. The second current source CS2 is connected between the sources (S) of the third transistor Q3 and the fourth transistor Q4 and the ground potential.

[0083] The first gate G1 of the first transistor Q1 is connected to the first input terminal T1, and the first voltage V1 is input to it. The second gate G2 of the second transistor Q2 is connected to the second input terminal T2, and the second voltage V2 is input to it. The third gate G3 of the third transistor Q3 is connected to the third input terminal T3, and the third voltage V3 is input to it. The fourth gate G4 of the fourth transistor Q4 is connected to the fourth input terminal T4, and the fourth voltage V4 is input to it.

[0084] The gain of each transistor (Q1 to Q4) can be adjusted by controlling the current values ​​of the first current source CS1 and the second current source CS2. The current values ​​of the first current source CS1 and the second current source CS2 may also be feedback-controlled while monitoring the output signals (Voutn, Voutp). Even in cases of characteristic variations of each element or fluctuations in the received signal, the output signal can be corrected by adjusting the current values ​​of the first current source CS1 and the second current source CS2.

[0085] Figure 9 shows the second type of receiving amplifier RA.

[0086] The receiving amplifier RA has a first input terminal T1, a second input terminal T2, a third input terminal T3, and a fourth input terminal T4. The receiving amplifier RA has two output terminals that output signals (Voutn, Voutp), and the voltage between these output terminals can be the output voltage Vout. The receiving amplifier RA may further include an amplifier that outputs the difference between the signals output from the two output terminals.

[0087] The first input terminal T1 can be used as an add input (+), the second input terminal T2 as a subtract input (-), the third input terminal T3 as an add input (+), and the fourth input terminal T4 as a subtract input (-). The first voltage V1 is input to the first input terminal T1, the second voltage V2 is input to the second input terminal T2, the third voltage V3 is input to the third input terminal T3, and the fourth voltage V4 is input to the fourth input terminal T4. In this case, the output voltage Vout can be expressed using a coefficient A as Vout = Voutp - Voutn = A × [(V1-V2) - (V3-V4)]. The second type of receiving amplifier RA also functions as a subtractor that subtracts (V3-V4) from (V1-V2) and outputs the result.

[0088] Figure 10 is a circuit diagram of the second type of receiving amplifier RA.

[0089] The receiving amplifier RA comprises a first transistor Q1 having a first gate G1, a second transistor Q2 having a second gate G2, a third transistor Q3 having a third gate G3, and a fourth transistor Q4 having a fourth gate G4.

[0090] The receiving amplifier RA has a first resistor R interposed between the drains of the first transistor Q1 and the drain of the fourth transistor Q4 and the power supply potential Vdd. L1 And a second resistor R interposed between the drains of the second transistor Q2 and the drains of the third transistor Q3 and the power supply potential Vdd. L2 It is equipped with [the following].

[0091] The receiving amplifier RA has a first resistor R L1 A first output terminal (Voutn) is located downstream of the second resistor R L2 It is equipped with a second output terminal (Voutp) located downstream of the transistor and a current source CS. The current source CS is connected between the sources (S) of the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 and the ground potential.

[0092] The first gate G1 of the first transistor Q1 is connected to the first input terminal T1, and the first voltage V1 is input to it. The second gate G2 of the second transistor Q2 is connected to the second input terminal T2, and the second voltage V2 is input to it. The third gate G3 of the third transistor Q3 is connected to the third input terminal T3, and the third voltage V3 is input to it. The fourth gate G4 of the fourth transistor Q4 is connected to the fourth input terminal T4, and the fourth voltage V4 is input to it.

[0093] In the second type of receiving amplifier RA (transceiver (TRB) side) shown in Figures 2 and 3, the first voltage V1 input to the first input terminal T1 is (FC + BC + Vcm_b), the second voltage V2 input to the second input terminal T2 is (BC + Vcm_b), the third voltage V3 input to the third input terminal T3 is Vcm_b, and the fourth voltage V4 input to the fourth input terminal T4 is Vcm_b.

[0094] In the second type of receiving amplifier RA (transceiver (TRF) side) shown in Figure 3, the first voltage V1 input to the first input terminal T1 is (FC + BC + Vcm_f), the second voltage V2 input to the second input terminal T2 is (FC + Vcm_f), the third voltage V3 input to the third input terminal T3 is Vcm_f, and the fourth voltage V4 input to the fourth input terminal T4 is Vcm_f.

[0095] In the second type of receiving amplifier RA (transceiver (TRB) side) shown in Figure 4, the first voltage V1 input to the first input terminal T1 is (FC + BC + Vcm_b), the second voltage V2 input to the second input terminal T2 is (-FC + BC + Vcm_b), the third voltage V3 input to the third input terminal T3 is Vcm_b, and the fourth voltage V4 input to the fourth input terminal T4 is Vcm_b.

[0096] In the second type of receiving amplifier RA (transceiver (TRF) side) shown in Figure 5, the first voltage V1 input to the first input terminal T1 is (FC + BC + Vcm_f), the second voltage V2 input to the second input terminal T2 is (FC - BC + Vcm_f), the third voltage V3 input to the third input terminal T3 is Vcm_f, and the fourth voltage V4 input to the fourth input terminal T4 is Vcm_f.

[0097] Figure 11 is the circuit diagram of the improved second type of receiving amplifier.

[0098] This receiving amplifier RA is an improved version of the receiving amplifier RA shown in Figure 10.

[0099] The difference between this receiving amplifier RA and the circuit structure shown in Figure 10 is that it has a first current source CS1 and a second current source CS2 instead of the current source CS, but the rest of the structure is the same as the receiving amplifier shown in Figure 10. Specifically, the first current source CS1 is connected between the sources (S) of the first transistor Q1 and the second transistor Q2 and the ground potential. The second current source CS2 is connected between the sources (S) of the third transistor Q3 and the fourth transistor Q4 and the ground potential.

[0100] The first gate G1 of the first transistor Q1 is connected to the first input terminal T1, and the first voltage V1 is input to it. The second gate G2 of the second transistor Q2 is connected to the second input terminal T2, and the second voltage V2 is input to it. The third gate G3 of the third transistor Q3 is connected to the third input terminal T3, and the third voltage V3 is input to it. The fourth gate G4 of the fourth transistor Q4 is connected to the fourth input terminal T4, and the fourth voltage V4 is input to it.

[0101] In this example as well, the gain of each transistor (Q1 to Q4) can be adjusted by controlling the current values ​​of the first current source CS1 and the second current source CS2. The current values ​​of the first current source CS1 and the second current source CS2 may also be feedback controlled while monitoring the output signals (Voutn, Voutp). Even in cases of characteristic variations of each element or fluctuations in the received signal, the output signal can be corrected by adjusting the current values ​​of the first current source CS1 and the second current source CS2.

[0102] Figure 12 is a circuit diagram of a transceiver with a group of switches on the input side of the receiving amplifier. Although the figure shows a backward transceiver, this configuration can also be applied to a forward transceiver.

[0103] The receiving amplifier RA in the figure represents either the first type receiving amplifier RA or the second type receiving amplifier. The transmitting and receiving device can be configured to switch the connection relationship between the multiple input terminals of the receiving amplifier RA, the transmission line, and the reference potential. In single-ended signaling, there is one transmission line, and in this case, the first input terminals T1 to the fourth input terminals T4 are connected to the first terminal B1, the second terminal B2, and the reference potential Vcm_b, as shown in the connection state in Figures 1 to 3. In differential signaling, there are two transmission lines, and in this case, the first input terminals T1 to the fourth input terminals T4 are connected to the first terminal B1, the second terminal B2, and the reference potential Vcm_b, as shown in the connection state in Figures 4 to 5.

[0104] The connection relationship between the third input terminal T3 and the fourth input terminal T4 can be switched without switching the connection relationship between the first input terminal T1 and the second input terminal T2. In this case, the third input terminal T3 can be provided with a first switch SW1 that connects the second input terminal T2 of the receiving amplifier RA to a reference potential Vcm_b, and a second switch SW2 that connects the second input terminal T2 of the receiving amplifier RA to the second output terminal D2.

[0105] In this configuration, the second input terminal T2 can be connected to the reference potential Vcm_b by turning on the first switch SW1, at which point the second switch SW2 is turned OFF. The second input terminal T2 can be connected to the second terminal B2 and the second output terminal D2 by turning off the first switch SW1 and turning on the second switch SW2.

[0106] The third input terminal T3 may be provided with a third switch SW3 that connects the third input terminal T3 of the receiving amplifier RA to the second output terminal D2, and a fourth switch SW4 that connects the third input terminal T3 of the receiving amplifier RA to a reference potential Vcm_b.

[0107] In this configuration, the third input terminal T3 can be connected to the second terminal B2 and the second output terminal D2 by turning on the third switch SW3, at which point the fourth switch SW4 is turned OFF. The third input terminal T3 can be connected to the reference potential Vcm_b by turning off the third switch SW3 and turning on the fourth switch SW4.

[0108] The transmitting and receiving device may optionally include a fifth switch SW5 for connecting the first input terminal T1 to the reference potential Vcm_b, and a sixth switch SW6 for connecting the first input terminal T1 to the first terminal B1 and the first output terminal D1. When the fifth switch SW5 is turned ON, the first input terminal T1 can be connected to the reference potential Vcm_b. When the sixth switch SW6 is turned ON, the first input terminal T1 can be connected to the first terminal B1.

[0109] The transmitting and receiving device may optionally include a seventh switch SW7 for connecting the fourth input terminal T4 to the reference potential Vcm_b, and an eighth switch SW8 for connecting the fourth input terminal T4 to the second terminal B2 and the second output terminal D2. When the seventh switch SW7 is turned ON, the fourth input terminal T4 can be connected to the reference potential Vcm_b. When the eighth switch SW8 is turned ON, the fourth input terminal T4 can be connected to the second terminal B2.

[0110] Furthermore, a ninth switch SW9 can be provided between the second terminal B2 and the first load resistor RB. When the ninth switch SW9 is turned ON, the second terminal B2 and the second output terminal D2 can be connected to the first load resistor RB.

[0111] In single-ended signaling, for example, the 6th switch SW6, the 2nd switch SW2, the 4th switch SW4, the 7th switch SW7, and the 9th switch SW9 are set to the ON state, and the remaining switches are set to the OFF state. In differential signaling, for example, if the transmitting and receiving device uses a common-mode driver, the same connection as in single-ended signaling can be made. In differential signaling, for example, if the device uses a differential driver, the 6th switch SW6, the 1st switch SW1, the 3rd switch SW3, the 7th switch SW7, and the 9th switch SW9 are set to the ON state, and the remaining switches are set to the OFF state. In this way, the transmitting and receiving device can be applied to both single-ended signaling and differential signaling by switching the switches. Note that switches that are not used do not need to be implemented.

[0112] Figure 13 is a circuit diagram of a transceiver equipped with a receiving amplifier having a 1-bit DAC (digital-to-analog converter). Although the figure shows a backward transceiver, this configuration can also be applied to a forward transceiver.

[0113] The transmit driver DRV is a differential driver and outputs an inverse-phase (complementary) first transmit signal (+BC+Vcm_b) and a second transmit signal (-BC+Vcm_b). The receive amplifier RA has the first input terminals T1 to the fourth input terminals T4 described above, as well as a first feedback terminal T10 and a second feedback terminal T20. The first output terminal (Voutn) of the receive amplifier RA is connected to the first feedback terminal T10 via the first inverter INV1. The second output terminal (Voutp) of the receive amplifier RA is connected to the second feedback terminal T20 via the second inverter INV2. The other configurations of the receive amplifier RA in this example are the same as those of the receive amplifier RA described above.

[0114] The first feedback terminal T10 is the gate of a transistor, and the drain of this transistor is connected to the drains of transistors having gates that become the first and third input terminals. The second feedback terminal T20 is the gate of a transistor, and the drain of this transistor is connected to the drains of transistors having gates that become the second and fourth input terminals.

[0115] The receiving amplifier RA is a first-type receiving amplifier, where a high-potential signal is input to the first input terminal T1 and a low-potential signal is input to the third input terminal T3. When a feedback function is implemented, the output voltage can be made more precise by utilizing the interpolation characteristics of the operational amplifier.

[0116] Figure 14 is the circuit diagram of the receiving amplifier RA.

[0117] The receiving amplifier RA includes the transistors shown in Figure 7 (first transistor Q1, second transistor Q2, third transistor Q3, fourth transistor Q4), as well as a first feedback transistor Q10 and a second feedback transistor Q20. These transistors are assumed to be NMOS field-effect transistors (FETs).

[0118] The feedback voltage (VFBp) from the first output terminal (Voutn) of the receiving amplifier RA is input to the first feedback terminal T10 (gate G10). The feedback voltage (VFBn) from the second output terminal (Voutp) of the receiving amplifier RA is input to the second feedback terminal T20 (gate G20). Each additional feedback transistor operates in the same way as a 1-bit DAC (digital-to-analog converter) would be implemented in an operational amplifier. In other words, the receiving amplifier RA has a 1-bit DAC. The source of each transistor is connected to a fixed potential, such as ground potential, via a current source CS.

[0119] In other words, in the transmission and reception device of FIGS. 13 and 14, the receiving amplifier RA includes a first 1-bit digital-to-analog converter (input terminal (T10)) and a second 1-bit digital-to-analog converter (input terminal (T20)). The input terminal (T10) of the first 1-bit digital-to-analog converter is the gate of the first feedback transistor Q10 and is connected to the first output terminal (Voutn) of the receiving amplifier RA. The output terminal of the first 1-bit digital-to-analog converter is connected to the first output terminal (Voutn) of the receiving amplifier RA through the drain of the first feedback transistor Q10. The input terminal (T20) of the second 1-bit digital-to-analog converter is the gate of the second feedback transistor Q20 and is connected to the second output terminal (Voutp) of the receiving amplifier RA. The output terminal of the second 1-bit digital-to-analog converter is connected to the second output terminal (Voutp) of the receiving amplifier RA through the drain of the second feedback transistor Q20.

[0120] Let the potential of the first node N1 at the source of these transistors be VN. Let the lower gate input voltage be VL, the higher gate input voltage be VH, the difference between them be ΔV = VH - VL, and the threshold voltage of the transistor be Vth. In this case, the first output voltage (Voutn) or the second output voltage (Voutp) is ((VL - VN + Vth + ΔV / 2) 2 +(ΔV / 2) 2 ) 1 / 2 + VN + Vth.

[0121] If the receiving amplifier RA is composed of an NMOS-FET, the first output voltage (Voutn) or the second output voltage (Voutp) is obtained by expanding the above equation into a power series, resulting in VL + ΔV / 2 + α. On the other hand, if the receiving amplifier RA is composed of a PMOS-FET with the same amplification factor as the NMOS-FET, the first output voltage (Voutn) or the second output voltage (Voutp) is obtained as VL + ΔV / 2 - α. In other words, by adding the output of the NMOS-FET receiving amplifier and the output of the PMOS-FET receiving amplifier, the error α can be canceled out. To perform such cancellation, one method is to connect the NMOS-FET receiving amplifier and the PMOS-FET receiving amplifier in parallel. In this case, the NMOS-FET group and the PMOS-FET group are connected in parallel. The final output voltage is the intermediate voltage of the output voltages of these receiving amplifiers.

[0122] The NMOS-FET receiving amplifier and the PMOS-FET receiving amplifier can be configured to operate across the entire range from ground potential to power supply potential Vdd (rail to rail). The NMOS-FET receiving amplifier (differential pair) may be positioned on the ground potential side, with its upstream output connected to the power supply potential Vdd via a load PMOS-FET. The PMOS-FET receiving amplifier (differential pair) may be positioned on the power supply potential side, with its downstream output connected to ground potential via a load NMOS-FET. These load PMOS-FETs and NMOS-FETs may be summing amplifiers composed of folded cascodes. This amplifier can be configured as a class AB push-pull output stage. The amplifier's output terminals can be connected to a common-mode feedback circuit to suppress output fluctuations. The amplifier's output signal is fed back to the gate of a transistor that controls the current flowing through the amplifier to suppress output fluctuations.

[0123] This configuration is applicable to Type 1 receiving amplifiers, but it is also applicable to Type 2 receiving amplifiers. Furthermore, while differential signaling is illustrated in this example, this configuration is also applicable to single-ended signaling.

[0124] Figure 15 is the circuit diagram of the improved receiving amplifier.

[0125] This receiving amplifier RA is an improved version of the receiving amplifier RA shown in Figure 14.

[0126] The difference between this receiving amplifier RA and the circuit structure shown in Figure 14 is that it has a first current source CS1, a second current source CS2, and a third current source CS3 instead of the current source CS, but the rest of the structure is the same as the receiving amplifier shown in Figure 14. Specifically, the first current source CS1 is connected between the first node N1, which connects the sources (S) of the first transistor Q1 and the second transistor Q2, and the ground potential. The second current source CS2 is connected between the second node N2, which connects the sources (S) of the third transistor Q3 and the fourth transistor Q4, and the ground potential. The third current source CS3 is connected between the third node N3, which connects the sources (S) of the first feedback transistor Q10 and the second feedback transistor Q20, and the ground potential.

[0127] The first gate G1 of the first transistor Q1 is connected to the first input terminal T1, and the first voltage V1 is input to it. The second gate G2 of the second transistor Q2 is connected to the second input terminal T2, and the second voltage V2 is input to it. The third gate G3 of the third transistor Q3 is connected to the third input terminal T3, and the third voltage V3 is input to it. The fourth gate G4 of the fourth transistor Q4 is connected to the fourth input terminal T4, and the fourth voltage V4 is input to it. The feedback voltage (VFBp) (inverted voltage) from the first output terminal (Voutn) of the receiving amplifier RA is input to the first feedback terminal T10 (gate G10). The feedback voltage (VFBn) (inverted voltage) from the second output terminal (Voutp) of the receiving amplifier RA is input to the second feedback terminal T20 (gate G20).

[0128] In this example as well, the gain of each transistor (Q1-Q4, Q10, Q20) can be adjusted by controlling the current values ​​of the first current source CS1, the second current source CS2, and the third current source CS3. The current values ​​of the first current source CS1, the second current source CS2, and the third current source CS3 may also be feedback controlled while monitoring the output signals (Voutn, Voutp). Even in cases of characteristic variations of each element or fluctuations in the received signal, the output signal can be corrected by adjusting the current values ​​of the first current source CS1, the second current source CS2, and the third current source CS3.

[0129] Figure 16 is a circuit diagram of a receiving amplifier equipped with multiple receiving amplifiers.

[0130] A PMOS type receiving amplifier RA is connected in parallel to an NMOS type receiving amplifier RA. The output signals of the NMOS type receiving amplifier RA (Voutn (NMOS), Voutp (NMOS)) are input to a current adder ADD (adding amplifier). The output signals of the PMOS type receiving amplifier RA (Voutn (PMOS), Voutp (PMOS)) are also input to the current adder ADD (adding amplifier). The current adder ADD adds the currents corresponding to these output voltages and outputs a first output signal (Voutn) and a second output signal (Voutp).

[0131] Figure 17 is a circuit diagram of a receiving amplifier RA equipped with multiple NMOS field-effect transistors.

[0132] The receiving amplifier RA may be the same as the one shown in Figure 14, but here we will use the second type of receiving amplifier RA. That is, in addition to the transistors shown in Figure 10 (first transistor Q1, second transistor Q2, third transistor Q3, fourth transistor Q4), the receiving amplifier RA includes a first feedback transistor Q10 and a second feedback transistor Q20. These transistors are NMOS-FETs.

[0133] The feedback voltage (VFBp) from the first output terminal (Voutn) of the receiving amplifier RA is input to the first feedback terminal T10 (gate G10). The feedback voltage (VFBn) from the second output terminal (Voutp) of the receiving amplifier RA is input to the second feedback terminal T20 (gate G20). Each additional feedback transistor operates in the same way as a 1-bit DAC (digital-to-analog converter) would be implemented in an operational amplifier. In other words, the receiving amplifier RA has a 1-bit DAC. The source of each transistor is connected to a fixed potential, such as ground potential, via a current source CS.

[0134] Figure 18 is the circuit diagram of the improved receiving amplifier.

[0135] This receiving amplifier RA is an improved version of the receiving amplifier RA shown in Figure 17.

[0136] The difference between this receiving amplifier RA and the circuit structure shown in Figure 17 is that it has a first current source CS1, a second current source CS2, and a third current source CS3 instead of the current source CS, but the rest of the structure is the same as the receiving amplifier shown in Figure 17. Specifically, the first current source CS1 is connected between the first node N1, which connects the sources (S) of the first transistor Q1 and the second transistor Q2, and the ground potential. The second current source CS2 is connected between the second node N2, which connects the sources (S) of the third transistor Q3 and the fourth transistor Q4, and the ground potential. The third current source CS3 is connected between the third node N3, which connects the sources (S) of the first feedback transistor Q10 and the second feedback transistor Q20, and the ground potential.

[0137] The first gate G1 of the first transistor Q1 is connected to the first input terminal T1, and the first voltage V1 is input to it. The second gate G2 of the second transistor Q2 is connected to the second input terminal T2, and the second voltage V2 is input to it. The third gate G3 of the third transistor Q3 is connected to the third input terminal T3, and the third voltage V3 is input to it. The fourth gate G4 of the fourth transistor Q4 is connected to the fourth input terminal T4, and the fourth voltage V4 is input to it. The feedback voltage (VFBp) (inverted voltage) from the first output terminal (Voutn) of the receiving amplifier RA is input to the first feedback terminal T10 (gate G10). The feedback voltage (VFBn) (inverted voltage) from the second output terminal (Voutp) of the receiving amplifier RA is input to the second feedback terminal T20 (gate G20).

[0138] In this example as well, the gain of each transistor (Q1-Q4, Q10, Q20) can be adjusted by controlling the current values ​​of the first current source CS1, the second current source CS2, and the third current source CS3. The current values ​​of the first current source CS1, the second current source CS2, and the third current source CS3 may also be feedback controlled while monitoring the output signals (Voutn, Voutp). Even in cases of characteristic variations of each element or fluctuations in the received signal, the output signal can be corrected by adjusting the current values ​​of the first current source CS1, the second current source CS2, and the third current source CS3.

[0139] Figure 19 is a circuit diagram of a receiving amplifier RA equipped with multiple PMOS field-effect transistors.

[0140] The receiving amplifier RA is a second type of receiving amplifier RA. That is, the receiving amplifier RA replaces the NMOS-FETs (first transistor Q1, second transistor Q2, third transistor Q3, fourth transistor Q4, first feedback transistor Q10, and second feedback transistor Q20) shown in Figure 14 with PMOS-FETs, and is equipped with a current source CS between the source of each transistor and the power supply potential Vdd. The receiving amplifier RA has a first resistor R interposed between the drain of the first transistor Q1 (fourth transistor Q4, first feedback transistor S10) and the ground potential. L1 The receiving amplifier RA has a second resistor R interposed between the drain of the second transistor Q2 (third transistor Q3, second feedback transistor S20) and the ground potential. L2 It is equipped with [the following].

[0141] The feedback voltage (VFBp) from the first output terminal (Voutn) of the receiving amplifier RA is input to the first feedback terminal T10 (gate G10). The feedback voltage (VFBn) from the second output terminal (Voutp) of the receiving amplifier RA is input to the second feedback terminal T20 (gate G20). Each additional feedback transistor operates in the same way as a 1-bit DAC (digital-to-analog converter) would be implemented in an operational amplifier. In other words, the receiving amplifier RA has a 1-bit DAC. The source of each transistor is connected to a fixed potential, such as ground potential, via a current source CS.

[0142] Figure 20 is a circuit diagram of an improved receiving amplifier equipped with multiple PMOS field-effect transistors.

[0143] This receiving amplifier RA is an improved version of the receiving amplifier RA shown in Figure 19.

[0144] The difference between this receiving amplifier RA and the circuit structure shown in Figure 19 is that it has a first current source CS1, a second current source CS2, and a third current source CS3 instead of the current source CS, but the rest of the structure is the same as the receiving amplifier shown in Figure 19. Specifically, the first current source CS1 is connected between the first node N1, which connects the sources (S) of the first transistor Q1 and the second transistor Q2, and the power supply potential Vdd. The second current source CS2 is connected between the second node N2, which connects the sources (S) of the third transistor Q3 and the fourth transistor Q4, and the power supply potential Vdd. The third current source CS3 is connected between the third node N3, which connects the sources (S) of the first feedback transistor Q10 and the second feedback transistor Q20, and the power supply potential Vdd.

[0145] The first gate G1 of the first transistor Q1 is connected to the first input terminal T1, and the first voltage V1 is input to it. The second gate G2 of the second transistor Q2 is connected to the second input terminal T2, and the second voltage V2 is input to it. The third gate G3 of the third transistor Q3 is connected to the third input terminal T3, and the third voltage V3 is input to it. The fourth gate G4 of the fourth transistor Q4 is connected to the fourth input terminal T4, and the fourth voltage V4 is input to it. The feedback voltage (VFBp) (inverted voltage) from the first output terminal (Voutn) of the receiving amplifier RA is input to the first feedback terminal T10 (gate G10). The feedback voltage (VFBn) (inverted voltage) from the second output terminal (Voutp) of the receiving amplifier RA is input to the second feedback terminal T20 (gate G20).

[0146] In this example as well, the gain of each transistor (Q1-Q4, Q10, Q20) can be adjusted by controlling the current values ​​of the first current source CS1, the second current source CS2, and the third current source CS3. The current values ​​of the first current source CS1, the second current source CS2, and the third current source CS3 may also be feedback controlled while monitoring the output signals (Voutn, Voutp). Even in cases of characteristic variations of each element or fluctuations in the received signal, the output signal can be corrected by adjusting the current values ​​of the first current source CS1, the second current source CS2, and the third current source CS3.

[0147] Figure 21 is a circuit diagram of an adding amplifier (current adder).

[0148] The output signals (Voutn(NMOS), Voutp(NMOS)) of the receiving amplifier consisting of NMOS-FETs shown in Figure 17 are input to the downstream nodes of the PMOS-FETs (Q11, Q12) on the power supply potential Vdd side of the summing amplifier, respectively. The output signals (Voutn(PMOS), Voutp(PMOS)) of the receiving amplifier consisting of PMOS-FETs shown in Figure 19 are input to the upstream nodes of the NMOS-FETs (Q16, Q26) on the ground potential side of the summing amplifier, respectively.

[0149] The summing amplifier features a folded cascode. Specifically, PMOS-FETs (Q11), (Q12), (Q13), (Q14), (Q15), and (Q16) are connected in series between the power supply potential Vdd and the ground potential. PMOS-FETs (Q21), (Q22), (Q23), (Q24), (Q25), and (Q26) are connected in series between the power supply potential Vdd and the ground potential.

[0150] The node between PMOS-FET(Q12) and PMOS-FET(Q13) is connected to the gate of PMOS-FET(Q31). The node between NMOS-FET(Q14) and NMOS-FET(Q15) is connected to the gate of NMOS-FET(Q32). The drain of PMOS-FET(Q12) is connected to the gate of NMOS-FET(Q32). The drain of NMOS-FET(Q14) is connected to the gate of NMOS-FET(Q31). PMOS-FET(Q31) and PMOS-FET(Q32) are connected in series between the power supply potential Vdd and the ground potential, and the node between them is the first output terminal (Voutn).

[0151] The node between PMOS-FET(Q22) and PMOS-FET(Q23) is connected to the gate of PMOS-FET(Q41). The node between NMOS-FET(Q24) and NMOS-FET(Q25) is connected to the gate of NMOS-FET(Q42). The drain of PMOS-FET(Q22) is connected to the gate of NMOS-FET(Q42). The drain of NMOS-FET(Q24) is connected to the gate of NMOS-FET(Q41). PMOS-FET(Q41) and PMOS-FET(Q42) are connected in series between the power supply potential Vdd and the ground potential, and the node between them is the second output terminal (Voutp).

[0152] Furthermore, Voutn = A(Voutn(NMOS) + Voutn(PMOS)) and Voutp = A(Voutp(NMOS) + Voutp(PMOS)), where A is the coefficient.

[0153] Figure 22 is a circuit diagram of the potential output circuit.

[0154] In the potential output circuit VCM, a first resistor R1 and a second resistor R2 are connected in series between the power supply potential Vdd and the fixed potential. The reference potential Vcm(Vcm_b,Vcm_f) can be the potential at the node between the first resistor R1 and the second resistor R2.

[0155] The first resistor R1 may be set to match the resistance value of the termination resistor in the transmitting driver (transmitter). Furthermore, the reference potential Vcm output by the potential output circuit VCM may also have a function to reduce the influence of common-mode voltage noise.

[0156] Figure 23 shows the circuit diagram of the transmitter TX (transmit driver DRV) (Figure 23(A)) and the circuit diagram of the receiver amplifier's potential output circuit VCM (Figure 23(B)).

[0157] The transmitter TX (transmit driver DRV) (Figure 23(A)) includes a first resistor (R1), a PMOS-FET (Q51), and an NMOS-FET (Q52) connected in series between the power supply potential Vdd and a fixed potential. A second resistor (R12) and a PMOS-FET (Q53) are directly connected between the power supply potential Vdd and the drain of the NMOS-FET (Q52). The downstream NMOS-FET (Q52) is a current source, and its gate electrode is connected to the gate of an NMOS-FET (Q54). The NMOS-FET (Q54) is connected between the bias potential (Bias) and the fixed potential. The pair of PMOS-FETs (Q51, Q53) form a differential pair, supplying an input voltage Vin+ to the gate of one PMOS-FET (Q51) and a complementary input voltage Vin- (inverting voltage) to the input voltage Vin+ to the gate of the other PMOS-FET (Q53).

[0158] The node between the first resistor R1 and the PMOS-FET (Q51) is the second output terminal D2 (Vout-). The node between the second resistor R12 and the PMOS-FET (Q53) is the first output terminal D1 (Vout+). The above-described transmitting driver DRV can have this circuit structure. Note that the first resistor (R1) and the second resistor (R12) can also be used as termination resistors for the transmission line.

[0159] The receiving amplifier's potential output circuit VCM (Figure 23(B)) has a circuit similar to that of the transmitter TX. Specifically, the potential output circuit VCM comprises a first resistor (R1), a PMOS-FET (Q51), and an NMOS-FET (Q52) connected in series between the power supply potential Vdd and a fixed potential. The downstream NMOS-FET (Q52) is a current source, and its gate electrode is connected to the gate and drain of an NMOS-FET (Q54). The NMOS-FET (Q54) is connected between the bias potential (Bias) and the fixed potential. The gate of the PMOS-FET (Q51) is supplied with a gate voltage that turns the transistor ON.

[0160] In transmitter TX, the differential input voltages (Vin+) and (Vin-) are complementary signals. The differential input voltages (Vin+) and (Vin-) are input to a pair of transistors (Q51, Q53), respectively. Let R1 be the resistance value of the first resistor (R1), R12 be the resistance value of the second resistor (R12), (Vout-) be the output voltage of the second output terminal D2, and Itail be the current flowing through the downstream NMOS-FET (Q52).

[0161] For example, if (Vin+) is a low level (=1) where PMOS-FET (Q51) turns ON, and (Vin-) is a high level (=0) where PMOS-FET (Q53) turns OFF, then (Vout-) = Vdd - (R1 × Itail) × (Vin+) = Vdd - (R1 × Itail). Also, (Vout+) = Vdd - (R12 × Itail) × (Vin-) = Vdd.

[0162] Conversely, if (Vin+) is at a high level (=0) where PMOS-FET (Q51) is OFF, and (Vin-) is at a low level (=1) where PMOS-FET (Q53) is ON, then (Vout-) = Vdd - (R1 × Itail) × (Vin+) = Vdd. Also, (Vout+) = Vdd - (R12 × Itail) × (Vin-) = Vdd - (R12 × Itail).

[0163] If the differential input voltage (signal) is a digital signal and uses commonly used coding such as 8B10B, the number of zeros and ones in (Vin+) and (Vin-) are equal, and on average, the voltages of these signals fluctuate around a center voltage of about 50% of the maximum voltage. The average value of the current flowing through the first resistor (R1) and the second resistor (R12) is (Itail / 2). The average common output voltage (Vcm) at the first output terminal D1 (Vout+) of the transmitter TX is Vcm = Vdd - (R12 × (Itail / 2)). The average common output voltage (Vcm) at the second output terminal D2 (Vout-) of the transmitter TX is Vcm = Vdd - (R1 × (Itail / 2)). Vcm is the voltage at the center of the amplitude of the output signals (Vout+, Vout-).

[0164] In the receiving amplifier's potential output circuit VCM, when generating Vcm, the current flowing through the NMOS-FET (52) and the first resistor (R1) in Figure 23(B) is set to (Itail / 2). In this case, Vcm = Vdd - (R1 × (Itail / 2)), which matches the Vcm generated in the transmitter TX.

[0165] The number of PMOS-FETs (Q51, Q53) for input in the transmitter TX is N (2 in this example), while the number of PMOS-FETs (Q51) in the receiver amplifier's potential output circuit VCM is M (1 in this example). N and M are natural numbers, and N may be a multiple of M, or M may be a multiple of N. The resistance value of the first resistor (R1) can also be changed.

[0166] Figure 24 is a circuit diagram of the potential output circuit (VCM) in the receiving amplifier.

[0167] The potential output circuit VCM of the receiver amplifier in this example is a variation of the circuit shown in Figure 23(B). The potential output circuit VCM in this example differs from the circuit in Figure 23(B) in that, in addition to the first resistor (R1), a second resistor (R12) is connected between the power supply potential Vdd and the PMOS-FET (Q51), but the other structures are the same. More specifically, the first resistor (R1) and the second resistor (R12) are connected in parallel between the power supply potential Vdd and the drain of the PMOS-FET (Q51), and the potential of this drain is output as Vcm. The resistance values ​​of the first resistor (R1) and the second resistor (R12) are equal. In this example, the same connection structure as the resistor connection structure in the transmitter TX is adopted. (Itail) flows through the NMOS-FET (52). Vcm = Vdd - (R1 × R12 / (R1 + R12)) × (Itail) = Vdd - (R1 × (Itail / 2)), which matches the Vcm generated at the transmitter TX.

[0168] Figure 25 shows the circuit diagram of an example transmitter TX (transmit driver DRV) (Figure 25(A)) and the circuit diagram of the potential output circuit VCM in the receiving amplifier (Figure 25(B)).

[0169] The transmitter TX (transmit driver) (Figure 25(A)) comprises a first transmitter TX1 and a second transmitter TX2.

[0170] The first transmitter TX1 includes a PMOS-FET (Q51), a resistor (R51), a resistor (R52), and an NMOS-FET (Q52) connected in series between the power supply potential Vdd and a fixed potential. The gates of the PMOS-FET (Q51) and NMOS-FET (Q52) of the first transmitter TX1 are connected, and one input voltage (Vin-) of the differential input signal is applied to these gates. One output signal is output from the first output terminal D1 (Vout+).

[0171] The circuit structure of the second transmitter TX2 is identical to that of the first transmitter TX1. The gates of the PMOS-FET (Q51) and NMOS-FET (Q52) of the second transmitter TX2 are connected, and the other input voltage (Vin+) of the differential input signal is applied to these gates. The other output signal is output from the second output terminal D2 (Vout-).

[0172] The receiving amplifier's potential output circuit VCM (Figure 25(B)) contains some of the same circuit structure as the transmitter TX. This circuit comprises a PMOS-FET (Q51), a resistor (R51), a resistor (R52), and an NMOS-FET (Q52) connected in series between the power supply potential Vdd and a fixed potential. The gates of the PMOS-FET (Q51) and NMOS-FET (Q52) are connected, and these gates are connected to the node between the resistors (R51) and (R52). The potential at this node generates the reference potential Vcm. The output signal of the transmitter TX also includes the reference potential Vcm as the amplitude center.

[0173] Figure 26 shows the circuit diagram of the transmitter (Figure 26(A)) and the circuit diagram of the potential output circuit VCM in the receiving amplifier (Figure 26(B)).

[0174] The transmitter TX (transmit driver) (Figure 26(A)) comprises a first transmitter TX1 and a second transmitter TX2.

[0175] The first transmitter TX1 includes a PMOS-FET (Q51) and an NMOS-FET (Q52) connected in series between the power supply potential Vdd and a fixed potential. The gates of the PMOS-FET (Q51) and NMOS-FET (Q52) of the first transmitter TX1 are connected, and one input voltage (Vin-) of the differential input signal is applied to these gates. A resistor (R50) is connected between the connection point of the PMOS-FET (Q51) and NMOS-FET (Q52) and the first output terminal D1 (Vout+). One output signal is output from the first output terminal (Vout+).

[0176] The circuit structure of the second transmitter TX2 is identical to that of the first transmitter TX1. The other input voltage (Vin+) of the differential input signal is applied to the connection point between the gate of the PMOS-FET (Q51) and the gate of the NMOS-FET (Q52) of the first transmitter TX1. The other output signal is output from the second output terminal D2 (Vout-).

[0177] The receiving amplifier's potential output circuit VCM (Figure 26(B)) contains some of the same circuit structure as the transmitter TX. This circuit comprises a PMOS-FET (Q51), a resistor (R51), a resistor (R52), and an NMOS-FET (Q52) connected in series between the power supply potential Vdd and a fixed potential. The gates of the PMOS-FET (Q51) and NMOS-FET (Q52) are connected, and this connection point is connected via a resistor (R501) to the connection point between the drains of the PMOS-FET (Q51) and NMOS-FET (Q52). The potential at this connection point (node) generates the reference potential Vcm. The output signal of the transmitter TX also includes the reference potential Vcm as the amplitude center.

[0178] If the transmitter TX (transmit driver DRV) outputs a differential signal, then the gates of the first transmitter TX1 and the second transmitter TX2 should be input with the differential signal. If the transmitter TX (transmit driver DRV) outputs a common-mode signal, then the gates of the first transmitter TX1 and the second transmitter TX2 should be input with the common-mode signal, or an inverter should be used to invert the output of one of the transmitters.

[0179] In the above explanation, in order to distinguish between signals from different receiving amplifiers, the first voltage V1, second voltage V2, third voltage V3, and fourth voltage V4 can be reinterpreted as the first voltage V1', second voltage V2', third voltage V3', and fourth voltage V4', respectively.

[0180] As described above, the various embodiments in this disclosure may be defined as follows.

[0181] The first embodiment of the simultaneous bidirectional transmitting and receiving device (see Figure 1) includes a transmitting driver connected to a first terminal of a first transmission line and a receiving amplifier connected to the first terminal. The transmitting driver is a differential driver including a first output terminal that outputs a first signal and a second output terminal that outputs a second signal that is in opposite phase to the first signal. The receiving amplifier includes a first input terminal connected to the first terminal and the first output terminal, a second input terminal connected to a reference potential, a third input terminal connected to the second output terminal, and a fourth input terminal connected to a reference potential. The receiving amplifier has an output terminal that outputs a signal proportional to (V1-V2)+(V3-V4) when a first voltage V1 is input to the first input terminal, a second voltage V2 is input to the second input terminal, a third voltage V3 is input to the third input terminal, and a fourth voltage V4 is input to the fourth input terminal. The receiving amplifier RA outputs a signal obtained by adding the signal input to the first input terminal T1 and the signal input to the third input terminal T3.

[0182] The second embodiment of the simultaneous bidirectional transmitting and receiving device (see Figures 2 and 3) includes a transmitting driver connected to a first terminal of a first transmission line and a receiving amplifier connected to the first terminal. The transmitting driver is an in-phase driver including a first output terminal that outputs a first signal and a second output terminal that outputs a second signal in phase with the first signal. The receiving amplifier includes a first input terminal connected to the first terminal and the first output terminal, a second input terminal connected to the second output terminal, a third input terminal connected to a reference potential, and a fourth input terminal connected to a reference potential. The receiving amplifier has an output terminal that outputs a signal proportional to (V1-V2)-(V3-V4) when a first voltage V1 is input to the first input terminal, a second voltage V2 to the second input terminal, a third voltage V3 to the third input terminal, and a fourth voltage V4 to the fourth input terminal. The receiving amplifier RA outputs a signal obtained by subtracting the signal input to the third input terminal T3 from the signal input to the first input terminal T1.

[0183] A third embodiment of the simultaneous bidirectional transmitting and receiving device (see Figures 4 and 5) comprises a transmitting driver connected to a first terminal of a first transmission line and a second terminal of a second transmission line, and a receiving amplifier connected to the first terminal and the second terminal. The transmitting driver is a differential driver including a first output terminal that outputs a first signal and a second output terminal that outputs a second signal that is in opposite phase to the first signal. The receiving amplifier includes a first input terminal connected to the first terminal and the first output terminal, a second input terminal connected to a reference potential, a third input terminal connected to the second terminal and the second output terminal, and a fourth input terminal connected to a reference potential. The receiving amplifier has an output terminal that outputs a signal proportional to (V1-V2)+(V3-V4) when a first voltage V1 is input to the first input terminal, a second voltage V2 is input to the second input terminal, a third voltage V3 is input to the third input terminal, and a fourth voltage V4 is input to the fourth input terminal.

[0184] The fourth embodiment of the simultaneous bidirectional transmitting and receiving device (see Figures 4 and 5) comprises a transmitting driver connected to a first terminal of a first transmission line and a second terminal of a second transmission line, and a receiving amplifier connected to the first terminal and the second terminal. The transmitting driver is an in-phase driver including a first output terminal that outputs a first signal and a second output terminal that outputs a second signal that is in phase with respect to the first signal. The receiving amplifier includes a first input terminal connected to the first terminal and the first output terminal, a second input terminal connected to the second terminal and the second output terminal, a third input terminal connected to a reference potential, and a fourth input terminal connected to a reference potential. The receiving amplifier has an output terminal that outputs a signal proportional to (V1-V2)-(V3-V4) when a first voltage V1 is input to the first input terminal, a second voltage V2 is input to the second input terminal, a third voltage V3 is input to the third input terminal, and a fourth voltage V4 is input to the fourth input terminal.

[0185] The fifth embodiment of the simultaneous bidirectional transmitting and receiving device (see Figure 7) includes a receiving amplifier comprising: a first transistor having a first gate; a second transistor having a second gate; a third transistor having a third gate; a fourth transistor having a fourth gate; a first resistor interposed between the drains of the first transistor and the third transistor and the power supply potential; a second resistor interposed between the drains of the second transistor and the fourth transistor and the power supply potential; a first output terminal provided downstream of the first resistor; a second output terminal provided downstream of the second resistor; and a current source to which the sources of the first transistor, the second transistor, the third transistor, and the fourth transistor are connected, wherein the first gate is connected to the first input terminal, the second gate is connected to the second input terminal, the third gate is connected to the third input terminal, and the fourth gate is connected to the fourth input terminal.

[0186] The sixth embodiment of the simultaneous bidirectional transmitting and receiving device (see Figure 8) includes a receiving amplifier comprising: a first transistor having a first gate; a second transistor having a second gate; a third transistor having a third gate; a fourth transistor having a fourth gate; a first resistor interposed between the drains of the first transistor and the third transistor and the power supply potential; a second resistor interposed between the drains of the second transistor and the fourth transistor and the power supply potential; a first output terminal provided downstream of the first resistor; a second output terminal provided downstream of the second resistor; a first current source to which the sources of the first and second transistors are connected; and a second current source to which the sources of the third and fourth transistors are connected. The first gate is connected to a first input terminal; the second gate is connected to a second input terminal; the third gate is connected to a third input terminal; and the fourth gate is connected to a fourth input terminal.

[0187] The seventh embodiment of the simultaneous bidirectional transmitting and receiving device (see Figure 10) includes a receiving amplifier comprising: a first transistor having a first gate; a second transistor having a second gate; a third transistor having a third gate; a fourth transistor having a fourth gate; a first resistor interposed between the drains of the first transistor and the fourth transistor and the power supply potential; a second resistor interposed between the drains of the second transistor and the third transistor and the power supply potential; a first output terminal provided downstream of the first resistor; a second output terminal provided downstream of the second resistor; and a current source to which the sources of the first transistor, the second transistor, the third transistor, and the fourth transistor are connected, wherein the first gate is connected to the first input terminal, the second gate is connected to the second input terminal, the third gate is connected to the third input terminal, and the fourth gate is connected to the fourth input terminal.

[0188] The eighth embodiment of the simultaneous bidirectional transmitting and receiving device (see Figure 11) includes a receiving amplifier comprising: a first transistor having a first gate; a second transistor having a second gate; a third transistor having a third gate; a fourth transistor having a fourth gate; a first resistor interposed between the drains of the first transistor and the fourth transistor and the power supply potential; a second resistor interposed between the drains of the second transistor and the third transistor and the power supply potential; a first output terminal provided downstream of the first resistor; a second output terminal provided downstream of the second resistor; a first current source to which the sources of the first and second transistors are connected; and a second current source to which the sources of the third and fourth transistors are connected. The first gate is connected to a first input terminal; the second gate is connected to a second input terminal; the third gate is connected to a third input terminal; and the fourth gate is connected to a fourth input terminal.

[0189] The simultaneous bidirectional transmitting and receiving device of the ninth embodiment (see Figure 12) includes a first switch that connects the second input terminal of the receiving amplifier to a reference potential, a second switch that connects the second input terminal of the receiving amplifier to a second output terminal, a third switch that connects the third input terminal of the receiving amplifier to a second output terminal, and a fourth switch that connects the third input terminal of the receiving amplifier to a reference potential.

[0190] The tenth embodiment of the simultaneous bidirectional transmitting and receiving device (see Figure 14) includes a receiving amplifier comprising a first feedback transistor and a second feedback transistor, wherein the gate of the first feedback transistor is connected to the first output terminal of the receiving amplifier, the drain of the first feedback transistor is connected to the drain of the first transistor, the gate of the second feedback transistor is connected to the second output terminal of the receiving amplifier, and the drain of the second feedback transistor is connected to the drain of the second transistor.

[0191] The 11th embodiment of the simultaneous bidirectional transmitting and receiving device (see Figure 15) includes a receiving amplifier comprising a first feedback transistor, a second feedback transistor, and a third current source to which the sources of the first and second feedback transistors are connected, wherein the gate of the first feedback transistor is connected to the first output terminal of the receiving amplifier, the drain of the first feedback transistor is connected to the drain of the first transistor, the gate of the second feedback transistor is connected to the second output terminal of the receiving amplifier, and the drain of the second feedback transistor is connected to the drain of the second transistor.

[0192] The communication system according to the above-described embodiment comprises one of the above-described simultaneous bidirectional transceivers and a second simultaneous bidirectional transceiver and a second transceiver and a second transceiver that communicates with the aforementioned simultaneous bidirectional transceiver and a second.

[0193] The differential signaling communication system described above (see Figures 4 and 5) is a communication system comprising a simultaneous bidirectional transceiver (TRB) and a second simultaneous bidirectional transceiver (TRF) that communicates with the TRB, wherein the terminal opposite to the first terminal B1 of the first transmission line TL1 is designated as the third terminal F1, and the terminal opposite to the second terminal B2 of the second transmission line TL2 is designated as the fourth terminal F2, and the second simultaneous bidirectional transceiver (TRF) comprises a second transmit driver DRV (FC side) connected to the third terminal F1, and a second receive amplifier RA (FC side) connected to the third terminal F1 and the fourth terminal F2, and the second transmit driver DRV (FC side) has a first output terminal D1 (FC side) that outputs a third signal (FC), and a second output terminal D2 (F) that outputs a fourth signal (-FC+Vcm_f) that is in the opposite phase to the third signal. The differential driver includes the C side and the second receiving amplifier RA (FC side), which includes a first input terminal T1 connected to the third terminal F1 and the first output terminal D1 (FC side) of the second transmitting driver DRV (FC side), a second input terminal T2 connected to a reference potential Vcm_f, a third input terminal T3 connected to the fourth terminal F2 and the second output terminal D2 (FC side) of the second transmitting driver DRV, and a fourth input terminal T4 connected to a reference potential Vcm_f. The second receiving amplifier RA (FC side) has an output terminal that outputs a signal that yields a signal proportional to (V1'-V2')+(V3'-V4') when a first voltage V1' is input to the first input terminal of the second receiving amplifier, a second voltage V2' is input to the second input terminal of the second receiving amplifier, a third voltage V3' is input to the third input terminal of the second receiving amplifier, and a fourth voltage V4' is input to the fourth input terminal of the second receiving amplifier.

[0194] While various exemplary embodiments have been described above, the present invention is not limited to these exemplary embodiments, and various omissions, substitutions, and modifications may be made. Furthermore, elements from different embodiments can be combined to form other embodiments. From the above description, it will be understood that various embodiments of this disclosure are described herein and can be modified in various ways without departing from the scope and spirit of this disclosure. Therefore, the various embodiments disclosed herein are not intended to be limiting, and the true scope and spirit are indicated by the claims. [Explanation of symbols]

[0195] ADD…Current adder (adding amplifier), B1…Terminal 1, B2…Terminal 2, CS…Current source, CB1…Capacitor 1, CB2…Capacitor 2, CF1…Capacitor 3, CF2…Capacitor 4, D1…Output terminal 1, D2…Output terminal 2, DRV…Transmitter driver, F1…Terminal 3, F2…Terminal 4, G1…Gate 1, G2…Gate 2, G3…Gate 3, G4…Gate 4, INV1…Inverter 1, INV2…Inverter 2, N1…Node, Q1…Transistor 1, Q2…Transistor 2, Q3…Transistor 3, Q4…Transistor 4, Q10…Feedback transistor 1, Q20…Feedback transistor 2, R L1 …First resistor, R L2 ...2nd resistor, RA...Receiver amplifier, R1...1st resistor, R2...2nd resistor, RB...1st load resistor, RF...2nd load resistor, SW1...1st switch, SW2...2nd switch, SW3...3rd switch, SW4...4th switch, SW5...5th switch, SW6...6th switch, SW7...7th switch, SW8...8th switch, SW9...9th switch, TL1...1st transmission line, TL2...2nd transmission line, TX...Transmitter (transmitter driver), T1...1st input terminal, T2...2nd input terminal, T3...3rd input terminal, T4...4th input terminal, T10...1st feedback terminal, T20...2nd feedback terminal, V1...1st voltage, V2...2nd voltage, V3...3rd voltage, V4...4th voltage, VCM...Potential output circuit, Vcm...Reference potential, Vdd...Power supply potential, Vin...Input voltage, Vout...Output voltage.

Claims

1. A transmitting driver connected to the first terminal of the first transmission line, The receiving amplifier connected to the first terminal, Equipped with, The sending driver is, A first output terminal that outputs the first signal, A second output terminal outputs a second signal that is inverse phase to the first signal, It is a differential driver that includes, The receiving amplifier is, A first input terminal connected to the first terminal and the first output terminal, A second input terminal connected to the reference potential, The third input terminal is connected to the second output terminal, The fourth input terminal is connected to the reference potential, Includes, The receiving amplifier is, First input terminal receives first voltage V1, The second input terminal receives the second voltage V2. Third input terminal has third voltage V3. The fourth input terminal receives the fourth voltage V4. If this is entered, It has an output terminal that outputs a signal that is proportional to (V1-V2) + (V3-V4), Simultaneous bidirectional transmission and reception device.

2. A transmitting driver connected to the first terminal of the first transmission line, The receiving amplifier connected to the first terminal, Equipped with, The sending driver is, A first output terminal that outputs the first signal, A second output terminal that outputs a second signal in phase with the first signal, It is an in-phase driver that includes, The receiving amplifier is, A first input terminal connected to the first terminal and the first output terminal, The second input terminal is connected to the second output terminal, A third input terminal connected to the reference potential, The fourth input terminal is connected to the reference potential, Includes, The receiving amplifier is, First input terminal receives first voltage V1, The second input terminal receives the second voltage V2. Third input terminal has third voltage V3. The fourth input terminal receives the fourth voltage V4. If this is entered, It has an output terminal that outputs a signal that is proportional to (V1-V2)-(V3-V4), Simultaneous bidirectional transmission and reception device.

3. A transmitting driver connected to the first terminal of the first transmission line and the second terminal of the second transmission line, A receiving amplifier connected to the first and second terminals, Equipped with, The sending driver is, A first output terminal that outputs the first signal, A second output terminal outputs a second signal that is inverse phase to the first signal, It is a differential driver that includes, The receiving amplifier is, A first input terminal connected to the first terminal and the first output terminal, A second input terminal connected to the reference potential, A third input terminal connected to the second terminal and the second output terminal, The fourth input terminal is connected to the reference potential, Includes, The receiving amplifier is, First input terminal receives first voltage V1, The second input terminal receives the second voltage V2. Third input terminal has third voltage V3. The fourth input terminal receives the fourth voltage V4. If this is entered, It has an output terminal that outputs a signal that is proportional to (V1-V2) + (V3-V4), Simultaneous bidirectional transmission and reception device.

4. A transmitting driver connected to the first terminal of the first transmission line and the second terminal of the second transmission line, A receiving amplifier connected to the first and second terminals, Equipped with, The sending driver is, A first output terminal that outputs the first signal, A second output terminal that outputs a second signal that is in phase with the first signal, It is an in-phase driver that includes, The receiving amplifier is, A first input terminal connected to the first terminal and the first output terminal, A second input terminal connected to the second terminal and the second output terminal, A third input terminal connected to the reference potential, The fourth input terminal is connected to the reference potential, Includes, The receiving amplifier is, First input terminal receives first voltage V1, The second input terminal receives the second voltage V2. Third input terminal has third voltage V3. The fourth input terminal receives the fourth voltage V4. If this is entered, It has an output terminal that outputs a signal that is proportional to (V1-V2)-(V3-V4), Simultaneous bidirectional transmission and reception device.

5. The receiving amplifier is, A first transistor having a first gate, A second transistor having a second gate, A third transistor having a third gate, A fourth transistor having a fourth gate, A first resistor is interposed between the drain of the first transistor and the drain of the third transistor and the power supply potential, A second resistor is interposed between the drain of the second transistor and the drain of the fourth transistor and the power supply potential, A first output terminal located downstream of the first resistor, A second output terminal located downstream of the second resistor, A current source to which the sources of the first transistor, second transistor, third transistor, and fourth transistor are connected, Equipped with, The first gate is connected to the first input terminal. The second gate is connected to the second input terminal. The third gate is connected to the third input terminal. The fourth gate is connected to the fourth input terminal. The simultaneous bidirectional transmitting and receiving device according to claim 1 or claim 3.

6. The receiving amplifier is, A first transistor having a first gate, A second transistor having a second gate, A third transistor having a third gate, A fourth transistor having a fourth gate, A first resistor is interposed between the drain of the first transistor and the drain of the third transistor and the power supply potential, A second resistor is interposed between the drain of the second transistor and the drain of the fourth transistor and the power supply potential, A first output terminal located downstream of the first resistor, A second output terminal located downstream of the second resistor, A first current source to which the sources of the first and second transistors are connected, A second current source to which the sources of the third and fourth transistors are connected, Equipped with, The first gate is connected to the first input terminal. The second gate is connected to the second input terminal. The third gate is connected to the third input terminal. The fourth gate is connected to the fourth input terminal. The simultaneous bidirectional transmitting and receiving device according to claim 1 or claim 3.

7. The receiving amplifier is, A first transistor having a first gate, A second transistor having a second gate, A third transistor having a third gate, A fourth transistor having a fourth gate, A first resistor is interposed between the drain of the first transistor and the drain of the fourth transistor and the power supply potential, A second resistor is interposed between the drain of the second transistor and the drain of the third transistor and the power supply potential, A first output terminal located downstream of the first resistor, A second output terminal located downstream of the second resistor, A current source to which the sources of the first transistor, second transistor, third transistor, and fourth transistor are connected, Equipped with, The first gate is connected to the first input terminal. The second gate is connected to the second input terminal. The third gate is connected to the third input terminal. The fourth gate is connected to the fourth input terminal. The simultaneous bidirectional transmitting and receiving device according to claim 2 or claim 4.

8. The receiving amplifier is, A first transistor having a first gate, A second transistor having a second gate, A third transistor having a third gate, A fourth transistor having a fourth gate, A first resistor is interposed between the drain of the first transistor and the drain of the fourth transistor and the power supply potential, A second resistor is interposed between the drain of the second transistor and the drain of the third transistor and the power supply potential, A first output terminal located downstream of the first resistor, A second output terminal located downstream of the second resistor, A first current source to which the sources of the first and second transistors are connected, A second current source to which the sources of the third and fourth transistors are connected, Equipped with, The first gate is connected to the first input terminal. The second gate is connected to the second input terminal. The third gate is connected to the third input terminal. The fourth gate is connected to the fourth input terminal. The simultaneous bidirectional transmitting and receiving device according to claim 2 or claim 4.

9. A first switch connects the second input terminal of the receiving amplifier to a reference potential, A second switch connects the second input terminal of the receiving amplifier to the second output terminal, A third switch connects the third input terminal of the receiving amplifier to the second output terminal, A fourth switch connects the third input terminal of the receiving amplifier to a reference potential, Equipped with, A simultaneous bidirectional transmitting and receiving device according to any one of claims 1 to 3.

10. The receiving amplifier is, First feedback transistor, Second feedback transistor, Equipped with, The gate of the first feedback transistor is connected to the first output terminal of the receiving amplifier. The drain of the first feedback transistor is connected to the drain of the first transistor. The gate of the second feedback transistor is connected to the second output terminal of the receiving amplifier. The drain of the second feedback transistor is connected to the drain of the second transistor. The simultaneous bidirectional transmitting and receiving device according to claim 5.

11. The receiving amplifier is, First feedback transistor, Second feedback transistor, A third current source to which the sources of the first and second feedback transistors are connected, Equipped with, The gate of the first feedback transistor is connected to the first output terminal of the receiving amplifier. The drain of the first feedback transistor is connected to the drain of the first transistor. The gate of the second feedback transistor is connected to the second output terminal of the receiving amplifier. The drain of the second feedback transistor is connected to the drain of the second transistor. The simultaneous bidirectional transmitting and receiving device according to claim 6.

12. A simultaneous bidirectional transmitting and receiving device according to claim 1 or claim 2, A second simultaneous bidirectional transceiver that communicates with this simultaneous bidirectional transceiver, A communication system equipped with this system.

13. The simultaneous bidirectional transmitting and receiving device according to claim 4, A second simultaneous bidirectional transceiver that communicates with this simultaneous bidirectional transceiver, In a communication system equipped with, The terminal on the opposite side of the first terminal of the first transmission line is designated as the third terminal. The terminal on the opposite side of the second terminal of the second transmission line is designated as the fourth terminal. The second simultaneous bidirectional transmitting and receiving device is: A second transmitting driver connected to the third terminal, A second receiving amplifier connected to the third and fourth terminals, Equipped with, The second transmission driver is, A first output terminal that outputs a third signal, A second output terminal outputs a fourth signal that is inverse phase to the third signal, It is a differential driver that includes, The second receiving amplifier is, The third terminal and the first input terminal connected to the first output terminal of the second transmitting driver, A second input terminal connected to the reference potential, The third input terminal is connected to the fourth terminal and the second output terminal of the second transmitting driver, The fourth input terminal is connected to the reference potential, Includes, The second receiving amplifier is, The first voltage V1' is applied to the first input terminal of the second receiving amplifier. The second voltage V2' is applied to the second input terminal of the second receiving amplifier. A third voltage V3' is applied to the third input terminal of the second receiving amplifier. The fourth voltage V4' is applied to the fourth input terminal of the second receiving amplifier. If this is entered, It has an output terminal that outputs a signal that is proportional to (V1' - V2') + (V3' - V4'), Communication system.

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