Indication device

JP2026094250AActive Publication Date: 2026-06-09SEMICON ENERGY LAB CO LTD

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
SEMICON ENERGY LAB CO LTD
Filing Date
2026-02-25
Publication Date
2026-06-09

AI Technical Summary

Benefits of technology

【0016】 開示する発明において、一例として、オフ電流の低い酸化物半導体を有するトランジスタ を用いて、回路を構成する。そのため、不要な電流が漏れて入ってきてしまうことを防ぐ ことが出来る。よって、正確な表示を行うことが出来る。

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Abstract

The objective is to provide semiconductor devices with low off-current, or to provide accurate table The objective is to provide a semiconductor device that performs a display, or a display device with a wide viewing angle. The objective is to provide such a device, or a display device that reduces screen burn-in. The task is to accomplish this. [Solution] In order to solve the above problem, oxide semiconductor (OS) A transistor having a (transistor), in particular a thin-film MOS transistor having an oxide semiconductor. And so, it forms a circuit. That oxide semiconductor is essentially an intrinsic semiconductor. Therefore, the off-current is very low.
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Claims

1. Within a single pixel, there is a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first to third subpixels are arranged in the column direction. The first sub-pixel has a first transistor, The second sub-pixel has a second transistor, The third sub-pixel has a third transistor, Either the source or the drain of the first transistor is always in electrical contact with the first source wiring. The gate of the first transistor is always in contact with the first gate signal line. Either the source or the drain of the second transistor is always in electrical contact with the second source wiring. The gate of the second transistor is always in contact with the first gate signal line. Either the source or drain of the third transistor is always in electrical contact with the third source wiring. The gate of the third transistor is always in contact with the first gate signal line. The channel length of the first transistor is approximately equal to the channel length of the second transistor. The channel length of the first transistor is approximately equal to the channel length of the third transistor. At least one of the first to third transistors is The first insulating layer, An oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel-forming region, A second insulating layer having a region in contact with the upper surface of the oxide semiconductor layer, A third insulating layer having a region located above the second insulating layer, The first insulating layer comprises oxygen and silicon, The second insulating layer comprises oxygen and silicon. The above-mentioned third insulating layer is a display device having nitrogen and silicon.

2. Within a single pixel, there is a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first to third subpixels are arranged in the column direction. The first sub-pixel has a first transistor, The second sub-pixel has a second transistor, The third sub-pixel has a third transistor, Either the source or the drain of the first transistor is always in electrical contact with the first source wiring. The gate of the first transistor is always in contact with the first gate signal line. Either the source or the drain of the second transistor is always in electrical contact with the second source wiring. The gate of the second transistor is always in contact with the first gate signal line. Either the source or drain of the third transistor is always in electrical contact with the third source wiring. The gate of the third transistor is always in contact with the first gate signal line. The ratio of the channel width to the channel length of the first transistor is approximately equal to the ratio of the channel width to the channel length of the second transistor. The ratio of the channel width to the channel length of the first transistor is approximately equal to the ratio of the channel width to the channel length of the third transistor. At least one of the first to third transistors is The first insulating layer, An oxide semiconductor layer having a region in contact with the upper surface of the first insulating layer and having a channel-forming region, A second insulating layer having a region in contact with the upper surface of the oxide semiconductor layer, A third insulating layer having a region located above the second insulating layer, The first insulating layer comprises oxygen and silicon, The second insulating layer comprises oxygen and silicon. The above-mentioned third insulating layer is a display device having nitrogen and silicon.