Photoelectric conversion element and imaging device

Abstract

To provide a photoelectric conversion element, etc., that can reduce parasitic sensitivity. [Solution] The photoelectric conversion element 10 comprises an upper electrode 6, a lower electrode 2, a photoelectric conversion layer 4 located between the upper electrode 6 and the lower electrode 2 and converting light into signal charge, and an electron blocking layer 3 located between the lower electrode 2 and the photoelectric conversion layer 4. When a first voltage is applied between the upper electrode 6 and the lower electrode 2, the capacitance between the upper electrode 6 and the lower electrode 2 is 1.5 times or more the capacitance between the upper electrode 6 and the lower electrode 2 when a second voltage different from the first voltage is applied between the upper electrode 6 and the lower electrode 2.

Description

Technical Field

[0001] The present disclosure relates to a photoelectric conversion element and an imaging device.

Background Art

[0002] Organic semiconductor materials have physical properties and functions that are not possessed by conventional inorganic semiconductor materials such as silicon. Therefore, in recent years, organic semiconductor materials have been actively studied as semiconductor materials that can realize new semiconductor devices and electronic devices.

[0003] For example, research has been conducted on realizing a photoelectric conversion element by thinning an organic semiconductor material and using it as a photoelectric conversion layer. A photoelectric conversion element using a thin film of an organic material can be used as a sensor such as an imaging device by extracting charges generated by light as an electrical signal.

[0004] For example, Patent Document 1 discloses a photoelectric conversion element provided with an electron blocking layer or a hole blocking layer between a photoelectric conversion layer and an electrode so as to prevent the backflow of charges from the electrode.

[0005] Also, Patent Document 2 discloses an imaging device that realizes a global shutter function by controlling the voltage applied to an electrode sandwiching a photoelectric conversion layer to be near 0V, thereby suppressing the accumulation of signal charges in a charge accumulation region. In Patent Document 2, the global shutter function is realized only by controlling the voltage applied to the electrode sandwiching the photoelectric conversion layer without passing through a transfer transistor.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

[0007] [Non-Patent Document 1] Masao Mizuno, et al., "Influence of Impurities on the Electronic State of Indium Oxide," KOBE STEEL ENGINEERING REPORTAS, December 1998, Vol. 48, No. 3, pp. 39-42. [Overview of the project] [Problems that the invention aims to solve]

[0008] However, for example, when implementing a global shutter function, simply controlling the voltage across the photoelectric conversion layer is insufficient to completely eliminate charges that are different from the desired signal, such as charges remaining in the photoelectric conversion layer during charge readout, and charges generated by incident light when a voltage near 0V is applied. As a result, there is a problem in photoelectric conversion elements and imaging devices where parasitic sensitivity, which is an unintended sensitivity caused by such charges, occurs.

[0009] Therefore, the object of this disclosure is to provide a photoelectric conversion element and an imaging device that can reduce parasitic sensitivity. [Means for solving the problem]

[0010] A photoelectric conversion element according to one aspect of the present disclosure comprises a first electrode, a second electrode, a photoelectric conversion layer located between the first electrode and the second electrode and converting light into a signal charge, and a charge blocking layer located between the second electrode and the photoelectric conversion layer, wherein the capacitance between the first electrode and the second electrode when a first voltage is applied between them is 1.5 times or more the capacitance between the first electrode and the second electrode when a second voltage different from the first voltage is applied between them.

[0011] In addition, an imaging device according to an aspect of the present disclosure includes the above photoelectric conversion element and a charge detection circuit that detects the signal charge during a period in which the first voltage is applied between the first electrode and the second electrode.

Advantages of the Invention

[0012] According to the present disclosure, it is possible to provide a photoelectric conversion element and an imaging device capable of reducing parasitic sensitivity.

Brief Description of the Drawings

[0013] [Figure 1] FIG. 1 is a schematic cross-sectional view showing the configuration of a photoelectric conversion element according to an embodiment. [Figure 2] FIG. 2 is an exemplary energy band diagram of a photoelectric conversion element according to an embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view showing the configuration of another photoelectric conversion element according to an embodiment. [Figure 4] FIG. 4 is an exemplary energy band diagram of another photoelectric conversion element according to an embodiment. [Figure 5A] FIG. 5A is an exemplary energy band diagram when a reverse bias voltage is applied to a photoelectric conversion element according to an embodiment. [Figure 5B] FIG. 5B is an exemplary energy band diagram when a forward bias voltage is applied to a photoelectric conversion element according to an embodiment. [Figure 6A] FIG. 6A is an exemplary energy band diagram when a reverse bias voltage is applied to another photoelectric conversion element according to an embodiment. [Figure 6B] FIG. 6B is an exemplary energy band diagram when a forward bias voltage is applied to another photoelectric conversion element according to an embodiment. [Figure 7] FIG. 7 is a diagram showing an example of schematic capacitance-voltage characteristics of a photoelectric conversion element. [Figure 8] FIG. 8 is a diagram showing an example of the circuit configuration of an imaging device according to an embodiment. [Figure 9]FIG. 9 is a schematic cross-sectional view showing the device structure of pixels in the imaging device according to the embodiment. [Figure 10] FIG. 10 is a diagram showing an example of the schematic current-voltage characteristics of the photoelectric conversion unit according to the embodiment. [Figure 11] FIG. 11 is a diagram showing a part of the schematic circuit configuration of pixels according to the embodiment. [Figure 12] FIG. 12 is a timing chart showing an example of the voltage supplied to the upper electrode of the photoelectric conversion unit according to the embodiment and the timing of operations in each row of the pixel array of the imaging device. [Figure 13] FIG. 13 is a timing chart showing an example of an operation for adjusting the sensitivity of photoelectric conversion by a pulse duty control method in the imaging device according to the embodiment. [Figure 14A] FIG. 14A is a diagram showing the schematic configuration of the photoelectric conversion element in Examples 1 to 3. [Figure 14B] FIG. 14B is a diagram showing the schematic configuration of the photoelectric conversion element in Examples 4 to 8. [Figure 15] FIG. 15 is a diagram showing the schematic configuration of the photoelectric conversion element in Comparative Examples 1 to 3.

Embodiments for Carrying Out the Invention

[0014] (Summary of the Present Disclosure) As an overview of one aspect of the present disclosure, examples of the photoelectric conversion element and the imaging device according to the present disclosure are shown below.

[0015] The photoelectric conversion element according to the first aspect of the present disclosure includes a first electrode, a second electrode, a photoelectric conversion layer located between the first electrode and the second electrode that converts light into signal charges, and a charge blocking layer located between the second electrode and the photoelectric conversion layer. When a first voltage is applied between the first electrode and the second electrode, the capacitance between the first electrode and the second electrode is 1.5 times or more the capacitance between the first electrode and the second electrode when a second voltage different from the first voltage is applied between the first electrode and the second electrode.

[0016] Normally, the capacitance between the first and second electrodes represents the capacitance derived from the dielectric constant, distance, and area of ​​all layers sandwiched between the first and second electrodes. However, depending on the voltage applied between the first and second electrodes, the capacitance may be larger than when the entire area between the first and second electrodes is considered a dielectric. This represents the injection of charge from the electrodes into the photoelectric conversion layer. In the photoelectric conversion element according to this embodiment, of the two voltages applied between the first and second electrodes, the capacitance when the first voltage is applied is 1.5 times or more than the capacitance when the second voltage is applied, meaning the capacitance is larger when the first voltage is applied. In other words, when the first voltage is applied between the first and second electrodes, charge injection into the photoelectric conversion layer is more likely to occur. Therefore, when the first voltage is applied between the first and second electrodes, it is possible to effectively cancel out charges of the opposite polarity to the charges injected from the electrodes that remain in the photoelectric conversion layer. As a result, the generation of sensitivity caused by residual charge in the photoelectric conversion layer can be suppressed, and parasitic sensitivity can be reduced.

[0017] Furthermore, for example, a photoelectric conversion element according to a second aspect of the present disclosure is a photoelectric conversion element according to a first aspect, wherein the absolute value of the first voltage is smaller than the absolute value of the second voltage, the first voltage is a voltage that does not cause sensitivity in the photoelectric conversion element, and the second voltage is a voltage that causes sensitivity in the photoelectric conversion element.

[0018] This allows for the reduction of parasitic sensitivity by canceling out residual charge in the photoelectric conversion layer when a first voltage is applied between the first and second electrodes, thereby preventing intentional sensitivity from being generated in the photoelectric conversion element. For example, the period during which the first voltage is applied between the first and second electrodes can be used as a non-exposure period in global shutter driving to read out signal charges while reducing parasitic sensitivity. Furthermore, for example, by using the first and second voltages as the voltages for adjusting the sensitivity of the photoelectric conversion element using a pulse duty cycle control method, sensitivity adjustment can be performed while suppressing parasitic sensitivity.

[0019] Furthermore, for example, a photoelectric conversion element according to a third aspect of the present disclosure is a photoelectric conversion element according to the first or second aspect, wherein the signal charge is a hole, and the first voltage is -3V or more and 0V or less with reference to the potential of the second electrode.

[0020] As a result, when a first voltage is applied between the first and second electrodes, electrons, which have a charge opposite in polarity to the signal charge, are more easily injected from the second electrode into the photoelectric conversion layer. This increases the recombination of holes and electrons in the photoelectric conversion layer, thereby reducing parasitic sensitivity.

[0021] Furthermore, for example, a photoelectric conversion element according to a fourth aspect of this disclosure is a photoelectric conversion element according to any one of the first to third aspects, wherein it is located between the photoelectric conversion layer and the first electrode, It further comprises an intermediate layer having intermediate energy levels.

[0022] As a result, when a first voltage is applied between the first electrode and the second electrode, the intermediate level of the intermediate layer can increase the injection of charge from the first electrode to the photoelectric conversion layer, increasing the cancellation of signal charges in the photoelectric conversion layer and reducing parasitic sensitivity.

[0023] Furthermore, for example, the photoelectric conversion element according to the fifth aspect of this disclosure is the photoelectric conversion element according to the fourth aspect, wherein the signal charge is a hole, and the electron affinity of the intermediate layer is smaller than the electron affinity of the photoelectric conversion layer.

[0024] This can further reduce parasitic sensitivity.

[0025] Furthermore, for example, a photoelectric conversion element according to a sixth aspect of this disclosure is a photoelectric conversion element according to a fourth or fifth aspect, wherein the intermediate layer includes a semiconductor material having the intermediate level due to association or impurities.

[0026] This facilitates the injection of charge from the first electrode to the photoelectric conversion layer via the intermediate layer.

[0027] Furthermore, for example, the photoelectric conversion element according to the seventh aspect of this disclosure is the photoelectric conversion element according to the sixth aspect, and the semiconductor material is an organic semiconductor material.

[0028] This facilitates the formation of intermediate layers containing intermediate energy levels.

[0029] Furthermore, for example, the photoelectric conversion element according to the eighth aspect of this disclosure is a photoelectric conversion element according to any one of the first to seventh aspects, wherein the first electrode is an ITO (Indium Tin Oxide) film formed in a film formation atmosphere in which the oxygen concentration in the film formation gas is 0.23% or less.

[0030] This allows for increased charge injection from the first electrode to the photoelectric conversion layer when a first voltage is applied between the first and second electrodes, thereby increasing the cancellation of signal charges in the photoelectric conversion layer and reducing parasitic sensitivity.

[0031] Furthermore, for example, a photoelectric conversion element according to the ninth aspect of this disclosure is a photoelectric conversion element according to any one of the first to eighth aspects, wherein the photoelectric conversion layer includes an organic semiconductor material.

[0032] This allows for the formation of a photoelectric conversion layer by coating or co-deposition, thus facilitating the formation of the photoelectric conversion layer.

[0033] Furthermore, for example, the photoelectric conversion element according to the tenth aspect of this disclosure is a photoelectric conversion element according to any one of the first to ninth aspects, wherein the charge blocking layer is an electron blocking layer, and the signal charge is a hole.

[0034] As a result, the presence of an electron blocking layer prevents electrons injected from the first electrode into the photoelectric conversion layer from being blocked, thereby suppressing dark current. Furthermore, the probability of the injected electrons canceling out the signal charge (hole) increases, reducing parasitic sensitivity.

[0035] Furthermore, for example, the photoelectric conversion element according to the 11th aspect of this disclosure is the photoelectric conversion element according to the 10th aspect, wherein the electron affinity of the electron blocking layer is smaller than the electron affinity of the photoelectric conversion layer, and the ionization potential of the electron blocking layer is larger than the ionization potential of the photoelectric conversion layer.

[0036] This increases the charge transfer barrier created by the electron blocking layer, further reducing parasitic sensitivity.

[0037] Furthermore, an imaging device according to a twelfth aspect of the present disclosure comprises a photoelectric conversion element according to any one of the first to eleventh aspects, and a charge detection circuit that detects the signal charge during the period in which the first voltage is applied between the first electrode and the second electrode.

[0038] This makes it possible to realize an imaging device that can reduce parasitic sensitivity during the period in which signal charge is detected.

[0039] Furthermore, for example, the imaging device according to the 13th aspect of this disclosure is the imaging device according to the 12th aspect, wherein the parasitic sensitivity of the imaging device is less than -100 dB.

[0040] This makes it possible to reduce noise in the imaging device.

[0041] The embodiments will be described below with reference to the drawings.

[0042] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. Furthermore, components in the following embodiments that are not described in an independent claim are described as optional components. In addition, the figures are not necessarily strictly illustrative. In each figure, substantially identical components are denoted by the same reference numerals, and redundant explanations may be omitted or simplified.

[0043] Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, for example, the scale may not necessarily match in each figure. Also, in each figure, substantially identical components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0044] Furthermore, in this specification, terms indicating relationships between elements such as verticals, terms indicating the shape of elements such as rectangles, and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent.

[0045] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather to terms defined by the relative positional relationship based on the stacking order in a stacked configuration. Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other.

[0046] Furthermore, in this specification, electromagnetic waves in general, including visible light, infrared rays, and ultraviolet rays, will be referred to as "light" for convenience.

[0047] (Embodiment) The following describes this embodiment.

[0048] [Photoelectric conversion element] First, the photoelectric conversion element according to this embodiment will be described. The photoelectric conversion element according to this embodiment is a charge readout type photoelectric conversion element. The photoelectric conversion element according to this embodiment can be used, for example, in an imaging device, a light sensor, or a photodetector. Figure 1 shows the photoelectric conversion element according to this embodiment. This is a schematic cross-sectional view showing the configuration of the photoelectric conversion element 10.

[0049] As shown in Figure 1, the photoelectric conversion element 10 is supported on a support substrate 1 and comprises a pair of electrodes, an upper electrode 6 and a lower electrode 2, a photoelectric conversion layer 4 located between the upper electrode 6 and the lower electrode 2, an intermediate layer 5 located between the upper electrode 6 and the photoelectric conversion layer 4, and an electron blocking layer 3 located between the lower electrode 2 and the photoelectric conversion layer 4. In this embodiment, the upper electrode 6 is an example of a first electrode, the lower electrode 2 is an example of a second electrode, and the electron blocking layer 3 is an example of a charge blocking layer.

[0050] The following describes each component of the photoelectric conversion element 10 according to this embodiment.

[0051] The support substrate 1 can be any substrate commonly used to support photoelectric conversion elements, such as a glass substrate, quartz substrate, semiconductor substrate, or plastic substrate.

[0052] The lower electrode 2 and the upper electrode 6 are membrane-like electrodes positioned opposite each other.

[0053] The lower electrode 2 collects the signal charge generated in the photoelectric conversion layer 4. The lower electrode 2 is formed from a metal, metal nitride, metal oxide, or conductive polysilicon. Examples of metals include aluminum, copper, titanium, and tungsten. An example of a method for imparting conductivity to polysilicon is doping it with impurities.

[0054] The upper electrode 6 is positioned opposite the lower electrode 2, with the photoelectric conversion layer 4 in between. The upper electrode 6 is a transparent electrode formed from, for example, a transparent conductive material. As the material for the upper electrode 6, for example, transparent conductive oxide (TCO) ITO(Indium Tin Oxide), IZO(Indium Tin Oxide), ITO(Indium Tin Oxide), IZO(Indium Tin Oxide) Examples include zinc oxide, azo (aluminum-doped zinc oxide), fto (florine-doped tin oxide), snO2, and tiO2. The upper electrode 6 may be fabricated using TCO and metallic materials such as aluminum (Al) and gold (Au), either individually or in combination, depending on the desired transmittance.

[0055] Furthermore, the materials for the lower electrode 2 and the upper electrode 6 are not limited to the conductive materials described above, and other materials may be used. For example, the lower electrode 2 may be a transparent electrode.

[0056] Various methods can be used to fabricate the lower electrode 2 and the upper electrode 6, depending on the materials used. For example, when using an ITO film for the lower electrode 2 and / or the upper electrode 6, chemical reaction methods such as electron beam method, sputtering method, resistance heating deposition method, sol-gel method, or coating of indium tin oxide dispersion may be used. In this case, after forming the ITO film, the lower electrode 2 and the upper electrode 6 may be subjected to further treatments such as UV-ozone treatment or plasma treatment.

[0057] The photoelectric conversion layer 4 includes a donor semiconductor material and an acceptor semiconductor material. The photoelectric conversion layer 4 is fabricated, for example, using an organic semiconductor material. The photoelectric conversion layer 4 can be fabricated using wet methods such as spin coating, or dry methods such as vacuum deposition. Vacuum deposition is a method in which the layer material is vaporized by heating under vacuum and deposited on the substrate. Furthermore, the electron blocking layer 3 and the intermediate layer 5, which will be described in detail later, can also be fabricated using the same method as the photoelectric conversion layer 4.

[0058] The thickness of the photoelectric conversion layer 4 is, for example, 50 nm or more. Furthermore, from the viewpoint of improving the photoelectric conversion characteristics, the thickness of the photoelectric conversion layer 4 may be 200 nm or more, and 400 nm or more. It may be present. Furthermore, the thickness of the photoelectric conversion layer 4 may be 1000 nm or less, from the viewpoint of suppressing a decrease in the photoelectric conversion efficiency of the photoelectric conversion element 10.

[0059] Furthermore, the photoelectric conversion layer 4 is a mixed film of a bulk heterostructure containing, for example, a donor semiconductor material such as a donor organic semiconductor material and an acceptor semiconductor material such as an acceptor organic semiconductor material. Alternatively, the photoelectric conversion layer 4 may have a laminated structure in which a layer composed of a donor semiconductor material and a layer composed of an acceptor semiconductor material are stacked. In addition, the photoelectric conversion layer 4 does not necessarily have a structure in which multiple layers are clearly stacked, but may, for example, be a layer having a region in which the content ratio of the donor semiconductor material is greater than the content ratio of the acceptor semiconductor material and a region in which the content ratio of the acceptor semiconductor material is greater than the content ratio of the donor semiconductor material.

[0060] The photoelectric conversion layer 4 is easily formed as a thin film by including a donor organic semiconductor material and an acceptor organic semiconductor material. Specific examples of the donor organic semiconductor material and the acceptor organic semiconductor material are given below.

[0061] Examples of donor organic semiconductor materials include triarylamine compounds, benzidine compounds, pyrazoline compounds, styrylamine compounds, hydrazone compounds, triphenylmethane compounds, carbazole compounds, polysilane compounds, thiophene compounds, phthalocyanine compounds, naphthalocyanine compounds, subphthalocyanine compounds, cyanine compounds, merocyanine compounds, oxonol compounds, polyamine compounds, indole compounds, pyrrole compounds, pyrazole compounds, polyarylene compounds, condensed aromatic carbocyclic compounds (e.g., naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, and fluorantene derivatives, etc.) and metal complexes having nitrogen-containing heterocyclic compounds as ligands.

[0062] Examples of acceptable organic semiconductor materials include fullerenes (e.g., C60 fullerene and C70 fullerene), and fullerene derivatives (e.g., PCBM (phenyl C 61 Methyl butyrate) and ICBA (Indene C60 Bis-adducts, etc.), condensed aromatic carbocyclic compounds (e.g., naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, and fluorantene derivatives, etc.), 5 to 7-membered heterocyclic compounds containing nitrogen, oxygen, and sulfur atoms (e.g., pyridine, pyrazine, pyrimidine, pyridazine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, cinnoline, isoquinoline, pteridine, acridine, phenazine, phenanthroline, tetrazole, pyrazole, imidazole) Examples include metal complexes having ligands such as thiazole, oxazole, indazole, benzimidazole, benzodriaazole, benzoxazole, benzothiazole, carbazole, purine, triazolopyridazine, triazolopyrimidine, tetrazaidene, oxadiazole, imidazopyridine, pyrrolidine, pyrrolopyridine, thiadiazolopyridine, dibenzazepine and tripenzuazepine, etc., polyarylene compounds, fluorene compounds, cyclopentadiene compounds, silyl compounds and nitrogen-containing heterocyclic compounds.

[0063] The donor organic semiconductor material and acceptor organic semiconductor material are not limited to the examples above. Any organic compound that can be formed as a photoelectric conversion layer by either a dry or wet method may be used as the donor organic semiconductor material and acceptor organic semiconductor material constituting the photoelectric conversion layer 4, including low-molecular-weight organic compounds and high-molecular-weight organic compounds.

[0064] Furthermore, the photoelectric conversion layer 4 may also contain semiconductor materials other than those mentioned above as donor semiconductor materials and acceptor semiconductor materials. Examples of semiconductor materials for the photoelectric conversion layer 4 include silicon semiconductors, compound semiconductors, quantum dots, perovskite materials, and carbon nanotubes. It may also contain, or a mixture of any two or more of these.

[0065] As described above, the photoelectric conversion element 10 according to this embodiment includes an electron blocking layer 3 provided between the lower electrode 2 and the photoelectric conversion layer 4, and an intermediate layer 5 provided between the upper electrode 6 and the photoelectric conversion layer 4. The electron blocking layer 3 is in contact with, for example, the lower electrode 2 and the photoelectric conversion layer 4. The intermediate layer 5 is in contact with, for example, the upper electrode 6 and the photoelectric conversion layer 4.

[0066] By providing the electron blocking layer 3, charge injection from the lower electrode 2 can be suppressed, thereby reducing unwanted signals that negatively affect the signal-to-noise ratio.

[0067] The thickness of the electron blocking layer 3 is, for example, 5 nm or more. This makes it easier to ensure the function of the electron blocking layer 3. To further improve the function of the electron blocking layer 3, it may be 50 nm or more, or even 400 nm or more. Furthermore, from the viewpoint of suppressing a decrease in the photoelectric conversion efficiency of the photoelectric conversion element 10, the thickness of the electron blocking layer 3 may be 800 nm or less.

[0068] The thickness of the intermediate layer 5 is, for example, 3 nm to 120 nm. This makes it easier to ensure the functionality of the intermediate layer 5. Furthermore, from the viewpoint of suppressing a decrease in the photoelectric conversion efficiency of the photoelectric conversion element 10, the thickness of the intermediate layer 5 may be 5 nm to 15 nm.

[0069] The materials used for the electron blocking layer 3 and the intermediate layer 5 are semiconductor materials having energy bands described later. The electron blocking layer 3 and the intermediate layer 5 are formed, for example, from organic semiconductor materials. The materials forming the electron blocking layer 3 and the intermediate layer 5 are not limited to organic semiconductor materials, but may also be oxide semiconductors or nitride semiconductors, or composite materials thereof.

[0070] Furthermore, the intermediate layer 5 may also contain the semiconductor material included in the photoelectric conversion layer 4. This improves the adhesion of the interface between the photoelectric conversion layer 4 and the intermediate layer 5 when they are in contact, as shown in the diagram.

[0071] Here, the functions of the electron blocking layer 3, the photoelectric conversion layer 4, and the intermediate layer 5 will be explained using energy band diagrams. Figure 2 is an exemplary energy band diagram of the photoelectric conversion element 10 shown in Figure 1. In Figure 2, the energy bands of each layer are shown as rectangles.

[0072] The photoelectric conversion layer 4 generates electron-hole pairs inside when irradiated with light. In the photoelectric conversion element 10, the holes in these pairs are collected by the lower electrode 2 and used as signal charges to be read out. In other words, the photoelectric conversion layer 4 converts light into signal charges.

[0073] The generated electron-hole pairs are separated into electrons and holes by the electric field applied to the photoelectric conversion layer 4. The electrons and holes move towards the lower electrode 2 side or the upper electrode 6 side, respectively, according to the electric field. Here, of the electron-hole pairs generated by absorbing light, the semiconductor material that donates electrons to the other material is the donor semiconductor material, and the semiconductor material that accepts electrons is the acceptor semiconductor material. When the photoelectric conversion layer 4 is irradiated with light, for example, the donor semiconductor material generates electron-hole pairs and donates electrons to the acceptor semiconductor material.

[0074] Figure 2 shows examples of energy bands when organic semiconductor materials are used as donor and acceptor semiconductor materials. When two different types of organic semiconductor materials are used, which one becomes the donor semiconductor material and which becomes the acceptor semiconductor material? Generally, the energy bands are determined by the relative positions of the HOMO (Highest-Occupied-Molecular-Orbital) energy levels and LUMO (Lowest-Unoccupied-Molecular-Orbital) energy levels of each of the two types of organic semiconductor materials at the contact interface. In Figure 2, the upper end of the rectangle showing the energy bands represents the LUMO energy level, and the lower end represents the HOMO energy level. The energy difference between the vacuum level and the LUMO energy level is called the electron affinity. The energy difference between the vacuum level and the HOMO energy level is called the ionization potential. In Figure 2, the lower the position, the larger the electron affinity and ionization potential. This is also true for the energy band diagrams that will be explained later.

[0075] As shown in Figure 2, of the two types of organic semiconductor materials contained in the photoelectric conversion layer 4, the one with a shallower LUMO energy level, i.e., lower electron affinity, is the donor semiconductor material, donor organic semiconductor material 4A. The other two types of organic semiconductor materials contained in the photoelectric conversion layer 4, the one with a deeper LUMO energy level, i.e., higher electron affinity, is the acceptor semiconductor material, acceptor organic semiconductor material 4B. Note that in Figure 2, the energy bands of donor organic semiconductor material 4A and acceptor organic semiconductor material 4B are slightly offset horizontally; this is for readability and does not represent the distribution of donor organic semiconductor material 4A and acceptor organic semiconductor material 4B within the photoelectric conversion layer 4. Also, the energy band of donor organic semiconductor material 4A is shown as a dashed rectangle; this is also for readability and is not intended to distinguish it from a solid rectangle. These same principles apply to the energy band diagrams described later.

[0076] Furthermore, when simply referring to the ionization potential of the photoelectric conversion layer 4, it refers to the ionization potential of the donor semiconductor material, such as the donor organic semiconductor material 4A, contained in the photoelectric conversion layer 4. Also, when simply referring to the electron affinity of the photoelectric conversion layer 4, it refers to the electron affinity of the acceptor semiconductor material, such as the acceptor organic semiconductor material 4B, contained in the photoelectric conversion layer 4.

[0077] The electron blocking layer 3 is provided to reduce dark current caused by the injection of electrons, which have a charge opposite in polarity to the signal charge, from the lower electrode 2, thereby suppressing the injection of electrons from the lower electrode 2 into the photoelectric conversion layer 4. This reduces unwanted signals that adversely affect the signal-to-noise ratio. As shown in Figure 2, in order to suppress the injection of electrons from the lower electrode 2 into the photoelectric conversion layer 4, the electron affinity of the material of the electron blocking layer 3 is smaller than the work function of the lower electrode 2. Also, as shown in Figure 2, the ionization potential of the electron blocking layer 3 may be greater than the ionization potential of the donor organic semiconductor material 4A of the photoelectric conversion layer 4. Furthermore, the electron affinity of the electron blocking layer 3 is smaller than, for example, the electron affinity of the acceptor organic semiconductor material 4B of the photoelectric conversion layer 4.

[0078] The electron affinity of the intermediate layer 5 is smaller than, for example, the electron affinity of the acceptor organic semiconductor material 4B of the photoelectric conversion layer 4. This allows electrons generated in the photoelectric conversion layer 4 to remain within the photoelectric conversion layer 4, further reducing parasitic sensitivity. Furthermore, the ionization potential of the intermediate layer 5 may be greater than, for example, the ionization potential of the donor organic semiconductor material 4A of the photoelectric conversion layer 4. This further reduces the dark current.

[0079] Furthermore, the intermediate layer 5 has intermediate energy levels in addition to the HOMO and LUMO energy levels. The presence of intermediate energy levels in the intermediate layer 5 promotes charge injection from the upper electrode 6 when the first voltage, described later, is applied between the lower electrode 2 and the upper electrode 6.

[0080] Intermediate layer 5 includes, for example, a semiconductor material having intermediate levels due to association or impurities. In other words, the intermediate levels in intermediate layer 5 are, for example, due to the association of the semiconductor material contained in intermediate layer 5. The intermediate energy level is a level created by aggregation, or a level created by the presence of impurities in the semiconductor material contained in the intermediate layer 5. This makes it easier for charge to be injected from the upper electrode 6 through the intermediate energy level into the photoelectric conversion layer 4 when the first voltage described later is applied between the lower electrode 2 and the upper electrode 6. For example, when two molecules of a compound constituting an organic semiconductor material associate, the HOMO energy levels and LUMO energy levels of each molecule interact with each other. For example, if the LUMO energy levels interact, an intermediate energy level with higher energy than the LUMO energy level is created, making it easier for electrons to be injected from the upper electrode 6 through the intermediate energy level into the photoelectric conversion layer 4. Also, if the HOMO energy levels interact with each other, an intermediate energy level with lower energy than the HOMO energy level is created, making it easier for holes to be injected from the upper electrode 6 through the intermediate energy level into the photoelectric conversion layer 4.

[0081] Semiconductor materials with intermediate levels due to association include materials with large π-conjugated systems, such as phthalocyanine compounds and naphthalocyanine compounds. Furthermore, when using phthalocyanine compounds and naphthalocyanine compounds, compounds that do not contain a central metal or ligands coordinating to the central metal are used. This facilitates interaction and association between π-conjugated systems, making it easier for intermediate levels to form. Additionally, for semiconductor materials with intermediate levels due to impurities, materials doped with impurities such as metal oxides are used.

[0082] As shown in Figure 2, the lower electrode 2 is electrically connected to a charge storage node 34, which will be described later, for example, when the photoelectric conversion element 10 is used in an imaging device. The charge storage node 34 is generated in the photoelectric conversion layer 4 and stores holes collected by the lower electrode 2 as signal charges. In this embodiment, an example where the signal charge is a hole will be described.

[0083] Furthermore, the photoelectric conversion element 10 may use electrons as the signal charge. In this case, electrons generated in the photoelectric conversion layer 4 are collected by the lower electrode 2 and stored as signal charge in the charge storage node 34. Also, when electrons are used as the signal charge, the photoelectric conversion element 10 is equipped with a hole blocking layer as a charge blocking layer instead of the electron blocking layer 3. The hole blocking layer is provided to reduce dark current caused by the injection of holes from the lower electrode 2 and to suppress the injection of holes from the lower electrode 2 into the photoelectric conversion layer 4. In order to suppress the injection of holes from the lower electrode 2 into the photoelectric conversion layer 4, the ionization potential of the material of the hole blocking layer is greater than the work function of the lower electrode 2. Also, the electron affinity of the hole blocking layer may be smaller than the electron affinity of the acceptor organic semiconductor material 4B of the photoelectric conversion layer 4. Also, the ionization potential of the hole blocking layer is greater than, for example, the ionization potential of the donor organic semiconductor material 4A of the photoelectric conversion layer 4.

[0084] [Another example of a photoelectric conversion element] In the above-described photoelectric conversion element 10, the injection of charge from the upper electrode 6 is facilitated by the inclusion of the intermediate layer 5, but the injection of charge from the upper electrode 6 may be facilitated by means other than the inclusion of the intermediate layer 5. Figure 3 is a schematic cross-sectional view showing the configuration of another photoelectric conversion element 11 according to this embodiment. Figure 4 is an exemplary energy band diagram of the photoelectric conversion element 11 shown in Figure 3. The photoelectric conversion element 11 differs from the photoelectric conversion element 10 in that it does not have an intermediate layer 5 and has an upper electrode 7 instead of an upper electrode 6. In the following description of the photoelectric conversion element 11, the differences from the photoelectric conversion element 10 will be the main focus, and the explanation of the common points will be omitted or simplified.

[0085] The upper electrode 7 has a work function smaller than that of the upper electrode 6. Furthermore, the carrier density of the upper electrode 7 is greater than that of the upper electrode 6. The upper electrode 7 is, for example, an ITO film formed in a deposition atmosphere where the oxygen concentration in the deposition gas is 0.23% or less.

[0086] For example, when forming an ITO film by sputtering, the target composition ratio is, for example, InO:SnO = 90:10, but it may also be InO:SnO = 95:5, or any other target composition ratio may be used. Furthermore, the ITO film is formed in a chamber with a deposition atmosphere in which a deposition gas adjusted to a predetermined oxygen concentration is introduced. In adjusting the deposition atmosphere for the ITO film, a deposition gas consisting only of argon or a deposition gas mixed with argon and oxygen with an adjusted oxygen concentration may be introduced into the chamber, or argon and oxygen as needed may be introduced into the chamber separately. The pressure inside the chamber is, for example, 0.3 Pa, but other values ​​may also be used.

[0087] ITO films, widely used as transparent conductive films, are known to exhibit significant variations in optical and electrical properties depending on their composition and film quality. Patent document 3 discloses that in an amorphous oxide composed of a quaternary compound of indium, gallium and / or aluminum, zinc, and oxygen, the work function can be controlled by the oxygen concentration in the deposition gas. Furthermore, non-patent document 1 shows that localized oxygen vacancies in ITO form donor levels, and carrier electrons emitted from these donor levels contribute to conductivity.

[0088] Furthermore, as shown in Patent Document 4, in the formation of an ITO film, reducing the oxygen concentration in the deposition gas can increase the carrier density and decrease the work function. In addition, reducing the oxygen concentration in the deposition gas can also reduce the sheet resistance of the ITO film. Specifically, an ITO film constituting the upper electrode 7 is formed using a deposition gas with an oxygen concentration of 0.23% or less. As a result, the carrier density of the upper electrode 7 increases and the work function of the upper electrode 7 decreases, so that when the first voltage described later is applied between the lower electrode 2 and the upper electrode 7, charge injection from the upper electrode 7 to the photoelectric conversion layer 4 can be promoted. Note that in this specification, an oxygen concentration of 0.23% or less in the deposition gas is used to mean that 0% (where the deposition gas contains no oxygen) is also included in this oxygen concentration range.

[0089] The sheet resistance of the upper electrode 7 is, for example, 60Ω / □ (Ω per square) or less.

[0090] The photoelectric conversion element 11 may further include the above-mentioned intermediate layer 5 between the photoelectric conversion layer 4 and the upper electrode 7.

[0091] [Driving the photoelectric conversion element] Next, the driving method for the photoelectric conversion elements 10 and 11 according to this embodiment will be described.

[0092] Figure 5A is an exemplary energy band diagram of the photoelectric conversion element 10 when a reverse bias voltage is applied between the lower electrode 2 and the upper electrode 6. Figure 5B is an exemplary energy band diagram of the photoelectric conversion element 10 when a forward bias voltage is applied between the lower electrode 2 and the upper electrode 6. Figure 6A is an exemplary energy band diagram of the photoelectric conversion element 11 when a reverse bias voltage is applied between the lower electrode 2 and the upper electrode 7. Figure 6B is an exemplary energy band diagram of the photoelectric conversion element 11 when a forward bias voltage is applied between the lower electrode 2 and the upper electrode 7. In this specification, a reverse bias voltage is defined as a voltage that creates an electric field between the upper electrode 6 or 7 and the lower electrode 2 such that a signal charge moves to the lower electrode 2. Also, a forward bias voltage is defined as a voltage that creates an electric field between the upper electrode 6 or 7 and the lower electrode 2 such that a signal charge moves to the upper electrode 6 or 7. Specifically, when the signal charge is a hole, the voltage applied between the upper electrode 6 or 7 and the lower electrode 2 such that the potential of the upper electrode 6 or 7 becomes higher than the potential of the lower electrode 2 is the reverse bias voltage, and the upper electrode The voltage applied between the upper electrode 6 or 7 and the lower electrode 2 such that the potential of electrode 6 or 7 is lower than the potential of the lower electrode 2 is defined as the forward bias voltage, and the following explanation will proceed accordingly.

[0093] The photoelectric conversion elements 10 and 11 are driven by switching between, for example, a photoelectric conversion mode and a signal readout mode. In the photoelectric conversion mode, for example, a second voltage, which is a reverse bias voltage as shown in Figures 5A and 6A, is applied between the upper electrode 6 or 7 and the lower electrode 2. The second voltage is, for example, between 1V and 10V with respect to the lower electrode 2. In the signal readout mode, for example, a first voltage, which is a forward bias voltage as shown in Figures 5B and 6B, is applied between the upper electrode 7 and the lower electrode 2. The first voltage is, for example, between -3V and 0V with respect to the lower electrode 2.

[0094] For example, in the photoelectric conversion mode, when light is incident on the photoelectric conversion layer 4 with a second voltage applied between the upper electrode 6 or 7 and the lower electrode 2, as shown in Figures 5A and 6A, electron-hole pairs are generated in the photoelectric conversion layer 4. Subsequently, of the generated electron-hole pairs, the holes, which are signal charges, move to the lower electrode 2, and the electrons, which are charges of the opposite polarity to the signal charges, move to the upper electrode 6 or 7. The holes that have moved to the lower electrode 2 are accumulated in the charge storage node 34, for example, when the photoelectric conversion elements 10 and 11 are used in an imaging device. Therefore, the second voltage is a voltage that causes sensitivity in the photoelectric conversion elements 10 and 11.

[0095] Subsequently, in signal readout mode, with a first voltage applied between the upper electrode 6 or 7 and the lower electrode 2 as shown in Figures 5B and 6B, a signal based on holes accumulated in the charge storage node 34 is read out via the lower electrode 2. Furthermore, the absolute value of the first voltage is smaller than the absolute value of the second voltage, and is a voltage that does not cause sensitivity in the photoelectric conversion elements 10 and 11. Therefore, in signal readout mode, the amount of signal charge accumulated in the charge storage node 34 does not change easily. Note that not causing sensitivity in the photoelectric conversion elements 10 and 11 means that the photoelectric conversion elements 10 and 11 do not experience substantial sensitivity; for example, the sensitivity of the photoelectric conversion elements 10 and 11 in signal readout mode is 5% or less of the sensitivity of the photoelectric conversion elements 10 and 11 in photoelectric conversion mode. The sensitivity of the photoelectric conversion elements 10 and 11 in signal readout mode may also be 1% or less of the sensitivity of the photoelectric conversion elements 10 and 11 in photoelectric conversion mode.

[0096] In the photoelectric conversion elements 10 and 11 according to this embodiment, electrons are easily injected from the upper electrode 6 or 7 into the photoelectric conversion layer 4. For example, in the photoelectric conversion element 10, as shown in Figure 5B, the provision of an intermediate layer 5 facilitates the injection of electrons from the upper electrode 6 into the photoelectric conversion layer 4 due to the intermediate energy levels of the intermediate layer 5. Also, in the photoelectric conversion element 11, as shown in Figure 6B, the provision of an upper electrode 7 with a small work function and high carrier density facilitates the injection of electrons from the upper electrode 7 into the photoelectric conversion layer 4. As a result, the photoelectric conversion elements 10 and 11 can reduce parasitic sensitivity.

[0097] Here, the ability to suppress parasitic sensitivity by injecting charge from the upper electrode 6 or 7 into the photoelectric conversion layer 4 will be explained in conjunction with the capacitance characteristics of the photoelectric conversion elements 10 and 11. The photoelectric conversion elements 10 and 11 have capacitance characteristics that result from the ease with which charge injection occurs into the photoelectric conversion layer 4 when a forward bias voltage is applied. As an example of the capacitance characteristics of the photoelectric conversion elements 10 and 11, the change in capacitance of the photoelectric conversion elements 10 and 11 due to the voltage applied between the upper electrode 6 or 7 and the lower electrode 2 will be explained using Figure 7. Figure 7 is a diagram showing an example of a schematic capacitance-voltage characteristic (CV characteristic) of the photoelectric conversion elements 10 and 11. In Figure 7, the vertical axis represents the capacitance output between the upper electrode 6 or 7 and the lower electrode 2, and the horizontal axis represents the voltage applied between the upper electrode 6 or 7 and the lower electrode 2. Also, on the horizontal axis of Figure 7, a positive voltage is the reverse bias voltage, and a negative voltage is the forward bias voltage. This is the voltage. In other words, in Figure 7, the voltage at which the signal charge moves to the lower electrode 2 is defined as a "positive" value, and the CV characteristics are shown. Also in Figure 7, the CV characteristics of the photoelectric conversion elements 10 and 11 according to this embodiment are shown by solid lines, and the CV characteristics of the photoelectric conversion element according to the comparative example are shown by dashed lines.

[0098] As shown in Figure 7, in photoelectric conversion elements 10 and 11, the capacitance between the upper electrode 6 or 7 and the lower electrode 2 is significantly larger when a forward bias voltage is applied between the upper electrode 6 or 7 and the lower electrode 2 compared to when a reverse bias voltage is applied between the upper electrode 6 or 7 and the lower electrode 2. This is because when a forward bias voltage is applied between the upper electrode 6 or 7 and the lower electrode 2, electrons are injected from the upper electrode 6 or 7 into the photoelectric conversion layer 4.

[0099] When a reverse bias voltage is applied between the upper electrode 6 or 7 and the lower electrode 2, the electron blocking layer 3 prevents electron injection from the lower electrode 2, resulting in a capacitance proportional to the distance between the upper electrode 6 or 7 and the lower electrode 2. On the other hand, as shown in Figures 5B and 6B, when a forward bias voltage is applied between the upper electrode 6 or 7 and the lower electrode 2, the electron blocking layer 3 blocks electron movement, allowing electrons to be injected near the interface between the electron blocking layer 3 and the photoelectric conversion layer 4. Therefore, when a forward bias voltage is applied, the capacitance between the upper electrode 6 or 7 and the lower electrode 2 is proportional to the distance between the lower electrode 2 and the location where the electrons are injected, and is greater than when a reverse bias voltage is applied. Consequently, the increased capacitance between the upper electrode 6 or 7 and the lower electrode 2 due to the application of a forward bias voltage depends, for example, on the dielectric constant and thickness of the electron blocking layer 3.

[0100] In this way, when a forward bias voltage is applied, electrons are injected into the photoelectric conversion layer 4, and the capacitance between the upper electrode 6 or 7 and the lower electrode 2 becomes large. As a result, the injected electrons couple with holes present in the photoelectric conversion layer 4, reducing the parasitic sensitivity in the photoelectric conversion elements 10 and 11.

[0101] Specifically, when light is incident on the photoelectric conversion layer 4 during the signal readout mode, holes generated in the photoelectric conversion layer 4, and holes that remain on the lower electrode 2 without being collected during the photoelectric conversion mode, move to the lower electrode 2 during the signal readout mode. This manifests as parasitic sensitivity, an unintended sensitivity, and causes noise. Therefore, it is desirable that there are many electrons in the photoelectric conversion layer 4 during the signal readout mode to recombine with these holes. In photoelectric conversion elements 10 and 11, when electrons and holes present in the photoelectric conversion layer 4 recombine during the signal readout mode, the electrons injected from the upper electrode 6 adequately promote the recombination of holes present in the photoelectric conversion layer 4. As a result, the movement of holes present in the photoelectric conversion layer 4 to the lower electrode 2 can be suppressed during the signal readout mode. Consequently, parasitic sensitivity can be reduced.

[0102] On the other hand, in the case of a photoelectric conversion element in the comparative example, where there is almost no increase in capacitance even when a forward bias voltage is applied, it means that electrons are not easily injected into the photoelectric conversion layer 4, and therefore parasitic sensitivity cannot be reduced.

[0103] Furthermore, by including an electron blocking layer 3 in the photoelectric conversion elements 10 and 11, electrons injected from the upper electrode 6 or 7 are blocked by the electron blocking layer 3, thereby suppressing dark current. At the same time, the probability of the injected electrons canceling out holes present in the photoelectric conversion layer 4 is increased, reducing parasitic sensitivity.

[0104] In photoelectric conversion elements 10 and 11, when a first voltage is applied between the upper electrode 6 or 7 and the lower electrode 2, the capacitance between the upper electrode 6 or 7 and the lower electrode 2 (hereinafter referred to as electrostatic) Capacitance C1 (also referred to as capacitance C1) is 1.5 times or more the capacitance between the upper electrode 6 or 7 and the lower electrode 2 (hereinafter also referred to as capacitance C2) when a second voltage is applied between the upper electrode 6 or 7 and the lower electrode 2. Capacitance C1 may be 3 times or more the capacitance C2. The first voltage is, for example, the forward bias voltage applied between the upper electrode 6 or 7 and the lower electrode 2 in the signal readout mode as described above. The second voltage is, for example, the reverse bias voltage applied between the upper electrode 6 or 7 and the lower electrode 2 in the photoelectric conversion mode as described above. Furthermore, the upper limit of the ratio of capacitance C1 to capacitance C2 depends on the dielectric constant and thickness of the electron blocking layer 3, but for example, from the viewpoint of ensuring the function of the electron blocking layer 3, capacitance C1 is 20 times or less the capacitance C2.

[0105] Capacitances C1 and C2 are the average values ​​of capacitance at each frequency, which are obtained by measuring the impedance at AC frequencies from 10 Hz to 10 kHz using an impedance measuring instrument such as an LCR meter connected to the lower electrode 2 and the upper electrode 6 or 7, when the photoelectric conversion elements 10 and 11 are not irradiated with light.

[0106] The first voltage does not have to be a forward bias voltage; for example, it may be 0V, or a reverse bias voltage of about 1V or less. Depending on the configuration of the intermediate layer 5 or the upper electrode 7, electron injection into the photoelectric conversion layer 4 may occur even if the first voltage is 0V or higher, so the capacitance of the photoelectric conversion elements 10 and 11 may increase. Also, even when electrons are used as the signal charge, if the configuration promotes hole injection when the first voltage is applied between the upper electrode 6 or 7 and the lower electrode 2, the above relationship between capacitance C1 and capacitance C2 will occur. In this way, by configuring the photoelectric conversion elements 10 and 11 so that when the first voltage is applied between the upper electrode 6 or 7 and the lower electrode 2, the injection of charges with the opposite polarity to the signal charge into the photoelectric conversion layer 4 is easily achieved, the capacitance C1 becomes 1.5 times or more than the capacitance C2, and parasitic sensitivity can be reduced.

[0107] As described above, the photoelectric conversion elements 10 and 11 according to this embodiment, by using the aforementioned intermediate layer 5 or upper electrode 7, increase the capacitance between the upper electrode 6 or 7 and the lower electrode 2 in the signal readout mode, that is, make it possible to create a state in which electrons are more likely to be abundant in the photoelectric conversion layer 4. As a result, it is possible to effectively reduce parasitic sensitivity by promoting the recombination of electrons and holes in the photoelectric conversion layer 4.

[0108] [Imaging device] Next, an imaging device equipped with a photoelectric conversion element according to this embodiment will be described with reference to Figures 8 and 9. Figure 8 is a diagram showing an example of the circuit configuration of an imaging device 100 that implements a photoelectric conversion unit 10A using the photoelectric conversion element 10 shown in Figure 1. Figure 9 is a schematic cross-sectional view showing an example of the device structure of a pixel 24 in the imaging device 100 according to this embodiment.

[0109] As shown in Figures 8 and 9, the imaging device 100 according to this embodiment comprises a semiconductor substrate 40, a charge detection circuit 35 provided on the semiconductor substrate 40, a photoelectric conversion unit 10A provided on the semiconductor substrate 40, and a plurality of pixels 24, each including a charge storage node 34 electrically connected to the charge detection circuit 35 and the photoelectric conversion unit 10A. The photoelectric conversion unit 10A of the plurality of pixels 24 is composed of the photoelectric conversion element 10 described above. In other words, each of the plurality of pixels 24 includes an upper electrode 6, a lower electrode 2, a photoelectric conversion layer 4, an intermediate layer 5, an electron blocking layer 3, a charge storage node 34, and a charge detection circuit 35. In this embodiment, the charge storage node 34 is an example of a charge storage region. The photoelectric conversion unit 10A may be composed of a photoelectric conversion element 11.

[0110] In the photoelectric conversion unit 10A, the upper electrode 6, intermediate layer 5, photoelectric conversion layer 4, electron blocking layer 3, and lower electrode 2 are arranged in that order from the light incident side to the imaging device 100. In this embodiment, light transmitted through the upper electrode 6 and the intermediate layer 5 is incident on the photoelectric conversion layer 4. Also, in this embodiment, the side on which light is incident on the imaging device 100 is opposite to the semiconductor substrate 40 side of the photoelectric conversion unit 10A.

[0111] The charge storage node 34 stores the signal charge generated by the photoelectric conversion unit 10A, and the charge detection circuit 35 detects the signal charge stored in the charge storage node 34. The charge detection circuit 35 provided on the semiconductor substrate 40 may be provided on the semiconductor substrate 40 or directly provided in the semiconductor substrate 40.

[0112] As shown in Figure 8, the imaging device 100 comprises a plurality of pixels 24 and peripheral circuits. The imaging device 100 is an image sensor realized on a single-chip integrated circuit and has a pixel array PA including a plurality of pixels 24 arranged in two dimensions. The imaging device 100 is an imaging device that operates in a global shutter manner in which the exposure periods of all the plurality of pixels 24 are unified. In other words, the imaging device 100 has a global shutter function. Details of the exposure period will be described later.

[0113] Multiple pixels 24 are arranged in two dimensions, i.e., in the row and column directions, on the semiconductor substrate 40 to form a photosensitive area which is a pixel area. Figure 8 shows an example in which the pixels 24 are arranged on a 2x2 matrix. The arrangement of pixels 24 is not limited to 2x2, and the number of rows and columns of pixels 24 is not particularly limited. Note that in Figure 8, for the sake of illustration, the circuit for individually setting the sensitivity of the pixels 24 (e.g., a pixel electrode control circuit) is omitted from the illustration. The imaging device 100 may also be a line sensor. In that case, the multiple pixels 24 may be arranged in one dimension. Note that in this specification, the row direction and column direction refer to the directions in which the rows and columns extend, respectively. That is, in Figure 8, the vertical direction on the paper is the column direction, and the horizontal direction is the row direction.

[0114] As shown in Figures 8 and 9, each pixel 24 comprises a photoelectric conversion unit 10A, a charge detection circuit 35, and a charge storage node 34 electrically connected to the photoelectric conversion unit 10A and the charge detection circuit 35. The charge detection circuit 35 includes an amplification transistor 21, a reset transistor 22, and an address transistor 23.

[0115] The photoelectric conversion unit 10A comprises a lower electrode 2 provided as a pixel electrode and an upper electrode 6 provided as a counter electrode. The entire photoelectric conversion unit 10A does not need to be an independent element for each pixel 24; a part of the photoelectric conversion unit 10A may span multiple pixels 24. A voltage for applying a predetermined bias voltage is supplied to the upper electrode 6 via the counter electrode signal line 26. If the photoelectric conversion unit 10A is composed of a photoelectric conversion element 11, a voltage for applying a predetermined bias voltage is supplied to the upper electrode 7 via the counter electrode signal line 26.

[0116] The lower electrode 2 is connected to the gate electrode 21G of the amplifying transistor 21, and the signal charge collected by the lower electrode 2 is stored in a charge storage node 34 located between the lower electrode 2 and the gate electrode 21G of the amplifying transistor 21. In this embodiment, the signal charge is a hole. That is, the charge storage node 34 is electrically connected to the lower electrode 2 and stores the holes generated in the photoelectric conversion layer 4.

[0117] The signal charge stored in the charge storage node 34 is applied to the gate electrode 21G of the amplifying transistor 21 as a voltage corresponding to the amount of signal charge. The amplifying transistor 21 amplifies this voltage, and the signal voltage is selectively read out by the address transistor 23. The reset transistor 22 has its source / drain electrodes connected to the lower electrode 2 via the charge storage node 34, and resets the signal charge stored in the charge storage node 34. In other words, the reset transistor 22 resets the potential of the gate electrode 21G and the lower electrode 2 of the amplifying transistor 21.

[0118] To selectively perform the above-described operations on multiple pixels 24, the imaging device 100 has a power supply line 31, a vertical signal line 27, an address signal line 36, and a reset signal line 37, each of which is connected to a pixel 24. Specifically, the power supply line 31 is connected to the source / drain electrodes of the amplification transistor 21, the vertical signal line 27 is connected to the source / drain electrodes of the address transistor 23, the address signal line 36 is connected to the gate electrode 23G of the address transistor 23, and the reset signal line 37 is connected to the gate electrode 22G of the reset transistor 22.

[0119] The peripheral circuitry includes a voltage supply circuit 19, a vertical scanning circuit 25, a horizontal signal readout circuit 20, multiple column signal processing circuits 29, multiple load circuits 28, and multiple differential amplifiers 32.

[0120] The voltage supply circuit 19 is electrically connected to the upper electrode 6 via the counter electrode signal line 26. The voltage supply circuit 19 supplies voltage to the upper electrode 6, thereby creating a potential difference between the upper electrode 6 and the lower electrode 2; in other words, it applies a voltage between the upper electrode 6 and the lower electrode 2. For example, the voltage supply circuit 19 supplies the upper electrode 6 with a voltage such that a second voltage is applied between the upper electrode 6 and the lower electrode 2 during the exposure period described later, and a first voltage different from the second voltage is applied between the upper electrode 6 and the lower electrode 2 during the non-exposure period.

[0121] The vertical scanning circuit 25 is connected to the address signal line 36 and the reset signal line 37, and selects multiple pixels 24 arranged in each row on a row-by-row basis, reads out the signal voltage, and resets the potential of the lower electrode 2. The power supply wiring 31, which is a source follower power supply, supplies a predetermined power supply voltage to each pixel 24. The horizontal signal readout circuit 20 is electrically connected to multiple column signal processing circuits 29. The column signal processing circuits 29 are electrically connected to the pixels 24 arranged in each column via vertical signal lines 27 corresponding to each column. The load circuit 28 is electrically connected to each vertical signal line 27. The load circuit 28 and the amplifying transistor 21 form a source follower circuit.

[0122] Multiple differential amplifiers 32 are provided, corresponding to each row. The negative input terminals of the differential amplifiers 32 are connected to the corresponding vertical signal lines 27. The output terminals of the differential amplifiers 32 are connected to the pixels 24 via feedback lines 33 corresponding to each row.

[0123] The vertical scanning circuit 25 applies a row selection signal to the gate electrode 23G of the address transistor 23 via the address signal line 36, which controls the on / off state of the address transistor 23. As a result, the row to be read is scanned and selected. A signal voltage is read from the pixel 24 of the selected row to the vertical signal line 27. The vertical scanning circuit 25 also applies a reset signal to the gate electrode 22G of the reset transistor 22 via the reset signal line 37, which controls the on / off state of the reset transistor 22. As a result, the row of pixel 24 to be reset is selected. The vertical signal line 27 transmits the signal voltage read from the pixel 24 selected by the vertical scanning circuit 25 to the column signal processing circuit 29.

[0124] The column signal processing circuit 29 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion (AD conversion).

[0125] The horizontal signal readout circuit 20 sequentially reads signals from multiple column signal processing circuits 29 to a horizontal common signal line.

[0126] The differential amplifier 32 is connected to the drain electrode of the reset transistor 22 via a feedback line 33. Therefore, the differential amplifier 32 receives the output value of the address transistor 23 at its negative terminal. The differential amplifier 32 performs feedback operation so that the gate potential of the amplifying transistor 21 becomes a predetermined feedback voltage. At this time, the output voltage value of the differential amplifier 32 is, for example, a positive voltage of 0V or near 0V. The feedback voltage refers to the output voltage of the differential amplifier 32.

[0127] As shown in Figure 9, the pixel 24 comprises a semiconductor substrate 40, a charge detection circuit 35, a photoelectric conversion unit 10A, and a charge storage node 34 (see Figure 8).

[0128] The semiconductor substrate 40 may be an insulating substrate or the like, with a semiconductor layer provided on the surface on which the photosensitive region is formed, for example, a p-type silicon substrate. The semiconductor substrate 40 has impurity regions 21D, 21S, 22D, 22S, and 23S, and element isolation regions 41 for electrical isolation between pixels 24. The impurity regions 21D, 21S, 22D, 22S, and 23S are, for example, n-type regions. Here, the element isolation region 41 is provided between the impurity region 21D and the impurity region 22D. This suppresses leakage of signal charge accumulated at the charge storage node 34. The element isolation region 41 is formed, for example, by ion implantation of acceptors under predetermined implantation conditions.

[0129] The impurity regions 21D, 21S, 22D, 22S, and 23S are, for example, diffusion regions formed within the semiconductor substrate 40. As shown in Figure 9, the amplifying transistor 21 includes impurity regions 21S and 21D and a gate electrode 21G. The impurity regions 21S and 21D function, for example, as the source region and drain region of the amplifying transistor 21. The channel region of the amplifying transistor 21 is formed between the impurity regions 21S and 21D.

[0130] Similarly, the address transistor 23 includes an impurity region 23S and an impurity region 21S, and a gate electrode 23G connected to the address signal line 36. In this example, the amplification transistor 21 and the address transistor 23 are electrically connected to each other by sharing the impurity region 21S. The impurity region 23S functions, for example, as the source region of the address transistor 23. The impurity region 23S has a connection to the vertical signal line 27 shown in Figure 8.

[0131] The reset transistor 22 includes impurity regions 22D and 22S and a gate electrode 22G connected to the reset signal line 37. The impurity region 22S functions, for example, as the source region of the reset transistor 22. The impurity region 22S has a connection to the reset signal line 37, as shown in Figure 8.

[0132] An interlayer insulating layer 50 is laminated on the semiconductor substrate 40 so as to cover the amplification transistor 21, the address transistor 23, and the reset transistor 22. In Figure 9, for the sake of clarity, the cross-sectional area of ​​the interlayer insulating layer 50 is omitted by shading.

[0133] Furthermore, a wiring layer (not shown) may be placed within the interlayer insulating layer 50. The wiring layer may be formed from a metal such as copper, and may include wiring such as the vertical signal line 27 described above as part of its structure. The number of insulating layers within the interlayer insulating layer 50 and the number of layers included in the wiring layer placed within the interlayer insulating layer 50 can be arbitrarily set.

[0134] The interlayer insulating layer 50 contains a contact plug 53 connected to the gate electrode 21G of the amplification transistor 21, and a contact connected to the impurity region 22D of the reset transistor 22. Plug 54, contact plug 51 connected to the lower electrode 2, and wiring 52 connecting contact plug 51, contact plug 54, and contact plug 53 are arranged. As a result, the impurity region 22D of the reset transistor 22 is electrically connected to the gate electrode 21G of the amplifying transistor 21. In the configuration illustrated in Figure 9, contact plugs 51, 53, and 54, wiring 52, the gate electrode 21G of the amplifying transistor 21, and the impurity region 22D of the reset transistor 22 constitute at least one part of the charge storage node 34.

[0135] The charge detection circuit 35 detects the signal charge captured by the lower electrode 2 and outputs a signal voltage. The charge detection circuit 35 includes an amplifying transistor 21, a reset transistor 22, and an address transistor 23, and is formed on a semiconductor substrate 40.

[0136] The amplifying transistor 21 is formed within a semiconductor substrate 40 and includes an impurity region 21D and an impurity region 21S that function as a drain electrode and a source electrode, respectively, a gate insulating layer 21X formed on the semiconductor substrate 40, and a gate electrode 21G formed on the gate insulating layer 21X.

[0137] The reset transistor 22 is formed within the semiconductor substrate 40 and includes an impurity region 22D and an impurity region 22S that function as a drain electrode and a source electrode, respectively, a gate insulating layer 22X formed on the semiconductor substrate 40, and a gate electrode 22G formed on the gate insulating layer 22X.

[0138] The address transistor 23 is formed within the semiconductor substrate 40 and includes impurity regions 21S and 23S that function as drain and source electrodes, respectively, a gate insulating layer 23X formed on the semiconductor substrate 40, and a gate electrode 23G formed on the gate insulating layer 23X. The impurity region 21S is connected in series with the amplifying transistor 21 and the address transistor 23.

[0139] The photoelectric conversion unit 10A described above is arranged on the interlayer insulating layer 50. In other words, in this embodiment, a plurality of pixels 24 constituting the pixel array PA are formed on the semiconductor substrate 40. The plurality of pixels 24 arranged in two dimensions on the semiconductor substrate 40 form a photosensitive region. The distance between two connected pixels 24 (i.e., the pixel pitch) may be, for example, about 2 μm.

[0140] The photoelectric conversion unit 10A has the same configuration as the photoelectric conversion element 10 described above.

[0141] A color filter 60 is formed above the photoelectric conversion unit 10A, and a microlens 61 is formed above the color filter 60. The color filter 60 is formed, for example, as an on-chip color filter by patterning, and a photosensitive resin in which dyes or pigments are dispersed is used. The microlens 61 is formed, for example, as an on-chip microlens, and an ultraviolet photosensitive material is used.

[0142] The imaging device 100 can be manufactured using general semiconductor manufacturing processes. In particular, when a silicon substrate is used as the semiconductor substrate 40, it can be manufactured using various silicon semiconductor processes.

[0143] Figure 10 shows an example of the schematic current-voltage characteristics (IV characteristics) of the photoelectric conversion unit 10A. In other words, the IV characteristics shown in Figure 10 are also an example of the IV characteristics of the photoelectric conversion element 10 described above. Note that the photoelectric conversion element 11 also has the same IV characteristics as the photoelectric conversion element 10, so the following explanation applies to the photoelectric conversion unit 10A composed of the photoelectric conversion element 11. It also applies.

[0144] In Figure 10, the vertical axis represents the current density flowing between the lower electrode 2 and the upper electrode 6, and the horizontal axis represents the voltage applied between the upper electrode 6 and the lower electrode 2. Furthermore, on the horizontal axis of Figure 10, a positive voltage represents the reverse bias voltage, and a negative voltage represents the forward bias voltage. In other words, in Figure 10, the voltage at which the signal charge moves to the lower electrode 2 is defined as a "positive" value, and the IV characteristics are shown.

[0145] In Figure 10, the thick solid line graph shows an example of the IV characteristics of the photoelectric conversion unit 10A when a voltage is applied between the lower electrode 2 and the upper electrode 6 under light illumination conditions. Hereafter, the state under light illumination may be referred to as "bright conditions." Also in Figure 10, an example of the IV characteristics of the photoelectric conversion unit 10A when a voltage is applied between the lower electrode 2 and the upper electrode 6 under unilluminated conditions is shown by a thick dashed line. Hereafter, the state under unilluminated conditions may be referred to as "dark conditions."

[0146] As shown in Figure 10, the photocurrent characteristics of the photoelectric conversion unit 10A according to this embodiment are generally characterized by a first voltage range, a second voltage range, and a third voltage range.

[0147] In the first voltage range, the dependence of the current change in the photoelectric conversion layer 4 on the voltage applied between the lower electrode 2 and the upper electrode 6, and the amount of light incident on the photoelectric conversion layer 4, is small. In other words, in the first voltage range, the difference between the current value that flows when light is incident on the photoelectric conversion layer 4 and the current value that flows when light is not incident can be considered to be small. In the first voltage range, even if hole-electron pairs are generated by the incidence of light on the photoelectric conversion layer 4, the absolute value of the voltage applied between the lower electrode 2 and the upper electrode 6 is not large, so recombination of the holes and electrons occurs before they separate. The first voltage range includes, for example, voltages near 0V and forward bias voltages with relatively small absolute values.

[0148] Furthermore, the second voltage range in Figure 10 is the voltage range of the reverse bias voltage, and it is the region in which the absolute value of the output current density increases as the reverse bias voltage increases. In other words, the second voltage range is the region in which the current value increases as the amount of light incident on the photoelectric conversion layer 4 and the reverse bias voltage applied between the lower electrode 2 and the upper electrode 6 increase.

[0149] Furthermore, the third voltage range is a voltage range in which the absolute value of the forward bias voltage is larger than that of the forward bias voltage range in the first voltage range, and is a region in which the output current density increases as the forward bias voltage increases. In other words, the third voltage range is a region in which the current increases as the forward bias voltage applied between the lower electrode 2 and the upper electrode 6 increases, even without light incidence to the photoelectric conversion layer 4.

[0150] The second voltage corresponding to the capacitance C2 mentioned above is, for example, a voltage within the second voltage range. In other words, Figures 5A and 6A above correspond to exemplary energy band diagrams when a voltage within the second voltage range is applied between the upper electrode 6 or 7 and the lower electrode 2 in the photoelectric conversion elements 10 and 11. Also, the first voltage corresponding to the capacitance C1 mentioned above is, for example, a voltage within the first voltage range. In other words, Figures 5B and 6B correspond to exemplary energy band diagrams when a forward bias voltage within the first voltage range is applied between the upper electrode 6 or 7 and the lower electrode 2 in the photoelectric conversion elements 10 and 11.

[0151] As described in detail later, the imaging device 100 has an IV characteristic in which the photoelectric conversion unit 10A of this embodiment has a first voltage range in which the difference between the current value that flows when light is incident on the photoelectric conversion layer 4 and the current value that flows when there is no light incident is small. Therefore, the imaging device 100 can easily realize a global shutter function.

[0152] Furthermore, since the photoelectric conversion unit 10A is composed of photoelectric conversion elements 10 or 11, as shown in Figures 5B and 6B, when a first voltage in the first voltage range is applied, the upper electrode 7, which has a small work function and a large carrier density, or the intermediate layer 5, which has an intermediate level, allows for a large number of electrons to be present in the photoelectric conversion layer 4 due to electrons injected from the upper electrode 6 or 7. In other words, the capacitance of the photoelectric conversion unit 10A can be increased. As a result, the effect of promoting recombination between holes, which are signal charges, and injected electrons in the photoelectric conversion layer 4 is enhanced, making it more difficult for holes to move to the lower electrode 2, and parasitic sensitivity is less likely to occur during the period when the first voltage is applied between the upper electrode 6 or 7 and the lower electrode 2.

[0153] In the above description, the photoelectric conversion unit 10A is positioned above the semiconductor substrate 40 with the lower electrode 2 facing the semiconductor substrate 40. However, the photoelectric conversion unit 10A may also be positioned with the lower electrode 2 facing the opposite side of the semiconductor substrate 40. In this case, since light transmitted through the lower electrode 2 is incident on the photoelectric conversion layer 4, the lower electrode 2 is a transparent electrode such as an ITO film. In this case, the lower electrode 2 is connected to a charge detection circuit 35 formed on the semiconductor substrate 40 via a contact plug that penetrates the photoelectric conversion unit 10A from the interlayer insulating layer 50 to the lower electrode 2.

[0154] [Operation of the imaging device] Next, the operation of the imaging device 100 will be explained with reference to Figures 11 and 12. Here, the operation of the imaging device 100 will be explained when holes are used as signal charges, as described above.

[0155] Figure 11 shows a schematic circuit configuration of pixel 24. For simplicity of explanation, this shows the case where one end of the charge storage node 34 is grounded and the potential is zero. This state corresponds, for example, to the case where the feedback line 33 shown in Figure 8 is set to 0V. In this state, if the voltage across the charge storage node 34 is Vc, then Vc is zero.

[0156] The voltage supply circuit 19 shown in Figure 8 supplies the upper electrode 6 with voltages that differ between the exposure period and the non-exposure period via the counter electrode signal line 26. In this specification, "exposure period" means the period for accumulating either electrons or holes generated by photoelectric conversion as signal charges in the charge storage node 34. That is, the "exposure period" may also be called the "charge storage period". In this specification, the period during the operation of the imaging device other than the exposure period is called the "non-exposure period". The "non-exposure period" may be a period during which the incidence of light to the photoelectric conversion unit 10A is blocked, or it may be a period during which light is irradiated to the photoelectric conversion unit 10A, but charge is not substantially accumulated in the charge storage node 34.

[0157] In the initial state, the potential difference between the lower electrode 2 and the upper electrode 6 of the photoelectric conversion unit 10A, that is, the bias voltage applied to the photoelectric conversion layer 4, the electron blocking layer 3, and the intermediate layer 5, is set to a value within the first voltage range. For example, the voltage supply circuit 19 supplies a voltage equal to the voltage of the lower electrode 2 to the upper electrode 6 using the counter electrode signal line 26. Here, if the voltage supplied to the upper electrode 6 is V2, then V2 is assumed to be the reference voltage Vref. In this case, if the bias voltage applied to the photoelectric conversion unit 10A is Vo, then Vo = V2 - Vc, so Vo = 0.

[0158] Next, the operation during the exposure period will be described. At the start of the exposure period, the voltage supply circuit 19 supplies a voltage V2 to the upper electrode 6 using the counter electrode signal line 26 so that a voltage within the second voltage range, i.e., a reverse bias voltage, is applied to the photoelectric conversion unit 10A. In other words, during the exposure period, the voltage supply circuit 19 supplies the upper electrode 6 with a voltage V2 that causes the photoelectric conversion layer 4 to be sensitive to photoelectric conversion. For example, if the photoelectric conversion layer 4 is made of an organic semiconductor material, the voltage V2 during the exposure period is a voltage of several volts to about 10 volts. As a result, holes in an amount corresponding to the amount of incident light on the photoelectric conversion layer 4 are accumulated as signal charges in the charge storage node 34 of each pixel 24.

[0159] Next, the operation during the non-exposure period will be described. After the exposure period ends, the voltage supply circuit 19 supplies a voltage V2 to the upper electrode 6 using the counter electrode signal line 26 so that a voltage within the first voltage range is applied to the photoelectric conversion unit 10A. In other words, during the non-exposure period, the voltage supply circuit 19 supplies a voltage V2 to the upper electrode 6 that recombines electrons and holes in the photoelectric conversion layer 4. For example, the voltage V2 supplied to the upper electrode 6 is set to a reference voltage Vref. In the charge storage node 34 of each pixel 24, holes are accumulated according to the amount of light incident on the photoelectric conversion layer 4 during the exposure period, and the value of Vc differs depending on the pixel 24. Since Vo = V2 - Vc, in pixels 24 that are not exposed and whose Vc has not changed, Vo is also zero. However, in pixels 24 where Vc has changed, Vo is not zero, but becomes a forward bias voltage. If the width of the first voltage range is sufficiently wide, even if the value of Vc differs for each pixel 24, the voltage V2 can be set so that the bias voltage Vo applied to the photoelectric conversion unit 10A falls within the first voltage range for each pixel 24. The variation in the value of the voltage Vc that falls within the first voltage range corresponds to the width of the dynamic range. For example, if the width of the first voltage range is 0.5V or more, the conversion gain is 50μV / e - In this imaging device, a dynamic range of 80 dB or more, equivalent to that of the human eye, can be secured.

[0160] When the upper electrode 6 is supplied with a voltage V2 within the first voltage range, holes are less likely to move to the charge storage node 34 even when light is incident on the pixel 24. In other words, the voltage supply circuit 19 supplies voltage to the upper electrode 6 such that the photoelectric conversion efficiency of multiple pixels 24, specifically the photoelectric conversion unit 10A, differs between the exposure period and the non-exposure period. Furthermore, when the upper electrode 6 is supplied with a voltage V2 within the first voltage range, holes accumulated in the charge storage node 34 are less likely to be discharged to the lower electrode 2, and charges supplied from the voltage supply circuit 19 via the lower electrode 2 are less likely to flow into the charge storage node 34.

[0161] Therefore, the holes accumulated in the charge storage node 34 of each pixel 24 are maintained in an amount corresponding to the amount of light incident on the photoelectric conversion layer 4. In other words, the holes accumulated in the charge storage node 34 of each pixel 24 can be retained even when light is incident on the photoelectric conversion layer 4 again, as long as the holes in the charge storage node 34 are not reset. For this reason, even when sequential readout operations are performed row by row during the non-exposure period, it is unlikely that new holes will accumulate in the charge storage node 34 during the readout operation. Therefore, rolling distortion does not occur, for example, as in a rolling shutter. Thus, a global shutter function can be realized with a simple pixel circuit such as a pixel 24, without the need for a transfer transistor and additional storage capacitance. Because the pixel circuit is simple, the pixel 24 can be miniaturized to an advantage in the imaging device 100.

[0162] Figure 12 is a timing chart showing an example of the relationship between the voltage V2 supplied to the upper electrode 6 of the photoelectric conversion unit 10A and the timing of operation in each row of the pixel array PA of the imaging device 100. For clarity, Figure 12 shows only the changes in voltage V2 and the exposure and signal readout timings for each row of the pixel array PA, indicated by R0 to R7. In the imaging device 100, during the non-exposure period N, the voltage supply circuit 19 supplies voltage Vb to the upper electrode 6 as voltage V2 such that the bias voltage Vo falls within a first voltage range, and during the exposure period E, it supplies voltage Va as voltage V2 such that the bias voltage Vo falls within a second voltage range.

[0163] As shown in Figure 12, during the non-exposure period N, the signal of pixels 24 in each row from R0 to R7 The readout of pixels R is performed sequentially. In other words, during the non-exposure period N, the charge detection circuit 35 detects the signal charge accumulated in the charge storage node 34 and outputs a signal corresponding to the amount of signal charge accumulated in the charge storage node 34. Furthermore, the start and end timings of the exposure period E coincide for all pixels 24 in all rows from R0 to R7. In other words, the imaging device 100 realizes a global shutter function in which all rows of the pixel array PA are exposed at once while sequentially reading out the signals of the pixels 24 in each row.

[0164] The bias voltage Vo when a voltage Vb is supplied to the upper electrode 6 during the non-exposure period N is, for example, the first voltage described above, and the bias voltage Vo when a voltage Va is supplied to the upper electrode 6 during the exposure period E is, for example, the second voltage described above. As described above, the magnitude of the bias voltage Vo applied between the lower electrode 2 and the upper electrode 6 also changes depending on the potential of the charge storage node 34, that is, the amount of signal charge stored. However, the voltage supply circuit 19 selectively supplies voltages to the upper electrode 6 such that the potential difference between the potential of the upper electrode 6 and the potential of the lower electrode 2 when the pixel 24 is reset becomes the first voltage and the second voltage, respectively. In other words, in this specification, when a first voltage or a second voltage is applied between the lower electrode 2 and the upper electrode 6, it means that a voltage is supplied to the upper electrode 6 such that the potential difference between the potential of the upper electrode 6 and the potential of the lower electrode 2 when the pixel 24 is reset becomes the first voltage or the second voltage.

[0165] In the imaging device 100 according to this embodiment, since the photoelectric conversion unit 10A is composed of a photoelectric conversion element 10, when a first voltage within a first voltage range is applied between the upper electrode 6 and the lower electrode 2, electrons injected from the upper electrode 6 or 7 cause an increase in the number of electrons in the photoelectric conversion layer 4. In other words, the capacitance between the upper electrode 6 and the lower electrode 2 increases. As a result, during the non-exposure period when the first voltage is applied, holes remaining in the photoelectric conversion layer 4 that cause parasitic sensitivity, and holes newly generated by light incident on the photoelectric conversion layer 4 during the non-exposure period, can be effectively recombined, thereby suppressing parasitic sensitivity. Therefore, for example, noise in the imaging device 100 can be reduced.

[0166] The parasitic sensitivity of the imaging device 100 is, for example, less than -100 dB. In this specification, the parasitic sensitivity is a value measured as follows. First, in both the bright and dark conditions, the imaging device 100 is driven in the global shutter manner as described above, and the signal value output from the charge detection circuit 35 is acquired during the non-exposure period N after the exposure period E. The output difference between the bright and dark conditions at this time is defined as the output difference during exposure. Also, in both the bright and dark conditions, the global shutter operation is performed by changing the conditions in the global shutter driving described above so that the same voltage as the non-exposure period N is supplied to the upper electrode 6 during the exposure period E, and the signal value output from the charge detection circuit 35 is acquired during the non-exposure period N after the exposure period E. The output difference between the bright and dark conditions at this time is defined as the output difference during non-exposure. Then, 20log 10 The parasitic sensitivity is calculated using the formula (output difference during non-exposure / output difference during exposure). Furthermore, the amount of light irradiated onto the photoelectric conversion unit 10A under bright conditions is 150 cd / m². 2 That is the case.

[0167] The operation of the imaging device 100 is not limited to the above example; for example, it may also perform operations that implement an electronic ND (Neutral Density) filter function to adjust the sensitivity of the photoelectric conversion.

[0168] For example, during the exposure period E in Figure 12, the voltage supply circuit 19, instead of supplying voltage Va, supplies a voltage to the upper electrode 6 as voltage V2 that corresponds to a predetermined ND value, which is a sensitivity reduction factor, based on the relationship between the bias voltage and the current value at that voltage (i.e., the amount of signal charge extracted by the photoelectric conversion layer 4). This enables the imaging device 100 to function as an electronic ND filter.

[0169] Furthermore, Figure 13 shows the photoelectric conversion in the imaging device 100 using a pulse duty cycle control method. This is a timing chart showing an example of the operation to adjust the sensitivity. As shown in Figure 13, the voltage supply circuit 19 supplies a pulsed voltage that repeats the above-mentioned voltages Va and Vb during the exposure period E, for example. In this way, the period during which the voltage supply circuit 19 supplies voltage Vb to the upper electrode 6 to make the bias voltage Vo the first voltage and the period during which it supplies voltage Va to the upper electrode 6 to make the bias voltage Vo the second voltage may be included in the exposure period E within the same frame. In this case, the duty cycle of the pulsed voltage that repeats voltages Va and Vb is set to a duty cycle corresponding to a predetermined ND value, and the voltage supply circuit 19 supplies voltage to the upper electrode 6. This also enables the electronic ND filter function of the imaging device 100. In this case, during the period during the exposure period E when voltage Vb is applied to the upper electrode 6, parasitic sensitivity is reduced, similar to the non-exposure period N described above, making it easier to accurately achieve the set ND value.

[0170] Thus, even when the imaging device 100 has an electronic ND filter function, the parasitic sensitivity of the imaging device 100 is reduced as described above during the period when the first voltage is applied between the upper electrode 6 and the lower electrode 2, so that the imaging device 100 can achieve imaging with less noise.

[0171] In the above explanation, holes were used as the signal charge, but electrons may also be used as the signal charge. In this case, when the first voltage is applied between the upper electrode 6 and the lower electrode 2, the injection of holes from the upper electrode 6 into the photoelectric conversion layer 4 is promoted, increasing the capacitance between the upper electrode 6 and the lower electrode 2. Therefore, in the photoelectric conversion layer 4, the electrons, which are the signal charge, and the injected holes recombine, thereby reducing parasitic sensitivity. In this case, the polarity of the voltage applied by the voltage supply circuit 19 between the upper electrode 6 and the lower electrode 2 is reversed compared to the explanation above. [Examples]

[0172] The photoelectric conversion element and imaging device according to this disclosure will be specifically described below in the examples, but this disclosure is not limited in any way to the following examples. In detail, a photoelectric conversion element and imaging device according to the embodiments of this disclosure, as well as a photoelectric conversion element and imaging device for characteristic comparison, were fabricated and their characteristics were evaluated.

[0173] (Fabrication of photoelectric conversion elements) Photoelectric conversion elements were fabricated in the examples and comparative examples. The schematic configurations of the photoelectric conversion elements in Examples 1 to 3 are shown in Figure 14A. The schematic configurations of the photoelectric conversion elements in Examples 4 to 8 are shown in Figure 14B. The schematic configurations of the photoelectric conversion elements related to Comparative Examples 1 to 3 are shown in Figure 15. The details of the fabrication of the photoelectric conversion elements in the examples and comparative examples will be described below.

[0174] [Example 1] A substrate with a TiN film deposited on it was used as the support substrate. TiN with a work function of 4.7 eV was used as the lower electrode, and an electron blocking layer was formed on the lower electrode by vacuum deposition of 9,9′-[1,1′-Biphenyl]-4,4′-diylbis[3,6-bis(1,1-dimethyl ethyl)]-9H-carbazole (also referred to as "material A") to a thickness of 50 nm as the electron blocking layer material.

[0175] Next, a photoelectric conversion layer was formed on the electron blocking layer by co-depositing subphthalocyanine (also referred to as "material B"), a donor organic semiconductor material, and C60 fullerene (also referred to as "material C"), an acceptor organic semiconductor material, in a weight ratio of 20:80 using vacuum deposition. The thickness of the photoelectric conversion layer obtained at this time was approximately 400 nm. Furthermore, as the subphthalocyanine, a subphthalocyanine having boron (B) as the central metal and chloride ions coordinated to B as ligands was used. Cyanine was used.

[0176] Next, an ITO film was formed on the photoelectric conversion layer as the upper electrode to a thickness of 50 nm by sputtering. The target composition used in the sputtering method was InO:SnO = 9:1. To adjust the deposition atmosphere for the ITO film, a deposition gas consisting only of argon (i.e., a deposition gas with 0% oxygen concentration) was introduced into the chamber, and the pressure inside the chamber was adjusted to 0.3 Pa. Subsequently, the substrate was heated at 200°C for 30 minutes to promote the crystallization of the ITO.

[0177] Subsequently, a 40 nm thick Al2O3 film was formed on the upper electrode as a encapsulating film by atomic layer deposition to obtain the photoelectric conversion element in Example 1.

[0178] [Example 2] In preparing the atmosphere for ITO film deposition, a deposition gas mixture of argon and oxygen with an oxygen concentration of 0.12% was introduced into the chamber. The same procedure as in Example 1 was followed to obtain the photoelectric conversion element in Example 2.

[0179] [Example 3] In preparing the atmosphere for ITO film deposition, a deposition gas mixture of argon and oxygen with an oxygen concentration of 0.23% was introduced into the chamber. The same procedure as in Example 1 was followed to obtain the photoelectric conversion element in Example 3.

[0180] [Example 4] Before forming the upper electrode, an intermediate layer was formed on the photoelectric conversion layer by vacuum deposition using a metal shadow mask to deposit 2,11,20,29-tetra-tert-butyl-2,3-naphthalocyanine (also referred to as "material D") as the intermediate layer material to a thickness of 10 nm, and the upper electrode was formed on the intermediate layer. The same procedure as in Example 2 was followed to obtain the photoelectric conversion element in Example 4.

[0181] [Example 5] In preparing the atmosphere for ITO film deposition, a deposition gas mixture of argon and oxygen with an oxygen concentration of 0.23% was introduced into the chamber. The same procedure as in Example 4 was followed to obtain the photoelectric conversion element in Example 5.

[0182] [Example 6] In preparing the atmosphere for ITO film deposition, a deposition gas mixture of argon and oxygen with an oxygen concentration of 0.67% was introduced into the chamber. The same procedure as in Example 4 was followed to obtain the photoelectric conversion element in Example 6.

[0183] [Example 7] Except for forming an electron blocking layer with a thickness of 150 nm, the same process as in Example 6 was followed to obtain the photoelectric conversion element in Example 7.

[0184] [Example 8] Except for forming an electron blocking layer with a thickness of 300 nm, the same process as in Example 6 was followed to obtain the photoelectric conversion element in Example 8.

[0185] [Comparative Example 1] The process for preparing the ITO film deposition atmosphere was the same as in Example 1, except that a deposition gas mixture of argon and oxygen with an oxygen concentration of 0.45% was introduced into the chamber. The process was carried out to obtain the photoelectric conversion element in Comparative Example 1.

[0186] [Comparative Example 2] In adjusting the atmosphere for ITO film deposition, a deposition gas mixture of argon and oxygen with an oxygen concentration of 0.67% was introduced into the chamber. The same procedure as in Example 1 was followed to obtain the photoelectric conversion element in Comparative Example 2.

[0187] [Comparative Example 3] In adjusting the atmosphere for ITO film deposition, a deposition gas mixture of argon and oxygen with an oxygen concentration of 1.1% was introduced into the chamber. The same procedure as in Example 1 was followed to obtain the photoelectric conversion element in Comparative Example 3.

[0188] (Fabrication of imaging device) Using photoelectric conversion elements having the same configuration as those in Example 1 as the photoelectric conversion units for each pixel, the imaging device in Example 1 was fabricated to have the circuit configuration shown in Figure 8. Similarly to Example 1, the imaging devices in Examples 2 to 8 and Comparative Examples 1 to 3 were fabricated using photoelectric conversion elements having the same configuration as those in Example 1 as the photoelectric conversion units for each pixel.

[0189] (Measurement of ionization potential and electron affinity) The ionization potential and electron affinity were measured for each material used in the examples and comparative examples.

[0190] In measuring the ionization potential, samples were first prepared by depositing each of the materials used in the examples and comparative examples onto a glass substrate on which an ITO film had been deposited. Next, the number of photoelectrons was measured for the prepared samples using an air-in-air photoelectron spectrometer (AC-3, RIKEN KEKI) when the ultraviolet irradiation energy was changed, and the energy position at which photoelectrons began to be detected was defined as the ionization potential.

[0191] In measuring electron affinity, samples were first prepared by depositing each of the materials used in the examples and comparative examples onto a quartz substrate. Next, the absorption spectra of the prepared samples were measured using a spectrophotometer (U4100, Hitachi High-Technologies), and the optical band gap was calculated from the absorption edge results of the obtained absorption spectra. The electron affinity was estimated by subtracting the calculated optical band gap from the ionization potential obtained from the ionization potential measurement above.

[0192] Table 1 shows the ionization potential and electron affinity of each material used in the examples and comparative examples.

[0193] [Table 1]

[0194] As shown in Table 1, in the photoelectric conversion elements of the examples and comparative examples, the ionization potential of material A constituting the electron blocking layer is 5.8 eV, and the photoelectric conversion layer The ionization potential of material C, which is a donor organic semiconductor material included, is 5.5 eV. In other words, in the photoelectric conversion element in the example, the ionization potential of the electron blocking layer is greater than the ionization potential of the donor organic semiconductor material included in the photoelectric conversion layer.

[0195] Furthermore, in the photoelectric conversion element in the embodiment, the electron affinity of material D constituting the intermediate layer is 3.7 eV, and the electron affinity of material B, an acceptor organic semiconductor material included in the photoelectric conversion layer, is 4.2 eV. In other words, in the photoelectric conversion element in the embodiment, the electron affinity of the intermediate layer is smaller than the electron affinity of the acceptor organic semiconductor material included in the photoelectric conversion layer.

[0196] Furthermore, in the photoelectric conversion elements of Examples 3 to 8, 2,11,20,29-tetra-tert-butyl-2,3-naphthalocyanine, which is material D forming the intermediate layer, is relatively prone to association and readily forms intermediate energy levels.

[0197] (Measurement of sheet resistance of ITO film) The sheet resistance was measured for the ITO films used in the examples and comparative examples.

[0198] In measuring the sheet resistance of the ITO film, first, an oxide film was formed on a Si substrate, and then an ITO film with a thickness of 50 nm was formed on the oxide film under the same conditions as for ITO film formation in Examples 1 to 8 and Comparative Examples 1 to 3. Next, the sheet resistance (unit: Ω / □) of the formed ITO film was measured using a 4-probe measuring instrument. The measurement results of the sheet resistance of the ITO film corresponding to each example and comparative example are shown in Table 2.

[0199] (Measurement of capacitance of photoelectric conversion element) The capacitance of the photoelectric conversion elements in the examples and comparative examples was measured.

[0200] In measuring the capacitance of the photoelectric conversion elements, the impedance of the photoelectric conversion elements in the examples and comparative examples was measured from 10 Hz to 10 kHz using an LCR meter (E4980A, Keysight Technologies) connected to the upper and lower electrodes, with no light incident on the photoelectric conversion elements. The average value of the capacitance at each frequency was then calculated. In addition, the capacitance C1 was measured when a first voltage of -1V was applied between the upper and lower electrodes, and the capacitance C2 was measured when a second voltage of 8V was applied between the upper and lower electrodes. Furthermore, a voltage at which the potential of the upper electrode became higher than the potential of the lower electrode was defined as a "positive" value.

[0201] Table 2 shows the capacitance C1, capacitance C2, and the ratio of capacitance C1 to capacitance C2.

[0202] (Evaluation of parasitic sensitivity) The parasitic sensitivity in the examples and comparative examples was evaluated.

[0203] In evaluating parasitic sensitivity, first, the imaging devices in the examples and comparative examples were set in a camera with a lens, and the output from the charge detection circuit of the imaging device was acquired in both bright and dark conditions at the driving voltage. Specifically, in both bright and dark conditions, the imaging device was driven using the global shutter method described in Figure 12, etc., and the signal charge was read out during the non-exposure period after the exposure period, and the signal value output from the charge detection circuit was acquired. The difference in output between bright and dark conditions at this time was defined as the output difference during exposure. Furthermore, in both bright and dark conditions, the global shutter operation was performed by changing the driving conditions in the above global shutter method to supply the same voltage to the upper electrode during the exposure period as during the non-exposure period, and the output from the charge detection circuit was acquired during the non-exposure period after the exposure period. The signal value output from the charge detection circuit was acquired during this period. The difference in output between bright and dark conditions was defined as the output difference in the non-exposure state. Then, 20log 10 The parasitic sensitivity was defined as the value calculated using the formula (output difference during non-exposure / output difference during exposure). The voltage applied between the upper and lower electrodes during exposure was 8V, and the voltage applied between the upper and lower electrodes during non-exposure was -1V. The amount of light irradiated onto the photoelectric conversion element in bright conditions was 150 cd / m². 2 The results of the parasitic sensitivity evaluation are shown in Table 2.

[0204] [Table 2]

[0205] Table 2 shows the sheet resistance, capacitance, and parasitic sensitivity of ITO films in the examples and comparative examples, as well as the oxygen concentration in the deposition gas, the thickness of the electron blocking layer, and the presence or absence of an intermediate layer during ITO film formation.

[0206] As shown in Table 2, the lower the oxygen concentration in the film deposition gas, the lower the sheet resistance.

[0207] Furthermore, in the photoelectric conversion elements of Examples 1 to 8, the ratio of capacitance C1 under the condition of -1V application to capacitance C2 under the condition of 8V application is 1.5 times or more, indicating that capacitance C1 increases significantly when the first voltage of -1V is applied. This is thought to be because electrons are easily injected from the upper electrode into the photoelectric conversion layer.

[0208] Furthermore, -1V in the measurement of capacitance C1 is, for example, a first voltage applied between the upper and lower electrodes during the non-exposure period with global shutter drive. Also, 8V in the measurement of capacitance C2 is, for example, a second voltage applied between the upper and lower electrodes during the exposure period with global shutter drive. In the photoelectric conversion elements of Examples 4 to 8, which have an intermediate layer, and in the photoelectric conversion elements of Examples 1 to 3, which do not have an intermediate layer and in which the oxygen concentration in the film formation gas during ITO film formation is 0.23% or less, the capacitance C1 during the non-exposure period with global shutter drive is 1.5 times or more than the capacitance C2 during the exposure period. Furthermore, the parasitic sensitivity of the imaging devices of Examples 1 to 8 using these photoelectric conversion elements is less than -100dB, indicating that the parasitic sensitivity has been greatly reduced. This suggests that the increase in capacitance C2 facilitates electron injection from the upper electrode, and consequently, holes in the photoelectric conversion layer are more easily eliminated by recombination, resulting in improved parasitic sensitivity.

[0209] Furthermore, comparing the photoelectric conversion elements in Examples 6 to 8, where the thickness of the electron blocking layer is varied, it can be seen that the capacitance C1 is smaller as the thickness of the electron blocking layer increases. This indicates that the capacitance decreases because the distance from the lower electrode to the position where electrons are injected into the photoelectric conversion layer increases as the electron blocking layer becomes thicker.

[0210] As described above, in the photoelectric conversion elements and imaging devices of Examples 1 to 8, the capacitance C1 increases when the first voltage is applied during the non-exposure period. In other words, when charge injection occurs in the photoelectric conversion layer, the recombination of residual signal charges in the photoelectric conversion layer is promoted, resulting in an effect of reducing parasitic sensitivity.

[0211] The imaging apparatus relating to this disclosure has been described above based on embodiments and examples, but this disclosure is not limited to these embodiments and examples. Without departing from the spirit of this disclosure, various modifications to the embodiments and examples that a person skilled in the art could conceive of, as well as other forms constructed by combining some of the components of the embodiments and examples, are also included in the scope of this disclosure. [Industrial applicability]

[0212] The photoelectric conversion element and imaging device described herein can be applied to various camera systems and sensor systems, such as medical cameras, surveillance cameras, in-vehicle cameras, rangefinder cameras, microscope cameras, drone cameras, and robot cameras. [Explanation of symbols]

[0213] 1. Support substrate 2 Lower electrode 3 electron blocking layer 4. Photoelectric conversion layer 4A Donor-type organic semiconductor materials 4B Acceptor-type organic semiconductor materials 5. Middle Class 6, 7 Upper electrode 10, 11 Photoelectric conversion elements 10A Photoelectric Conversion Unit 19 Voltage supply circuit 20 Horizontal signal readout circuit 21 Amplifying transistors 22 Reset transistor 23 Address Transistors 21D, 21S, 22D, 22S, 23S impurity region 21G, 22G, 23G gate temperature 21X, 22X, 23X gate insulation layer 24 pixels 25 Vertical scanning circuit 26 Opposite electrode signal line 27 Vertical signal lines 28 Load circuit 29-column signal processing circuit 31 Power wiring 32 Differential Amplifiers 33 Feedback Line 34 Charge Storage Nodes 35 Charge detection circuit 36 Address signal lines 37 Reset signal line 40 Semiconductor substrates 41 Element isolation region 50 interlayer insulating layer 51, 53, 54 Contact plugs 52 Wiring 60 Color Filters 61 Microlenses 100 Imaging device

Claims

1. First electrode and, The second electrode and A photoelectric conversion layer located between the first electrode and the second electrode, which converts light into a signal charge, The device comprises a charge blocking layer located between the second electrode and the photoelectric conversion layer, When a first voltage is applied between the first electrode and the second electrode, the capacitance between the first electrode and the second electrode is 1.5 times or more the capacitance between the first electrode and the second electrode when a second voltage different from the first voltage is applied between the first electrode and the second electrode. Photoelectric conversion element.

2. The absolute value of the first voltage is less than the absolute value of the second voltage. The first voltage is a voltage that does not cause sensitivity in the photoelectric conversion element. The second voltage is a voltage that causes sensitivity in the photoelectric conversion element. The photoelectric conversion element according to claim 1.

3. The aforementioned signal charge is a hole, The first voltage is between -3V and 0V, with reference to the potential of the second electrode. The photoelectric conversion element according to claim 1.

4. The system further comprises an intermediate layer located between the photoelectric conversion layer and the first electrode, having an intermediate energy level. The photoelectric conversion element according to claim 1.

5. The aforementioned signal charge is a hole, The electron affinity of the intermediate layer is smaller than the electron affinity of the photoelectric conversion layer. The photoelectric conversion element according to claim 4.

6. The intermediate layer comprises a semiconductor material having the intermediate level due to association or impurities. The photoelectric conversion element according to claim 4.

7. The aforementioned semiconductor material is an organic semiconductor material. The photoelectric conversion element according to claim 6.

8. The first electrode is an ITO (Indium Tin Oxide) film formed in a film-forming atmosphere with an oxygen concentration of 0.23% or less in the film-forming gas. The photoelectric conversion element according to claim 1.

9. The aforementioned photoelectric conversion layer includes an organic semiconductor material. The photoelectric conversion element according to claim 1.

10. The charge blocking layer is an electron blocking layer, The aforementioned signal charge is a hole. The photoelectric conversion element according to claim 1.

11. The electron affinity of the electron blocking layer is smaller than the electron affinity of the photoelectric conversion layer. The ionization potential of the electron blocking layer is greater than the ionization potential of the photoelectric conversion layer. The photoelectric conversion element according to claim 10.

12. A photoelectric conversion element according to any one of claims 1 to 11, The device comprises a charge detection circuit that detects the signal charge during the period in which the first voltage is applied between the first electrode and the second electrode, Imaging device.

13. The parasitic sensitivity of the imaging device is less than -100 dB. The imaging apparatus according to claim 12.

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