FIFO memory and circuitry

Abstract

Providing a FIFO memory, etc., that can output while maintaining the timing difference between vertical synchronization signals, horizontal synchronization signals, etc., and image data. [Solution] The FIFO memory 10 that stores and outputs image data DA includes a write address counter 20 that generates a write address ADW, a read address counter 30 that generates a read address ADR, and a data buffer 40 that stores the vertical synchronization signal VSY, the horizontal synchronization signal HSY, the data enable signal DE, and the image data DA based on the write address ADW, and outputs the stored vertical synchronization signal VSY, the horizontal synchronization signal HSY, the data enable signal DE, and the image data DA based on the read address ADR.

Description

Technical Field

[0005] ,

[0001] The present invention relates to a FIFO memory, a circuit device, and the like.

Background Art

[0002] In a circuit device that handles video signals, a FIFO memory that stores and outputs image data is used. For example, Patent Document 1 discloses a FIFO memory in which a write address counter and a read address counter sequentially generate addresses in a wrap-around manner. According to this Patent Document 1, since it is not necessary to reset the count value to the initial value for each frame unit, it is possible to prevent the data for each frame unit from disappearing near the block boundary.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a configuration in which only image data is stored in a FIFO memory, there is a problem that it is difficult to output while maintaining the timing difference between the input image data, the vertical synchronization signal, and the horizontal synchronization signal. In particular, in the transfer of data between different clock systems such as an asynchronous FIFO, the timing is shifted.

Means for Solving the Problems

[0005] One aspect of the present disclosure relates to a FIFO memory for storing and outputting image data, comprising: a write address counter for generating a write address; a read address counter for generating a read address; and a data buffer for storing a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and the image data based on the write address, and for outputting the stored vertical synchronization signal, the horizontal synchronization signal, the data enable signal, and the image data based on the read address.

[0006] Another aspect of this disclosure relates to a circuit device including the asynchronous FIFO memory described above and a synchronous second FIFO memory for storing the image data from the FIFO memory. [Brief explanation of the drawing]

[0007] [Figure 1] An example configuration of the FIFO memory in this embodiment. [Figure 2] A diagram illustrating how data is written to a data buffer. [Figure 3] A diagram illustrating how data is written to a data buffer. [Figure 4] Detailed configuration example of FIFO memory. [Figure 5] Example configuration of a FIFO memory in a comparative example. [Figure 6] An example configuration for a synchronous FIFO memory. [Figure 7] A signal waveform diagram illustrating the operation of a synchronous FIFO memory. [Figure 8] Full and empty diagrams. [Figure 9] An example configuration for an asynchronous FIFO memory. [Figure 10] A signal waveform diagram illustrating the operation of an asynchronous FIFO memory. [Figure 11] A signal waveform diagram illustrating the operation of an asynchronous FIFO memory. [Figure 12] A signal waveform diagram illustrating the operation of an asynchronous FIFO memory. [Figure 13] A diagram illustrating the problem that occurs when the write address is reset in an asynchronous FIFO memory. [Figure 14] Diagram illustrating an asynchronous FIFO memory. [Figure 15] A signal waveform diagram illustrating the operation when the clock frequencies of the write clock and read clock are approximately the same. [Figure 16] A signal waveform diagram illustrating the operation when the read clock has a higher clock frequency than the write clock. [Figure 17] An example of the configuration of the circuit device of this embodiment. [Figure 18] A signal waveform diagram illustrating the operation of a circuit device. [Modes for carrying out the invention]

[0008] The following describes this embodiment. Note that the embodiment described below does not unduly limit the scope of the claims. Furthermore, not all of the configurations described in this embodiment are necessarily essential components.

[0009] 1. FIFO memory Figure 1 shows an example configuration of the FIFO memory 10 of this embodiment. The FIFO memory 10 includes a write address counter 20, a read address counter 30, and a data buffer 40. The FIFO memory 10 is a First-In First-Out memory, which stores and outputs image data. For example, the FIFO memory 10 is a memory that buffers image data. Note that the configuration of the FIFO memory 10 of this embodiment is not limited to the configuration shown in Figure 1, and various modifications can be made, such as omitting some of these components or adding other components.

[0010] The write address counter 20 generates write address ADW. For example, the write address counter 20 counts the write address ADW and outputs the write address ADW generated by the counting process to the data buffer 40.

[0011] The read address counter 30 generates a read address ADR. For example, the read address counter 30 performs a count process on the read address ADR and outputs the read address ADR generated by the count process to the data buffer 40.

[0012] The data buffer 40 stores the vertical synchronization signal VSY, the horizontal synchronization signal HSY, the data enable signal DE, and the image data DA based on the write address ADW. This data buffer 40 is, for example, a ring buffer. For example, the data buffer 40 stores the vertical synchronization signal VSY, the horizontal synchronization signal HSY, the data enable signal DE, and the image data DA as write data DAW in a storage area of a predetermined number of bits specified by the write address ADW from the write address counter 20. Here, storing a signal means storing a logic level of "0" or "1" corresponding to the voltage level of the signal. Also, storing the vertical synchronization signal VSY, the horizontal synchronization signal HSY, the data enable signal DE, and the image data DA includes the case of storing them after delaying them as will be described later.

[0013] The data buffer 40 also outputs the stored vertical synchronization signal VSY, horizontal synchronization signal HSY, data enable signal DE, and image data DA based on the read address ADR. For example, in the data buffer 40, the vertical synchronization signal VSY, horizontal synchronization signal HSY, data enable signal DE, and image data DA stored in a storage area of a predetermined number of bits specified by the read address ADR from the read address counter 30 are read out from the storage area as read data DAR. In this case, since the data buffer 40 is a buffer of the FIFO memory 10, the vertical synchronization signal VSY, horizontal synchronization signal HSY, data enable signal DE, and image data DA are written and read in a first-in, first-out manner. Note that the data buffer 40, which is a storage circuit, can be realized by a memory such as a RAM, and specifically, for example, by an SRAM.

[0014] FIG. 2 and FIG. 3 are explanatory diagrams of data writing to the data buffer 40. In FIG. 2, during the period of timing t1, the vertical synchronization signal VSY and the horizontal synchronization signal HSY are at the high level which is the active level. Also, during the periods of timings t2 and t3, the horizontal synchronization signal HSY is at the high level. Further, during the period of timing t4, the data enable signal DE becomes the high level and the image data DA[23:0] is input. Here, the image data DA[23:0] is, for example, 24-bit data in which each of R, G, and B is 8 bits, but the number of bits of the image data DA is not limited to this, and it may be less than 24 bits or more than 24 bits. Also, in the following, the explanation will be given assuming that the active level is the high level and the non-active level is the low level, but the active level may be the low level and the non-active level may be the high level.

[0015] Figure 3 shows the write data DAW stored in the data buffer 40 in the case of Figure 2. During the period of timing t1 in Figure 2, the vertical sync signal VSY and the horizontal sync signal HSY are at a high level. Therefore, "1", "1", and "0" are written to the bits corresponding to VSY, HSY, and DE at address AD1 of the data buffer 40. Also, since the image data DA[23:0] has not yet been input during the period of timing t1, all 0s are written to the 24 bits corresponding to DA[23:0] at address AD1.

[0016] Furthermore, during the timing periods t2 and t3, only the horizontal synchronization signal HSY is at a high level. As a result, "0", "1", and "0" are written to the bits corresponding to VSY, HSY, and DE in addresses AD2 and AD3 of the data buffer 40. Additionally, all 0s are written to the 24 bits corresponding to DA[23:0] in addresses AD2 and AD3.

[0017] During the timing t4 period, the data enable signal DE becomes high level and the image data DA[23:0] is input. Therefore, "0", "0", and "1" are written to the bits corresponding to VSY, HSY, and DE at address AD4 of the data buffer 40. Also, the bits D23, D22, D21, D20, etc., which are the bits of the image data DA, are written to the 24 bits corresponding to DA[23:0] at address AD4.

[0018] When writing to the data buffer 40 in this manner, the write data DAW corresponding to VSY, HSY, DE, DA[23:0] as shown in Figure 3 is written to addresses AD1, AD2, AD3, AD4, etc., which are specified by the write address ADW from the write address counter 20.

[0019] On the other hand, when reading from the data buffer 40, the read data DAR corresponding to VSY, HSY, DE, DA[23:0] in Figure 3 is read from addresses AD1, AD2, AD3, AD4, etc., which are specified by the read address ADR from the read address counter 30.

[0020] In this way, for example, as shown in Figure 2, a FIFO memory 10 can be realized that outputs the vertical sync signal VSY, horizontal sync signal HSY, data enable signal DE, and image data DA input from the write side to the read side while maintaining the timing difference. Furthermore, even for timings t1, t2, and t3 in Figure 2 where there is no image data DA, the vertical sync signal VSY and horizontal sync signal HSY can be output from the FIFO memory 10 while maintaining the timing difference. Also, in Figures 2 and 3, data is written to the data buffer 40 only during the active period when any of VSY, HSY, or DE is active. Therefore, it is possible to prevent the FIFO memory 10 from operating unnecessarily during the inactive period when all of VSY, HSY, and DE are inactive, thereby achieving low power consumption. In addition, the extra buffer capacity of the FIFO memory 10 used to store data during the inactive period can be reduced, and the buffer capacity of the data buffer 40 can be saved.

[0021] Figure 4 shows a detailed configuration example of the FIFO memory 10. In addition to the configuration in Figure 1, Figure 4 includes a delay circuit 50 and a write enable generation circuit 60. Note that the configuration of the FIFO memory 10 is not limited to the configuration in Figure 4, and various modifications can be made, such as omitting some of these components or adding other components. For example, in Figure 4, for the sake of explanation, the case where the FIFO memory 10 is synchronous is mainly used as an example, but the FIFO memory 10 may also be asynchronous. In the case of an asynchronous type, a configuration in which the write address ADW is copied to the read address ADR can be adopted, as will be described later.

[0022] The delay circuit 50 is a circuit that delays the vertical sync signal VSY, the horizontal sync signal HSY, the data enable signal DE, and the image data DA and outputs them to the data buffer 40. The vertical sync signal VSY, horizontal sync signal HSY, data enable signal DE, and image data DA, which have been delayed by the delay circuit 50, are then written to the data buffer 40 as write data DAW.

[0023] The write enable generation circuit 60 generates a write enable signal ENW and outputs it to the write address counter 20. For example, the write enable generation circuit 60 activates the write enable signal ENW to the write address counter 20 when at least one of the vertical sync signal VSY, horizontal sync signal HSY, and data enable signal DE is active. For example, when the active level is high, the write enable generation circuit 60 is implemented by an OR circuit, and the write enable signal ENW is raised to a high level when at least one of the vertical sync signal VSY, horizontal sync signal HSY, and data enable signal DE is high. When the write enable signal ENW is active in this way, the write data DAW is written to the data buffer 40, and the write address ADW is counted and updated (incremented) to the next address. Taking Figures 2 and 3 as examples, at timing t1, VSY and HSY are active, so the write enable signal ENW is activated and VSY, HSY, DE, and DA are written to address AD1. At timings t2 and t3, HSY becomes active, so the write enable signal ENW becomes active, and VSY, HSY, DE, and DA are written to addresses AD2 and AD3. At timing t4, DE becomes active, so the write enable signal ENW becomes active, and VSY, HSY, DE, and DA are written to address AD4. In this way, the write data DAW is written to the data buffer 40 only during the active period when at least one of the horizontal synchronization signal HSY and the data enable signal DE is active. Therefore, unnecessary operation of the FIFO memory 10 during the inactive period can be eliminated, resulting in lower power consumption and saving buffer capacity of the data buffer 40.

[0024] In Figure 4, the write address counter 20 and read address counter 30 are reset based on the vertical synchronization signal VSY. For example, a reset signal based on the vertical synchronization signal VSY is input to the reset terminal R of the write address counter 20 and read address counter 30, resetting the write address ADW and read address ADR. In this way, the write address ADW and read address ADR can be periodically reset using the vertical synchronization signal VSY. As a result, even if the FIFO memory 10 falls into an abnormal state due to noise or disturbances in the input signal that shorten the period of the vertical synchronization signal, it will be able to return to a normal state from the next frame or the next line.

[0025] It is also possible to implement a modified version in which the write address counter 20 and read address counter 30 are reset based on the horizontal sync signal HSY instead of the vertical sync signal VSY. Furthermore, in the asynchronous FIFO memory 10 described later, the write address ADW of the write address counter 20 is copied to the read address ADR of the read address counter 30 based on the vertical sync signal VSY.

[0026] For example, in circuit devices that handle video signals, such as display controllers, it is necessary to use a FIFO (First-In, First-Out) to transfer image data synchronously or asynchronously between different clock systems, or to store image data and output it continuously. In this case, it is desirable that the input video signal is passed to the next stage while maintaining its resolution and frame rate.

[0027] In this embodiment, the FIFO memory 10 stores HSY, VSY, DE, and DA video signals in the FIFO data buffer 40, and periodically resets the write address ADW and read address ADR based on the vertical synchronization signal VSY to recover from malfunctions. To perform this reset based on the vertical synchronization signal VSY, a configuration is adopted in which the write data DAW to the FIFO data buffer 40 is intentionally delayed by the delay circuit 50.

[0028] For example, Figure 5 shows an example configuration of a comparative example FIFO memory 510 of this embodiment. In the FIFO memory 510 of Figure 5, only the image data from the VSY, HSY, DE, and DA video signals is written to the FIFO data buffer 540. The write address counter 520 and read address counter 530 are reset based on the vertical synchronization signal VSY, and the write address ADW and read address ADR are output to the data buffer 540. In the configuration of this comparative example in Figure 5, there is a problem in that it is difficult to output while maintaining the timing difference between the input image data DA and the vertical synchronization signal VSY and horizontal synchronization signal HSY. In particular, the timing will be off when transferring image data DA between different clock systems, such as in an asynchronous FIFO.

[0029] In contrast to such comparative examples, a configuration is also conceivable in which the timing of VSY, HSY, and DA is synchronized by outputting image data DA in synchronization with the internally generated vertical synchronization signal VSY and horizontal synchronization signal HSY. However, this configuration has the problem that multiple lines of image data DA must be stored in the data buffer 540 before the data is read out. In this case, conversely, if the vertical synchronization signal VSY and horizontal synchronization signal HSY are generated in accordance with the image data DA output from the FIFO's data buffer 540, they can be output at the desired timing. However, there is a problem that VSY and HSY cannot be generated for frame lines that do not have image data DA.

[0030] In this embodiment, the vertical synchronization signal VSY, the horizontal synchronization signal HSY, the data enable signal DE, and the image data DA are written to the FIFO's data buffer 40. This makes it possible to output the vertical synchronization signal VSY, the horizontal synchronization signal HSY, and the data enable signal DE while maintaining the timing difference with the image data DA with simple processing. Furthermore, in order to properly reset the write address counter 20 and the read address counter 30 based on the vertical synchronization signal VSY, a configuration is adopted in which the vertical synchronization signal VSY, the horizontal synchronization signal HSY, the data enable signal DE, and the image data DA are delayed by the delay circuit 50 before being written to the data buffer 40.

[0031] In this embodiment, the data written to the FIFO's data buffer 40 includes the vertical synchronization signal VSY, the horizontal synchronization signal HSY, the data enable signal DE, and the image data DA, and writing is performed only during the active period, as explained in Figures 2 and 3. The vertical synchronization signal VSY is used to reset the write address counter 20, etc., and to ensure a stable reset, the write data DAW, delayed by the delay circuit 50, is written to the data buffer 40. In the case of a synchronous FIFO, both the write address ADW and the read address ADR are reset to their initial values ​​at the timing of the vertical synchronization signal VSY, and writing to the data buffer 40 begins after the reset. By delaying the data writing in this way, time is secured for the reset, enabling a stable reset.

[0032] On the other hand, in the case of an asynchronous FIFO, as described later, the write address counter 20 is not reset. Instead, at the timing of the vertical synchronization signal VSY, the write address ADW of the write address counter 20 is copied to the read address ADR of the read address counter 30, and after the copy, writing to the data buffer 40 begins. In this way, even if an abnormal condition occurs, such as a mismatch between the write address ADW and the read address ADR, the copy will align the read address ADR and the write address ADW to the same address, allowing the system to return to a normal state. For example, in an asynchronous FIFO, if the write address ADW is also reset, an inconsistency with the read address ADR will occur, leading to unexpected malfunctions. Therefore, the reset by copying is limited to the read address ADR only.

[0033] 2. Synchronous FIFO, Asynchronous FIFO Figure 6 shows an example configuration of the synchronous FIFO memory 10, and Figure 7 shows a signal waveform diagram illustrating its operation. In Figure 6, in addition to the configuration in Figure 4, pulse width setting circuits 18 and 19 and comparison circuits 70 and 71 are provided. Note that the configuration of the synchronous FIFO memory 10 is not limited to the configuration in Figure 6, and various modifications can be made, such as omitting some of these components or adding other components.

[0034] The pulse width setting circuits 18 and 19 are circuits that set the pulse widths of the vertical sync signal VSY and the horizontal sync signal HSY, respectively, to the pulse width specified by the write clock CKW. Then, when the vertical sync signal VSY, whose pulse width has been set in this way, is input to the reset terminal R, the write address counter 20 and the read address counter 30 are reset, and the write address ADW and read address ADR are reset.

[0035] The delay circuit 50 includes a flip-flop circuit 51 to which a write clock CKW is input at the clock terminal and a vertical sync signal VSY, a horizontal sync signal HSY, a data enable signal DE, and image data DA are input at the input terminal. Although the illustration in Figure 6 is simplified, the delay circuit 50 actually has 27 bits of flip-flop circuit 51. By providing a delay circuit 50 with such a flip-flop circuit 51, the vertical sync signal VSY, the horizontal sync signal HSY, the data enable signal DE, and the image data DA can be delayed by the delay time defined by the write clock CKW.

[0036] The write enable generation circuit 60 generates a write enable signal ENW by taking the logical OR of the vertical sync signal VSY, horizontal sync signal HSY, and data enable signal DE after the delay by the delay circuit 50 using an OR gate, and outputs it to the write address counter 20.

[0037] The write address counter 20 is reset by the vertical synchronization signal VSY, whose pulse width is set by the pulse width setting circuit 18, and its count value, write address ADW. Furthermore, when the write enable signal ENW becomes active, the write address counter 20 performs an update process that increments the write address ADW. The read address counter 30 is reset by the vertical synchronization signal VSY, whose pulse width is set by the pulse width setting circuit 18, and its count value, read address ADR. Furthermore, when the read enable signal ENR becomes active, the read address counter 30 performs an update process that increments the read address ADR.

[0038] The comparison circuit 70 compares the write address ADW and the read address ADR and outputs a full signal FUL when it determines that the data stored in the data buffer 40 is full. The comparison circuit 71 compares the write address ADW and the read address ADR and outputs an empty signal EMP when it determines that the data stored in the data buffer 40 is empty. The read enable signal ENR input to the read address counter 30 is generated, for example, based on this empty signal EMP.

[0039] Figure 8 is an explanatory diagram of the empty and full states of the FIFO's data buffer 40. In Figure 8, the write pointer WP is the pointer indicated by the write address ADW, and the read pointer RP is the pointer indicated by the read address ADR.

[0040] As shown in A1 of Figure 8, for example, when 27 bits of data for one address have been stored, and the read enable signal ENR becomes active and the read pointer RP corresponding to the read address ADR is updated, the data buffer 40 becomes empty as shown in A2. For example, from the state in A1, if the read address ADR is updated to match the write address ADW, it becomes empty. That is, the comparison circuit 71 in Figure 6 outputs an empty signal EMP.

[0041] For example, starting from the empty state shown in A3 of Figure 8, the write enable signal ENW updates the write pointer WP corresponding to the write address ADW. As shown in A4, when data equal to the buffer capacity of the data buffer 40 is written, the data buffer 40 becomes full. That is, the comparison circuit 70 in Figure 6 outputs a full signal FUL.

[0042] Next, the operation of the synchronous FIFO memory 10 will be explained using the signal waveform diagram in Figure 7. As shown in B1 of Figure 7, when the vertical synchronization signal VSY reaches the active level (high level), the write address ADW of the write address counter 20 and the read address ADR of the read address counter 30 are reset to 0. Also, as shown in B2, when the vertical synchronization signal VSY and the horizontal synchronization signal HSY reach high levels, the write enable signal ENW reaches high levels after a delay of one clock cycle of the write clock CKW by the delay circuit 50. Then, 27-bit write data DAW[26:0] with VSY=1, HSY=1, DE=0, DA=0000... is written to the data buffer 40 after a delay of the delay time by the delay circuit 50. Also, as shown in B3, the write address ADW is incremented from 0 to 1, and the data buffer 40 reaches the state shown in A1 of Figure 8. The increment, which is the update of the write address ADW, is performed, for example, at the timing of the next write clock CKW (pixel clock) after the write enable signal ENW reaches high levels.

[0043] When the write data DAW is written to the data buffer 40 in this way, the empty signal EMP becomes a low level, which is the inactive level, as shown in B4. Since the read enable signal ENR is the inverse of the empty signal EMP, the read enable signal ENR becomes a high level, which is the active level, as shown in B5. As a result, the read data DAR is read from the data buffer 40. Also, as shown in B6, the read address ADR is incremented from 0 to 1. When the read data DAR is read in this way, the data buffer 40 becomes empty, as shown in A2 of Figure 8, and the empty signal EMP changes from a low level to a high level.

[0044] As shown in Figure 7, the read enable signal ENR of the read address counter 30 is generated based on the empty signal EMP of the data buffer 40. That is, a read enable generation circuit (not shown) generates the read enable signal ENR based on the empty signal EMP and outputs it to the read address counter 30. In this way, the empty signal EMP can be effectively utilized to generate the read enable signal ENR with simple processing and circuitry. The generated read enable signal ENR then makes it possible to read the read data DAR from the data buffer 40.

[0045] Next, as shown in B7 and B8 of Figure 7, when the horizontal synchronization signal HSY goes high, the write enable signal ENW goes high after a delay of the delay time by the delay circuit 50, and the write data DAW[26:0] with VSY=0, HSY=1, DE=0, DA=0000... is written to the data buffer 40. Also, the write address ADW is incremented sequentially from 1 to 2, and from 2 to 3. Furthermore, when the empty signal EMP goes low, the read enable signal ENR goes high, and the read data DAR is read sequentially from the data buffer 40. Also, the read address ADR is incremented sequentially from 1 to 2, and from 2 to 3.

[0046] As shown in B9, when the data enable signal DE goes high and image data DA is input, the write enable signal ENW goes high after a delay of the delay time by the delay circuit 50, and write data DAW[26:0] with VSY=0, HSY=0, DE=1, DA=D23, D22, D21... is written to the data buffer 40. Also, the write address ADW is incremented from 3 to 4. Furthermore, when the empty signal EMP goes low, the read enable signal ENR goes high, and read data DAR is read from the data buffer 40. Also, the read address ADR is incremented from 3 to 4.

[0047] Then, as shown in B10, image data DA for one line is sequentially written to the data buffer 40 along with VSY, HSY, and DE until the horizontal synchronization signal HSY goes high. One line is one horizontal scan line. For high-definition, 1280 pixels of image data DA are written to the data buffer 40 as one line of image data; for full high-definition, 1920 pixels; and for 4K, 3840 pixels. For example, the buffer capacity (storage capacity) of the data buffer 40 is large enough to store one line of image data DA. Each time one pixel of image data DA is written to the data buffer 40 along with VSY, HSY, and DE, the write address ADW is incremented as shown in B11. Also, each time one pixel of image data DA is read from the data buffer 40 along with VSY, HSY, and DE, the read address ADR is incremented as shown in B12.

[0048] In this manner, the image data DA for each line is written, and when, for example, the image data DA for one frame is written, the vertical synchronization signal VSY becomes high level, and the write address ADW and read address ADR are reset to 0 as shown in B12. In this embodiment, by periodically resetting the write address ADW and read address ADR based on the vertical synchronization signal VSY, the FIFO memory 10 can return to a normal state even if it falls into an abnormal state due to noise or input signal disturbances.

[0049] In this embodiment, the vertical sync signal VSY, horizontal sync signal HSY, data enable signal DE, and image data DA are delayed by the delay circuit 50 and written to the data buffer 40 as write data DAW. By delaying the writing of the write data DAW in this way, time can be secured to reset the write address ADW and read address ADR based on the vertical sync signal VSY, making it possible to achieve a stable reset. For example, if the write address ADW and read address ADR are reset based on the vertical sync signal VSY without delaying the writing of the write data DAW, there is a risk of malfunctions occurring where the reset occurs at the timing of the write. In this embodiment, however, since the writing of the write data DAW is delayed by the delay circuit 50, it is possible to effectively prevent the occurrence of such malfunctions.

[0050] Figure 9 shows an example configuration of the asynchronous FIFO memory 10, and Figure 10 shows a signal waveform diagram illustrating its operation. In addition to the configuration in Figure 4, Figure 9 includes pulse width setting circuits 18 and 19, a reset generation circuit 31, comparison circuits 70 and 71, G2B conversion circuits 72, 73, 74, and 75, and flip-flop circuits 76, 77, 78, and 79. Note that the configuration of the asynchronous FIFO memory 10 is not limited to the configuration in Figure 9, and various modifications can be made, such as omitting some of these components or adding other components.

[0051] The delay circuit 50 receives a write clock CKW as input to the clock terminal and includes multiple cascaded flip-flop circuits 51, 52, 53, 54, 55, and 56. VSY, HSY, DE, and DA are input to the input terminal of the first-stage flip-flop circuit 51, and the final-stage flip-flop circuit 56 outputs write data DAW, which is VSY, HSY, DE, and DA delayed. Although the illustration in Figure 9 is simplified, in reality, each of the flip-flop circuits 51, 52, 53, 54, 55, and 56 is provided as a flip-flop circuit with 27 bits of data.

[0052] The reset generation circuit 31 also includes a toggle circuit 32, multiple cascaded multi-stage flip-flop circuits 33, 34, and 35, and an OR circuit 36. The toggle circuit 32 receives a vertical synchronization signal VSY, whose pulse width is set by the pulse width setting circuit 18, as input to its input terminal, and performs a toggle operation based on the write clock CKW, outputting a signal TG. The signal TG from the toggle circuit 32 is then input to the input terminal of the first stage flip-flop circuit 33 of the flip-flop circuits 33, 34, and 35, which have the read clock CKR input to their clock terminals. The signal TS from the second stage flip-flop circuit 34 and the signal TD from the final stage flip-flop circuit 35 are then input to the OR circuit 36, which outputs a reset signal RSAD. The reset signal RSAD is a signal that resets the read address ADR by copying the write address ADW to the read address ADR.

[0053] The G2B conversion circuit 72 is a circuit that converts Gray code to binary code. In the asynchronous FIFO memory 10 in Figure 9, Gray code counters are used as the write address counter 20 and read address counter 30, rather than binary counters. Gray code counters are used to prevent data corruption during asynchronous data transfer. While the address value of binary code changes by multiple bits during the counting process, the address value of Gray code changes by only one bit, thus preventing data corruption during asynchronous data transfer. For this reason, the write address counter 20 and read address counter 30 output the Gray code write address ADW and read address ADR, respectively. Since the address of the data buffer 40 needs to be a binary code address, the G2B conversion circuits 72 and 73 convert the Gray code write address ADW and read address ADR to the binary code write address ADW and read address ADR.

[0054] Furthermore, the Gray code read address ADR from the read address counter 30 is input to the clock terminal of the write clock CKW, and then to the input terminal of the first stage flip-flop circuit 76 of the cascaded flip-flop circuits 76 and 77. Since the read address ADR is in Gray code, data corruption can be prevented when the read address ADR from the read system is synchronized with the write clock CKW of the write system. The output of the second stage flip-flop circuit 77 is then input to the G2B conversion circuit 74, where the Gray code of the read address ADR synchronized with the write clock CKW is converted to binary code. The comparison circuit 70 then compares the binary code write address ADW from the G2B conversion circuit 72 with the binary code read address ADR from the G2B conversion circuit 74 to determine whether it is full or not, and outputs a full signal FUL.

[0055] Furthermore, the Gray code write address ADW from the write address counter 20 is input to the clock terminal of the read clock CKR, and then input to the input terminal of the first stage flip-flop circuit 78 of the cascaded flip-flop circuits 78 and 79. Since the write address ADW is in Gray code, data corruption can be prevented when the write address ADW from the write system is synchronized with the read clock CKR of the read system. The output of the second stage flip-flop circuit 79 is then input to the G2B conversion circuit 75, where the Gray code of the write address ADW synchronized with the read clock CKR is converted to binary code. The comparison circuit 71 then compares the binary code read address ADR from the G2B conversion circuit 73 with the binary code write address ADW from the G2B conversion circuit 75 to determine whether it is empty or not, and outputs an empty signal EMP.

[0056] Next, the operation of the asynchronous FIFO memory 10 will be explained using the signal waveform diagram in Figure 10. As shown in C1 of Figure 10, when the vertical synchronization signal VSY becomes high, the reset signal RSAD becomes high after a delay equal to the delay time of the synchronization process by the read clock CKR in the reset generation circuit 31. As a result, as shown in C2, the write address ADW of the write address counter 20 is copied to the read address ADR of the read address counter 30. In Figure 10, the write address ADW is 0, so the read address ADR becomes 0 due to the copy.

[0057] Furthermore, as shown in C3, when the vertical sync signal VSY and the horizontal sync signal HSY become high, the delay circuit 50 causes the write enable signal ENW to become high after a delay of multiple clock cycles of the write clock CKW, and the write data DAW[26:0] with VSY=1, HSY=1, DE=0, DA=0000... is written to the data buffer 40. Compared to the synchronous FIFO memory 10 in Figure 6, the asynchronous FIFO memory 10 in Figure 9 has a longer delay time in the delay circuit 50. Also, as shown in C4, the write address ADW is incremented from 0 to 1, and the data buffer 40 becomes the state shown in A1 of Figure 8.

[0058] When the write data DAW is written to the data buffer 40 in this way, the empty signal EMP goes to a low level as shown in C5. Since the read enable signal ENR is the inverse of the empty signal EMP, the read enable signal ENR goes to a high level as shown in C6. As a result, the read data DAR is read from the data buffer 40. Also, as shown in C7, the read address ADR is incremented from 0 to 1. When the read data DAR is read in this way, the data buffer 40 becomes empty as shown in A2 of Figure 8, and the empty signal EMP changes from a low level to a high level.

[0059] As shown in Figure 10, similar to Figure 7, the read enable signal ENR of the read address counter 30 is generated based on the empty signal EMP of the data buffer 40. This allows for the effective use of the empty signal EMP to generate the read enable signal ENR with simple processing and circuitry.

[0060] Next, as shown in C8 and C9, when the horizontal synchronization signal HSY goes high, the write enable signal ENW goes high after a delay of the delay time by the delay circuit 50, and the write data DAW[26:0] with VSY=0, HSY=1, DE=0, DA=0000... is written to the data buffer 40. Also, the write address ADW is incremented sequentially from 1 to 2, and from 2 to 3. Furthermore, when the empty signal EMP goes low, the read enable signal ENR goes high, and the read data DAR is read sequentially from the data buffer 40. Also, the read address ADR is incremented sequentially from 1 to 2, and from 2 to 3.

[0061] As shown in C10, when the data enable signal DE goes high and image data DA is input, the write enable signal ENW goes high after a delay of the delay time by the delay circuit 50, and write data DAW[26:0] with VSY=0, HSY=0, DE=1, DA=D23, D22, D21... is written to the data buffer 40. Also, the write address ADW is incremented from 3 to 4. Furthermore, when the empty signal EMP goes low, the read enable signal ENR goes high, and read data DAR is read from the data buffer 40. Also, the read address ADR is incremented from 3 to 4.

[0062] Then, as shown in C11, one line of image data DA is sequentially written to the data buffer 40 along with VSY, HSY, and DE until the horizontal synchronization signal HSY goes high. Each time one pixel of image data DA is written to the data buffer 40 along with VSY, HSY, and DE, the write address ADW is incremented as shown in C12. Also, each time one pixel of image data DA is read from the data buffer 40 along with VSY, HSY, and DE, the read address ADR is incremented as shown in C13.

[0063] In this way, the image data DA for each line is written, and when, for example, the image data DA for one screen is written, the vertical synchronization signal VSY becomes high level, a high-level pulsed reset signal RSAD is generated as shown in C14, and the write address ADW is copied to the read address ADR as shown in C15. By performing a reset that periodically copies the write address ADW to the read address ADR based on the vertical synchronization signal VSY, the FIFO memory 10 can return to a normal state even if it falls into an abnormal state due to noise or input signal disturbances.

[0064] Figure 11 is a signal waveform diagram illustrating the detailed operation of the asynchronous FIFO memory 10. As shown in D1 of Figure 11, when the vertical synchronization signal VSY becomes high, the toggle circuit 32 in Figure 9 toggles the signal TG from low to high, as shown in D2, based on the write clock CKW. This signal TG is input to the first stage flip-flop circuit 33 of the flip-flop circuits 33, 34, and 35, which operate based on the read clock CKR. The signal TM output by flip-flop circuit 33 is input to the next stage flip-flop circuit 34, and the signal TS output by flip-flop circuit 34 is input to the next stage flip-flop circuit 35. Then, as shown in D3 of Figure 11, the OR circuit 36 ​​receives the signal TS from flip-flop circuit 34 and the signal TD from flip-flop circuit 35, and outputs a high-level pulse signal, the reset signal RSAD, to the read address counter 30. This reset signal RSAD copies the write address ADW of the write address counter 20 to the read address ADR of the read address counter 30.

[0065] Furthermore, when the vertical sync signal VSY and the horizontal sync signal HSY reach high levels, as shown in D5, the delay circuit 50 causes the write enable signal ENW to reach high levels after a delay of multiple clock cycles of the write clock CKW, and VSY=1, HSY=1, DE=0, and DA are written to the data buffer 40.

[0066] Figure 12 is also a signal waveform diagram illustrating the detailed operation of the asynchronous FIFO memory 10. In Figure 12, as shown in E1, when the vertical synchronization signal VSY becomes high, the toggle circuit 32 toggles the signal TG from high to low, as shown in E2. Then, signals TM, TS, and TD change as shown in E3, and a high-level pulse signal, the reset signal RSAD, is generated as shown in E4. As a result, as shown in E5, the write address ADW is copied to the read address ADR, and the read address ADR is set to 21, the same as the write address ADW. That is, in Figure 11, the write address ADW=0 was copied to the read address ADR, but in Figure 12, the write address ADW=21 is copied to the read address ADR. The write address ADW that is copied in this way is not limited to 0; for example, the write address ADW when the vertical synchronization signal VSY becomes high is copied to the read address ADR.

[0067] In the synchronous FIFO memory 10, as explained in Figures 6 and 7, the write address ADW and read address ADR were reset based on the vertical synchronization signal VSY. In contrast, in the asynchronous FIFO memory 10, as explained in Figures 9 to 12, the write address ADW was copied to the read address ADR based on the vertical synchronization signal VSY, for the following reasons.

[0068] For example, Figure 13 shows the signal waveform when the write address ADW and read address ADR are reset based on the vertical synchronization signal VSY in an asynchronous FIFO memory 10. For example, in F1 of Figure 13, the write address ADW is reset to 0 based on the vertical synchronization signal VSY. This write address ADW=0 is then delayed by synchronization by the read clock CKR in the flip-flop circuits 78 and 79, as shown in ADWM=0 and ADWS=0 in F2, and input to the comparison circuit 71, where it is compared with the read address ADR to determine if it is empty.

[0069] On the other hand, the vertical synchronization signal VSY is delayed by synchronization with the read clock CKR in the flip-flop circuits 33, 34, and 35 as shown in F3, and the reset signal RSAD is generated by the OR circuit 36 ​​as shown in F4. Consequently, when the comparison is performed by the comparison circuit 71, the read address ADR=21 overtakes the write address ADWS=0, resulting in a malfunction where proper determination cannot be made.

[0070] In this embodiment, as explained in Figures 10 to 12, a method is employed to copy the write address ADW to the read address ADR based on the vertical synchronization signal VSY. Therefore, while preventing the occurrence of malfunctions as explained in Figure 13, even if the FIFO memory 10 falls into an abnormal state due to noise or input signal disturbances, it can be restored to a normal state.

[0071] In this embodiment, the delay time from when the vertical synchronization signal VSY becomes active until the write enable signal ENW of the write address counter 20 becomes active is longer than the delay time from when the vertical synchronization signal VSY becomes active until the write address ADW is copied to the read address ADR. For example, in Figure 10, after the write address ADW is copied to the read address ADR based on the vertical synchronization signal VSY as shown in C2, the write enable signal ENW becomes high level and active as shown in C3. This is achieved, for example, in Figure 9, by providing the delay circuit 50 with more flip-flop circuits 51, 52, 53, 54, 55, and 56 than the flip-flop circuits 33, 34, and 35 of the reset generation circuit 31. That is, the delay time of the delay circuit 50 is set so that the read enable signal ENR becomes active after the write address ADW is copied to the read address ADR. In this way, the write enable signal ENW becomes active after the write address ADW is copied to the read address ADR. Therefore, after the write address ADW and read address ADR are set to the same address value through copying, the addresses of the write address ADW and read address ADR can be updated appropriately.

[0072] As described above, the FIFO memory 10 of this embodiment, which stores and outputs image data, includes a write address counter 20 that generates a write address ADW, a read address counter 30 that generates a read address ADR, and a data buffer 40. As shown in Figures 1, 2, and 3, the data buffer 40 stores the vertical synchronization signal VSY, the horizontal synchronization signal HSY, the data enable signal DE, and the image data DA based on the write address ADW. The data buffer 40 also outputs the stored vertical synchronization signal VSY, horizontal synchronization signal HSY, data enable signal DE, and image data DA based on the read address ADR.

[0073] In this embodiment, not only the image data DA, but also the vertical synchronization signal VSY, the horizontal synchronization signal HSY, and the data enable signal DE are written to the FIFO's data buffer 40. This makes it possible to realize a FIFO memory 10 that can transfer the vertical synchronization signal VSY, the horizontal synchronization signal HSY, the data enable signal DE, and the image data DA input from the write side to the read side while maintaining the timing difference.

[0074] Furthermore, as shown in Figures 4, 6, and 9, the FIFO memory 10 of this embodiment includes a delay circuit 50 that delays the vertical synchronization signal VSY, the horizontal synchronization signal HSY, the data enable signal DE, and the image data DA before outputting them to the data buffer 40.

[0075] In this way, when resetting the write address ADW or read address ADR, the writing of the vertical sync signal VSY, horizontal sync signal HSY, data enable signal DE, and image data DA to the data buffer 40 is delayed, thereby ensuring sufficient time for the reset and enabling a stable reset. The reset referred to here includes not only resetting the write address ADW or read address ADR to an initial value such as 0, but also resets such as copying the write address ADW to the read address ADR.

[0076] Furthermore, as shown in Figures 4, 6, and 9, this embodiment includes a write enable generation circuit 60 that activates a write enable signal ENW to the write address counter 20 when at least one of the vertical sync signal VSY, the horizontal sync signal HSY, and the data enable signal DE is active.

[0077] In this way, data is written to the data buffer 40 during the active period when at least one of the vertical sync signal VSY, the horizontal sync signal HSY, and the data enable signal DE is active. Therefore, unnecessary operation of the FIFO memory 10 during the inactive period can be eliminated, resulting in lower power consumption and saving buffer capacity of the data buffer 40.

[0078] Furthermore, in Figures 6 and 7, B1, the write address ADW of the write address counter 20 and the read address ADR of the read address counter 30 are reset based on the vertical synchronization signal VSY. For example, a signal based on the vertical synchronization signal VSY is input to the reset terminals of the write address counter 20 and the read address counter 30, and the write address ADW and read address ADR are reset.

[0079] In this way, the write address ADW and read address ADR can be periodically reset using the vertical synchronization signal VSY, and even if the FIFO memory 10 enters an abnormal state, it can be restored to a normal state by resetting.

[0080] Furthermore, in Figures 9 and 10, at C2 and C15, the write address ADW of the write address counter 20 is copied to the read address ADR of the read address counter 30 based on the vertical synchronization signal VSY. For example, when the reset signal RSAD, which is a signal based on the vertical synchronization signal VSY, becomes active, the write address ADW is copied to the read address ADR, and the write address ADW and the read address ADR have the same address value.

[0081] In this way, the write address ADW can be periodically copied to the read address ADR using the vertical synchronization signal VSY, and even if the FIFO memory 10 falls into an abnormal state, it can be restored to a normal state.

[0082] Furthermore, as shown in C2 and C3 of Figure 10, the delay time from when the vertical synchronization signal VSY becomes active until the write address ADW is copied to the read address ADR is shorter than the delay time from when the vertical synchronization signal VSY becomes active until the write enable signal ENW of the write address counter 20 becomes active.

[0083] In this way, after the write address ADW is copied to the read address ADR, the write enable signal ENW becomes active, allowing for proper address updates of the write address ADW and read address ADR after the copy.

[0084] Furthermore, in Figures 7B4 and 7B5, and Figures 10C5 and 10C6, the read enable signal ENR of the read address counter 30 is generated based on the empty signal EMP of the data buffer 40. As an example, the inverted signal of the empty signal EMP is used as the read enable signal ENR.

[0085] In this way, the empty signal EMP can be effectively utilized to generate a read enable signal ENR with simple processing and circuitry, and the generated read enable signal ENR makes it possible to read data from the data buffer 40.

[0086] 3. Clock frequencies of the write clock and read clock. As shown in Figure 14, in the asynchronous FIFO memory 10, VSY, HSY, DE, and DA are passed between the write system, which uses the write clock CKW, and the read system, which uses the read clock CKR. Figure 15 shows the signal waveform when the clock frequencies of the write clock CKW and the read clock CKR are approximately the same. For the sake of simplicity, address reset delays and write data delays will be omitted from the explanation below.

[0087] In Figure 15, the clock frequencies of the write clock CKW and the read clock CKR are almost the same, and the VSYI, HSYI, DEI, and DAI signals on the write side are passed to the read side as VSYQ, HSYQ, DEQ, and DAQ. Then, in Figure 15, as shown in G1, when the write enable signal ENW becomes active and data (VSYI, HSYI, DEI, DAI) is written to the data buffer 40, as shown in G2, the read enable signal ENR immediately becomes active and data (VSYQ, HSYQ, DEQ, DAQ) is read from the data buffer 40. For example, as explained in Figure 10, this type of read control can be achieved by setting the read enable signal ENR to the inverted signal of the empty signal EMP.

[0088] On the other hand, Figure 16 shows the signal waveform when the clock frequency of the read clock CKR is higher than the clock frequency of the write clock CKW. In asynchronous FIFO memory 10, the read clock CKR often has a higher clock frequency. When the clock frequency of the read clock CKR is higher in this way, for example, in a method that generates a read enable signal based on an empty signal, it becomes impossible to continuously read image data from the data buffer 40. For example, even if image data is written to the data buffer 40, the data is immediately read out of the data buffer 40 and it becomes empty, making it difficult to continuously read image data of multiple pixels based on the read clock CKR.

[0089] Therefore, in Figure 16, after the write enable signal ENW is activated, one line of image data is written to the data buffer 40 as shown in H1. One line of image data is, for example, 1280 pixels for high-definition, 1920 pixels for full high-definition, and 3840 pixels for 4K. After one line of image data is written to the data buffer 40, the read enable signal ENR is activated as shown in H2, and one line of image data is read continuously based on the read clock CKR. For example, after writing the image data to the data buffer 40, the read address ADR is sequentially incremented to read the image data written to the data buffer 40. Here, it is not necessary to write until the data buffer 40 is full. In this way, even if the clock frequency of the read clock CKR is higher than the clock frequency of the write clock CKW, it is possible to read image data of multiple pixels continuously.

[0090] In Figure 16, the read enable signal ENR of the read address counter 30 is generated based on the write enable signal ENW of the write address counter 20. For example, in Figures 7 (B4, B5) and 10 (C5, C6), the read enable signal ENR was generated based on the empty signal EMP, but in Figure 16, as shown in H3, the read enable signal ENR is generated based on the write enable signal ENW. For example, when the write enable signal ENW changes from active to inactive, the read enable signal ENR is activated.

[0091] In this way, after the write enable signal ENW is activated and data is written to the data buffer 40, the read enable signal ENR is activated, making it possible to read data from the data buffer 40.

[0092] Specifically, as shown in H1 of Figure 16, the write enable signal ENW becomes active for a predetermined period TP after the horizontal synchronization signal becomes active. The predetermined period TP is, for example, a period corresponding to multiple clock cycles of the write clock CKW. Specifically, the predetermined period TP is the period for writing one line of image data. Then, as shown in H2 and H3 of Figure 16, after the predetermined period TP has elapsed and the write enable signal ENW has gone from active to inactive, the read enable signal ENR becomes active.

[0093] In this way, the write enable signal ENW becomes active, data is written to the data buffer 40, and after a predetermined period has elapsed and data writing is complete, the read enable signal ENR becomes active, and data is read from the data buffer 40. This makes it possible, for example, when the clock frequency of the read clock CKR is higher than the clock frequency of the write clock CKW, to continuously read out image data of multiple pixels written to the data buffer 40 during a predetermined period while the read enable signal ENR is active.

[0094] Although Figure 16 does not show the case where the write enable signal ENW is delayed, in this case, after copying the write address ADW to the read address ADR, the write enable signal ENW should be activated and the write address ADW should be incremented. Then, after one line of image data has been written to the data buffer 40, the read enable signal ENR should be activated and the read address ADR should be incremented.

[0095] 4.Circuit device Next, a circuit device 2 including the FIFO memory 10 of this embodiment will be described. Figure 17 shows an example of the configuration of the circuit device 2 of this embodiment. In Figure 17, the FIFO memory 10 of this embodiment is provided with FIFO memory 10A and FIFO memory 10B. FIFO memories 10A and 10B are, for example, asynchronous FIFO memories, with FIFO memory 10A being a FIFO memory for the first channel and FIFO memory 10B being a FIFO memory for the second channel. A FIFO memory 12 is also provided downstream of FIFO memories 10A and 10B. FIFO memory 12 is, for example, a synchronous FIFO memory. A multiplexer 14 is also provided downstream of FIFO memory 12.

[0096] The configuration of the circuit device 2 in this embodiment is not limited to the configuration shown in Figure 17, and various modifications can be made, such as omitting some of these components or adding other components. For example, in Figure 17, two FIFO memories 10A and 10B are provided for the first channel and the second channel, but only one FIFO memory 10 for one channel may be provided. Also, in Figure 17, a FIFO memory 12 and a multiplexer 14 are provided after the FIFO memories 10A and 10B, but a configuration without these FIFO memories 12 and multiplexer 14 may also be used.

[0097] Furthermore, if a FIFO memory 10 (10A, 10B) is provided in the circuit device 2 of this embodiment, the FIFO memory 10 can be provided, for example, in the input interface circuit or output interface circuit of the circuit device 2. When provided in the input interface circuit, the FIFO memory 10 becomes a circuit that passes VSY, HSY, DE, DA from outside the circuit device 2 to the internal circuit of the circuit device 2. When provided in the output interface circuit, the FIFO memory 10 becomes a circuit that passes VSY, HSY, DE, DA from the internal circuit of the circuit device 2 to the outside of the circuit device 2.

[0098] Furthermore, circuit device 2 is an integrated circuit device, such as an IC (Integrated Circuit). For example, circuit device 2 is an IC manufactured by a semiconductor process, and is a semiconductor chip in which circuit elements are formed on a semiconductor substrate. In addition to the components shown in Figure 17, circuit device 2 may also include processing circuits that perform control processing and calculation processing, and memory circuits that store information. If circuit device 2 is a display controller, it may also include image processing circuits that perform image processing based on image data.

[0099] In Figure 17, FIFO memory 10A buffers the input VSYI1, HSYI1, DEI1, and DAI1 of the first channel in its data buffer and outputs them to the subsequent FIFO memory 12. FIFO memory 10B buffers the input VSYI2, HSYI2, DEI2, and DAI2 of the second channel in its data buffer and outputs them to the subsequent FIFO memory 12.

[0100] The asynchronous FIFO memories 10A and 10B are FIFO memories for asynchronous data transfer and absorbing inter-channel delays, and are the asynchronous FIFO memories described in Figure 9. That is, as shown in C5 and C6 in Figure 10, a read-enable signal is generated based on the empty signal. Therefore, when data is written to the data buffer, the read-enable signal becomes active, and the data is immediately read from the data buffer. For this reason, it is possible to implement this with a data buffer with a small buffer capacity.

[0101] The synchronous FIFO memory 12 is a type of FIFO memory in which only image data is written to the data buffer, while the vertical synchronization signal, horizontal synchronization signal, and data enable signal are not written to the data buffer. When one line of image data is written to the FIFO memory 12, it outputs the written image data line continuously.

[0102] Figure 18 is a signal waveform diagram illustrating the operation of the circuit device 2 in Figure 17. In the asynchronous FIFO memories 10A and 10B, lines without data are also written as dummy data, as shown in J1 in Figure 18. The read enable signal shown in J2 is generated by the empty signal, and as soon as data is written to the data buffer, the data is read out from the data buffer. As shown in J3, for example, when 1 line + 1 data is sent from the asynchronous FIFO memories 10A and 10B to the synchronous FIFO memory 12, the vertical synchronization signal VSYQ1 / 2 and the horizontal synchronization signal HSYQ1 / 2 are output.

[0103] Then, as shown in J4, data is written to the data buffers of FIFO memories 10A and 10B, and as shown in J5, the written data is sent from FIFO memories 10A and 10B to FIFO memory 12. Then, as shown in J6, one line of data that has been sent is written to the data buffer of FIFO memory 12. Here in Figure 18, VSYR1 / 2, HSYR1 / 2, DER1 / 2, and DAR1 / 2 represent the vertical synchronization signal, horizontal synchronization signal, data enable signal, and image data sent from FIFO memories 10A and 10B to FIFO memory 12.

[0104] As shown in J7, in the case of an active line, after the horizontal synchronization signal HSYQ1 / 2, image data for one line, which has been written to the data buffer of the FIFO memory 12, is output. No image data is output for inactive lines where dummy data is written.

[0105] As described above, the circuit device 2 of this embodiment includes asynchronous FIFO memories 10A and 10B, and a synchronous FIFO memory 12 that stores image data from the FIFO memories 10A and 10B, as shown in Figure 17. The FIFO memory 12 is a second FIFO memory. Here, Figure 17 shows two asynchronous FIFO memories 10A and 10B, but a configuration with only one asynchronous FIFO memory is also possible.

[0106] With this configuration, the circuit device 2 enables asynchronous data transfer using the asynchronous FIFO memories 10A and 10B. The data received from the FIFO memories 10A and 10B is stored in the data buffer of the synchronous FIFO memory 12, and the stored data can be output from the FIFO memory 12. For example, it becomes possible to store one line of data from the asynchronous FIFO memories 10A and 10B in the data buffer of the synchronous FIFO memory 12, and then continuously output the stored one line of data from the synchronous FIFO memory 12.

[0107] As described above, the FIFO memory of this embodiment, which stores and outputs image data, includes a write address counter that generates a write address and a read address counter that generates a read address. The FIFO memory also includes a data buffer that stores a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and image data based on the write address, and outputs the stored vertical synchronization signal, horizontal synchronization signal, data enable signal, and image data based on the read address.

[0108] According to this embodiment, not only image data but also vertical synchronization signals, horizontal synchronization signals, and data enable signals are written to the FIFO's data buffer. This makes it possible to realize a FIFO memory that can transfer input vertical synchronization signals, horizontal synchronization signals, data enable signals, and image data while maintaining the timing difference.

[0109] Furthermore, this embodiment may include a delay circuit that delays the vertical synchronization signal, horizontal synchronization signal, data enable signal, and image data before outputting them to the data buffer.

[0110] In this way, when resetting the write address or read address, the vertical synchronization signal, horizontal synchronization signal, data enable signal, and image data writing are delayed, allowing for a stable reset.

[0111] Furthermore, in this embodiment, a write enable generation circuit may be included that activates a write enable signal to the write address counter when at least one of the vertical sync signal, horizontal sync signal, and data enable signal is active.

[0112] In this way, data writing occurs during the active period when at least one of the vertical synchronization signal, horizontal synchronization signal, and data enable signal is active, thus eliminating unnecessary operation of the FIFO memory during the inactive period.

[0113] In this embodiment, the write address of the write address counter and the read address of the read address counter may be reset based on the vertical synchronization signal.

[0114] This allows the write and read addresses to be periodically reset using the vertical synchronization signal.

[0115] In this embodiment, the write address of the write address counter may be copied to the read address of the read address counter based on the vertical synchronization signal.

[0116] In this way, the write address can be periodically copied to the read address using the vertical synchronization signal.

[0117] Furthermore, in this embodiment, the delay time from when the vertical synchronization signal becomes active until the write enable signal of the write address counter becomes active may be longer than the delay time from when the vertical synchronization signal becomes active until the write address is copied to the read address.

[0118] This way, the write enable signal becomes active after the write address has been copied to the read address.

[0119] In this embodiment, the read-enable signal of the read address counter may also be generated based on the empty signal of the data buffer.

[0120] This method allows us to effectively utilize empty signals and generate read-enable signals with simple processing and circuits.

[0121] In this embodiment, the read enable signal for the read address counter may be generated based on the write enable signal for the write address counter.

[0122] In this way, the write enable signal becomes active, data is written to the data buffer, and then the read enable signal is activated to read data from the data buffer.

[0123] In this embodiment, the write enable signal may remain active for a predetermined period after the horizontal synchronization signal becomes active, and after the predetermined period has elapsed and the write enable signal has gone from active to inactive, the read enable signal may become active.

[0124] In this way, the write enable signal becomes active, data is written to the data buffer, and after a predetermined period has elapsed and data writing is complete, the read enable signal becomes active, and data is read from the data buffer.

[0125] Furthermore, the circuit device of this embodiment relates to a circuit device that includes the asynchronous FIFO memory described above and a synchronous second FIFO memory for storing image data from the FIFO memory.

[0126] According to this configuration, the asynchronous FIFO memory enables asynchronous data transfer, and the data transferred from the asynchronous FIFO memory can be stored in the data buffer of the synchronous second FIFO memory and output.

[0127] Although this embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novelty and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, any term that appears at least once in the specification or drawings together with a broader or synonymous term may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. In addition, the FIFO memory, the configuration and operation of the circuit device, etc., are not limited to those described in this embodiment, and various modifications are possible. [Explanation of symbols]

[0128] 2...Circuit device, 10, 10A, 10B, 12...FIFO memory, 14...Multiplexer, 18, 19...Pulse width setting circuit, 20...Write address counter, 30...Read address counter, 31...Reset generation circuit, 32...Toggle circuit, 33, 34, 35...Flip-flop circuit, 36...OR circuit, 40...Data buffer, 50...Delay circuit, 51, 52, 53, 54, 55, 56...Flip-flop circuit, 60...Write enable generation circuit, 70, 71...Comparer circuit, 72, 73, 74, 75...Conversion circuit, 76, 77, 78, 79...Flip-flop Circuit, 510...FIFO memory, 520...Write address counter, 530...Read address counter, 540...Data buffer, ADR...Read address, ADW...Write address, CKR...Read clock, CKW...Write clock, DA...Image data, DAR...Read data, DAW...Write data, DE...Data enable signal, EMP...Empty signal, ENR...Read enable signal, ENW...Write enable signal, FUL...Full signal, HSY...Horizontal sync signal, RSAD...Reset signal, TP...Determined period, VSY...Vertical sync signal

Claims

1. A FIFO memory that stores and outputs image data, A write address counter that generates write addresses, A read address counter that generates read addresses, A data buffer that stores the vertical synchronization signal, the horizontal synchronization signal, the data enable signal, and the image data based on the write address, and outputs the stored vertical synchronization signal, the horizontal synchronization signal, the data enable signal, and the image data based on the read address, A FIFO memory characterized by including [a specific element].

2. In the FIFO memory described in claim 1, A FIFO memory characterized by including a delay circuit that delays the vertical synchronization signal, the horizontal synchronization signal, the data enable signal, and the image data and outputs them to the data buffer.

3. In the FIFO memory described in claim 1, A FIFO memory characterized by including a write enable generation circuit that activates a write enable signal to the write address counter when at least one of the vertical sync signal, the horizontal sync signal, and the data enable signal is active.

4. In the FIFO memory described in any one of claims 1 to 3, A FIFO memory characterized in that the write address of the write address counter and the read address of the read address counter are reset based on the vertical synchronization signal.

5. In the FIFO memory described in any one of claims 1 to 3, A FIFO memory characterized in that the write address of the write address counter is copied to the read address of the read address counter based on the vertical synchronization signal.

6. In the FIFO memory described in claim 5, A FIFO memory characterized in that the delay time from when the vertical synchronization signal becomes active until the write address is copied to the read address is longer than the delay time from when the vertical synchronization signal becomes active until the write enable signal of the write address counter becomes active.

7. In the FIFO memory described in any one of claims 1 to 3, A FIFO memory characterized in that the read enable signal of the read address counter is generated based on the empty signal of the data buffer.

8. In the FIFO memory described in any one of claims 1 to 3, A FIFO memory characterized in that the read enable signal of the read address counter is generated based on the write enable signal of the write address counter.

9. In the FIFO memory described in claim 8, The aforementioned light enable signal becomes active for a predetermined period of time after the aforementioned horizontal synchronization signal becomes active. A FIFO memory characterized in that, after the predetermined period has elapsed and the write enable signal changes from active to inactive, the read enable signal becomes active.

10. an asynchronous FIFO memory as described in any one of claims 1 to 3, A synchronous second FIFO memory that stores the image data from the aforementioned FIFO memory, A circuit device characterized by including the following.

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