Data processing device, program, and data processing method

Abstract

This software performs high-speed solution searching for combinatorial optimization problems. [Solution] Based on evaluation function information 11a relating to the evaluation function of a combinatorial optimization problem including multiple sets of state variables, the processing unit 12 performs a first process for each trial in which it changes the value of any of the state variables included in the multiple sets of state variables. This first process is performed using a first probability (ρ) calculated with a first number of parallel processes corresponding to the number of sets of state variables. The processing unit 12 also performs a second process based on the evaluation function information 11a in which it selects one second state variable for each trial and determines in parallel for each of the multiple sets of state variables whether or not its value can be changed. This second process is performed using a second probability (1-ρ). Furthermore, the processing unit 12 updates the value of the first state variable selected from the candidates determined by the first process and updates the value of the second state variable whose value change is permitted by the second process.

Description

[Technical Field]

[0001] The present invention relates to a data processing device, a program, and a data processing method. [Background technology]

[0002] One method for finding solutions to combinatorial optimization problems is the Markov-Chain Monte Carlo (MCMC) method. In the serial trial-based solution search of the MCMC method, one state variable of the evaluation function of the combinatorial optimization problem is selected for each trial, and changes in the value of that state variable (state transitions) are accepted with acceptance probabilities defined by the Metropolis method or the Gibbs method.

[0003] Furthermore, if state transitions are continuously rejected in each trial of the MCMC method, the state will remain unchanged for a long period of time. To prevent this, a method has been proposed to generate a sequence of samples that transition to a different state in each trial (see, for example, Patent Documents 1 and 2). Such a method is called a rejection-free method (hereinafter sometimes abbreviated as the RF method). [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-174616 [Patent Document 2] Japanese Patent Publication No. 2023-149806 [Overview of the project] [Problems that the invention aims to solve]

[0005] In RF method solution search, when the acceptance probability in MCMC method serial trial search is small, the search is faster than serial trial search. Conversely, when the acceptance probability is high, MCMC method serial trial search is advantageous because it requires less computation per trial than RF method solution search.

[0006] In one aspect, the present invention aims to provide a data processing device, a program, and a data processing method that can perform high-speed solution searching for combinatorial optimization problems. [Means for solving the problem]

[0007] In one embodiment, a data processing device is provided, which includes: a storage unit that stores evaluation function information relating to an evaluation function for a combinatorial optimization problem including a group of multiple state variables; and a processing unit that, when performing multiple trials to change the value of any of the state variables included in the group of multiple state variables based on the evaluation function information, performs a first process for each trial to determine a candidate for a first state variable whose value is to be changed in parallel for each of the group of multiple state variables, using a first probability calculated using a first parallel number corresponding to the number of the group of multiple state variables; performs a second process for each trial to select one second state variable based on the evaluation function information and determine in parallel for each of the group of multiple state variables whether or not its value can be changed, using a second probability obtained by subtracting the first probability from 1; updates the value of the first state variable selected from the candidates determined by the first process; and updates the value of the second state variable whose value change is permitted by the second process.

[0008] In one embodiment, a program is provided. In one embodiment, a data processing method is provided. [Effects of the Invention]

[0009] In one aspect, the present invention enables high-speed solution searching for combinatorial optimization problems. [Brief explanation of the drawing]

[0010] [Figure 1] This figure shows an example of a data processing device according to the first embodiment. [Figure 2] This figure shows the relationship between the computational complexity of solution search using serial trials in the MCMC method and the RF method, and the escape probability. [Figure 3]This figure shows an example of a data processing device according to the second embodiment. [Figure 4] This figure shows an example of the overall control circuit and arithmetic processing circuit. [Figure 5] This is a diagram showing an example of an update circuit. [Figure 6] This figure shows an example of how metropolis selection works. [Figure 7] This timing chart shows an example of the operation timing of data processing equipment during solution search. [Figure 8] This is a flowchart showing an example of the processing procedure of the data processing device according to the second embodiment. [Figure 9] This flowchart shows an example of a processing procedure for selecting a state variable whose value changes. [Figure 10] This flowchart shows an example of the update control processing procedure. [Figure 11] A flowchart illustrating an example of the processing procedure for an arithmetic processing circuit. [Figure 12] This figure shows an example of a data processing device according to the third embodiment. [Figure 13] This figure shows an example of an update circuit for a data processing device according to the third embodiment. [Figure 14] This is a flowchart showing an example of the processing procedure of the data processing device according to the fourth embodiment. [Figure 15] This flowchart shows an example of the update control processing procedure in the fifth embodiment. [Figure 16] This figure shows an example of a data processing device according to the sixth embodiment. [Figure 17] This figure shows an example of a primary selection circuit included in the arithmetic processing circuit according to the sixth embodiment. [Figure 18] This figure shows an example of an update circuit included in the arithmetic processing circuit according to the sixth embodiment. [Figure 19] This is a schematic diagram illustrating an example of using integer variables. [Figure 20] This figure shows an example of data processing device hardware. [Modes for carrying out the invention]

[0011] The embodiments for carrying out the invention will be described below with reference to the drawings. [First Embodiment] Figure 1 shows an example of a data processing device according to the first embodiment.

[0012] The data processing device 10 performs a search for a solution to a combinatorial optimization problem. The data processing device 10 may be a client device or a server device. The data processing device 10 may also be called a computer.

[0013] The data processing device 10 of the first embodiment includes a storage unit 11 and a processing unit 12. The storage unit 11 may include volatile semiconductor memory such as RAM (Random Access Memory), or it may include non-volatile storage such as HDD (Hard Disk Drive) or flash memory. Furthermore, the storage unit 11 may include both volatile semiconductor memory and non-volatile storage.

[0014] The memory unit 11 stores evaluation function information 11a relating to an evaluation function for a combinatorial optimization problem that includes a set of multiple state variables. The combinatorial optimization problem is converted into, for example, an Ising-type evaluation function. The evaluation function is sometimes called an objective function or energy function. The evaluation function includes multiple state variables and multiple weight coefficients. In an Ising-type evaluation function, the state variables are binary variables that take values ​​of 0 or 1. The state variables may also be expressed as bits. The solution to the combinatorial optimization problem is represented by the values ​​of the multiple state variables. The solution that minimizes the value of the evaluation function corresponds to the optimal solution of the combinatorial optimization problem. Hereinafter, the value of the evaluation function will be called energy.

[0015] The Ising-type evaluation function can be expressed by equation (1).

[0016]

number

[0017] The state vector x represents the state of the Ising model, with multiple state variables as its elements. Equation (1) is the evaluation function formulated in the form of QUBO (Quadratic Unconstrained Binary Optimization). Note that for the problem of maximizing energy, the sign of the evaluation function should be reversed.

[0018] The first term on the right-hand side of equation (1) is the product of the values ​​of the two state variables and the weight coefficients for all possible combinations of two state variables that can be selected from all state variables, without any omissions or overlaps. The subscripts i and j are the indices of the state variables. i x is the i-th state variable. j is the j-th state variable. Hereafter, we will assume that there are n state variables. ij This is a weight coefficient that indicates the weight between the i-th state variable and the j-th state variable, or the strength of the bond. ij =W ji And W ii = 0. When the number of state variables is n, W ij The number of items is n × n.

[0019] The second term on the right-hand side of equation (1) is the sum of the products of each state variable's bias and the value of that state variable. i This indicates the bias for the i-th state variable. The evaluation function information 11a stored in the memory unit 11 includes weight coefficients and biases included in the evaluation function as described above.

[0020] Multiple state variable groups are, for example, obtained by randomly or deterministically dividing the multiple state variables included in the evaluation function into multiple groups. Each of these multiple state variable groups may be a group of state variables from the N state variables included in the evaluation function that have a 1-hot constraint. A group of state variables with a 1-hot constraint is a group of state variables that has the constraint that only one state variable has a value of 1, and the values ​​of the other state variables are 0. An example of using a group of state variables with a 1-hot constraint will be explained in the sixth embodiment.

[0021] The memory unit 11 may also store the calculation conditions for the solution search. For solution searches using the RF method and serial trial solutions using the MCMC method following the Metropolis method or the Gibbs method, techniques such as the pseudo-annealing method and the replica exchange method can be applied. When a solution search is performed using the pseudo-annealing method, the calculation conditions may include, for example, the maximum value of the temperature parameter, the temperature parameter change schedule, the minimum value of the temperature parameter, and the search termination conditions.

[0022] The processing unit 12 can be implemented using electronic circuits such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). However, the processing unit 12 can also be implemented using processors such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or a DSP (Digital Signal Processor). The processor executes programs stored in memory such as RAM (which may also be the storage unit 11). A collection of processors may be called a multiprocessor or simply a "processor." Furthermore, the processing unit 12 may include both a processor and electronic circuits such as an ASIC or FPGA.

[0023] When the processing unit 12 executes a plurality of trials to change the value of any of the state variables included in the plurality of state variable groups based on the evaluation function information 11a, for each trial, the processing unit 12 performs a first process of determining candidates for the first state variable whose value is to be changed in parallel for each of the plurality of state variable groups. The processing unit 12 performs the first process with a first probability (hereinafter denoted as ρ). Hereinafter, the first process is referred to as RF selection. ρ is calculated using a first parallel number corresponding to the number of the plurality of state variable groups. When the plurality of state variable groups are obtained by dividing N state variables included in the evaluation function into M parts, ρ is the value obtained by dividing M, which is the first parallel number, by N, that is, M / N.

[0024] In RF selection, for example, the processing unit 12 determines the candidates by the RF method using the amount of change in energy (value of the evaluation function) when the value of the state variable included in each of the plurality of state variable groups changes.

[0025] When the value of the state variable x i included in a certain division unit changes to 1 - x i , the change amount of the state variable x i is Δx i =(1 - x i ) - x i =1 - 2x i and can be expressed as such. Therefore, for the evaluation function E(x), the amount of change in energy (ΔE i ) accompanying the change in the state variable x i can be expressed by the following formula (2).

[0026]

Equation

[0027] h i is called the local field (LF). The change amount of h j when the value of x i changes is Δh i (j) =W ij Δx j and is expressed as such. The processing unit 12 calculates h i ]>regarding x iKeep h i When the value of Δh changes, i (j) by h i You may update it.

[0028] In the RF method, the index = j of a candidate state variable whose value changes in a given division unit is the x included in that division unit. i ΔE related to i It can be expressed by the following equation (3) using .

[0029]

number

[0030] In equation (3), r i is ΔE i 0 generated in response to <r i This is a uniformly random number < 1. T is the value of the temperature parameter. The max operator indicates that it takes the maximum value among the arguments. argmin i This indicates the value of i that minimizes the argument.

[0031] Furthermore, the processing unit 12, based on the evaluation function information 11a, performs a second process in which it selects one second state variable for each trial and determines in parallel for each of the multiple state variable groups whether or not the value can change, using a second probability obtained by subtracting ρ from 1 (hereinafter referred to as 1-ρ). Hereinafter, this second process is referred to as metropolis selection.

[0032] In metropolis selection, the processing unit 12 determines whether or not to allow a change in the value of the second state variable, for example, according to the acceptance probability of the change in the value of the second state variable using the metropolis method or the Gibbs method.

[0033] In the Metropolis method and the Gibbs method, when searching for a nearest neighbor transition from a given state to another state with lower energy, transitions to states with higher energy are probabilistically accepted, not just those with lower energy. ΔE i Acceptance probability A: Accepting a change in the value of a state variable that causes this change.i This can be expressed by equation (4).

[0034]

number

[0035] β is the reciprocal of the temperature parameter T (T>0) (β=1 / T), and is called the inverse temperature. The min operator indicates that the minimum value of the arguments is taken. The upper right-hand side of equation (4) corresponds to the Metropolis method. The lower right-hand side of equation (4) corresponds to the Gibbs method.

[0036] The reasons for selecting RF according to ρ calculated using the first parallelism number and selecting Metropolis according to 1-ρ will be explained later. Furthermore, the processing unit 12 updates the value of the first state variable selected from the candidates determined by RF selection. For example, the processing unit 12 can select the first state variable based on the evaluation value (hereinafter referred to as score) of each candidate determined by RF selection. As the score, max(0,ΔE) of equation (3) j )+Tlog(-log(r j )) can be used. The candidate with the smallest score is selected as the first state variable. This can result in state transitions that can have lower energy.

[0037] Furthermore, the processing unit 12 updates the values ​​of the second state variables whose values ​​are permitted to change due to metropolis selection. If, due to metropolis selection, there are multiple second state variables whose values ​​are permitted to change in a group of multiple state variables, the processing unit 12, for example, randomly selects one second state variable and updates its value.

[0038] In the example shown in Figure 1, the processing unit 12 includes a control processing unit 12a, M arithmetic processing units 12b1 to 12bM, and a secondary selection unit 12c. The control processing unit 12a controls the solution search. For example, the control processing unit 12a controls the values ​​of T included in equation (3) and β included in equation (4), and controls the switching between RF selection and metropolis selection according to probability ρ.

[0039] The number of arithmetic processing units 12b1 to 12bM is the same as the number of first parallelisms (M) mentioned above, and they process each group of state variables in parallel. If multiple groups of state variables are obtained by dividing the N state variables included in the evaluation function into M parts, each of the arithmetic processing units 12b1 to 12bM is responsible for processing N / M of the state variables.

[0040] When RF selection is performed, each of the arithmetic processing units 12b1 to 12bM determines the candidate by performing the calculation in equation (3) using the above change amount when the value of each state variable included in the state variable group responsible for processing changes.

[0041] When metropolis selection is performed, each of the arithmetic processing units 12b1 to 12bM selects one second state variable per trial from the group of state variables responsible for processing. Each of the arithmetic processing units 12b1 to 12bM selects, for example, a second state variable corresponding to an index specified by the control processing unit 12a. Then, using the amount of change when the value of the selected second state variable changes, the arithmetic processing units 12b1 to 12bM decide whether or not to allow the change in the value of the second state variable according to the acceptance probability shown in equation (4) using the metropolis method or the Gibbs method.

[0042] Furthermore, the arithmetic processing units 12b1 to 12bM update the value of the first or second state variable selected by the secondary selection unit 12c. In RF selection, the secondary selection unit 12c selects a first state variable, which is one of the candidates determined by the arithmetic processing units 12b1 to 12bM, based on the aforementioned score. In metropolis selection, if there are multiple second state variables whose values ​​have been allowed to change by the arithmetic processing units 12b1 to 12bM, the secondary selection unit 12c selects, for example, one second state variable randomly. Note that the control processing unit 12a may also perform the function of the secondary selection unit 12c.

[0043] (Reasons for RF selection according to ρ calculated using the first parallelism number, and Metropolis selection according to 1-ρ) In the serial trial-based solution search of the MCMC method using metropolis selection as described above, the probability α of the state transitioning from the current state to a different state (hereinafter referred to as the escape probability) can be expressed by the following equation (5).

[0044]

number

[0045] In equation (5), A i This is the acceptance probability shown in equation (4). Figure 2 shows the relationship between the computational complexity and escape probability for solution search using serial trials of the MCMC method and the RF method. The horizontal axis represents the escape probability (α), and the vertical axis represents the computational complexity per update of the state variable (logarithmic scale). Note that solution search using the RF method includes RF selection as described above.

[0046] Figure 2 shows ΔE in the serial trial. i x using i The computational amount required to determine whether the value of can change or not (ΔE in the RF method) i The computational cost of a single operation using this method is set to 1. The computational cost of solution search using the RF method is constant at N.

[0047] As shown in Figure 2, when α is less than 1 / N, the computational complexity of solution search using the RF method is less than that of solution search using serial trials. Therefore, solution search using the RF method is more advantageous than solution search using serial trials. Note that if the solution is in a local minimum, α becomes small, and in some cases α << 1 / N.

[0048] When α is greater than 1 / N, the computational complexity of solution search using the RF method is greater than that of solution search using serial trials. Therefore, solution search using serial trials is more advantageous than solution search using the RF method. When there are k (>1) escape destinations, α will be greater than or equal to k / N, and α will be greater than 1 / N.

[0049] As described above, it is possible to determine which method—RF-based solution search or serial trial-based solution search—is more advantageous based on α. ​​However, as shown in equation (5), calculating α requires N exponential operations and N integral operations, making it difficult to reduce the total computational load.

[0050] For example, the following literature proposes performing selection serially with probability ρ using the IIT (Informed Importance Tempering) method, which is a generalization of the RF method without calculating α, and performing serial trials using Metropolis selection with probability 1-ρ.

[0051] Literature: Guanxun Li, Aaron Smith and Quan Zhou, "Importance is Important: A Guide to Informed Importance Tempering Methods", arXiv:2304.06251v1 [stat.CO], 13 Apr 2023 If we let ρ = A / N (where A is a predetermined constant greater than 0 and less than or equal to N), then the following inequality (6) holds for the expected value of the computational complexity K(x).

[0052]

number

[0053] The left-hand side of equation (6) is the expected value of K(x). As shown in equation (6), the expected value of K(x) is on the order of the smaller of the computational complexity of the RF method's solution search (N / A) and the computational complexity of the serial trials (1 / α).

[0054] When A=1, equation (6) can be expressed as equation (7) below.

[0055]

number

[0056] When A=1, regardless of the escape probability (α), the expected value of K(x) is less than or equal to twice the smaller of the computational complexity of the RF method's solution search (N) and the computational complexity of the serial trial (1 / α). In other words, the optimal selection method is automatically chosen without having to calculate α and choose between RF selection and Metropolis selection.

[0057] As described above, the data processing device 10 of the first embodiment processes multiple state variable groups in parallel. This is because it becomes possible to process the computation amount K(x) in M ​​parallel, potentially increasing the processing speed (reducing the time required for computation).

[0058] When processing N state variables of an evaluation function by dividing them into M parts, the total computation time is determined by the amount of computation required for each division. If serial trials are performed in M ​​parallel, the escape probability is 1-(1-α) when α<<1. M Since ≈ Mα, by applying equation (8) below, where N is N / M, α is Mα, and ρ is M / N in equation (7), a speed improvement proportional to the degree of parallelism (M) can be obtained.

[0059]

number

[0060] In other words, by performing RF selection with probability ρ = M / N and metropolis selection with probability 1 - ρ, the speed improvement described above can be achieved, enabling faster solution searching for combinatorial optimization problems. As described above, in the data processing device 10 of the first embodiment, the storage unit 11 stores evaluation function information 11a relating to an evaluation function for a combinatorial optimization problem including a plurality of state variable groups. Based on the evaluation function information 11a, the processing unit 12 performs RF selection, which determines candidates for a first state variable whose value will be changed in parallel for each of the plurality of state variable groups, using a first probability (ρ) calculated using a first parallel number corresponding to the number of state variable groups. Furthermore, based on the evaluation function information 11a, the processing unit 12 performs metropolis selection, which determines whether or not to change the value of one second state variable in parallel for each of the plurality of state variable groups, using a second probability (1-ρ). In addition, the processing unit 12 updates the value of the first state variable selected from the candidates determined by RF selection and updates the value of the second state variable whose value change is permitted by metropolis selection. As a result, for the reasons described above, a speed improvement proportional to the degree of parallelism (M) is obtained, and the solution search for the combinatorial optimization problem can be performed at high speed.

[0061] In large-scale combinatorial optimization problems, the time it takes to transition from a state with high initial energy to a low-energy state where the optimal solution can be expected (referred to as the time during which initial relaxation occurs, or initial relaxation time) becomes longer. In the data processing device 10 of this embodiment, the initial relaxation can be completed in a short time due to the effect of the above-mentioned speedup.

[0062] Furthermore, there are combinatorial optimization problems where the acceptance probability is high, not only during initial relaxation. For example, there are problems where many local optima are distributed within a flat energy landscape, and problems where the acceptance probability changes significantly and irregularly during the search process. When searching for solutions to such problems, applying RF selection when the acceptance probability is high reduces efficiency. However, in the data processing device 10 of this embodiment, computational efficiency can be improved by performing RF selection and metropolis selection according to the above probabilities (ρ, 1-ρ).

[0063] Such a data processing device 10 is expected to be useful as a means of quickly obtaining solutions when solving various problems in modern society that can be transformed into combinatorial optimization problems. The data processing device 10 may also have a function to sample the state during the solution search. An example of the sampling function will be described in the second embodiment.

[0064] [Second Embodiment] Figure 3 shows an example of a data processing device according to the second embodiment. The data processing device 20 includes an overall control circuit 21, arithmetic processing circuits 22a1, 22a2, ..., 22aM, a second-order selection circuit 23, and a sample acquisition circuit 24. These circuits can be implemented using electronic circuits such as ASICs or FPGAs. Furthermore, these circuits can also be implemented using one or more processors or processor cores.

[0065] Note that in Figure 3, the memory unit that stores evaluation function information related to the evaluation function of the combinatorial optimization problem is omitted from the illustration. The overall control circuit 21 has the same functions as the control processing unit 12a in the first embodiment. The overall control circuit 21 controls RF selection or metropolis selection, which is performed using the arithmetic processing circuits 22a1 to 22aM. For example, the overall control circuit 21 controls the temperature parameter (T) used in the arithmetic processing circuits 22a1 to 22aM, and controls the switching between two types of solution search according to probability ρ (hereinafter referred to as mode switching control). In the following explanation, it is assumed that ρ = M / N. N is the number of state variables included in the evaluation function, and M is the number of divisions of the state variables.

[0066] The arithmetic processing circuits 22a1 to 22aM have the same functions as the arithmetic processing units 12b1 to 12bM in the first embodiment. The arithmetic processing circuits 22a1 to 22aM perform processing on M groups of state variables (each containing n = N / M state variables) obtained by dividing the N state variables of the evaluation function into M parts, in M ​​parallel.

[0067] When RF selection is performed, the arithmetic processing circuits 22a1 to 22aM determine candidate state variables whose values ​​will be changed by performing the calculation in equation (3) using the amount of energy change when the value of each of the n state variables responsible for processing changes. Each of the arithmetic processing circuits 22a1 to 22aM determines one of the above candidates per trial and outputs its index. In addition, the arithmetic processing circuits 22a1 to 22aM calculate and output a score for each candidate. The score is calculated using the max(0,ΔE) formula in equation (3). j )+Tlog(-log(r j )) can be used.

[0068] When metropolis selection is performed, the arithmetic processing circuits 22a1 to 22aM, under the control of the overall control circuit 21, select one state variable per trial from the n state variables responsible for processing. Then, the arithmetic processing circuits 22a1 to 22aM use the amount of energy change when the value of the selected state variable changes to determine whether the value of that state variable can be changed, according to the acceptance probability shown in equation (4). In this way, the acceptance or rejection of values ​​for M state variables is performed in parallel at one time. Each of the arithmetic processing circuits 22a1 to 22aM outputs the index of the selected state variable and a signal indicating whether the change is possible or not.

[0069] Furthermore, if a state variable whose value is to be changed by the second-order selection circuit 23 is selected, the arithmetic processing circuits 22a1 to 22aM update the value of that state variable. The secondary selection circuit 23 has the same function as the secondary selection unit 12c in the first embodiment. The secondary selection circuit 23 selects one of the above candidates determined by RF selection by the arithmetic processing circuits 22a1 to 22aM as the index of the state variable whose value is changed, based on the score. The score is max(0,ΔE) of equation (3). j )+Tlog(-log(r j When )) is used, the second-order selection circuit 23 selects the index of the candidate with the smallest score as the index of the state variable whose value is changed, and outputs it.

[0070] The second-order selection circuit 23 outputs whether there are any state variables whose values ​​are allowed to change, and if there are any state variables whose values ​​are allowed to change, their indices, when the arithmetic processing circuits 22a1 to 22aM perform metropolis selection. If there are multiple state variables whose values ​​are allowed to change, the second-order selection circuit 23, for example, randomly selects and outputs the index of one of the state variables.

[0071] Alternatively, the processing performed by the quadratic selection circuit 23 described above may be carried out by the overall control circuit 21. In that case, the quadratic selection circuit 23 may not be necessary. Or, the overall control circuit 21 can also be called the quadratic selection circuit.

[0072] The sample acquisition circuit 24 performs sampling of state variables whose values ​​are updated. Sampling is useful when the probability or expected value of a specific state occurring is meaningful, such as in risk assessment. Sampling can be performed using the RF method and the IIT method, which is a generalization of the RF method.

[0073] The sampled state is J k (k=1,…,L), sample weights w k , the function of the state is f(j k If we assume that the expected value E(f) of the state function is given by the following equation (9).

[0074]

number

[0075] Furthermore, when solution search is performed using the RF method, the sum of the escape probabilities (α) in the arithmetic processing circuits 22a1 to 22aM is w k If a serial trial solution search is performed using metropolis selection, the number of trials until the change in value is acceptable is w k This can be done. However, if it is not necessary to reproduce the probability distribution or calculate the expected value of the state function, w k The calculation process can be omitted.

[0076] Furthermore, if sampling is not performed, the sample acquisition circuit 24 may be omitted. FIG. 4 is a diagram showing an example of the overall control circuit and the arithmetic processing circuit. In FIG. 4, an example of the arithmetic processing circuit 22a1 is shown among the arithmetic processing circuits 22a1 to 22aM, but the other arithmetic processing circuits 22a2 to 22aM have the same configuration as the arithmetic processing circuit 22a1.

[0077] The overall control circuit 21 includes a random number generator 21a and a comparator 21b as elements used to perform mode switching control. The random number generator 21a generates a uniform random number (r) where 0 < r < 1. As the random number generator 21a, for example, a pseudo-random number sequence generator such as a Mersenne twister can be used.

[0078] The comparator 21b compares the probability ρ (= M / N) with r. When r ≤ ρ, the comparator 21b outputs mode = 1, and when r > ρ, the comparator 21b outputs mode = 0. mode is a variable for specifying whether to perform solution search by the RF method or solution search by serial trial for the arithmetic processing circuits 22a1 to 22aM. In the following description, when 1 is set in mode (mode = 1), it is assumed that RF selection is performed for the arithmetic processing circuits 22a1 to 22aM. Also, when 0 is set in mode (mode = 0), it is assumed that Metropolis selection is performed for the arithmetic processing circuits 22a1 to 22aM.

[0079] Note that the overall control circuit 21 may calculate ρ = M / N using the parallel number M, or may acquire ρ calculated using the parallel number M from the outside. The arithmetic processing circuit 22a1 includes a primary selection circuit 22b1 and an update circuit 22c1.

[0080] When mode = 1, the primary selection circuit 22b1 performs RF selection, so for the state variables i = 1 to n, it executes the operation of Equation (3) and outputs the index = j of the candidate state variables whose values are to be changed. The r used in the operation of Equation (3) i is a uniform random number where 0 < r i < 1 generated by the primary selection circuit 22b1 for each trial. r iThis can be generated using a pseudorandom number generator such as a Mersenne Twister. ΔE used in the calculation of equation (3) i This is obtained by the update circuit 22c1. When mode=1, the first-order selection circuit 22b1 further uses the score of equation (3) max(0,ΔE j )+Tlog(-log(r j Output.

[0081] The first-order selection circuit 22b1, when mode=0, performs metropolis selection, selecting one state variable per trial from the state variables i=1 to n. For example, the first-order selection circuit 22b1 selects a state variable corresponding to the index = j (where j is one of 1 to n) supplied from the overall control circuit 21.

[0082] Then, the first-order selection circuit 22b1 calculates ΔE when the value of the selected state variable changes. i Using this method, the possibility of a change in the value of the state variable (transition feasibility) is determined according to the acceptance probability shown in equation (4). When using the Metropolis method, the possibility of a transition according to the acceptance probability shown in equation (4) can be expressed by whether or not the following equation (10) is satisfied.

[0083]

number

[0084] ΔE j This is the state variable x from i=1 to n. i x randomly selected from j This is the change in energy when the value of changes. ΔE j This is obtained by the update circuit 22c1. When equation (10) is satisfied, the first-order selection circuit 22b1 is x j The signal Update=1 is output to indicate that the change in the value of has been accepted. When equation (10) is not satisfied, the first-order selector circuit 22b1 outputs the signal Update=1. j The signal Update=0 is output to indicate that the change in the value was rejected.

[0085] Figure 5 shows an example of an update circuit. In addition to the update circuit 22c1 included in the arithmetic processing circuit 22a1, Figure 5 also shows update circuits 22c2 to 22cM included in the arithmetic processing circuits 22a2 to 22aM.

[0086] The update circuit 22c1 includes a memory circuit 22d1, a multiplier 22d2, an adder 22d3, a memory circuit 22d4, a ΔE calculation circuit 22d5, a selector 22d6, an adder 22d7, and a memory circuit 22d8.

[0087] The memory circuit 22d1 contains the weight coefficient (W) included in the evaluation function. ij The memory circuit 22d1 stores (i=1~n, j=1~N). Then, the memory circuit 22d1 stores W corresponding to the index = j selected by the secondary selection circuit 23. ij Read it out.

[0088] The multiplier 22d2 is W ij and x j Change Δx j Product of (W ij Δx j Outputs ). The adder 22d3 is stored in the memory circuit 22d1, as shown in equation (2) h i (i=1~n) W ij Δx j By adding this, a new h i Calculate (h i (Updated).

[0089] The memory circuit 22d4 has n h i Remember this. The ΔE calculation circuit 22d5 is Δx i and h i Using this, we obtain the ΔE shown in equation (2). i Calculate.

[0090] Selector 22d6 is used when index = j matches any of i = 1 to n, and Δx j It outputs the result, and if it does not match any of i=1 to n, it outputs 0. The adder 22d7 is controlled by selector 22d6 when Δx jWhen outputting, x stored in the memory circuit 22d8 i (i = 1 to n) of x j adds Δx j to calculate a new x j (x j is updated).

[0091] The memory circuit 22d4 stores n x i . Regarding the update circuits 22c2 to 22cM included in the arithmetic processing circuits 22a2 to 22aM, an index = j and Δx j are supplied, and the same processing as that of the update circuit 22c1 is performed in parallel with the update circuit 22c1. Note that the update circuit 22c2 performs the update processing of x i and h i and the calculation processing of ΔE i for i = n + 1 to 2n, and the update circuit 22cM performs the update processing of x i and h i and the calculation processing of ΔE i for i = (M - 1)n + 1 to Mn.

[0092] The update circuits 22c1 to 22cM all perform the same operation and do not depend on the outputs of other update circuits. Also, the operations of the update circuits 22c1 to 22cM are the same regardless of whether the solution search is by RF selection or by metropolis selection.

[0093] Figure 6 is a diagram showing an operation example of metropolis selection. When the overall control circuit 21 causes the arithmetic processing circuits 22a1 to 22aM to perform metropolis selection, for example, it supplies the arithmetic processing circuits 22a1 to 22aM with indices from 1 to n in order from 1.

[0094] Each of the arithmetic processing circuits 22a1 to 22aM selects a state variable corresponding to the supplied index and performs a transition feasibility determination. The arithmetic processing circuit 22a1 is in charge of the processing of x1 to x n as n state variables, and the arithmetic processing circuit 22a2 is in charge of the processing of x n+1 to x 2nThe arithmetic processing circuit 22aM is responsible for processing x as n state variables. (M-1)n+1 ~x Mn It is responsible for processing x. For example, if index = j is supplied from the overall control circuit 21, the arithmetic processing circuit 22a1 will process x j Selecting this option, the arithmetic processing circuit 22a2 is x n+j Selecting this option, the arithmetic processing circuit 22aM is x (M-1)n+j Selecting an option and performing a transition feasibility check in M ​​parallel steps is the first step.

[0095] Furthermore, when the overall control circuit 21 executes the function of the secondary selection circuit 23 or when sampling is performed, the Update signal output by the arithmetic processing circuits 22a1 to 22aM is supplied to the overall control circuit 21, as shown in Figure 6.

[0096] Next, we will explain an example of the operation timing of the data processing device 20 during solution search. Figure 7 is a timing chart showing an example of the operation timing of the data processing unit in solution search. Figure 7 shows the timing of mode switching control by the overall control circuit 21 and variable selection processing by the M arithmetic processing circuits 22a1 to 22aM. The variable selection processing includes the process of selecting candidate state variables whose values ​​will change by RF selection, or the process of selecting state variables by serial trials using metropolis selection and determining whether a transition is possible. Furthermore, Figure 7 shows the timing of the secondary selection processing by the secondary selection circuit 23 and the update processing by the arithmetic processing circuits 22a1 to 22aM. The cycles of the 1st to 4th serial trials are denoted as S1 to S4, respectively. Also, in order to perform RF selection, each of the arithmetic processing circuits 22a1 to 22aM calculates ΔE corresponding to the change in the values ​​of n state variables. i The cycles used to calculate this are denoted as R1 to Rn.

[0097] During the period t1-t2, mode=0, so each of the arithmetic processing circuits 22a1-22aM ​​selects one state variable and determines whether a transition is possible. In the example in Figure 7, the state variable selected in arithmetic processing circuit 22a2 is determined to be transitionable. In this case, the secondary selection circuit 23 selects and outputs the index of that state variable. "S1-2" indicates that the secondary selection circuit 23 outputs the index of the state variable selected in the second arithmetic processing circuit 22a2 during cycle S1 of the first serial trial. The arithmetic processing circuits 22a1-22aM ​​perform an update process (x) corresponding to the change in the value of the selected state variable. i h i Perform the update.

[0098] During the timing period t2 to t4, mode=1, so in each of the arithmetic processing circuits 22a1 to 22aM, n (=N / M) state variables are selected in order, and ΔE i The calculation is performed. Then, during the period t3 to t4, each of the arithmetic processing circuits 22a1 to 22aM outputs the index of a candidate state variable whose value is changed, according to equation (3), and also outputs the score of each candidate. The second-order selection circuit 23 selects and outputs one index from the M candidates based on the score. "R2-2" indicates that the second-order selection circuit 23 outputs the index of the state variable selected by the second arithmetic processing circuit 22a2 in cycle R2. The arithmetic processing circuits 22a1 to 22aM perform an update process (x) corresponding to the change in the value of the selected state variable. i h i Perform the update.

[0099] During the periods t4-t5 and t5-t6, mode=0, so the same processing as during the period t1-t2 is performed. However, during the period t4-t5, the state variables selected by the arithmetic processing circuits 22a1 and 22aM are determined to be transitionable. Also, during the period t5-t6, the state variables selected by the arithmetic processing circuits 22a1 and 22a2 are determined to be transitionable. In this case, the secondary selection circuit 23 randomly selects and outputs the index of one of the state variables. In the example in Figure 7, “S2-M,” that is, the index of the state variable selected by the Mth arithmetic processing circuit 22aM in cycle S2 of the second serial trial, is output. Also, “S3-2,” that is, the index of the state variable selected by the second arithmetic processing circuit 22a2 in cycle S3 of the third serial trial, is output.

[0100] During the period from timing t6 to t8, mode=1, so the same processing as during the period from timing t2 to t4 is performed. However, during the period from timing t7 to t8, the second-order selection circuit 23 outputs "Rn-1", that is, the index of the state variable selected in the first arithmetic processing circuit 22a1 in cycle Rn.

[0101] During the period from timing t8 to t9, mode=0, so the same processing as during the period from timing t1 to t2 is performed. However, during the period from timing t8 to t9, the state variable selected by the arithmetic processing circuit 22a1 is determined to be transitionable. Therefore, the secondary selection circuit 23 outputs the index of the state variable selected by the first arithmetic processing circuit 22a1 in "S4-1", that is, cycle S4 of the fourth serial trial.

[0102] Next, the processing procedure (data processing method) of the data processing device of the second embodiment will be described. Figure 8 is a flowchart showing an example of the processing procedure of the data processing device according to the second embodiment. In the processing shown in Figure 8, an example is shown in which solution search is performed using the same evaluation function information with multiple replicas.

[0103] First, initialization is performed (step S10). In the process of step S10, W ij This includes setting evaluation function information such as N state variables (x i Setting the initial value of the value of ), N local fields (h i Initial values ​​for ) are set, etc.

[0104] The process from step S11 to step S15 is a loop process that is repeated for the number of replicas (labeled as the replica loop in Figure 8). Furthermore, the process from step S12 to step S14 is a loop process that is repeated for a predetermined number of iterations (labeled as the iteration loop in Figure 8).

[0105] In step S13, the selection and update operations of state variables whose values ​​are to be changed are performed. An example of the procedure for step S13 will be described later (see Figures 9 to 11). Once the process in step S13 has been repeated a predetermined number of iterations, the process for the next replica is performed.

[0106] After processing of all replicas is complete, it is determined whether a predetermined termination condition is met (step S16). If it is determined that the predetermined termination condition is met, the processing of the data processing device 20 is completed; if it is determined that the termination condition is not met, the processing from step S11 is repeated.

[0107] Figure 9 is a flowchart illustrating an example of a processing procedure for selecting a state variable whose value changes. Figure 9 shows an example of a selection control procedure, which is one of the processes of the overall control circuit 21 in the process of step S13 shown in Figure 8.

[0108] The overall control circuit 21 generates a uniform random number (r) where 0 < r < 1 (step S20). Then, the overall control circuit 21 determines whether r ≤ ρ (step S21). ρ is M / N. When the overall control circuit 21 determines that r ≤ ρ, it sets 1 in mode (step S22), and when it determines that r > ρ, it sets 0 in mode (step S23).

[0109] After the processing of steps S22 and S23, the overall control circuit 21 sets index = j to j + 1 (step S24). After sending j and mode to the arithmetic processing circuits 22a1 to 22aM (step S25), it ends the selection control.

[0110] Figure 10 is a flowchart showing an example of the processing procedure of the update control. In Figure 10, an example of the update control procedure, which is one of the processes of the overall control circuit 21 in the processing of step S13 shown in Figure 8, is shown.

[0111] The overall control circuit 21 determines whether mode = 1 (step S30). When the overall control circuit 21 determines that mode = 1, it calculates the reciprocal of the sum of the escape probabilities α i and sets it as the weight (w) of the sample used when sampling. The overall control circuit 21 causes the arithmetic processing circuits 22a1 to 22aM to update x j corresponding to the index selected by the secondary selection circuit 23 based on the score (step S32). Then, the overall control circuit 21 outputs w, and acquires the values of N state variables from the arithmetic processing circuits 22a1 to 22aM and outputs them as the updated state (y) (step S33). Note that the output w and y are acquired by the sample acquisition circuit 24. After the processing of step S33, the overall control circuit 21 sets w to 0 (step S34) and ends the update control.

[0112] If the overall control circuit 21 determines that mode is not 1, it sets w to w+1 (step S35). After the processing in step S35, the overall control circuit 21 determines whether the number of accepted values ​​(the number of transitions that were determined to be possible in the transition feasibility determination performed in M ​​parallel) is 1 or more (step S36). The number of accepted values ​​can be detected by the number of Updates with a value of 1 among the Updates output by the arithmetic processing circuits 22a1 to 22aM.

[0113] If the overall control circuit 21 determines that the number of accepted data is 1 or more, it instructs the secondary selection circuit 23 to randomly select the index of one state variable and has one of the arithmetic processing circuits 22a1 to 22aM update the value of that state variable (step S37). The overall control circuit 21 then outputs w and retrieves the values ​​of N state variables from the arithmetic processing circuits 22a1 to 22aM, outputting them as the updated state (y) (step S38). The output w and y are acquired by the sample acquisition circuit 24. After the processing in step S38, the overall control circuit 21 sets w to 0 (step S39) and terminates the update control.

[0114] Figure 11 is a flowchart showing an example of the processing procedure of an arithmetic processing circuit. In Figure 11, an example of the processing procedure of the i-th arithmetic processing circuit 22ai among the arithmetic processing circuits 22a1 to 22aM is shown.

[0115] The arithmetic processing circuit 22ai sets the index = j and mode sent by the overall control circuit 21 (step S40). Then, the arithmetic processing circuit 22ai performs Update i Set to 0 (step S41). Next, the arithmetic processing circuit 22ai determines whether mode=1 or not (step S42). If the arithmetic processing circuit 22ai determines that mode=1, it performs the process in step S43; if it determines that mode=1 or not, it performs the process in step S47.

[0116] In step S43, the arithmetic processing circuit 22ai calculates the escape probability α according to equation (5). iThis is calculated. Note that this step is unnecessary if sampling is not performed. After the processing in step S43, a loop process for RF selection (labeled as the RF loop in Figure 11) is performed (steps S44-S46). In the processing in step S45, RF selection is performed. In RF selection, ΔE of equation (3) i The following is calculated: ΔE for n state variables i To calculate this, the RF selection is repeated n times by a loop. In the nth step S45 of the RF selection, the index = j of the candidate state variable whose value changes is calculated according to equation (3).

[0117] In step S47, metropolis selection is performed for j. In metropolis selection, ΔE is applied to the index = j set in step S40. j The calculation of x is performed. For example, if the arithmetic processing circuit 22ai is the arithmetic processing circuit 22a2 shown in Figure 6, then x n+j ΔE is the amount of energy change associated with a change in its value. n+j ΔE j It is calculated as follows.

[0118] Then, the arithmetic processing circuit 22ai determines whether or not to accept a change in the value of the state variable specified by index = j (whether or not a transition is possible) (step S48). Whether or not a transition is possible can be determined by whether or not the relationship shown in equation (10) is satisfied.

[0119] The arithmetic processing circuit 22ai performs an Update if it determines in step S48 that a transition is possible, or after the completion of the loop processing in steps S44 to S46. i Set it to 1 (Step S49).

[0120] If it is determined after the processing in step S49, or during the processing in step S48, that a transition is not possible, the processing for one trial of the arithmetic processing circuit 22ai is terminated. Note that the processing procedure shown in Figures 8 to 11 is just one example, and the order of processing may be changed as appropriate.

[0121] As described above, in the data processing device 20 of the second embodiment, each of the arithmetic processing circuits 22a1 to 22aM performs RF selection and metropolis selection based on evaluation function information for each division unit obtained by dividing the N state variables of the evaluation function into M divisions. Each of the arithmetic processing circuits 22a1 to 22aM performs RF selection with a probability of M / N and metropolis selection with a probability of 1-(M / N) according to the control of the overall control circuit 21. As a result, for the same reasons as explained in the first embodiment, a speed improvement proportional to the degree of parallelism (M) is obtained, and the solution search for combinatorial optimization problems can be performed at high speed.

[0122] In addition, the same effects as those of the data processing device 10 of the first embodiment can be obtained. [Third Embodiment] Figure 12 shows an example of a data processing device according to the third embodiment. In Figure 12, the same reference numerals are used for the same elements as in the data processing device 20 shown in Figure 3.

[0123] In the data processing device 20 of the second embodiment described above, the arithmetic processing circuits 22a1 to 22aM have update circuits 22c1 to 22cM as shown in Figure 5. In other words, the number of parallel processes M and the number of parallel processes for the update process were the same. In contrast, the data processing device 30 of the third embodiment performs the update process with a number of parallel processes different from the number of parallel processes M.

[0124] The arithmetic processing circuits 31a1, 31a2, ..., 31aM do not include update circuits; an update circuit 32 is provided separately from the arithmetic processing circuits 31a1 to 31aM. Each of the arithmetic processing circuits 31a1 to 31aM has a primary selection circuit 22b1 as shown in Figure 4.

[0125] Figure 13 shows an example of an update circuit for a data processing device according to the third embodiment. The update circuit 32 has K update units 32a1, 32a2, ..., 32aK. The configuration of each update unit 32a1 to 32aK is the same as that of the update circuit 22c1 shown in Figure 5. However, for i=1 to N / K, update unit 32a1 has x i and h i Update process and ΔE i The calculation process is performed, and the update unit 32a2 calculates x for i = N / K + 1 to 2N / K. i and h i Update process and ΔE i The calculation process is performed. In addition, the update unit 32aK calculates x for i = NN / K + 1 ~ N. i and h i Update process and ΔE i The calculation process is performed.

[0126] K is different from M. Also, the number of update units 32a1 to 32aK used may be changed under the control of the overall control circuit 21. With this configuration, when the computational overhead of updating state variables is large, implementing a circuit that updates with a different degree of parallelism than M has the effect of reducing the overall time overhead. In the update process, W ij Processing time may vary depending on the density. For example, W ij If = 0, the update process can sometimes be skipped. Therefore, when the coefficient density is small (W is 0) ij If the number of parallel processes is large, it may be possible to improve the overall computational efficiency and processing performance by controlling the degree of parallelism of the update process (making K smaller), and if it is large, by increasing the degree of parallelism (making K larger).

[0127] [Fourth Embodiment] In the second embodiment, the probability ρ of performing solution search by RF method is assumed to be constant at N / M, but it may be varied.

[0128] Figure 14 is a flowchart showing an example of the processing procedure of the data processing device according to the fourth embodiment. In Figure 14, an example is shown in which solution search is performed using the same evaluation function information with multiple replicas, similar to the process shown in Figure 8.

[0129] First, initialization is performed (step S50). In the process of step S50, W ij This includes setting evaluation function information such as N state variables (x i Setting the initial value of the value of ), N local fields (h i Initial values ​​for ) are set. Also, for example, N / M is set as the initial value of the probability ρ.

[0130] Subsequently, the overall control circuit 21 determines whether a predetermined update condition for ρ, indicating that the initial relaxation has ended, has been met (step S51). For example, the overall control circuit 21 determines that the update condition has been met when the number of iterations reaches a predetermined number. Alternatively, the overall control circuit 21 may determine that the update condition has been met when the period during which the minimum energy is not updated is longer than a predetermined period, or when the update frequency of the minimum energy falls below a predetermined frequency.

[0131] If the update conditions for ρ are met, the overall control circuit 21 updates ρ by increasing it (step S52). The method of updating ρ can be appropriately selected, such as increasing it by 10% compared to the original value, or increasing it by a larger percentage than the previous increase.

[0132] If it is determined after the processing in step S52, or after the processing in step S51, that the update condition for ρ is not met, then the processing in steps S53 to S58 is performed. The processing in steps S53 to S58 is the same as the processing in steps S11 to S16 shown in Figure 8.

[0133] If it is determined that a predetermined termination condition has been met during the process in step S58, the processing of the data processing device of the fourth embodiment is terminated. If it is determined that the termination condition has not been met, the process from step S51 is repeated.

[0134] According to the process described above, the escape probability (α) tends to be high, and during initial relaxation when metropolis selection is favorable, the probability (1-ρ) of selecting metropolis increases. Conversely, after initial relaxation when the escape probability (α) is low and metropolis selection is unfavorable, the probability ρ of selecting RF increases. This allows for efficient solution searching.

[0135] [Fifth Embodiment] In the update control of the overall control circuit 21 in the second embodiment, as shown in Figure 10, if the number of acceptances in the metropolis selection by the arithmetic processing circuits 31a1 to 31aM is 1 or more, the secondary selection circuit 23 is instructed to randomly select the index of one state variable. The overall control circuit 21 then instructs one of the arithmetic processing circuits 22a1 to 22aM to update the value of that state variable.

[0136] In the update control of the overall control circuit 21 in the fifth embodiment shown below, if the number of accepted values ​​is 1 or more during the initial relaxation phase, the values ​​of each accepted state variable are updated. Figure 15 is a flowchart showing an example of the update control processing procedure in the fifth embodiment.

[0137] The processing in steps S60 to S66 is the same as the processing in steps S30 to S36 in the update control shown in Figure 10. In step S66, if the overall control circuit 21 determines that the number of accepted values ​​is 1 or more, it determines whether the current state of the solution search is the initial relaxation stage (step S67). The overall control circuit 21 determines that it is not the initial relaxation stage if, for example, the minimum energy has not been updated for a predetermined number of iterations, or if the number of iterations from the initial state has exceeded a predetermined number.

[0138] If the overall control circuit 21 determines that it is the initial relaxation phase, it instructs the secondary selection circuit 23 to select an index for each accepted state variable, and has the arithmetic processing circuits 22a1 to 22aM continuously update the values ​​of each state variable (step S68). Until the updating process for each state variable is complete, the overall control circuit 21 stops the metropolis selection and RF selection from the arithmetic processing circuits 22a1 to 22aM. After the updating process for each state variable is complete, metropolis selection or RF selection is performed according to probability ρ. Since no sampling output is performed during the initial relaxation phase, the processing in step S71 is performed after the processing in step S68.

[0139] If the process in step S67 determines that it is not the initial relaxation stage, the overall control circuit 21 causes the secondary selection circuit 23 to randomly select an index of one state variable, and causes one of the arithmetic processing circuits 22a1 to 22aM to update the value of that state variable (step S69).

[0140] After the processing in step S69, the processing in step S70 is performed. The processing in steps S70 and S71 is the same as the processing in steps S38 and S39 shown in Figure 10. The above processing speeds up the solution search process, especially during initial relaxation when the acceptance probability is high.

[0141] [Sixth Embodiment] In the data processing device of the sixth embodiment shown below, the multiple state variable groups that are processed in parallel are the multiple state variables included in the evaluation function that have a one-hot constraint.

[0142] Figure 16 shows an example of a data processing device according to the sixth embodiment. The data processing unit 40 includes an overall control circuit 41, arithmetic processing circuits 42a1, 42a2, ..., 42am, and a second-order selection circuit 43. These circuits can be implemented using electronic circuits such as ASICs or FPGAs. Furthermore, these circuits can also be implemented using one or more processors or processor cores.

[0143] Note that in Figure 16, the memory unit that stores evaluation function information related to the evaluation function of the combinatorial optimization problem is omitted from the illustration. The overall control circuit 41 controls the solution search performed by the arithmetic processing circuits 42a1 to 42am. For example, the overall control circuit 41 controls the temperature parameter (T) used by the arithmetic processing circuits 42a1 to 42am, and performs mode switching control according to probability ρ. In the sixth embodiment, the overall control circuit 41 outputs mode=1 with a probability of ρ=1 / m, causing the arithmetic processing circuits 42a1 to 42am to perform RF selection, and outputs mode=0 with a probability of 1-ρ, causing the arithmetic processing circuits 42a1 to 42am to perform metropolis selection.

[0144] The arithmetic processing circuits 42a1 to 42am perform processing in parallel on multiple sets of state variables, each having a 1-hot constraint. Figure 17 shows an example of a first-order selection circuit included in the arithmetic processing circuit according to the sixth embodiment. In the example in Figure 17, a group of state variables consisting of k state variables is shown, each having a 1-hot constraint. State variables with a 1-hot constraint are referred to as 1-hot variables below.

[0145] Each of the m first-order selectors 42b1, 42b2, ..., 42bm performs RF selection when mode=1. In this case, each of the first-order selectors 42b1 to 42bm performs ΔE when the value of each of the k (k-bit) 1-hot variables whose value is 0 changes. i By performing the operation in equation (3) using this, we determine the candidate 1-hot variable whose value changes to 1. In the sixth embodiment, ΔE i This represents the change in energy when one of the 1-hot variables, whose value is 0, is changed to 1, and the other 1-hot variable, whose value is 1, is changed to 0.

[0146] Each of the m first-order selection circuits 42b1 to 42bm performs metropolis selection when mode = 0. In this case, each of the first-order selection circuits 42b1 to 42bm randomly selects one of the k (k-bit) 1-hot variables whose value is 0 per trial. Then, the first-order selection circuits 42b1 to 42bm perform the above ΔE when the value of the selected 1-hot variable changes. i Using this, we determine whether the value of the 1-hot variable can change according to the acceptance probability shown in equation (4).

[0147] Figure 18 shows an example of an update circuit included in the arithmetic processing circuit according to the sixth embodiment. m update circuits 42c1 to 42cm update the value of a 1-hot variable when that 1-hot variable is selected. For example, update circuit 42c1 has a 1-hot variable update circuit 42d1 and a ΔE calculation circuit 42e1.

[0148] The 1-hot variable update circuit 42d1 updates the value of a 1-hot variable specified by index=j to 1 if that 1-hot variable matches any of the k 1-hot variables it is responsible for processing. Furthermore, the 1-hot variable update circuit 42d1 updates the value of any 1-hot variables that were previously 1 to 0.

[0149] The ΔE calculation circuit 42e1 calculates ΔE according to the change in the value of the above 2-bit 1-hot variable. i Perform the calculation. The second-order selection circuit 43 in Figure 16 has the same function as the second-order selection circuit 23 in the second embodiment. The second-order selection circuit 43 selects one of the above candidates determined by RF selection by the arithmetic processing circuits 42a1 to 42am as the index of a 1-hot variable whose value is changed based on the score. The score is max(0,ΔE) of equation (3). j )+Tlog(-log(r j When )) is used, the second-order selection circuit 43 selects the index of the candidate with the smallest score as the index of the 1-hot variable whose value is changed, and outputs it.

[0150] When the secondary selection circuit 43 and the arithmetic processing circuits 42a1 to 42am perform metropolis selection, they output whether there are any 1-hot variables whose values ​​are allowed to change, and if there are any 1-hot variables whose values ​​are allowed to change, they output their indices. If there are multiple 1-hot variables whose values ​​are allowed to change, the secondary selection circuit 43, for example, randomly selects and outputs the index of one of the 1-hot variables.

[0151] According to the data processing device 40 of the sixth embodiment described above, even for problems involving a group of state variables with 1-hot constraints, a speed improvement effect proportional to the number of parallel processes m can be obtained, enabling high-speed solution searching.

[0152] [Seventh Embodiment] In the embodiments described above, the state variable was assumed to be a binary variable of either 0 or 1, but an integer variable can also be used as the state variable.

[0153] Figure 19 is a schematic diagram illustrating an example of using integer variables. m integer variables x i In this case, the subneighbor is x i The difference is Δx i It can be defined as a set of variables (i=1~m). The integer variable x i The number of neighbors p per variable is Δx i There are more cases than for binary variables like ∈{-4,-3,-2,-1,1,2,3,4}.

[0154] m integer variables x i The first-order selection circuit 45, used when there are p neighbors per variable, selects one from mp neighbors. j is a m integer variable x i This is an index that indicates one of the following, and p is an index that indicates one of the p neighbors.

[0155] Note that Δx i From ΔE i The formula (2) for calculating h i Δh used when updatingi (j) =W ij Δx j The same applies when the state variable is an integer variable. [Other examples of data processing device hardware configurations] The data processing devices of the first to seventh embodiments can also be implemented with the hardware shown below.

[0156] Figure 20 shows an example of data processing device hardware. The data processing device 50 is, for example, a computer and includes a processor 51, RAM 52, HDD 53, GPU 54, input interface 55, media reader 56 and communication interface 57, and accelerator card 58. The above unit is connected to a bus.

[0157] The processor 51 is a processor such as a GPU or CPU, which includes arithmetic circuits that execute program instructions and memory circuits such as cache memory. The processor 51 loads at least a portion of the program and data stored in the HDD 53 into the RAM 52 and executes the program. The processor 51 may have multiple processor cores. The data processing unit 50 may also have multiple processors. The processor that executes one of the multiple processes performed by the data processing unit 50 may be different from the processor that executes a different process from the multiple processes. A collection of multiple processors (multiprocessor) may be called a "processor". A processor may also be called a processor circuitry.

[0158] RAM 52 is a volatile semiconductor memory that temporarily stores programs executed by the processor 51 and data used by the processor 51 for calculations. The data processing device 50 may be equipped with other types of memory besides RAM 52, and may be equipped with multiple types of memory.

[0159] HDD53 is a non-volatile storage device that stores software programs such as the OS (Operating System), middleware, and application software, as well as data. The programs include, for example, a program that instructs the data processing device 50 to search for a solution to a combinatorial optimization problem. The data processing device 50 may also include other types of storage devices such as flash memory or SSDs (Solid State Drives), and may include multiple non-volatile storage devices.

[0160] The GPU 54 outputs an image (for example, an image related to the calculation results of a combinatorial optimization problem) to the display 54a connected to the data processing unit 50, according to instructions from the processor 51. The display 54a can be a CRT (Cathode Ray Tube) display, a liquid crystal display (LCD), a plasma display panel (PDP), an organic electro-luminescence (OEL) display, or the like.

[0161] The input interface 55 acquires input signals from input devices 55a connected to the data processing unit 50 and outputs them to the processor 51. Input devices 55a can include pointing devices such as mice, touch panels, touchpads, and trackballs, as well as keyboards, remote controllers, and button switches. Furthermore, multiple types of input devices may be connected to the data processing unit 50.

[0162] The media reader 56 is a reading device that reads programs and data recorded on the recording medium 56a. Examples of recording media 56a include magnetic disks, optical disks, magneto-optical disks (MO), and semiconductor memory. Magnetic disks include flexible disks (FD) and HDDs. Optical disks include CDs (Compact Discs) and DVDs (Digital Versatile Discs).

[0163] The media reader 56 copies programs and data read from the recording medium 56a to other recording media such as RAM 52 or HDD 53. The read programs are executed by the processor 51, for example. The recording medium 56a may be a portable recording medium and may be used for distributing programs and data. The recording medium 56a and HDD 53 may also be referred to as computer-readable recording media.

[0164] The communication interface 57 is connected to the network 57a and communicates with other information processing devices via the network 57a. The communication interface 57 may be a wired communication interface connected by a cable to a communication device such as a switch, or it may be a wireless communication interface connected by a wireless link to a base station.

[0165] The accelerator card 58 is a hardware accelerator that searches for solutions to combinatorial optimization problems. The accelerator card 58 has an FPGA 58a and DRAM (Dynamic Random Access Memory) 58b.

[0166] FPGA58a implements, for example, the functions of the processing unit 12 shown in Figure 1. DRAM58b, for example, implements the functions of the memory unit 11 shown in Figure 1. Furthermore, the processor 51 may implement the functions of the control processing unit 12a of the processing unit 12 shown in Figure 1. Also, there may be multiple accelerator cards 58, for example, to perform processing for multiple replicas.

[0167] The processor 51 may implement all the functions of the processing unit 12 shown in Figure 1. In that case, the accelerator card 58 may not be necessary. Alternatively, for example, multiple arithmetic circuits included within the processor may perform the functions of the arithmetic processing units 12b1 to 12bM shown in Figure 1.

[0168] The processing methods in the data processing devices described above can also be implemented in software by having a computer execute a program as shown in Figure 20.

[0169] Programs can be stored on computer-readable storage media. Examples of storage media include magnetic disks, optical disks, magneto-optical disks, and semiconductor memory. Magnetic disks include flexible disks (FDs) and hard disk drives (HDDs). Optical disks include compact discs (CDs), CD-R (recordable) / RW (rewritable), digital versatile discs (DVDs), and DVD-R / RWs. Programs may be distributed on portable storage media. In such cases, the program may be copied from the portable storage media to other storage media and executed.

[0170] The above describes one aspect of the data processing apparatus, program, and data processing method of the present invention based on embodiments, but these are merely examples and the invention is not limited to those described above. [Explanation of symbols]

[0171] 10 Data Processing Devices 11 Storage section 11a Evaluation function information 12 Processing Units 12a Control Processing Unit 12b1~12bM Arithmetic Processing Unit 12c Secondary Selection Section

Claims

1. A memory unit that stores evaluation function information for an evaluation function of a combinatorial optimization problem involving multiple sets of state variables, Based on the evaluation function information, when performing multiple trials to change the value of any of the state variables included in the group of multiple state variables, a processing unit is performed for each trial in which a first process is performed in parallel for each of the group of multiple state variables to determine a candidate for the first state variable whose value will be changed, using a first probability calculated using a first parallel number corresponding to the number of the group of multiple state variables; a second process is performed in parallel for each trial in which one second state variable is selected based on the evaluation function information and whether or not its value can be changed, using a second probability obtained by subtracting the first probability from 1; the value of the first state variable selected from the candidates determined by the first process is updated; and the value of the second state variable whose value change is permitted by the second process is updated. A data processing device having

2. The data processing apparatus according to claim 1, wherein the processing unit determines the candidate using a rejection-free method in the first processing, using the amount of change in the value of the evaluation function when the value of each of the plurality of state variable groups changes.

3. The data processing device according to claim 1, wherein the processing unit determines whether or not the value of the second state variable can be changed in the second processing according to the acceptance probability of the change in the value of the second state variable according to the Metropolis method or the Gibbs method.

4. The data processing device according to claim 1, wherein, in the case where the plurality of state variable groups are obtained by dividing the N state variables included in the evaluation function into M parts, the first probability is the value obtained by dividing the first parallel number M by N.

5. The data processing device according to claim 1, wherein the processing unit selects the first state variable based on the evaluation value of each of the candidates determined by the first processing.

6. The aforementioned processing unit, Each of the first parallel arithmetic circuits performs the first process with the first probability and the second process with the second probability, A selection circuit that selects a first state variable based on the evaluation value of each of the candidates determined by the first process, and selects one of the second state variables if changes in the values ​​of multiple second state variables are accepted, A data processing device according to claim 1, having the following features.

7. The update process for updating the value of the first state variable or the second state variable is performed with a second parallelism that is different from the first parallelism. The data processing device according to claim 1.

8. The data processing device according to claim 1, wherein the processing unit increases the first probability when a predetermined update condition indicating that the initial relaxation has been completed is met.

9. The data processing device according to claim 1, wherein, if a change in the values ​​of a plurality of second state variables is accepted during initial relaxation, the processing device updates the accepted values ​​of the plurality of second state variables and then performs the first processing or the second processing.

10. The data processing device according to claim 1, wherein each of the plurality of state variable groups is a group of state variables that have a 1-hot constraint among the plurality of state variables included in the evaluation function, and the first probability is the reciprocal of the first parallelism.

11. Based on evaluation function information relating to an evaluation function for a combinatorial optimization problem including a set of multiple state variables stored in the memory unit, when performing multiple trials to change the value of any of the state variables included in the set of multiple state variables, for each trial, a first process is performed to determine a candidate for the first state variable whose value is changed in parallel for each of the set of multiple state variables, using a first probability calculated with a first parallel number corresponding to the number of the set of multiple state variables. Based on the evaluation function information, a second process is performed in which one second state variable is selected for each trial and the possibility of a change in value is determined in parallel for each of the multiple state variable groups, using a second probability obtained by subtracting the first probability from 1. The value of the first state variable selected from the candidates determined by the first process is updated. The second process updates the value of the second state variable whose value change is permitted by the second process. A program that instructs a computer to perform a process.

12. The memory unit stores evaluation function information related to the evaluation function of a combinatorial optimization problem that includes multiple sets of state variables. The processing unit, When performing multiple trials to change the value of any of the state variables included in the group of state variables based on the evaluation function information, for each trial, a first process is performed to determine a candidate for the first state variable whose value is changed, in parallel for each of the group of state variables, using a first probability calculated with a first parallel number corresponding to the number of the group of state variables. Based on the evaluation function information, a second process is performed in which one second state variable is selected for each trial and the possibility of a change in value is determined in parallel for each of the multiple state variable groups, using a second probability obtained by subtracting the first probability from 1. The value of the first state variable selected from the candidates determined by the first process is updated. The second process updates the value of the second state variable whose value change is permitted by the second process. Data processing method.

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