Statistical-driven rate stabilizer

JP2026097705AActive Publication Date: 2026-06-16水野善郎

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
水野善郎
Filing Date
2025-05-23
Publication Date
2026-06-16

AI Technical Summary

Benefits of technology

【0016】 本発明の第二の観点では、ひげゼンマイを改変しない機械式時計用歩度安定装置において、 A)テンプ固有周波数F0と同期した駆動信号を生成するファンダメンタルドライバと、 B)前記ドライバが出力するパルス幅tp、振幅Vpおよび Duty 比D0がそれぞれ一定に保持され、位相0度±δおよび180度±δの2つの位相窓に左右対称のパルスエネルギーEpを注入してテンプを駆動するパルスジェネレータおよびこれに接続されたアクチュエータと、 C)前記駆動は連続時間T_condが6時間を超えない条件でのみ実行され、実行中にテンプ振幅が上限θ_max(75度)を超えた場合パルス注入を停止する振幅監視回路と、 D)前記駆動の実行条件が満たされた場合にのみ、テンプの周波数を±1000 ppm以内で粗調整するコンディショニング制御回路と、 を備え、前記駆動中および駆動終了後も前記パルス幅tp、振幅Vpおよび Duty 比D0は変化せず、テンプ及びひげゼンマイの剛性又は減衰を周期変調しないことを特徴とする歩度安定装置が提供される。

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Abstract

The object of the present invention is to provide a timekeeping device for watches that can stabilize the rate over a long period of time with extremely low power consumption, without directly injecting mechanical vibrations into the balance wheel, while utilizing an external reference. [Solution] This mechanical watch rate stabilizer is based on a statistical drive method with constant pulse width and amplitude, and autonomously switches between four modes—normal mode, ΔΣ1 bitstream mode, low detune frequency hopping mode, and chirp search mode—based on actual current consumption. It achieves both rate stability and low power consumption without modifying the hairspring or maintaining constant instantaneous energy.
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Claims

1. In a rate stabilization device for mechanical watches that does not modify the hairspring, a) At least one detection means selected from an optical reflection sensor or a magnetic sensor that non-contactly detects the temp amplitude A and phase φ, b) Temp natural frequency F 0 At even half-period positions, a constant pulse width tp, a constant amplitude Vp, and a constant duty cycle D 0 A pulse generator that outputs a pulse external force command having, c) An actuator that injects pulsed external force into the temperature support portion in response to the pulsed external force command, d) A control circuit that operates in a rate correction mode, which performs rate correction by statistically updating the pulse injection probability P(t) (0≦P≦1), which is the probability of injecting the pulsed external force, based on the phase difference with an external reference oscillator, or by controlling the average duty cycle D(t) or the drive frequency, and a control circuit that stops excitation by setting P(t)=0 when the Temp amplitude exceeds the upper limit A_max, Equipped with, The device is a rate stabilization device characterized by not periodically modulating the rigidity, inertia, quality coefficient, or position of the resting point of the balance wheel and hairspring.

2. A rate stabilization device according to claim 1, characterized in that the control circuit detects the injection phase of the injection and operates in a rate correction mode in which rate correction is performed by changing the pulse injection probability P(t) in real time in proportion to the magnitude of the injection phase.

3. A rate stabilization device according to claim 1, characterized in that the control circuit operates in a rate correction mode in which rate correction is performed only by the average duty cycle D(t) based on a 1-bit stream generated by a ΔΣ modulator.

4. In the apparatus according to claim 1, the control circuit is the temperature natural frequency F 0 A rate stabilization device characterized by operating in a rate correction mode that corrects the rate while pseudo-randomly hopping between multiple frequencies of ±ΔF_ppm centered on twice the frequency of the given frequency.

5. A rate stabilization device according to claim 1, characterized in that it operates in a chirp search mode in which a burst that chirp sweeps the frequency is injected to relock only when the phase difference exceeds a predetermined threshold.

6. In the apparatus according to any one of claims 1 to 5, The average current consumption I_avg is measured, and I_avg is the first threshold I 1 Select the rate correction mode described in claim 3 if less than I 1 The above is the second threshold I 2 Select the rate correction mode described in claim 4 if less than I 2 The rate stabilizer is characterized by comprising a mode management circuit that selects the chirp search mode described in claim 5.

7. In the apparatus according to claim 6, I_avg is the third threshold I 3 A rate stabilization device characterized by prohibiting the chirp sweep described in claim 5 if the value exceeds or the battery level is less than 30%.

8. A rate stabilization device according to any one of claims 1 to 5, characterized in that the displacement of the actuator is within ±200 nm, and this displacement causes a decrease in the temperature quality coefficient of less than 1%.

9. In a rate stabilization device for mechanical watches that does not modify the hairspring, a) Fundamental driver that generates a drive signal synchronized with the template specific frequency F 0 and b) Actuator and, c) The pulse width tp, amplitude Vp, and duty cycle D output by the fundamental driver. 0 A pulse generator drives the actuator to inject symmetrical pulse energy into the temperature into two phase windows of phase 0 degrees ± δ and 180 degrees ± δ, while each of these is kept constant. d) A monitoring circuit that ensures the drive is performed only under the condition that the continuous time T_cond does not exceed 6 hours, and that pulse injection is stopped if the temp amplitude exceeds the upper limit θ_max (75 degrees) during execution. e) A conditioning control circuit that, only when the execution conditions for the drive are met, roughly adjusts the frequency of the Temp to within ±1000 ppm, The pulse width tp, amplitude Vp, and duty cycle D are maintained during and after the drive. 0 A rate stabilization device characterized by not changing the rigidity or damping of the balance wheel and hairspring, and not periodically modulating them.

10. A rate stabilization device according to claim 9, wherein the conditioning control circuit automatically switches to the rate correction mode according to any one of claims 1 to 4 or the chirp search mode according to claim 5 when the Temp amplitude has decayed to a reference amplitude after the end of the drive.