Indication device

Abstract

To provide a display device that can achieve high PPI and high resolution. [Solution] An embodiment of the present specification includes a first light-emitting element and a second light-emitting element, a drive transistor connected between a first node and a third node to control the drive current flowing to the first light-emitting element and the second light-emitting element, a first mode selection unit connected between the first node and a first power supply line supplying a first power supply voltage and operating by a mode signal, and a second mode selection unit connected between the third node and the first light-emitting element and the second light-emitting element and operating by a mode signal.

Description

Technical Field

[0001] This specification relates to a display device, and more particularly, to a display device capable of achieving a high PPI (Pixels Per Inch; PPI) and a high resolution.

Background Art

[0002] Generally, display devices are widely used as display screens of various electronic devices such as mobile communication terminals, electronic notebooks, e-books, PMPs (Portable Multimedia Players), navigations, UMPCs (Ultra Mobile PCs), mobile phones, smartphones, tablet PCs (Personal Computers), watch phones, electronic pads, wearable devices, watch phones, portable information devices, navigations, vehicle control display devices, televisions, notebook computers, and monitors.

[0003] In recent years, research and development have been conducted on display devices capable of reducing the bezel area where an image is not displayed with the same size of the display panel and implementing the maximum screen.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by this specification is to provide a display device capable of implementing a high PPI (Pixels Per Inch; PPI) and a high resolution.

[0005] Another problem to be solved by this specification is to provide a display device with a reduced bezel area.

[0006] The problems of this specification are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0007] A display device according to one embodiment of this specification includes a first light-emitting element and a second light-emitting element, a drive transistor connected between a first node and a third node to control the drive current flowing to the first light-emitting element and the second light-emitting element, a first mode selection unit connected between the first node and a first power supply line supplying a first power supply voltage and operating by a mode signal, and a second mode selection unit connected between the third node and the first light-emitting element and the second light-emitting element and operating by a mode signal.

[0008] A display device according to another embodiment of this specification includes a substrate including a display area on which a plurality of subpixels are arranged and a non-display area surrounding the display area, and a gate drive unit arranged in the non-display area, each of the plurality of subpixels comprising a first light-emitting element and a second light-emitting element, a drive transistor connected between a first node and a third node, a first transistor connected between the third node and a second node corresponding to the gate electrode of the drive transistor, a second transistor connected between a data line to which a data signal is applied and the first node, a third transistor connected between a first power supply line supplying a first power supply voltage and the first node and operating by a first mode signal, and a fourth transistor connected between the first power supply line and the first node and operating by a second mode signal The device includes a starter transistor, a fifth transistor connected between the drive transistor and the first light-emitting element and operated by a first mode signal, a sixth transistor connected between the drive transistor and the second light-emitting element and operated by a second mode signal, a seventh transistor connected between the second power supply line supplying a second power supply voltage and the first node, an eighth transistor connected between the third power supply line supplying a third power supply voltage and the fourth node corresponding to the first electrode of the first light-emitting element, a ninth transistor connected between the third power supply line and the fifth node corresponding to the first electrode of the second light-emitting element, a tenth transistor connected between the fourth power supply line supplying a fourth power supply voltage and the second node, and a storage capacitor connected between the first power supply line and the second node.

[0009] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0010] This specification provides a display device that can achieve high PPI (Pixels Per Inch; PPI) and high resolution by reducing the number of wires arranged around a pixel.

[0011] This specification provides a display device that reduces the bezel area by reducing the number of gate drive units.

[0012] The effects described herein are not limited to those exemplified above, and a wider variety of effects are included within this specification. [Brief explanation of the drawing]

[0013] [Figure 1] This is a block diagram of a display device according to one embodiment of this specification. [Figure 2] This is a block diagram of the gate drive unit of a display device according to one embodiment of this specification. [Figure 3] This is a plan view of a display device according to one embodiment of this specification. [Figure 4] This is a circuit diagram for a subpixel of a display device according to one embodiment of this specification. [Figure 5a] This is a waveform diagram illustrating the sub-pixel circuit in Figure 4. [Figure 5b] This is a waveform diagram illustrating the sub-pixel circuit in Figure 4. [Figure 6] This is a schematic diagram of a subpixel of a display device according to another embodiment of this specification. [Figure 7] This is a plan view of the subpixels of a display device according to yet another embodiment of this specification. [Figure 8] Figure 7 is a circuit diagram for a subpixel. [Figure 9] This is a plan view of the subpixels of a display device according to yet another embodiment of this specification. [Figure 10] Figure 9 is a circuit diagram for the subpixel. [Modes for carrying out the invention]

[0014] The advantages and features of this specification, and the methods for achieving them, will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, and can be embodied in various different forms. Merely, these embodiments are provided so that the disclosure of this specification is complete, and to fully inform those with ordinary knowledge in the technical field to which this specification pertains of the scope of the invention.

[0015] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary, so this specification is not limited to the matters illustrated. Throughout the specification, the same reference numerals refer to the same components. Also, when explaining this specification, if it is determined that a detailed description of related known technologies may muddy the gist of this specification, that detailed description will be omitted. When terms such as "including", "having", "being made" are used in this specification, unless "only" is used, other parts can be added. When a component is expressed in the singular, unless there is a specific description to the contrary, it includes the case of including a plurality.

[0016] When interpreting a component, it is interpreted as including an error range even without a separate explicit description.

[0017] In the case of an explanation regarding a positional relationship, for example, when a positional relationship between two parts is described such as "on ~", "above ~", "below ~", "next to ~", etc., unless "immediately" or "directly" is used, one or more other parts may be positioned between the two parts.

[0018] An element or layer being referred to as "on" another element or layer includes both the case of being immediately above the other element and the case of having another layer or another element intervening in the middle.

[0019] Also, although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical idea of this specification.

[0020] Throughout the specification, the same reference numerals refer to the same components.

[0021] The area and thickness of each configuration shown in the drawings are shown for the convenience of explanation, and this specification is not necessarily limited to the area and thickness of the shown configuration.

[0022] The respective features of the various embodiments of this specification can be partially or wholly combined or combined with each other, enabling various technical linkages and drives, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0023] Hereinafter, this specification will be described with reference to the drawings.

[0024] FIG. 1 is a block diagram of a display device according to an embodiment of this specification.

[0025] The display device 100 according to an embodiment of this specification may apply an electroluminescent display device. The electroluminescent display device may utilize an organic light emitting diode display device, a quantum dot light emitting diode display device, or an inorganic light emitting diode display device.

[0026] Referring to Figure 1, the display device 100 can include a display panel PN, a data drive unit DD, a gate drive unit GD, and a timing controller TC.

[0027] The display panel PN can generate an image to be presented to the user. For example, the display panel PN can generate and display an image presented to the user through a pixel PX in which multiple sub-pixel circuits are arranged.

[0028] The data drive unit DD, gate drive unit GD, and timing controller TC can provide signals for the operation of each pixel PX through signal wiring. The signal wiring may include, for example, data wiring DL and gate wiring GL.

[0029] Data routing DL may be arranged in the column direction and include multiple routings connected to pixels PX arranged in one column direction, and gate routing GL may be arranged in the row direction and include multiple routings connected to pixels PX arranged in one row direction.

[0030] In some cases, the display device 100 may further include a power supply unit. In such cases, power supply voltages for driving the pixels PX may be provided through power supply wiring connecting the power supply unit and the display panel PN. For example, the power supply unit may provide a high-potential drive voltage, a low-potential drive voltage, and an initialization voltage to the pixels PX. The high-potential drive voltage, low-potential drive voltage, and initialization voltage may be constant voltages at a certain level. The power supply unit may also provide power supply voltages to the data drive unit DD and the gate drive unit GD. The data drive unit DD and the gate drive unit GD can be driven based on the power supply voltages provided by the power supply unit.

[0031] For example, the data drive unit DD can apply a data signal to each pixel PX through the data wiring DL, the gate drive unit GD can apply a gate signal to each pixel PX through the gate wiring GL, and the power supply unit can supply a power voltage to each pixel PX through the power supply voltage wiring.

[0032] The timing controller TC can control the data drive unit DD and the gate drive unit GD. For example, the timing controller TC can realign digital video data input from an external source to match the resolution of the display panel PN and supply it to the data drive unit DD.

[0033] The data drive unit DD can convert digital video data input from the timing controller TC into analog data voltages based on data control signals and supply them to numerous data wirings DL.

[0034] The gate drive unit GD can generate scan signals and mode signals based on gate control signals. The gate drive unit GD may include a scan drive unit and a mode signal drive unit. The scan drive unit can generate and supply scan signals to scan wiring in a row-by-row manner to drive at least one scan wiring connected for each row of pixels. The mode signal drive unit can generate and supply mode signals to mode signal wiring in a row-by-row manner to drive at least one mode signal wiring connected for each row of pixels.

[0035] Depending on the embodiment, the gate driver unit GD may be arranged on the display panel PN using a GIP (Gate-driver In Panel) method. For example, the gate driver unit GD may be divided into multiple units and arranged on at least two sides of the display panel PN.

[0036] The display panel PN may include a display area and a non-display area surrounding the display area.

[0037] The display area of ​​the display panel PN may include multiple pixels PX arranged in the row and column directions. Pixels PX may be located in areas where multiple data lines DL and multiple gate lines GL intersect.

[0038] A single pixel PX can contain multiple subpixels that emit different colors from each other. For example, a pixel PX can use three subpixels to embody blue, red, and green. However, it is not limited to this, and a pixel PX may, in some cases, contain additional subpixels to further embody a specific color (e.g., white).

[0039] In a pixel PX, the area that embodies blue can be called a blue subpixel, the area that embodies red can be called a red subpixel, and the area that embodies green can be called a green subpixel.

[0040] Each of the multiple subpixels includes a first light-emitting element and a second light-emitting element that emit the same color, and may include a first lens that refracts light from the first light-emitting element in a specific direction and a second lens that refracts light from the second light-emitting element in a specific direction. Thus, the first and second lenses can limit the field of view of each of the multiple subpixels.

[0041] A detailed explanation of the first and second lenses will be provided later, with reference to Figure 3.

[0042] A non-display area may be located around the display area. The non-display area may contain various components for driving multiple subpixels located on a pixel PX. For example, the non-display area may contain signal wiring for transmitting signals, power wiring for applying power, and at least a portion of the gate drive unit GD. The non-display area may be referred to as the bezel area.

[0043] Figure 2 is a block diagram of the gate drive unit of a display device according to one embodiment of this specification. In Figure 2, for the convenience of the invention, only the gate drive unit GD for one pixel line is shown.

[0044] Referring to Figure 2, the gate drive unit GD is symmetrically arranged in the non-display areas NA on both sides of the display area AA, and can supply scan signals and mode signals to multiple pixels PX.

[0045] Each gate drive unit GD may include a first scan drive unit SC1(n), a second scan drive unit SC2(n), a third scan drive unit SC3(n), a fourth scan drive unit SC4(n), a first mode drive unit MC1(n), and a second mode drive unit MC2(n). Each of the first scan drive unit SC1(n), second scan drive unit SC2(n), third scan drive unit SC3(n), fourth scan drive unit SC4(n), first mode drive unit MC1(n), and second mode drive unit MC2(n) may include multiple stages.

[0046] Each gate drive unit GD may be arranged in the following order from a position adjacent to the display area AA: second scan drive unit SC2(n), first scan drive unit SC1(n), third scan drive unit SC3(n), fourth scan drive unit SC4(n), second mode drive unit MC2(n), and first mode drive unit MC1(n). However, this is not limiting and may be modified by design.

[0047] The first scan drive unit SC1(n) can output the first scan signal (SCAN1(n) in Figure 4) through the first scan line SL1. The second scan drive unit SC2(n) can output the second scan signal (SCAN2(n) in Figure 4) through the second scan line SL2. The third scan drive unit SC3(n) can output the third scan signal (SCAN3(n) in Figure 4) through the third scan line SL3. The fourth scan drive unit SC4(n) can output the fourth scan signal (SCAN4(n) in Figure 4) through the fourth scan line SL4. The first mode drive unit MC1(n) can output the first mode signal (S(n) in Figure 4) through the first mode line ML1. The second mode drive unit MC2(n) can output the second mode signal (P(n) in Figure 4) through the second mode line ML2.

[0048] One of the first scan drive unit SC1(n), second scan drive unit SC2(n), third scan drive unit SC3(n), and fourth scan drive unit SC4(n) may be composed of a shift resist circuit, while the remaining scan drive units, first mode drive unit MC1(n) and second mode drive unit MC2(n), may be composed of edge trigger circuits. For example, the second scan drive unit SC2(n) may be composed of a shift resist circuit, and the first scan drive unit SC1(n), third scan drive unit SC3(n), fourth scan drive unit SC4(n), first mode drive unit MC1(n), and second mode drive unit MC2(n) may be composed of edge trigger circuits. However, this is not limiting, and may be modified by design.

[0049] The first scan signal SC1(n) can be used to drive a transistor (e.g., a compensation transistor) included in the sub-pixel circuit. The second scan signal SC2(n) can be used to drive a transistor (e.g., a data supply transistor) included in the sub-pixel circuit. The third scan signal SC3(n) can be used to drive a transistor (e.g., a bias transistor) included in the sub-pixel circuit. The fourth scan signal SC4(n) can be used to drive a transistor (e.g., an initialization transistor) included in the sub-pixel circuit. The first mode signal S(n) and the second mode signal P(n) can be used to drive a transistor (e.g., a light emission control transistor) included in the sub-pixel circuit. For example, by using the first mode signal S(n) and the second mode signal P(n) to control the light emission control transistor of a pixel, multiple light-emitting elements can be selectively made to emit light.

[0050] Figure 3 is a plan view of a display device according to one embodiment of this specification. Figure 3 shows the plane of the pixel region PA when three subpixels are arranged in the pixel region PA.

[0051] Referring to Figure 3, the pixel region PA can include a blue subpixel region BPA that embodies blue, a red subpixel region RPA that embodies red, and a green subpixel region GPA that embodies green. Depending on the embodiment, the blue subpixel region BPA may correspond to the first subpixel, the red subpixel region RPA to the second subpixel, and the green subpixel region GPA to the third subpixel. Each subpixel may be associated with a subpixel circuit. A corresponding subpixel circuit may be arranged for each subpixel.

[0052] The pixel region PA may include first lens regions BWE, RWE, GWE and second lens regions BNE, RNE, GNE, which provide different viewing angles from each other.

[0053] The first lens regions BWE, RWE, and GWE may contain a first light-emitting element (first light-emitting element ED1 in Figure 4) and first lenses BWR, RWR, and GWR. The first lenses BWR, RWR, and GWR may be positioned on the first lens regions BWE, RWE, and GWR of each pixel region PA. For example, light generated by the first light-emitting element ED1 of each pixel region PA may be emitted through the first lenses BWR, RWR, and GWR of the corresponding pixel region PA. The first lenses BWR, RWR, and GWR may have a shape that does not restrict light in at least one direction. The first lenses BWR, RWR, and GWR can provide a first-value field of view. For example, the planar shape of the first lenses BWR, RWR, and GWR located within each pixel region PA may have a bar shape extending in a first direction.

[0054] In such cases, the direction of light propagation emitted from the first lens areas BWE, RWE, and GWE of the pixel area PA does not need to be restricted to the first direction. For example, content (or images) provided through the first lens areas BWE, RWE, and GWE of the pixel area PA can be shared with the user and people in the surrounding area adjacent to them in the first direction. When content is provided through the first lens areas BWE, RWE, and GWE, the mode of providing content to a first field of view range that is wider than the second field of view range provided by the second lens areas BNE, RNE, and GNE may be called the first mode or wide field of view mode.

[0055] The second lens regions BNE, RNE, and GNE may contain a second light-emitting element (second light-emitting element ED2 in Figure 4) and second lenses BNR, RNR, and GNR. The second lenses BNR, RNR, and GNR may be located on the second lens regions BNE, RNE, and GNE of each pixel region PA. Light generated by the second light-emitting element ED2 of the pixel region PA may be emitted through the second lenses BNR, RNR, and GNR of the corresponding pixel region PA. The second lenses BNR, RNR, and GNR may restrict the direction of light propagation to a first direction and / or a second direction. The second lenses BNR, RNR, and GNR may provide a second-value field of view. For example, the planar shape of the second lenses BNR, RNR, and GNR located within the pixel region PA may be circular.

[0056] In such cases, the direction of light propagation emitted from the second lens regions BNE, RNE, and GNE of the pixel region PA may be restricted to the first and second directions. For example, content provided by the second lens regions BNE, RNE, and GNE of the pixel region PA may not be shared with people around the user. When content is provided through the second lens regions BNE, RNE, and GNE, the mode of providing content to a second field of view range that is narrower than the first field of view range provided by the first lens regions BWE, RWE, and GWE may be referred to as the second mode or narrow field of view mode.

[0057] The first lens regions BWE, RWE, and GWE of the pixel region PA may contain one first lens BWR, RWR, or GWR and one first light-emitting element (first light-emitting element ED1 in Figure 4). The second lens regions BNE, RNE, and GNE of the pixel region PA may contain a second light-emitting element (second light-emitting element ED2 in Figure 4) and a number of second lenses BNR, RNR, and GNR.

[0058] Figure 4 is a circuit diagram for a subpixel of a display device according to one embodiment of this specification. Figure 4 shows an exemplary subpixel circuit applicable to the subpixel circuit of a display device according to one embodiment of this specification.

[0059] Referring to Figure 4, the sub-pixel circuit can drive the first light-emitting element ED1 and the second light-emitting element ED2 by controlling the drive current flowing to them. The sub-pixel circuit may include a drive transistor DT, first to tenth transistors T1 to T10, and a storage capacitor Cst. Each of the transistors DT and T1 to T10 may include a first electrode, a second electrode, and a gate electrode. One of the first and second electrodes may be the source electrode, and the other of the first and second electrodes may be the drain electrode.

[0060] Each of the transistors DT and T1-T10 may be a P-type thin-film transistor or an N-type thin-film transistor. In the embodiment shown in Figure 4, the first transistor T1 and the tenth transistor T10 are N-type thin-film transistors, and the remaining transistors DT and T2-T9 are P-type thin-film transistors. However, the embodiment is not limited to this, and depending on the embodiment, all or part of transistors DT and T1-T10 may be P-type thin-film transistors or N-type thin-film transistors. Furthermore, the N-type thin-film transistors may be oxide thin-film transistors, and the P-type thin-film transistors may be polycrystalline silicon thin-film transistors.

[0061] In the following explanation, the first transistor T1 and the tenth transistor T10 are N-type thin-film transistors, while the remaining transistors DT, T2 to T9 are P-type thin-film transistors. Therefore, the first transistor T1 and the tenth transistor T10 turn on when a high voltage is applied, while the remaining transistors DT, T2 to T9 turn on when a low voltage is applied.

[0062] For example, the first transistor T1 constituting the sub-pixel circuit can function as a compensation unit, the second transistor T2 as a data supply unit, the third transistor T3 and fourth transistor T4 as a first mode selection unit, the fifth transistor T5 and sixth transistor T6 as a second mode selection unit, the seventh transistor T7 as a bias unit, and the eighth to tenth transistors T8, T9, and T10 as an initialization unit.

[0063] The first light-emitting element ED1 and the second light-emitting element ED2 may include an anode electrode and a cathode electrode. For example, the anode electrode of the first light-emitting element ED1 may be connected to a fourth node N4, and the cathode electrode may be connected to a low-potential drive voltage VSS. For example, the anode electrode of the second light-emitting element ED2 may be connected to a fifth node N5, and the cathode electrode may be connected to a low-potential drive voltage VSS.

[0064] The drive transistor DT may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode connected to the second node N2. The drive transistor DT can supply a drive current to the first light-emitting element ED1 and the second light-emitting element ED2 based on the voltage at the second node N2 (or the data voltage held in the storage capacitor Cst, described later).

[0065] The first transistor T1 may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode that receives the first scan signal Scan1(n). The first transistor T1 is turned on in response to the first scan signal Scan1(n) and can sample the threshold voltage Vth of the drive transistor DT by being diode-connected between the second node N2 and the third node N3.

[0066] A storage capacitor Cst may be connected between a second node N2 and a first power supply voltage line VDDL to which a first power supply voltage VDD is applied. For example, the first power supply voltage VDD may be a high-potential drive voltage, and the first power supply voltage line VDDL may be a high-potential drive voltage line. The storage capacitor Cst can hold or maintain the provided high-potential drive voltage VDD.

[0067] The second transistor T2 may include a first electrode connected to the data line DL, a second electrode connected to the first node N1, and a gate electrode that receives the second scan signal Scan2(n). The second transistor T2 can be turned on in response to the second scan signal Scan2(n) and transmit the data voltage VDATA to the first node N1.

[0068] The third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are connected between the high-potential drive voltage line VDDL and the first light-emitting element ED1 and the second light-emitting element ED2, forming a current transfer path through which the drive current Id generated by the drive transistor DT travels.

[0069] The third transistor T3 may include a first electrode connected to the high-potential drive voltage line VDDL and receiving the high-potential drive voltage VDD, a second electrode connected to the first node N1, and a gate electrode connected to the first mode signal line ML1 and receiving the first mode signal S(n).

[0070] The fourth transistor T4 may include a first electrode connected to the high-potential drive voltage line VDDL and receiving the high-potential drive voltage VDD, a second electrode connected to the first node N1, and a gate electrode connected to the second-mode signal line ML2 and receiving the second-mode signal P(n).

[0071] When driven in the first mode, the fifth transistor T5 can form a current path between the drive transistor DT and the first light-emitting element ED1. The fifth transistor T5 may include a first electrode connected to the third node N3, a second electrode connected to the fourth node N4, and a gate electrode connected to the first mode signal line ML1 to receive the first mode signal S(n). In this case, the fourth node N4 may be connected to the anode electrode of the first light-emitting element ED1.

[0072] The fifth transistor T5 can be turned on or turned off by the first mode signal S(n). Therefore, the fifth transistor T5 can form a current path between the third node N3 and the first light-emitting element ED1 in response to a low-level first mode signal S(n), which is the turn-on level. That is, the fifth transistor T5 can form a current path between the drive transistor DT and the first light-emitting element ED1 in response to a low-level first mode signal S(n). Therefore, the fifth transistor T5 can also be referred to as the first light-emitting control transistor that controls the light emission of the first light-emitting element ED1.

[0073] That is, the third transistor and the fifth transistors T3 and T5 are turned on in response to the first mode signal S(n), in which case a drive current Id is supplied to the first light-emitting element ED1, and the first light-emitting element ED1 can emit light with a brightness corresponding to the drive current Id.

[0074] When driven in second mode, the sixth transistor T6 can form a current path between the drive transistor DT and the second light-emitting element ED2. The sixth transistor T6 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5, and a gate electrode connected to the second mode signal line ML2 to receive the second mode signal P(n). In this case, the fifth node N5 may be connected to the anode electrode of the second light-emitting element ED2.

[0075] The sixth transistor T6 can be turned on or turned off by the second mode signal P(n). Therefore, the sixth transistor T6 can form a current path between the third node N3 and the second light-emitting element ED2 in response to a low-level second mode signal P(n), which is the turn-on level. That is, the sixth transistor T6 can form a current path between the drive transistor DT and the second light-emitting element ED2 in response to a low-level second mode signal P(n). Therefore, the sixth transistor T6 can also be referred to as a second light-emitting control transistor that controls the light emission of the second light-emitting element ED2.

[0076] That is, the fourth transistor and the sixth transistors T4 and T6 are turned on in response to the second mode signal P(n), in which case a drive current Id is supplied to the second light-emitting element ED2, and the second light-emitting element ED2 can emit light with a brightness corresponding to the drive current Id.

[0077] The seventh transistor T7 may include a first electrode connected to a second power supply voltage line VOBSL to which the second power supply voltage VOBS is applied, a second electrode connected to the first node N1, and a gate electrode that receives the third scan signal Scan3(n). For example, the second power supply voltage VOBS may be a bias voltage, and the second power supply voltage line VOBSL may be a bias voltage line.

[0078] The eighth transistor T8 may include a first electrode connected to a third power supply voltage line VARL to which the third power supply voltage VAR is applied, a second electrode connected to the fourth node N4, and a gate electrode that receives the third scan signal SCAN3(n). For example, the third power supply voltage VAR may be a first initialization voltage, and the third power supply voltage line VARL may be a first initialization voltage line.

[0079] The ninth transistor T9 may include a first electrode connected to a third power supply voltage line VARL to which the third power supply voltage VAR is applied, a second electrode connected to the fifth node N5, and a gate electrode that receives the third scan signal SCAN3(n). For example, the third power supply voltage VAR may be a first initialization voltage, and the third power supply voltage line VARL may be a first initialization voltage line.

[0080] The eighth transistor T8 and the ninth transistor T9 are turned on in response to the third scan signal Scan3(n) before the first light-emitting element ED1 and the second light-emitting element ED2 emit light (or after the first light-emitting element ED1 and the second light-emitting element ED2 emit light), and the first initialization voltage VAR can be used to initialize the anode electrodes (or pixel electrodes) of the first light-emitting element ED1 and the second light-emitting element ED2. The first light-emitting element ED1 and the second light-emitting element ED2 may have parasitic capacitors formed between their anode and cathode electrodes. While the first light-emitting element ED1 and the second light-emitting element ED2 are emitting light, the parasitic capacitors are charged, and the anode electrodes of the first light-emitting element ED1 and the second light-emitting element ED2 can have a specific voltage. Therefore, by applying the first initialization voltage VAR to the anode electrodes of the first light-emitting element ED1 and the second light-emitting element ED2 through the eighth transistor T8 and the ninth transistor T9, the amount of charge accumulated in the first light-emitting element ED1 and the second light-emitting element ED2 can be initialized.

[0081] In this embodiment, the gate electrodes of the eighth transistor T8 and the ninth transistor T9 are configured to receive the third scan signal SCAN3(n) in common. However, the configuration is not necessarily limited to this, and the gate electrodes of the eighth transistor T8 and the ninth transistor T9 may be configured to receive separate scan signals and be controlled independently.

[0082] The tenth transistor T10 may include a first electrode connected to a fourth power supply voltage line VINIL to which the fourth power supply voltage VINI is applied, a second electrode connected to a second node N2, and a gate electrode that receives the fourth scan signal SCAN4(n). For example, the fourth power supply voltage VINI may be a second initialization voltage, and the fourth power supply voltage line VINIL may be a second initialization voltage line.

[0083] The tenth transistor T10 is turned on in response to the fourth scan signal SCAN4(n), and the second initialization voltage VINI can be used to initialize the gate electrode of the drive transistor DT. Unwanted charge may remain on the gate electrode of the drive transistor DT due to the high potential drive voltage VDD held in the storage capacitor Cst. Therefore, the amount of residual charge can be initialized by applying the second initialization voltage VINI to the gate electrode of the drive transistor DT through the tenth transistor T10.

[0084] Figures 5a and 5b are waveform diagrams illustrating the sub-pixel circuit of Figure 4. Figures 5a and 5b illustrate the operation of the scan signal and mode signal during the refresh period in the sub-pixel circuit. Figure 5a illustrates the operation of the first mode, and Figure 5b illustrates the operation of the second mode.

[0085] The display device according to the embodiment of this specification can operate as a VRR (variable refresh rate) mode display device. VRR mode operates at a constant frequency and can increase the refresh rate at which the data voltage VDATA is updated when high-speed operation is required to operate the pixels, or decrease the refresh rate at times when power consumption is reduced or low-speed operation is required to operate the pixels.

[0086] Each of the multiple pixels PX may be driven through a combination of a 1-second refresh frame and a 1-second hold frame. In this specification, a set is defined as a repeating combination of a refresh period in which the data voltage VDATA is updated for 1 second and a hold period in which the data voltage VDATA is not updated. A set period can be the period in which the combination of refresh and hold periods is repeated.

[0087] When the refresh rate is driven at 120Hz, it can be driven solely by the refresh period. That is, 120 refresh periods can be driven within one second. One refresh period is 1 / 120 = 8.33ms, and one set period is also 8.33ms.

[0088] When the refresh rate is driven at 60Hz, the refresh period and hold period can be driven alternately. That is, the refresh period and hold period can be driven alternately 60 times each within 1 second. The duration of one refresh period and one hold period is 0.5 / 60 = 8.33ms, and the duration of one set period is 16.66ms.

[0089] When the refresh rate is 1Hz, one frame can be driven by one refresh period followed by 119 hold periods. Alternatively, when the refresh rate is 1Hz, one frame can be driven by multiple refresh periods and multiple hold periods. In this case, the duration of each refresh period and hold period is 1 / 120 = 8.33ms, and one set is 1s.

[0090] During the refresh period, a new data voltage VDATA is charged and applied to the drive transistor DT, whereas during the hold period, the data voltage VDATA from the previous frame is maintained and used as is. On the other hand, the hold period can also be called a skip period, as the process of applying a new data voltage VDATA to the drive transistor DT is omitted.

[0091] Each of the multiple pixels PX can initialize the voltage charged or remaining within the sub-pixel circuit during the refresh period. Specifically, each of the multiple pixels PX can remove the influence of the data voltage VDATA and high-potential drive voltage VDD held in the previous frame during the refresh period. Therefore, each of the multiple pixels PX can display the image corresponding to the new data voltage VDATA during the hold period.

[0092] Each of the multiple pixels PX can display an image by providing a drive current corresponding to the data voltage VDATA to the first light-emitting element ED1 or the second light-emitting element ED2 during the hold period, and can maintain the turn-on state of the first light-emitting element ED1 or the second light-emitting element ED2.

[0093] Referring to Figures 5a and 5b, the difference in the drive signals between the first mode and the second mode lies in the first mode signal S(n) and the second mode signal P(n). In the first mode, only the first light-emitting element ED1 may emit light, and in the second mode, only the second light-emitting element ED2 may emit light. In the first mode, the second mode signal P(n), which controls the emission of light from the second light-emitting element ED2, is output only at a high level, which is the turn-off level, so that only the first light-emitting element ED1 emits light. In the second mode, the first mode signal S(n), which controls the emission of light from the first light-emitting element ED1, may be output only at a high level, which is the turn-off level, so that only the second light-emitting element ED2 emits light.

[0094] Referring to Figures 5a and 5b, the refresh period in the first and second modes may include at least one bias interval Tobs1, Tobs2, initialization interval Ti, sampling interval Ts, and emission interval Te, but this is merely an example and is not necessarily limited to this order.

[0095] Referring to Figure 5a, the refresh period may include at least one bias interval, Tobs1, Tobs2.

[0096] At least one bias section, Tobs1, Tobs2, is a section in which on-bias stress operation (OBS) is performed with the bias voltage VOBS applied.

[0097] In the first bias section Tobs1 and the second bias section Tobs2, the first mode signal S(n) and the second mode signal P(n) are at high voltage, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. The first scan signal SCAN1(n) is at high voltage, and the first transistor T1 is turned on. The second scan signal SC2 is at high voltage, and the fourth scan signal SCAN4(n) is at low voltage, and the second transistor T2 and the tenth transistor T10 are turned off. The third scan signal SC3(n) is input at low voltage, and the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on. When the seventh transistor T7 is turned on, the bias voltage VOBS is applied to the first electrode of the drive transistor DT connected to the first node N1.

[0098] Here, the bias voltage VOBS is supplied to the third node N3, which is the second electrode of the drive transistor DT, thereby reducing the charging time or charging delay of the voltages at the fourth node N4 and fifth node N5, which are the anode electrodes of the first light-emitting element ED1 and the second light-emitting element ED2, during the light-emitting period. At this time, the drive transistor DT will maintain an even stronger saturation state.

[0099] For example, as the bias voltage VOBS increases, the voltage at the third node N3, which is the drain electrode of the drive transistor DT, may increase, and the gate-source voltage or drain-source voltage of the drive transistor DT may decrease. Therefore, it is preferable that the bias voltage VOBS is at least greater than the data voltage VDATA.

[0100] In this case, the magnitude of the drive current Id passing through the drive transistor DT may decrease, reducing the stress on the drive transistor DT under positive bias stress conditions and eliminating the charging delay of the third node N3 voltage. In other words, performing on-bias stress operation (OBS) before sampling the threshold voltage Vth of the drive transistor DT can mitigate the hysteresis of the drive transistor DT.

[0101] Therefore, on-bias stress operation (OBS) can be defined as the operation of directly applying a suitable bias voltage to the drive transistor DT during the non-emitting period in at least one bias interval, Tobs1, Tobs2.

[0102] Furthermore, when the eighth transistor T8 and the ninth transistor T9 are turned on in at least one bias section Tobs1 and Tobs2, the anode electrode (or pixel electrode) of the first light-emitting element ED1 connected to the fourth node N4 and the anode electrode (or pixel electrode) of the second light-emitting element ED2 connected to the fifth node N5 are initialized to the first initialization voltage VAR.

[0103] However, the gate electrodes of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 may be configured to receive separate scan signals and be controlled independently. That is, it is not required that the bias voltage be applied simultaneously to the first electrode of the drive transistor DT and the anode electrodes of the first light-emitting element ED1 and the second light-emitting element ED2 during the bias section.

[0104] Referring to Figure 5a, the sub-pixel circuit may operate with an initialization interval Ti during the refresh period. The initialization interval Ti is the period in which the voltage of the gate electrode of the drive transistor DT is initialized.

[0105] The first scan signal SCAN1(n), the second scan signal SCAN2(n), the third scan signal SCAN3(n), the fourth scan signal SCAN4(n), the first mode signal S(n), and the second mode signal P(n) are high voltage, and the first transistor T1 and the tenth transistor T10 are turned on. The second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off. When the first transistor T1 and the tenth transistor T10 are turned on, the gate electrode and the second electrode of the drive transistor DT connected to the second node N2 are initialized to the second initialization voltage VINI.

[0106] Referring to Figure 5a, the sub-pixel circuit may operate with a sampling interval Ts during the refresh period. The sampling interval Ts is the interval over which the threshold voltage Vth of the drive transistor DT is sampled.

[0107] The first scan signal SCAN1(n), the third scan signal SCAN3(n), the first mode signal S(n), and the second mode signal P(n) are high voltages, while the second scan signal SCAN2(n) and the fourth scan signal SCAN4(n) are low voltages. As a result, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off, the first transistor T1 remains on, and the second transistor T2 is turned on. That is, with the second transistor T2 turned on, a data voltage VDATA is applied to the drive transistor DT, and the first transistor T1 can sample the threshold voltage Vth of the drive transistor DT by being diode-connected between the second node N2 and the third node N3.

[0108] Referring to Figure 5a, the sub-pixel circuit may operate including an emission interval Te during the refresh period. The emission interval Te is the interval in which the first light-emitting element ED1 emits light with a drive current corresponding to the sampled threshold voltage Vth and the sampled data voltage.

[0109] The first mode signal S(n) is low voltage, and the third transistor T3 and the fifth transistor T5 are turned on.

[0110] When the third transistor T3 turns on, the high-potential drive voltage VDD is applied to the first electrode of the drive transistor DT connected to the first node N1 through the third transistor T3. The fifth transistor T5, which is turned on by the drive transistor DT, applies a drive current Id to the first light-emitting element ED1. At this time, the value of the threshold voltage Vth of the drive transistor DT becomes irrelevant, and the drive transistor DT operates with a drive current Id corresponding to the sampled data voltage, with the threshold voltage Vth of the drive transistor DT compensated. As a result, in the first mode, the drive current Id is applied only to the first light-emitting element ED1, and only the first light-emitting element ED1 emits light.

[0111] Referring to Figure 5b, in the second mode, the refresh period operates identically for the remaining section excluding the light emission section Te, so it is omitted here. The sub-pixel circuit may operate including the light emission section Te during the refresh period. The light emission section Te is the section in which the second light-emitting element ED2 is made to emit light with a drive current corresponding to the sampled threshold voltage Vth and the sampled data voltage.

[0112] The second-mode signal P(n) is low voltage, and the fourth transistor T4 and the sixth transistor T6 are turned on.

[0113] When the fourth transistor T4 turns on, the high-potential drive voltage VDD is applied to the first electrode of the drive transistor DT connected to the first node N1 through the fourth transistor T4. The sixth transistor T6, which is turned on by the drive transistor DT, applies a drive current Id to the second light-emitting element ED2. As a result, in the third mode, the drive current Id is applied only to the third light-emitting element ED3, and only the third light-emitting element ED3 emits light.

[0114] Existing display devices require numerous wires to apply drive signals and power supplies to drive the sub-pixel circuits. In particular, controlling multiple light emission control transistors requires separate light emission control wiring for each transistor, resulting in high wiring density within the pixel and limiting the achievement of high PPI (Pixels Per Inch) and high resolution.

[0115] As a result, the display device 100 according to one embodiment of this specification can achieve high PPI (Pixels Per Inch) and high resolution. Specifically, a third transistor T3 and a fourth transistor T4 are connected between the high-potential drive voltage line VDDL to which a high-potential drive voltage VDD is applied and the source electrode of the drive transistor DT, a fifth transistor T5 is connected between the drain electrode of the drive transistor DT and the first light-emitting element ED1, and a sixth transistor T6 is connected between the drain electrode of the drive transistor DT and the second light-emitting element ED2. The third transistor T3 and the fifth transistor T5 operate in accordance with the first mode signal S(n), and the fourth transistor T4 and the sixth transistor T6 operate in accordance with the second mode signal P(n) to cause the first light-emitting element ED1 and the second light-emitting element ED2 to emit light. Therefore, in the display device 100 according to one embodiment of this specification, the first light-emitting element ED1 or the second light-emitting element ED2 can be made to emit light by mode selection using only the first mode signal S(n) and the second mode signal P(n) without a separate light emission control signal. This reduces the number of wires arranged in the subpixels, lowers the wiring density in the pixel circuit, and improves the PPI (Pixels Per Inch) and resolution.

[0116] In existing display devices, the sub-pixel circuits that drive pixels require first to fourth scan signals and first to third light emission signals. Therefore, to provide these drive signals, first to fourth scan drive units and first to third light emission drive units are necessary. However, this leads to the problem that the area of ​​the non-display region of the display panel increases in order to accommodate the first to fourth scan drive units and first to third light emission drive units.

[0117] As a result, in the display device 100 according to one embodiment of this specification, the bezel area can be minimized. Specifically, the sub-pixel circuit includes a light-emitting transistor that operates only on a first mode signal S(n) and a second mode signal P(n), which reduces the number of drive signals required to drive the sub-pixel circuit. Therefore, in the display device 100 according to one embodiment of this specification, the number of drive signals required to drive the sub-pixel circuit can be reduced, and the number of gate drive units that generate the drive signals can be reduced, thereby minimizing the area of ​​the non-display region where the gate drive units are located, and thus minimizing the bezel area.

[0118] Figure 6 is a circuit diagram for a subpixel of a display device according to another embodiment of this specification. Figure 6 is a circuit diagram for the same subpixel as in Figure 4. When comparing Figure 6 with the subpixel circuit of Figure 4, the remaining components except for the boost capacitor Cbst are the same, so redundant explanations are omitted.

[0119] Referring to Figure 6, the subpixel circuit of the display device 200 according to other embodiments of this specification may further include a boost capacitor Cbst.

[0120] The boost capacitor Cbst may be connected between the second scan signal line to which the second scan signal SCAN2(n) is applied and the gate electrode of the drive transistor DT. For example, the first electrode of the boost capacitor Cbst may be connected to the second scan signal line to which the second scan signal SCAN2(n) is applied and the gate electrode of the second transistor T2, and the second electrode of the boost capacitor Cbst may be connected to the gate electrode of the drive transistor DT.

[0121] This allows the second scan signal SCAN2(n), held in the boost capacitor Cbst, to be applied to the gate electrode of the drive transistor DT. In other words, the voltage of the gate electrode of the drive transistor DT can be changed by the amount of the voltage change of the second scan signal SCAN2(n).

[0122] In the display device 200 according to other embodiments of this specification, the first light-emitting element ED1 or the second light-emitting element ED2 can be made to emit light by mode selection using only the first mode signal S(n) and the second mode signal P(n) without a separate light emission control signal. This reduces the number of wires arranged in the sub-pixel circuit, lowers the wiring density within the pixel circuit, and improves the PPI (Pixels Per Inch) and resolution.

[0123] In the display device 200 according to other embodiments of this specification, the drive signals for driving the subpixel circuits can be reduced and the gate drive unit that generates the drive signals can be reduced, thereby minimizing the area of ​​the non-display region where the gate drive unit is located and minimizing the bezel area.

[0124] In the display device 200 according to other embodiments of this specification, a boost capacitor Cbst is connected between the second scan signal line to which the second scan signal SCAN2(n) is applied and the gate electrode of the drive transistor DT, thereby changing the voltage applied to the gate electrode of the drive transistor DT by the voltage level of the second scan signal SCAN2(n). As a result, in the display device 200 according to other embodiments of this specification, the voltage applied to the gate electrode of the drive transistor DT can be changed faster by the voltage level of the second scan signal SCAN2(n), and the change to black hue can be made faster and more accurate.

[0125] Figure 7 is a plan view of a subpixel of a display device according to another embodiment of this specification. Figure 8 is a circuit diagram of the subpixel of Figure 7. Figure 7 is a diagram illustrating two pixels arranged adjacent to each other in the column direction. Figure 8 is a diagram illustrating two subpixel circuits arranged adjacent to each other in the column direction in Figure 7.

[0126] For the sake of clarity, in the following, the horizontal direction on a plane will be referred to as the first direction (or row direction), and the vertical direction on a plane will be referred to as the second direction (or column direction).

[0127] Referring to Figure 7, in the pixel area of ​​the display device 300 according to another embodiment of this specification, a plurality of data lines DL, at least one first power supply voltage line VDDL, and at least one third power supply voltage line VARL may be arranged in the first direction.

[0128] For example, three data lines DL connected to a red subpixel SPC1, a green subpixel, and a blue subpixel, respectively, may be arranged in the first direction, and one high-potential drive voltage line VDDL and one third power supply voltage line VARL may also be arranged in the first direction.

[0129] In the pixel region, a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, a second power supply voltage line VOBSL, third power supply voltage lines VARL_R and VARL_GB, a fourth power supply voltage line VINIL, a first mode line ML1, and a second mode line ML2 may be arranged in the second direction. For example, the third scan line SL3 may be arranged to overlap with the second power supply voltage line VOBSL, both on different layers. The fourth scan line SL4 may be arranged to overlap with the fourth power supply voltage line VINIL, both on different layers. For example, the first mode line ML1 may be arranged adjacent to the second mode line ML2. For example, the third power supply voltage line VARL_R, which supplies the third power supply voltage to the red subpixel, may be arranged to overlap with the third power supply voltage line VARL_GB, which supplies the third power supply voltage to the blue and green subpixels, both on different layers. However, this is not limited to these arrangements.

[0130] Referring to Figures 7 and 8, subpixels arranged adjacent to each other in the first direction may be arranged symmetrically with respect to the third power supply voltage lines VARL_R and VARL_GB. For example, the first subpixel SPC1 may be located above the third power supply voltage lines VARL_R and VARL_GB with respect to the third power supply voltage lines VARL_R and VARL_GB, and the second subpixel SPC2 may be located below the third power supply voltage lines VARL_R and VARL_GB. In this case, the drive transistor DT, the first to tenth transistors T1 to T10 and storage capacitor Cst that constitute the first subpixel SPC1 may be arranged symmetrically with respect to the third power supply voltage lines VARL_R and VARL_GB with respect to the drive transistor DT, the first to tenth transistors T1 to T10 and storage capacitor Cst that constitute the second subpixel SPC2.

[0131] The first subpixel SPC1 and the second subpixel SPC2 can share the third power supply voltage lines VARL_R and VARL_GB. For example, the first subpixel SPC1 and the second subpixel SPC2 may be red subpixels, and they can be connected to the third power supply voltage line VARL_R, which supplies the third power supply voltage to the red subpixels. For example, the eighth transistor T8 and the ninth transistor T9 of the first subpixel SPC1 and the second subpixel SPC2, respectively, can be connected to the third power supply voltage line VARL_R.

[0132] In another embodiment of the display device 300 described herein, the first light-emitting element ED1 or the second light-emitting element ED2 can be made to emit light by mode selection using only the first mode signal S(n) and the second mode signal P(n) without a separate light emission control signal. This reduces the number of wires arranged in the subpixels, lowers the density of wires within the subpixels, and improves the PPI (Pixels Per Inch) and resolution.

[0133] In another embodiment of the display device 300 described herein, the drive signals for driving the sub-pixel circuits can be reduced and the gate drive unit that generates the drive signals can be reduced, thereby minimizing the area of ​​the non-display region where the gate drive unit is located and minimizing the bezel area.

[0134] Existing display devices have a problem in that each sub-pixel has its own third power supply voltage line, VARL_R, and VARL_GB, and these lines are connected to each sub-pixel, resulting in a large number of wires being placed on each sub-pixel within the display area AA.

[0135] Therefore, in the display device 300 according to another embodiment of this specification, the first sub-pixel SPC1 and the second sub-pixel SPC2, which are arranged adjacent to each other in the first direction, are arranged symmetrically with respect to the third power supply voltage lines VARL_R and VARL_GB. The first sub-pixel SPC1 and the second sub-pixel SPC2 share the third power supply voltage lines VARL_R and VARL_GB. The first sub-pixel SPC1 and the second sub-pixel SPC2 are connected to the third power supply voltage lines VARL_R and VARL_GB. Thus, in the display device 300 according to another embodiment of this specification, the first sub-pixel SPC1 and the second sub-pixel SPC2, which are arranged adjacent to each other in the first direction, are connected by sharing one third power supply voltage line VARL_R and VARL_GB. This reduces the number of wires arranged in the sub-circuit and lowers the wiring density within the pixel circuit, thereby increasing the degree of design freedom or improving the PPI (Pixels Per Inch; PPI) and resolution.

[0136] Figure 9 is a plan view of a subpixel of a display device according to another embodiment of this specification. Figure 10 is a circuit diagram of the subpixel of Figure 9. Figure 9 is a diagram illustrating two pixels arranged adjacent to each other in the column direction. Figure 10 is a diagram illustrating two subpixel circuits arranged adjacent to each other in the column direction in Figure 9.

[0137] Referring to Figure 9, in the pixel area of ​​the display device 400 according to another embodiment of this specification, a plurality of data lines DL, at least one first power supply voltage line VDDL, and at least one third power supply voltage line VARL may be arranged in the first direction.

[0138] For example, three data lines DL connected to a red subpixel SPC1, a green subpixel circuit, and a blue subpixel circuit, respectively, may be arranged in the first direction, and one high-potential drive voltage line VDDL and one third power supply voltage line VARL may also be arranged in the first direction.

[0139] In the pixel region, a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, a second power supply voltage line VOBSL, third power supply voltage lines VARL_R and VARL_GB, a fourth power supply voltage line VINIL, a first mode line ML1, and a second mode line ML2 may be arranged in the second direction. For example, the third scan line SL3 may be arranged to overlap with the second power supply voltage line VOBSL, on different layers. For example, the first mode line ML1 may be arranged adjacent to the second mode line ML2. For example, the third power supply voltage line VARL_R, which supplies the third power supply voltage to the red subpixel, may be arranged to overlap with the third power supply voltage line VARL_GB, which supplies the third power supply voltage to the blue and green subpixels, on different layers. For example, the fourth scan line SL4 may be arranged to overlap with the fourth power supply voltage line VINIL, on different layers. However, it is not limited to these arrangements.

[0140] Referring to Figures 9 and 10, subpixels arranged adjacent to each other in the first direction may be arranged symmetrically with respect to each other. For example, a first subpixel SPC1 may be located above the fourth power supply voltage line VINIL with respect to the fourth power supply voltage line VINIL, and a second subpixel SPC2 may be located below the fourth power supply voltage line VINIL. In this case, the drive transistor DT, the first to tenth transistors T1 to T10 and the storage capacitor Cst constituting the first subpixel SPC1 may be arranged symmetrically with respect to the fourth power supply voltage line VINIL with respect to the drive transistor DT, the first to tenth transistors T1 to T10 and the storage capacitor Cst constituting the second subpixel SPC2.

[0141] The first subpixel SPC1 and the second subpixel SPC2 can share the fourth power supply voltage line VINIL. For example, the first subpixel SPC1 and the second subpixel SPC2 may be red subpixels, and the first subpixel SPC1 and the second subpixel SPC2 can be connected to the fourth power supply voltage line VINIL, which is supplied with the fourth power supply voltage VINI. For example, the tenth transistor T10 of each of the first subpixel SPC1 and the second subpixel SPC2 can be connected to the fourth power supply voltage line VINIL.

[0142] In another embodiment of the display device 400 described herein, the first light-emitting element ED1 or the second light-emitting element ED2 can be made to emit light by mode selection using only the first mode signal S(n) and the second mode signal P(n) without a separate light emission control signal. This reduces the number of wires arranged in the subpixels, lowers the wiring density in the pixel circuit, and improves the PPI (Pixels Per Inch) and resolution.

[0143] In another embodiment of the display device 400 described herein, the drive signals for driving the sub-pixel circuits can be reduced and the gate drive unit that generates the drive signals can be reduced, thereby minimizing the area of ​​the non-display region where the gate drive unit is located and minimizing the bezel area.

[0144] Existing display devices have a problem in that each sub-pixel has its own fourth power supply voltage line VINIL, and each sub-pixel has its own fourth power supply voltage line VINIL connected to it, resulting in a large number of wires being placed on the sub-pixels within the display area AA.

[0145] Therefore, in the display device 400 according to another embodiment of this specification, the first subpixel SPC1 and the second subpixel SPC2, which are arranged adjacent to each other in the first direction, are arranged symmetrically with respect to the fourth power supply voltage line VINIL. The first subpixel SPC1 and the second subpixel SPC2 share the fourth power supply voltage line VINIL. The first subpixel SPC1 and the second subpixel SPC2 are connected to the fourth power supply voltage line VINIL. Thus, in the display device 400 according to another embodiment of this specification, the first subpixel SPC1 and the second subpixel SPC2, which are arranged adjacent to each other in the first direction, are connected by sharing a single fourth power supply voltage line VINIL. This reduces the number of wires arranged in the subpixels and lowers the wiring density in the pixel circuit, thereby increasing the degree of design freedom or improving the PPI (Pixels Per Inch; PPI) and resolution.

[0146] The display devices according to the embodiments of this specification can be described as follows.

[0147] An embodiment of the present specification includes a first light-emitting element and a second light-emitting element, a drive transistor connected between a first node and a third node to control the drive current flowing to the first light-emitting element and the second light-emitting element, a first mode selection unit connected between the first node and a first power supply line supplying a first power supply voltage and operating by a mode signal, and a second mode selection unit connected between the third node and the first light-emitting element and the second light-emitting element and operating by a mode signal.

[0148] According to another feature of the present invention, the first mode selection unit may include a third transistor connected between a first power supply line supplying a first power supply voltage and a first node and operated by a first mode signal, and a fourth transistor connected between the first power supply line and the first node and operated by a second mode signal.

[0149] According to yet another feature of the present invention, the second mode selection unit may include a fifth transistor connected between the drive transistor and the first light-emitting element and operated by the first mode signal, and a sixth transistor connected between the drive transistor and the second light-emitting element and operated by the second mode signal.

[0150] Another feature of the present invention further includes a first transistor connected between a third node and a second node corresponding to the gate electrode of a drive transistor, a second transistor connected between a data line to which a data signal is applied and the first node, a seventh transistor connected between a second power supply line supplying a second power supply voltage and the first node, an eighth transistor connected between a third power supply line supplying a third power supply voltage and a fourth node corresponding to the first electrode of a first light-emitting element, a ninth transistor connected between a third power supply line and a fifth node corresponding to the first electrode of a second light-emitting element, a tenth transistor connected between a fourth power supply line supplying a fourth power supply voltage and the second node, and a storage capacitor connected between the first power supply line and the second node.

[0151] According to other features of the present invention, the driving transistor includes a first electrode connected to a first node, a second electrode connected to a third node, and a gate electrode connected to the second node, the first transistor includes a first electrode connected to a second node, a second electrode connected to a third node, and a gate electrode that receives a first scan signal, the second transistor includes a first electrode connected to a data line, a second electrode connected to a first node, and a gate electrode that receives a second scan signal, the third transistor includes a first electrode connected to a first power line, a second electrode connected to a first node, and a gate electrode that receives a first mode signal, the fourth transistor includes a first electrode connected to a first power line, a second electrode connected to a first node, and a gate electrode that receives a second mode signal, and the fifth transistor includes a first electrode connected to a third node, and a gate electrode connected to a fourth node. The sixth transistor includes a second electrode connected to a third node, a second electrode connected to a fifth node, and a gate electrode that receives a second mode signal; the seventh transistor includes a first electrode connected to a second power line, a second electrode connected to a first node, and a gate electrode that receives a third scan signal; the eighth transistor includes a first electrode connected to a third power line, a second electrode connected to a fourth node, and a gate electrode that receives a third scan signal; the ninth transistor includes a first electrode connected to a third power line, a second electrode connected to a fifth node, and a gate electrode that receives a third scan signal; and the tenth transistor may include a first electrode connected to a fourth power line, a second electrode connected to a second node, and a gate electrode that receives a fourth scan signal.

[0152] According to another feature of the present invention, the first and tenth transistors are n-type oxide transistors, and the driving transistor, second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor, eighth transistor, and ninth transistor may be P-type LTPS (Low-Temperature Polycrystalline Silicon) transistors.

[0153] According to another feature of the present invention, when the third and fifth transistors are turned on in response to a first mode signal, the first light-emitting element may emit light, and when the fourth and sixth transistors are turned on in response to a second mode signal, the second light-emitting element may emit light.

[0154] Another feature of the present invention may further include a boost capacitor connected between the second scan signal line to which the second scan signal is applied and the gate electrode of the drive transistor.

[0155] Other embodiments of this specification include a display device comprising a substrate including a display area on which a plurality of subpixels are arranged and a non-display area surrounding the display area, and a gate drive unit arranged in the non-display area, each of the plurality of subpixels comprising a first light-emitting element and a second light-emitting element, a drive transistor connected between a first node and a third node, a first transistor connected between the third node and a second node corresponding to the gate electrode of the drive transistor, a second transistor connected between a data line to which a data signal is applied and the first node, a third transistor connected between a first power supply line supplying a first power supply voltage and the first node and operating by a first mode signal, and a fourth transistor connected between the first power supply line and the first node and operating by a second mode signal. The system includes a 5th transistor connected between the drive transistor and the 1st light-emitting element and operated by a 1st mode signal, a 6th transistor connected between the drive transistor and the 2nd light-emitting element and operated by a 2nd mode signal, a 7th transistor connected between the 2nd power supply line supplying a 2nd power supply voltage and the 1st node, an 8th transistor connected between the 3rd power supply line supplying a 3rd power supply voltage and the 4th node corresponding to the 1st electrode of the 1st light-emitting element, a 9th transistor connected between the 3rd power supply line and the 5th node corresponding to the 1st electrode of the 2nd light-emitting element, a 10th transistor connected between the 4th power supply line supplying a 4th power supply voltage and the 2nd node, and a storage capacitor connected between the 1st power supply line and the 2nd node.

[0156] According to another feature of the present invention, the gate drive unit may include a first scan drive unit that provides a first scan signal to a plurality of subpixels, a second scan drive unit that provides a second scan signal to a plurality of subpixels, a third scan drive unit that provides a third scan signal to a plurality of subpixels, a fourth scan drive unit that provides a fourth scan signal to a plurality of subpixels, a first mode signal drive unit that provides a first mode signal, and a second mode signal drive unit that provides a second mode signal.

[0157] According to yet another feature of the present invention, each of the plurality of subpixels may further include a first lens positioned to overlap with the light-emitting region of a first light-emitting element and to provide a first-value field of view, and a second lens positioned to overlap with the light-emitting region of a second light-emitting element and to provide a second-value field of view that is lower than the first-value field of view.

[0158] According to yet another feature of the present invention, each of the plurality of subpixels can be selectively driven in a first mode and a second mode, in the first mode, a first light-emitting element emits light and the light from the first light-emitting element is output by a first lens at a first field of view angle, and in the second mode, a second light-emitting element emits light and the light from the second light-emitting element is output by a second lens at a second field of view angle.

[0159] According to another feature of the present invention, the first and tenth transistors are n-type oxide transistors, and the driving transistor, second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor, eighth transistor, and ninth transistor may be P-type LTPS (Low-Temperature Polycrystalline Silicon) transistors.

[0160] According to yet another feature of the present invention, each of the subpixels may further include a boost capacitor connected between the second scan signal line to which the second scan signal is applied and the gate electrode of the drive transistor.

[0161] According to another feature of the present invention, in each of a plurality of subpixels, the driving transistor includes a first electrode connected to a first node, a second electrode connected to a third node, and a gate electrode connected to the second node, wherein the first transistor includes a first electrode connected to a second node, a second electrode connected to a third node, and a gate electrode that receives a first scan signal, wherein the second transistor includes a first electrode connected to a data line, a second electrode connected to a first node, and a gate electrode that receives a second scan signal, wherein the third transistor includes a first electrode connected to a first power line, a second electrode connected to a first node, and a gate electrode that receives a first mode signal, wherein the fourth transistor includes a first electrode connected to a first power line, a second electrode connected to a first node, and a gate electrode that receives a second mode signal, wherein the fifth transistor includes a first electrode connected to a third node, The sixth transistor includes a second electrode connected to the fourth node and a gate electrode that receives the first mode signal; the seventh transistor includes a first electrode connected to the second power line, a second electrode connected to the first node, and a gate electrode that receives the second mode signal; the eighth transistor includes a first electrode connected to the third power line, a second electrode connected to the fourth node, and a gate electrode that receives the third scan signal; the ninth transistor includes a first electrode connected to the third power line, a second electrode connected to the fifth node, and a gate electrode that receives the third scan signal; and the tenth transistor may include a first electrode connected to the fourth power line, a second electrode connected to the second node, and a gate electrode that receives the fourth scan signal.

[0162] According to another feature of the present invention, a plurality of subpixels arranged adjacent to each other in the column direction can share a third power supply line.

[0163] According to another feature of the present invention, a plurality of subpixels arranged adjacent to each other in the column direction can share a fourth power supply line.

[0164] Although embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to these embodiments and can be modified and implemented in various ways without deviating from the technical concept of this specification. Therefore, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Accordingly, the embodiments described above should be understood to be illustrative and non-limiting in all respects. All technical concepts within the scope equivalent to the claims of this specification should be construed as being included in the scope of rights of this specification.

Claims

1. First light-emitting element and second light-emitting element, A drive transistor connected between the first node and the third node controls the drive current flowing to the first and second light-emitting elements, A first mode selection unit is connected between the first node and the first power supply line that supplies the first power supply voltage and operates by a mode signal, A pixel circuit including a third node and a second mode selection unit connected between the first and second light-emitting elements and operated by the mode signal.

2. The first mode selection unit is, A third transistor connected between the first power supply line that supplies the first power supply voltage and the first node, and which operates by a first mode signal, The pixel circuit according to claim 1, further comprising a fourth transistor connected between the first power line and the first node and operated by a second mode signal.

3. The second mode selection unit is, A fifth transistor is connected between the drive transistor and the first light-emitting element and operates according to the first mode signal, The pixel circuit according to claim 2, further comprising a sixth transistor operated by the second mode signal connected between the drive transistor and the second light-emitting element.

4. A first transistor is connected between the third node and the second node corresponding to the gate electrode of the drive transistor, A second transistor is connected between the data line to which a data signal is applied and the first node, A seventh transistor is connected between the second power supply line that supplies the second power supply voltage and the first node, An eighth transistor is connected between a third power supply line that supplies a third power supply voltage and a fourth node corresponding to the first electrode of the first light-emitting element, A ninth transistor is connected between the third power line and the fifth node corresponding to the first electrode of the second light-emitting element, A tenth transistor is connected between the fourth power supply line that supplies the fourth power supply voltage and the second node, The pixel circuit according to claim 3, further comprising a storage capacitor connected between the first power line and the second node.

5. The drive transistor includes a first electrode connected to the first node, a second electrode connected to the third node, and a gate electrode connected to the second node. The first transistor includes a first electrode connected to the second node, a second electrode connected to the third node, and a gate electrode that receives the first scan signal. The second transistor includes a first electrode connected to the data line, a second electrode connected to the first node, and a gate electrode that receives the second scan signal. The third transistor includes a first electrode connected to the first power line, a second electrode connected to the first node, and a gate electrode that receives the first mode signal. The fourth transistor includes a first electrode connected to the first power line, a second electrode connected to the first node, and a gate electrode that receives the second mode signal. The fifth transistor includes a first electrode connected to the third node, a second electrode connected to the fourth node, and a gate electrode that receives the first mode signal. The sixth transistor includes a first electrode connected to the third node, a second electrode connected to the fifth node, and a gate electrode that receives the second mode signal. The seventh transistor includes a first electrode connected to the second power line, a second electrode connected to the first node, and a gate electrode that receives the third scan signal. The eighth transistor includes a first electrode connected to the third power line, a second electrode connected to the fourth node, and a gate electrode that receives the third scan signal. The ninth transistor includes a first electrode connected to the third power line, a second electrode connected to the fifth node, and a gate electrode that receives the third scan signal. The pixel circuit according to claim 4, wherein the 10th transistor includes a first electrode connected to the 4th power line, a second electrode connected to the 2nd node, and a gate electrode that receives the 4th scan signal.

6. The first transistor and the tenth transistor are n-type oxide transistors, The pixel circuit according to claim 4, wherein the drive transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are P-type LTPS (Low-Temperature Polycrystalline Silicon) transistors.

7. When the third transistor and the fifth transistor are turned on in response to the first mode signal, the first light-emitting element emits light. The pixel circuit according to claim 4, wherein the second light-emitting element emits light when the fourth transistor and the sixth transistor are turned on in response to the second mode signal.

8. The pixel circuit according to claim 4, further comprising a boost capacitor connected between a second scan signal line to which a second scan signal is applied and the gate electrode of the drive transistor.

9. A substrate including a display area on which multiple subpixels are arranged and a non-display area surrounding the display area, The gate drive unit is located in the non-display area, Each of the aforementioned subpixels is, First light-emitting element and second light-emitting element, A drive transistor connected between the first node and the third node, A first transistor is connected between the third node and the second node corresponding to the gate electrode of the drive transistor, A second transistor is connected between the data line to which a data signal is applied and the first node, A third transistor connected between a first power supply line supplying a first power supply voltage and the first node, and operated by a first mode signal, A fourth transistor connected between the first power line and the first node and operating by a second-mode signal, A fifth transistor is connected between the drive transistor and the first light-emitting element and operates according to the first mode signal, A sixth transistor operated by the second mode signal connected between the drive transistor and the second light-emitting element, A seventh transistor is connected between the second power supply line that supplies the second power supply voltage and the first node, An eighth transistor is connected between a third power supply line that supplies a third power supply voltage and a fourth node corresponding to the first electrode of the first light-emitting element, A ninth transistor is connected between the third power line and the fifth node corresponding to the first electrode of the second light-emitting element, A tenth transistor is connected between the fourth power supply line that supplies the fourth power supply voltage and the second node, A display device including a storage capacitor connected between the first power line and the second node.

10. The gate drive unit is A first scan drive unit that provides a first scan signal to the plurality of subpixels, A second scan drive unit that provides a second scan signal to the plurality of subpixels, A third scan drive unit that provides a third scan signal to the plurality of subpixels, A fourth scan drive unit that provides a fourth scan signal to the plurality of subpixels, A first mode signal drive unit that provides the first mode signal, The display device according to claim 9, further comprising a second mode signal drive unit that provides the second mode signal.

11. Each of the aforementioned subpixels is, A first lens is arranged to overlap with the light-emitting region of the first light-emitting element and to provide a first value field of view, The display device according to claim 9, further comprising a second lens arranged to overlap with the light-emitting region of the second light-emitting element and providing a second value field of view that is lower than the first value field of view.

12. Each of the aforementioned subpixels is selectively driven in a first mode and a second mode. In the first mode, the first light-emitting element emits light, and the light from the first light-emitting element is output by the first lens at the first value of field of view angle. The display device according to claim 11, wherein in the second mode, the second light-emitting element emits light, and the light from the second light-emitting element is output by the second lens at the second value of field of view angle.

13. The first transistor and the tenth transistor are n-type oxide transistors, The display device according to claim 9, wherein the drive transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are P-type LTPS (Low-Temperature Polycrystalline Silicon) transistors.

14. Each of the aforementioned subpixels is, The display device according to claim 9, further comprising a boost capacitor connected between a second scan signal line to which a second scan signal is applied and the gate electrode of the drive transistor.

15. In each of the aforementioned subpixels, The drive transistor includes a first electrode connected to the first node, a second electrode connected to the third node, and a gate electrode connected to the second node. The first transistor includes a first electrode connected to the second node, a second electrode connected to the third node, and a gate electrode that receives the first scan signal. The second transistor includes a first electrode connected to the data line, a second electrode connected to the first node, and a gate electrode that receives the second scan signal. The third transistor includes a first electrode connected to the first power line, a second electrode connected to the first node, and a gate electrode that receives the first mode signal. The fourth transistor includes a first electrode connected to the first power line, a second electrode connected to the first node, and a gate electrode that receives the second mode signal. The fifth transistor includes a first electrode connected to the third node, a second electrode connected to the fourth node, and a gate electrode that receives the first mode signal. The sixth transistor includes a first electrode connected to the third node, a second electrode connected to the fifth node, and a gate electrode that receives the second mode signal. The seventh transistor includes a first electrode connected to the second power line, a second electrode connected to the first node, and a gate electrode that receives the third scan signal. The eighth transistor includes a first electrode connected to the third power line, a second electrode connected to the fourth node, and a gate electrode that receives the third scan signal. The ninth transistor includes a first electrode connected to the third power line, a second electrode connected to the fifth node, and a gate electrode that receives the third scan signal. The display device according to claim 9, wherein the 10th transistor includes a first electrode connected to the 4th power line, a second electrode connected to the 2nd node, and a gate electrode that receives the 4th scan signal.

16. The display device according to claim 9, wherein a plurality of subpixels among the plurality of subpixels arranged to be adjacent in the column direction share the third power supply line.

17. The display device according to claim 9, wherein a plurality of subpixels among the plurality of subpixels arranged to be adjacent in the column direction share the fourth power supply line.

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