Gaming machine

Abstract

Proceed with the game appropriately. [Solution] A gaming machine that can be connected to a specific unit that lends out gaming value, comprising: a gaming control means for controlling the progress of the game; a gaming value management means for managing the gaming value; and a sound control means for controlling the output of sound according to the progress of the game, wherein the sound control means may output a first sound based on processing related to the progress of the game, may output a second sound based on processing related to the transfer of gaming value with the specific unit, may output a third sound when predetermined conditions are met, may output the second sound superimposed on the output of the first sound, and may not output the second sound while the third sound is being output.

Description

Technical Field

[0001] The present invention relates to a gaming machine.

Background Art

[0002] Smart pachislots that can progress the game without the intervention of actual medals while maintaining the playability of slot machines have been studied (for example, Patent Document 1). Also, smart pachinko machines that enclose and circulate pachinko balls so that the player can progress the game without touching the pachinko balls have been studied (for example, Patent Document 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In such smart pachislots and smart pachinko machines, there is no need to provide a path for circulating game media such as pachinko balls and medals outside the gaming machine. In smart pachislots, the physical game media itself becomes unnecessary. Thus, in smart pachislots, the game media itself is not used, and in smart pachinko machines, by using non-magnetic pachinko balls, it becomes possible to prevent acts of gambling that assume the use of metallic game media. Also, since there is no need to provide a mechanism for inserting and dispensing game media inside the gaming machine, design costs and manufacturing costs can be reduced. Furthermore, by centrally managing the lending of game media to players and the counting of acquired game media, it becomes possible to prevent fraud and suppress the element of chance.

[0005] On the other hand, for configurations that utilize electronic game media (game value) or non-magnetic game media instead of physical game media, a new mechanism is needed to manage the electronic game media and ensure that the game proceeds appropriately. For example, the lending process for lending electronic game media to smart pachislot or smart pachinko machines, and the counting process for counting game media acquired by smart pachislot or smart pachinko machines, must also proceed appropriately.

[0006] In view of these problems, the present invention aims to provide a gaming machine that can appropriately manage the game. [Means for solving the problem]

[0007] To solve the above problems, the present invention provides a gaming machine that can be connected to a specific unit that lends out gaming value, and comprises: a gaming control means for controlling the progress of the game; a gaming value management means for managing the gaming value; and a sound control means for controlling the output of sound according to the progress of the game, wherein the sound control means may output a first sound based on processing related to the progress of the game, may output a second sound based on processing related to the transfer of the gaming value to the specific unit, may output a third sound when predetermined conditions are met, may output the second sound superimposed on the output of the first sound, and may not output the second sound while the output of the third sound is in operation. [Effects of the Invention]

[0008] According to the present invention, it becomes possible to conduct games appropriately. [Brief explanation of the drawing]

[0009] [Figure 1] This is an external view diagram illustrating the general mechanical configuration of a smart pachislo machine. [Figure 2] This is a block diagram showing the general electrical configuration of the smart pachislo machine and its dedicated unit. [Figure 3] This is an external view illustrating the general mechanical configuration of the smart pachislo machine and its dedicated unit. [Figure 4] This is a flowchart showing the main processing of the main control board. [Figure 5] This is an explanatory diagram illustrating other circuit board configurations. [Figure 6] This is an explanatory diagram illustrating the packaging method of the case. [Figure 7] This is an explanatory diagram illustrating the CPU and memory areas that execute each function of a smart pachislo machine. [Figure 8] This is an explanatory diagram illustrating the format for notifying information about gaming machines. [Figure 9] This is an explanatory diagram illustrating the format for notifying information about gaming machines. [Figure 10] This is an explanatory diagram illustrating the format for notifying information about gaming machines. [Figure 11] This is an explanatory diagram illustrating the format for notifying information about gaming machines. [Figure 12] This is an explanatory diagram to show the format of the count notification. [Figure 13] This is an explanatory diagram illustrating the format of the loan receipt result response. [Figure 14] This is an explanatory diagram illustrating the format of a loan notification. [Figure 15] This is a timing chart showing the notification timings for gaming machine information notifications, counting notifications, loan notifications, and loan receipt result responses. [Figure 16] This is an explanatory diagram illustrating the timing of sending information notifications for gaming machines. [Figure 17] This is a flowchart illustrating the flow of the counting switch monitoring process in a medal CPU. [Figure 18] This is a flowchart illustrating the counting process in a medal CPU. [Figure 19] This is a timing chart used to explain the counting process. [Figure 20] This is a timing chart to explain the display methods for the number of game tokens played. [Figure 21]It is a flowchart showing the flow of counting switch processing in the medal CPU. [Figure 22] It is a time chart explaining the setting of the counted medal number. [Figure 23] It is a flowchart showing the flow of counting switch processing according to a modification example that effectively processes all signals multiple times. [Figure 24] It is a time chart explaining the setting of the counted medal number according to a modification example that effectively processes all signals multiple times. [Figure 25] It is a diagram explaining the operation when the game sound and the counting sound overlap. [Figure 26] It is a flowchart explaining the counting sound processing executed by the effect control means. [Figure 27] It is a flowchart explaining the flow of volume control processing executed by the effect control means. [Figure 28] It is a flowchart showing the flow of command reception processing in the medal CPU. [Figure 29] It is a flowchart showing the flow of command reception processing in the medal CPU. [Figure 30] It is a flowchart showing the flow of command reception processing in the medal CPU. [Figure 31] It is a flowchart showing the flow of command monitoring processing. [Figure 32] It is a flowchart showing the flow of command monitoring processing. [Figure 33] It is a flowchart showing the flow of command monitoring processing. [Figure 34] It is a flowchart showing the communication specification at power-on. [Figure 35] It is a flowchart showing the communication specification during operation. [Figure 36] It is a flowchart showing the communication specification at the end of the game. [Figure 37] It is a flowchart showing the flow of bet processing in the medal CPU. [Figure 38]This is an explanatory diagram showing an actual calculation example of betting. [Figure 39] This flowchart illustrates the process of updating the setting change signal. [Figure 40] This flowchart shows the process for updating the setting confirmation signal. [Figure 41] This is an explanatory diagram illustrating a comparative example of communication processing between the main CPU and the medal CPU. [Figure 42] This is a flowchart illustrating the concept of sending a single byte of a command, and a diagram showing the command. [Figure 43] This is an explanatory diagram showing the communication process between the main CPU and the medal CPU. [Figure 44] This is an explanatory diagram illustrating the communication process between the main CPU and the sub-CPU. [Figure 45] This is an explanatory diagram illustrating other communication processes between the main CPU and the sub-CPU. [Figure 46] This is a flowchart to explain the communication process. [Figure 47] This is an explanatory diagram illustrating the display method of electronic medals. [Figure 48] This is an explanatory diagram illustrating the display method of electronic medals. [Figure 49] This is an explanatory diagram for describing the information display on gaming machines. [Figure 50] This is an explanatory diagram for describing the display of information on gaming machines and the display to prevent excessive gambling. [Figure 51] This is an explanatory diagram for describing the display of gaming machine information, the display to prevent excessive gambling, and the display of suggestive information. [Figure 52] This is an explanatory diagram for explaining suggestive displays. [Figure 53] This is an explanatory diagram for describing the test firing of the smart pachislo machine. [Figure 54] This is an explanatory diagram to show how a slot machine works. [Figure 55] This is an explanatory diagram for describing the operation of a smart pachislo machine. [Modes for carrying out the invention]

[0010] Preferred embodiments of the present invention will be described in detail below with reference to the attached drawings. The dimensions, materials, and other specific numerical values ​​shown in these embodiments are merely examples to facilitate understanding of the invention and do not limit the present invention unless otherwise specified. In this specification and drawings, elements having substantially the same function and configuration are denoted by the same reference numerals to avoid redundant explanations, and elements not directly related to the present invention are omitted from the illustrations.

[0011] (First embodiment: Smart Pachislo 100) Smart Pachislo 100 maintains the gameplay of a slot machine while allowing gameplay to proceed without the use of physical tokens. Note that slot machines are conventional, general-purpose gaming machines that differ from Smart Pachislo 100 in that they use physical tokens to advance gameplay. In Smart Pachislo 100, instead of physical tokens, electronic tokens are used as electronic game value for gameplay.

[0012] (Mechanical configuration of Smart Pachislo 100) As shown in the external view of Figure 1, the Smart Pachislo 100 as a gaming machine is provided with a casing 102 and a front upper door 104 and a front lower door 106 that are rotatably arranged vertically at one end of the front of the casing 102. A colorless, transparent symbol display window 108 made of glass or transparent resin is provided approximately in the lower center of the front upper door 104. Three reels 110 (left reel 110a, middle reel 110b, and right reel 110c) are provided in the casing 102 at positions corresponding to the symbol display window 108, and each is rotatably installed independently. Multiple types of symbols are arranged in each of the outer surfaces of the left reel 110a, middle reel 110b, and right reel 110c, for example, in areas divided into 20 equal parts. The player can see, through the symbol display window 108, the three consecutive symbols located in the upper, middle, and lower rows of the left reel 110a, the middle reel 110b, and the right reel 110c, totaling nine symbols.

[0013] An operating panel mounting base 111 is formed at the top of the front lower door 106, and the operating panel mounting base 111 is equipped with a counting switch 112, a game token count display device 114, a bet switch 116, a start switch 118, a stop switch 120, a payout switch 121, a performance switch 122, and the like.

[0014] The counting switch 112 is a push switch that detects an operation to transfer some or all of the electronically held electronic tokens that can be used for gameplay, which are electronically held by the smart pachislo 100, to a dedicated unit 350 described later. The counting switch 112 has two operation options: a short press of less than 500 msec and a long press of 500 msec or more. With a short press of the counting switch 112, one electronic token is counted for each operation, and with a long press, 50 electronic tokens are counted at the timing of counting notifications, which occur every 300 msec. The total number of electronic tokens that can be used for gameplay, which are electronically held by the smart pachislo 100, is sometimes referred to as the "number of game tokens," and the memory unit that holds the electronic tokens is sometimes referred to as the "token holding unit."

[0015] The game token count display device 114 displays the total number of electronic tokens held in the token holder, i.e., the number of game tokens. However, the number of game tokens does not include the number of electronic tokens bet. Therefore, the game token count display device 114 displays the number obtained by subtracting the number of electronic tokens bet from the number of electronic tokens acquired by the player. The number of game tokens is displayed on a 5-digit or 6-digit 7-segment display or the like, positioned where the player can see it, as follows: The numerical range is 0 to 16368, taking into account the maximum difference in tokens during one business day, and if the higher digit of a significant number is 0, that number is left blank (off). When the number reaches 15000 or more, a notification prompting the player to count is issued, the dispensing of electronic tokens is restricted, and a test counting signal is output for approximately 3500 msec. However, the player can continue playing. When the number reaches 16369 or more, the progress of the game is restricted. Specifically, the bet switch 116, start switch 118, and payout switch 121 are prohibited from being activated. Alternatively, instead of prohibiting the payout of electronic tokens when the value is likely to reach 16369 or higher, the payout of electronic tokens may be prohibited until the player performs the counting. For example, the game may be stopped when the value reaches 16357 or higher, which is 12 tokens (maximum payout (e.g., 15 tokens) - prescribed number (e.g., 3 tokens)) minus 12 tokens, the maximum difference in tokens obtainable in one game, from 16369. Furthermore, the token count display device 114 will display the updated token count within approximately 300 msec after the token count held by the smart pachislo 100 is updated.

[0016] The bet switch 116 inserts (bets) a predetermined number of electronic tokens from those held in the token holder. The bet switch 116 includes a max bet switch that inserts (bets) a predetermined number of electronic tokens required for one game, and a 1 bet switch that inserts an additional one electronic token within the predetermined range.

[0017] The start switch 118 is composed of, for example, a lever capable of detecting tilting operations, and detects the player's operation to start the game. The stop switches 120 (stop switches 120a, 120b, and 120c) are provided corresponding to the left reel 110a, the middle reel 110b, and the right reel 110c, respectively, and detect the player's stopping operation. The payout switch 121 detects the operation to return all electronic tokens bet by a single operation of the bet switch 116 to the token holder. The effect switches 122 are composed of, for example, a push switch and cross switches arranged up, down, left, and right, and detect the player's pressing and rotating operations.

[0018] A liquid crystal display unit 124 is provided at the upper center of the front upper door 104 to display various images related to the performance. In addition, performance lamps 126, which are made up of, for example, high-brightness light-emitting diodes (LEDs), are provided at the top and left and right of the front upper door 104. Speakers 128 are provided at the left and right positions of the front lower door 106 to provide auditory effects such as sound effects and musical tones.

[0019] In Smart Pachislo 100, once gameplay is possible and a specified number of electronic tokens have been bet, the active lines are activated and the operation of the start switch 118 becomes valid. Here, betting includes both inserting electronic tokens held in the token holder via the operation of the bet switch 116 and automatically inserting electronic tokens based on the display of a replay symbol on an active line. The active lines are the lines used to determine the winning combination.

[0020] When the player operates the start switch 118, the game begins, and various processes such as the lottery for winning types are executed, while the left reel 110a, middle reel 110b, and right reel 110c are controlled to rotate. Subsequently, the left reel 110a, middle reel 110b, and right reel 110c are stopped according to the operation of the stop switches 120a, 120b, and 120c, respectively. If a winning combination that allows for the payout of electronic tokens is achieved based on the lottery result for winning types and the combination of symbols displayed on the active lines, the number of electronic tokens corresponding to the winning combination are paid out (stored) in the token holder and the game ends. If the player does not win a winning type that allows for the payout of electronic tokens, or if they win but do not get a payout, the game ends when the left reel 110a, middle reel 110b, and right reel 110c all stop.

[0021] In this embodiment, the above-mentioned game 1 refers to the game from the time when an electronic medal held in the medal holder is inserted via the operation of the bet switch 116, or when an electronic medal is automatically inserted based on the display of a replay symbol on the active line, until the left reel 110a, middle reel 110b, and right reel 110c are controlled to rotate and a winning type lottery is performed in response to the operation of the start switch 118 by the player, and the left reel 110a, middle reel 110b, and right reel 110c are stopped in response to the lottery result of the winning type lottery and the operation of multiple stop switches 120a, 120b, and 120c by the player, and until the electronic medal is dispensed if a winning symbol that can be dispensed with an electronic medal is hit. Furthermore, if the player fails to win a prize that can award electronic tokens, or if they win a prize but do not win, the game ends when the left reel 110a, middle reel 110b, and right reel 110c all stop. However, the start of a game may be interpreted as the player operating the start switch 118 instead of inserting the electronic tokens or winning a replay. The number of times such a game is repeated is defined as the number of games.

[0022] (Electrical configuration of Smart Pachislo 100) Figure 2 is a block diagram showing the schematic electrical configuration of the smart pachislo 100 and the dedicated unit 350. As shown in Figure 2, the smart pachislo 100 and the dedicated unit 350 are electrically connected via a game ball dispensing device connection terminal board 206. The smart pachislo 100 is equipped with a control board that includes a main control board 200 (main control unit) for controlling the progress of the game, a sub-control board 202 (sub-control unit) for controlling the effects according to the progress of the game, and a medal count control board 204 for controlling the number of electronic medals (number of game medals) held in the medal holding section. Note that the transmission of electrical signals between the main control board 200 and the sub-control board 202 is restricted to one direction only, from the main control board 200 to the sub-control board 202, from the viewpoint of preventing fraud. The dedicated unit 350 is equipped with a dedicated unit control board 360 for sending and receiving electronic medals to and from the smart pachislo 100.

[0023] (Main control board 200) The main control board 200 has a semiconductor integrated circuit including a main CPU 200a which is a central processing unit, a main ROM 200b which stores programs and the like, and a main RAM 200c which functions as a work area, and comprehensively controls the entire smart pachislo 100. In addition, even if the power is cut off, the data in the main RAM 200c will not be erased unless a setting change is made and a RAM clear is performed.

[0024] Furthermore, the main control board 200 has functional units such as initialization means 300, betting means 302, winning type lottery means 304, reel control means 306, determination means 308, payout control means 310, game state control means 312, performance state control means 314, and command transmission means 316, which are operated by the main CPU 200a cooperating with the main RAM 200c based on a program stored in the main ROM 200b.

[0025] The main control board 200 receives various detection signals from the bed switch 116, start switch 118, stop switches 120a, 120b, 120c, and settlement switch 121. Based on the received detection signals, the main CPU 200a performs various processes.

[0026] The initialization means 300 performs initialization processing on the main control board 200. The betting means 302 places bets on electronic tokens to be used for playing the game. The winning type lottery means 304, based on the operation of the start switch 118, performs a winning type lottery to determine whether a winning combination is correct, and more specifically, whether a winning type that includes the winning combination is correct, as will be described in more detail later.

[0027] The reel control means 306 controls the rotation of the left reel 110a, middle reel 110b, and right reel 110c in response to the operation of the start switch 118, and controls the stopping of the corresponding left reel 110a, middle reel 110b, and right reel 110c in response to the operation of the stop switches 120a, 120b, and 120c corresponding to the rotating left reel 110a, middle reel 110b, and right reel 110c, respectively.

[0028] Furthermore, a reel drive control unit 150 is connected to the main control board 200. This reel drive control unit 150 drives the stepping motor 152 based on the rotation start signals for the left reel 110a, middle reel 110b, and right reel 110c transmitted from the reel control means 306 in response to the operation signal of the start switch 118. The reel drive control unit 150 also stops driving the stepping motor 152 based on the stop signals for the left reel 110a, middle reel 110b, and right reel 110c respectively, and the detection signal from the rotation position detection circuit 154, transmitted from the reel control means 306 in response to the operation signal of the stop switch 120.

[0029] The determination means 308 determines whether or not a combination of symbols corresponding to a winning combination is displayed on an active line. Here, the display of a combination of symbols corresponding to a winning combination on an active line is sometimes simply referred to as a win. Based on the fact that a combination of symbols corresponding to a winning combination has been displayed on an active line (a win has been achieved), the payout control means 310 pays out a number of electronic medals (value) corresponding to the winning combination to the medal holder.

[0030] The game state control means 312 refers to the result of the winning type lottery and the result of the judgment means 308 to transition the game state to one of several types of game states. The performance state control means 314 refers to the result of the winning type lottery, the result of the judgment means 308, and the game state transition information to transition the performance state to one of several types of performance states. The game states include a non-internal game state, an internal game state which is transitioned to when a bonus role is won in the non-internal game state, and a bonus game state which is transitioned to when a symbol combination corresponding to a bonus role is displayed on an active line in the internal game state. The performance states include a non-AT (Assist Time) performance state which does not perform an auxiliary performance to assist in winning a specific role (correct role) when a winning type is won in which a specific role (correct role) and other winning roles (incorrect roles) overlap, and an AT performance state which performs an auxiliary performance. A "special winning combination" refers to a winning combination that is more advantageous than other winning combinations, not only in terms of the payout of electronic tokens resulting from winning that combination, but also in terms of all the game benefits that can be obtained from winning that combination.

[0031] The command transmission means 316 sequentially determines game-related commands in conjunction with the operation of the betting means 302, the winning type lottery means 304, the reel control means 306, the determination means 308, the payout control means 310, the game state control means 312, the performance state control means 314, etc., and sequentially transmits the determined commands to the sub-control board 202.

[0032] Furthermore, the main control board 200 is equipped with a random number generator (random number generation means) 200d. The random number generator 200d sequentially increments a count value, and after counting a predetermined number of times, it resets the count value (changes the sequence of numbers to set an initial value), thereby looping the count value within a predetermined numerical range. The main control board 200 obtains random values ​​by extracting the count value from the random number generator 200d at a predetermined time. The random values ​​generated by the random number generator 200d of the main control board 200 (hereinafter referred to as the winning type lottery random numbers) are used to determine the type of game prize to be given to the player, for example, by the winning type lottery means 304 to determine the winning type.

[0033] (Sub-control board 202) Furthermore, the sub-control board 202, like the main control board 200, has various semiconductor integrated circuits including a sub-CPU 202a which is a central processing unit, a sub-ROM 202b which stores programs, etc., and a sub-RAM 202c which functions as a work area, and controls the performance in particular based on commands from the main control board 200. Also, like the main RAM 200c, the sub-RAM 202c is connected to a backup power supply (not shown), so that data is retained without being erased even if the power is cut off. In addition, the sub-control board 202 is also provided with a random number generator (random number generation means) 202d, like the main control board 200, and the random values ​​generated by the random number generator 202d (hereinafter referred to as performance lottery random numbers) are mainly used to determine the type of performance.

[0034] Furthermore, the sub-control board 202 has functional units such as an initialization determination means 330, a command receiving means 332, and a performance control means 334, which function through the cooperation of the sub-CPU 202a with the sub-RAM 202c based on a program stored in the sub-ROM 202b.

[0035] The initialization determination means 330 executes the initialization process on the sub-control board 202. The command receiving means 332 receives commands from other control boards, such as the main control board 200, and processes the commands.

[0036] The performance control means 334 receives a detection signal from the performance switch 122 and determines the game performance to be performed by the liquid crystal display unit 124, speaker 128, and performance lamp 126 based on the received command. Specifically, the performance control means 334 determines the image data to be displayed on the liquid crystal display unit 124 and the lighting data for the performance through the lighting equipment such as the performance lamp 126, as well as the audio data that constitutes the sound to be output from the speaker 128. Then, the performance control means 334 executes the determined game performance. Note that auxiliary performances are also included in the performance.

[0037] (Medal count control board 204) Furthermore, the medal count control board 204 is connected to the main control board 200 and has various semiconductor integrated circuits, including a medal CPU 204a which is a central processing unit, a medal ROM 204b which stores programs, etc., and a medal RAM 204c which functions as a work area, and manages the electronic medals used for gaming. The medal count control board 204 is also connected to a dedicated unit 350 via a game ball dispensing device connection terminal board 206.

[0038] Here, the game ball dispensing device connection terminal board 206 is a connection terminal board for connecting the smart pachislo 100 and the dedicated unit 350, and it receives signals related to the dispensing of electronic tokens, transmits the results of the dispensing and receipt of electronic tokens, transmits signals related to the counting of electronic tokens, and transmits various information of the smart pachislo 100.

[0039] (Dedicated unit 350) The dedicated unit 350 is installed near the smart pachislo 100 and can lend electronic tokens to players and count the electronic tokens won by players. The dedicated unit 350 is equipped with a dedicated unit control board 360. The dedicated unit control board 360 is connected to a cash input section 362, a card insertion section 364, a lending switch 366, a return switch 368, a game switch 370, a rate display device 372, and a tokens won display device 374.

[0040] The cash input section 362 functions as a slot for inserting cash. The card insertion section 364 allows for the insertion and withdrawal of a card medium capable of storing electronic tokens. The dispensing switch 366 is a push switch that detects the operation to transfer electronic tokens corresponding to the number of units of cash held in the dedicated unit 350 to the smart pachislo 100. The return switch 368 is a push switch that detects the operation to transfer electronic tokens held in the dedicated unit 350 to a card medium and to withdraw that card medium from the dedicated unit 350 through the card insertion section 364. The game switch 370 is a push switch that detects the operation to transfer electronic tokens held in the dedicated unit 350 to the smart pachislo 100. The unit value display device 372 displays the number of units held in the dedicated unit 350, that is, the number of units corresponding to the cash inserted from the cash input section. The acquired token count display device 374 displays the acquired token count, which is the total number of electronic tokens held in the dedicated unit 350.

[0041] Figure 3 is an external view illustrating the general mechanical configuration of the Smart Pachislo 100 and its dedicated unit 350. Referring to Figure 3, the process of starting and ending gameplay on the Smart Pachislo 100 will be explained.

[0042] When a player attempts to play on the Smart Pachislo 100, they first insert cash into the cash input section 362 of the dedicated unit 350 shown in Figure 3. The unit's unit 350 then displays a unit equivalent to the inserted cash (for example, "10" for a 1,000 yen insertion) on its unit display device 372. When the player operates the dispensing switch 366, the electronic tokens corresponding to the number of tokens held by the dedicated unit 350 (for example, "50") are transferred to the Smart Pachislo 100 all at once. The number of electronic tokens transferred (for example, "50") is then displayed on the Smart Pachislo 100's token count display device 114. Specifically, when the Smart Pachislo 100 receives a dispensing notification from the dedicated unit 350 (described later), if the dispensing notification is successful, it accepts the transfer of electronic tokens and notifies "successful" in the dispensing receipt result response. On the other hand, if the message length and command values ​​in the loan notification are normal, but other information is abnormal, Smart Pachislo 100 will notify "abnormal" in the loan receipt result response described later. Also, if the loan notification has not been received normally, or if the message length and command values ​​of the loan notification are abnormal, Smart Pachislo 100 will discard the received message without displaying an error and will wait until it can receive a loan notification with at least a normal message length and command. Furthermore, if the lending process cannot be completed, that is, if the gaming machine information notification described later is abnormal, the number of counted medals in the counting notification described later (the number of digitized medals transferred to the dedicated unit 350 at once) is "1" or more, the number of gaming medals displayed on the gaming medal count display device 114 is 15,000 or more, the checksum of the received lending notification is abnormal, the lending serial numbers of the received lending notification are not consecutive, the number of lending medals in the received lending notification is "51" or more, or if the gaming machine information notification sent from the medal CPU 204a to the dedicated unit 350 described later is notifying anything other than hall control / fraud monitoring information, the smart pachislo 100 will notify "abnormal" in the lending receipt result response.

[0043] Next, when the player operates the bet switch 116, electronic tokens are placed. At this time, the token count display device 114 displays a value (for example, "47") which is the number of electronic tokens that have been placed (for example, "3"). Thus, the player can start playing. If, as a result of the game, a small win is achieved that pays out 11 tokens, the number of electronic tokens that have been paid out (for example, "11") is displayed as a payout display on a part of the LCD display unit 124, and the token count display device 114 displays a value (for example, "58") which is the number of electronic tokens that have been paid out added to the payout.

[0044] Furthermore, if the payout switch 121 is operated after the player has placed an electronic token by operating the bet switch 116, but before the start switch 118 is operated (to start the game), the number of electronic tokens that were placed (for example, "3") will be added to the token count display device 114 (for example, to "50"), and the bet state will be canceled.

[0045] When a player finishes playing, they operate the counting switch 112 to transfer the electronic tokens held in the token holder to the dedicated unit 350. The number of tokens held in the token holder is then displayed on the token count display device 374 of the dedicated unit 350, while "0" is displayed on the token count display device 114. When the player operates the return switch 368, the electronic tokens held by the dedicated unit 350 are transferred to a card, and the card is withdrawn from the dedicated unit 350 through the card insertion section 364. In this way, the player can accumulate the electronic tokens they have acquired on a card.

[0046] If a player wishes to play again, they can insert a card containing stored electronic tokens into the card slot 364 instead of using cash, and play using the electronic tokens stored on the card. The electronic tokens stored on the card are then transferred to the dedicated unit 350, and the total number of electronic tokens stored on the card is displayed on the acquired token display device 374. The player can also transfer the electronic tokens held by the dedicated unit 350 to the smart pachislo 100 by operating the game switch 370 instead of the dispensing switch 366.

[0047] When the dispensing switch 366 or the counting switch 112 is operated, the medal CPU 204a performs the dispensing or counting process for the electronic medal and sends a command to the main CPU 200a to that effect. Upon receiving this command, the main CPU 200a sends a command to the sub-CPU 202a to that effect. The sub-CPU 202a then outputs a predetermined sound to the speaker 128 to indicate the movement of the electronic medal as it is actually dispensed or counted during the dispensing or counting process. During the counting process, the sub-CPU 202a may output the predetermined sound to the speaker 128 for both a short press and a long press of the counting switch 112, or it may output the predetermined sound to the speaker 128 for only one of the short press or long press of the counting switch 112. Furthermore, when the counting switch 112 is completed during the counting process (for example, pressed and released), the sub-CPU 202a may output a predetermined sound indicating that counting is complete, or, after the counting process is complete, output a predetermined sound to prevent forgetting to remove the card from the card insertion unit 364. In this way, the player can audibly confirm that the lending process and counting process are being performed appropriately. In addition, the sub-CPU 202a may notify the player that the lending process and counting process are being performed not only through the speaker 128, but also through other devices such as the liquid crystal display unit 124 and the effect lamps 126. Here, the CPU (Central Processing Unit) is used as an example of the main control unit, but various arithmetic elements such as MPU (Micro Processor Unit), DSP (Digital Signal Processor), FPGA (Field Programmable Gate Array) can be applied.

[0048] With Smart Pachislo 100, physical tokens are not required, making it possible to prevent cheating by inserting simulated tokens or using illegally brought-in tokens. Furthermore, since there is no need to install a mechanism for inserting and dispensing game tokens inside the game machine, design and manufacturing costs can be reduced. In addition, fraud prevention is possible by centrally managing the lending of game tokens to players and the counting of acquired game tokens. Moreover, by centrally managing data, it is possible to curb the element of gambling and, consequently, strengthen measures against addiction.

[0049] The specific processing in the main control board 200 will be explained below based on a flowchart.

[0050] (Main processing of the main control board 200) Figure 4 is a flowchart showing the main processing of the main control board 200. Here, we will first explain the outline of one game after initialization, following the main processing of the main control board 200, and then explain the details of each process. In addition, here we will explain in detail the processes related to the features of this embodiment, and omit the explanation of configurations unrelated to the features of this embodiment. Although we will omit a detailed explanation, when each process is executed, the switches used in each process (bet switch 116, start switch 118, stop switches 120a, 120b, 120c) are activated at the start of the process and deactivated at the end of the process.

[0051] (Step S100) When the Smart Pachislo 100 is powered on via the power switch and becomes energized, the initialization means 300 performs an initialization process in preparation for the start of gameplay. The initialization means 300 can also change settings. Setting changes involve changing the setting values ​​that indicate the degree of advantage in stages (for example, 6 stages). Setting changes also include resetting to the same setting value (a process that changes the current setting value to the same setting value as the current setting value (overwriting, maintaining)). While the power is on, the initialization means 300 continuously generates backup data and stores this backup data in the main RAM 200c. Therefore, even if an unexpected power outage occurs, the initialization process can use the stored backup data to restore the state before the power outage. For example, even if an unexpected power outage occurs while the reels 110 are rotating, after the recovery operation, the game will start again from a state where each reel 110 is rotating. Therefore, the initialization process does not basically initialize (clear the RAM) the main RAM 200c.

[0052] (Step S200) Next, the betting means 302 places an electronic token bet through the player's operation of the bet switch 116. The command transmission means 316 generates an insertion command indicating that the operation has been performed and transmits the generated insertion command to the sub-control board 202. The command transmission means 316 also transmits a game token insertion command, including transmission information indicating the number of tokens to be inserted, to the token count control board 204.

[0053] (Step S300) Next, the winning type lottery means 304 activates the game start operation on the start switch 118 and transitions to a state waiting for operation of the start switch 118. Here, in response to the player's operation of the start switch 118, the winning type lottery means 304 obtains a winning type lottery random number of 1 from the winning type lottery random numbers updated by the random number generator 200d of the main control board 200 at the time the start switch 118 is operated. The winning type lottery means 304 then determines a winning type lottery table corresponding to the currently set game state from the winning type lottery table, and determines which winning area in the determined winning type lottery table the obtained winning type lottery random number corresponds to, and determines the winning type or non-winning as the lottery result for the determined winning area. Furthermore, when the winning role "RBB" is determined in the winning type lottery, the game state control means 312 transitions the game state from a non-internal game state to an RBB internal game state. Furthermore, after the lottery result is determined in response to the operation of the start switch 118, the command transmission means 316 generates a winning type command that includes the lottery result of the winning type lottery (winning type or not winning) and information regarding the game state, and transmits the generated winning type command to the sub-control board 202.

[0054] (Step S400) When the start switch 118 is operated, the reel control means 306 drives the stepping motor 152 to rotate the left reel 110a, the middle reel 110b, and the right reel 110c. In this reel rotation process, after a predetermined time (for example, 4.1 seconds) has elapsed since the start of rotation of the left reel 110a, the middle reel 110b, and the right reel 110c in the previous game (wait), the rotation of the left reel 110a, the middle reel 110b, and the right reel 110c in the current game begins, and when all of the left reel 110a, the middle reel 110b, and the right reel 110c have reached a steady rotation, the process moves to step S500.

[0055] (Step S500) Next, the reel control means 306 activates the stop switches 120a, 120b, and 120c, and when it receives an operation of the stop switches 120a, 120b, or 120c by the player, it controls the stopping of one of the left reel 110a, middle reel 110b, or right reel 110c corresponding to that operation. In addition, when any of the stop switches 120a, 120b, or 120c is operated, the command transmission means 316 generates a stop command (first stop command, second stop command, third stop command) indicating the information of the operated stop switch 120a, 120b, or 120c each time an operation is made, and sequentially transmits the generated stop commands to the sub-control board 202.

[0056] (Step S600) Next, the determination means 308 determines which predetermined combination (winning combination) corresponds to the symbol combination displayed on the effective line A, which is the line for determining the winning combination, and updates the net increase counter according to that symbol combination if the player is in the advantageous section and a small win has occurred. Here, the advantageous section is a game section that is advantageous to the player, including a game section that has the performance related to the instruction function, that is, a game section in which auxiliary effects (instruction functions) are executed. Furthermore, in the advantageous section, if an auxiliary effect is activated as a result of a lottery etc. related to the operation of an auxiliary effect performed by the main control board 200, the main control board 200 may transmit information indicating the content of the instruction to peripheral boards such as the sub-control board 202, only when the content of the instruction is displayed on the notification means so that it can be identified. Furthermore, the game state control means 312, in the RBB internal game state, if the symbol combination displayed on the active line A corresponds to the winning combination "RBB", transitions the game state from the RBB internal game state to the RBB operating game state. In addition, the command transmission means 316 generates an entry command that includes the symbol combination displayed on the active line A, and the number of electronic medals to be paid out when a symbol combination corresponding to a minor role is displayed on the active line A, and transmits the generated entry command to the sub-control board 202.

[0057] (Step S700) Furthermore, the payout control means 310, based on the symbol combinations (stopping patterns of the reels 110) displayed on the active line A, for example, when a symbol combination corresponding to a minor role is displayed on the active line A, executes the payout process for the electronic medals corresponding to that minor role, and when a symbol combination corresponding to a replay role is displayed on the active line A, automatically executes the process for placing a bet for the next game. In addition, when the electronic medal payout process is completed, the command transmission means 316 generates a payout command indicating that the payout process has been completed and transmits the generated payout command to the sub-control board 202. The command transmission means 316 also transmits a payout completion command, which includes transmission information indicating the number of medals paid, to the medal count control board 204.

[0058] (Step S800) The game state control means 312 transitions the game state from the RBB-operated game state to the non-internal game state when a predetermined number of electronic tokens are dispensed during the RBB-operated game state. The performance state control means 314 changes the performance state and changes between advantageous and non-advantageous sections. The command transmission means 316 generates a game transition command including the changed game state or performance state, etc., when the game state or performance state is changed, and transmits the generated game transition command to the sub-control board 202. Thus, when the game transition process S800 is completed, the game ends.

[0059] One game is executed through a series of processes from step S200 to step S800. Thereafter, the process from step S200 to step S800 is repeated.

[0060] (Relationship between circuit boards) Furthermore, although this explanation uses the example shown in Figure 2, where a medal count control board 204 is provided separately from the main control board 200 in the smart pachislo 100, and the medal count control board 204 operates independently, the configuration of the boards and CPU can be varied in other cases as well.

[0061] Figure 5 is an explanatory diagram illustrating other board configurations. In the embodiment described above, as shown in Figure 5(a), the main control board 200 is equipped with a main CPU 200a (first control unit) that controls the progress of the game, and the medal count control board 204 is equipped with a medal CPU 204a (second control unit) that manages the electronic medals used for the game. The main control board 200 and the medal count control board 204 are connected via a harness, and the medal count control board 204 is connected to the game ball dispensing device connection terminal board 206 via a harness. The game ball dispensing device connection terminal board 206 receives power (VL) from the dedicated unit 350, uses that power as input to an insulating element such as a photocoupler, generates a VL connection signal indicating the connection status with the dedicated unit 350, and outputs it to the medal count control board 204. The medal count control board 204 can determine whether power is being supplied from the dedicated unit 350, or in other words, whether power is being supplied to the dedicated unit 350 and whether it is properly connected, by the ON / OFF status of the VL connection signal. With this board configuration, modifications to the configuration of the existing main control board 200 and increases in occupied area can be kept to a minimum, thereby reducing design costs.

[0062] Furthermore, the medal count control board 204 does not necessarily have to be separate from the main control board 200; as long as it fulfills its function, it may be integrally formed with the main control board 200. Specifically, as shown in Figure 5(b), the main control board 200 may house both the main CPU 200a, which controls the progress of the game, and the medal CPU 204a, which manages the electronic medals used for the game, and the main control board 200 and the game ball dispensing device connection terminal board 206 may be connected via a harness. In this case, by housing both the main CPU 200a and the medal CPU 204a on a single main control board 200, connectors and harnesses used for information exchange between the two can be eliminated, reducing the occupied area and improving the reliability of information transmission.

[0063] Furthermore, in the example shown in Figure 5(c), the main CPU 200a located on the main control board 200 manages the electronic tokens used for gameplay instead of the token CPU 204a, and the main control board 200 and the game ball dispensing device connection terminal board 206 are connected via a harness. Here, since the main CPU 200a on the main control board 200 controls the progress of the game and manages the electronic tokens, the connection lines that handle information exchange between the main CPU 200a and the token CPU 204a are no longer necessary, further reducing the occupied area and improving the reliability of information transmission.

[0064] Here, at least the main control board 200 must be enclosed in a main board case to prevent fraud. In addition, if the medal count control board 204, which has a function for managing the electronic medals used for gameplay, is a separate component, it must be enclosed in the main board case together with the main control board 200.

[0065] Figure 6 is an explanatory diagram illustrating the method of enclosing the case. For example, as shown in Figure 5(a), if the main control board 200, the medal count control board 204, and the game ball dispensing device connection terminal board 206 are each formed separately, and the main control board 200 and the medal count control board 204 are connected, and the medal count control board 204 and the game ball dispensing device connection terminal board 206 are connected, then as shown in Figure 6(a), it is conceivable to enclose the main control board 200, the medal count control board 204, and the game ball dispensing device connection terminal board 206 all in one main board case 200e. Here, as shown in Figure 6(a), an example is given in which the main control board 200 and the medal count control board 204 are integrally formed by directly and fixedly connecting the connectors to each other without using a harness, but they may also be connected via a harness.

[0066] Furthermore, as shown in Figures 5(b) and 5(c), if the main control board 200 is equipped with a main CPU 200a and a medal CPU 204a, or if the main CPU 200a is equipped alone, and the main control board 200 and the game ball dispensing device connection terminal board 206 are connected via a harness, then, with the main control board 200 and the game ball dispensing device connection terminal board 206 connected, the main control board 200 may be individually sealed in the main board case 200e and the game ball dispensing device connection terminal board 206e, as shown in Figure 6(b), or, as shown in Figure 6(c), the main control board 200 and the game ball dispensing device connection terminal board 206 may be individually sealed in a single main board case 200e.

[0067] In any case, the main control board 200, the medal count control board 204, and the game ball dispensing device connection terminal board 206 are all enclosed in a case. Furthermore, in this case, the structure must be such that it is easy to check not only the front surface of the board but also the back surface.

[0068] In the examples shown in Figures 5(a) and 5(b), the Smart Pachislo 100 operates with the main CPU 200a and the medal CPU 204a operating independently. The main CPU 200a controls the progress of the game, while the medal CPU 204a manages the electronic medals used in the game.

[0069] Figure 7 is an explanatory diagram illustrating the CPUs and areas (used areas or unused areas as described above) that execute each function of the Smart Pachislo 100. In Figure 7, "◎" indicates a typical execution area when the functions are divided between two CPUs, the main CPU 200a and the medal CPU 204a, as shown in Figures 5(a) and 5(b); "○" indicates an executable execution area; and "×" indicates an unexecutable execution area. For example, when the functions are divided between two CPUs, as shown in No. 12 of Figure 7, the medal CPU 204a's used area is generally responsible for functions such as controlling the game medal count display device 114 and controlling communication with the dedicated unit 350 (indicated by "◎" in Figure 7), but it is also possible for the main CPU 200a's used area to handle part or all of these functions (indicated by "○" in Figure 7).

[0070] (Communication between the smart pachislo machine and its dedicated unit) As described above, the Smart Pachislo 100 and the dedicated unit 350 ensure each other's normal operation by exchanging various information (messages) via serial communication. The serial communication uses an asynchronous communication method with full-duplex communication control. For example, the communication speed is 62500bps, and each byte of data is represented by 1 start bit, 8 data bits, and 1 stop bit. In this case, the character transmission time is 0.16msec to 3.9msec, and if the next start bit is not received within 3.9msec, that character is considered one message. For example, the Smart Pachislo 100 (in this case, for example, the medal CPU 204a of the medal count control board 204) sends the following game machine information notification, count notification, and loan receipt result response to the dedicated unit 350 via this serial communication.

[0071] Figures 8 to 11 are explanatory diagrams illustrating the format of the gaming machine information notification. As shown in Figure 8, the gaming machine information notification transmits one of three pieces of gaming machine information—gaming machine performance information, gaming machine installation information, and hall control / fraud monitoring information—to the dedicated unit 350, and the message length is variable, ranging from 18 to 57 bytes. Specifically, the first byte of the gaming machine information notification message indicates the message length (12h to 39h), and the second byte indicates the command type (in this case, gaming machine information notification) as "01h". The third byte indicates a sequence number from 00h to FFh as a serial number. This serial number is notified as 00h when the power is turned on and is incremented by 1 each time a notification is made. However, the notification following FFh will be 01h instead of 00h.

[0072] The fourth byte indicates the type of gaming machine. Bit 7 of the gaming machine type indicates the management medium, with "0" representing gaming balls and "1" representing gaming tokens. Bits 6-4 indicate the organizational classification, with "0" representing the Japan Amusement Machine Industry Association and "1" representing the Japan Electronic Amusement Machine Industry Association. Bits 3-0 indicate the type of gaming machine, with "1" representing pachinko machines, "2" representing slot machines, "3" representing arrangement ball machines, and "4" representing jankyu machines. The fifth byte indicates the type of gaming machine information. For example, if the gaming machine information is gaming machine performance information, it will be "00h", if the gaming machine information is gaming machine installation information, it will be "01h", and if the gaming machine information is hall computer / fraud monitoring information, it will be "02h". From the sixth byte onward, the gaming machine information (either gaming machine performance information, gaming machine installation information, or hall computer / fraud monitoring information) is displayed in a variable length.

[0073] For example, if the gaming machine information type is "00h", the gaming machine performance information is represented as 51 bytes and includes, as shown in Figure 9, the total number of tokens inserted, the total number of tokens paid out, MY (maximum difference in tokens), the total number of tokens paid out by special features, the total number of tokens paid out by consecutive special features, the feature ratio, the consecutive feature ratio, the advantageous section ratio, the feature ratio including instructions, the feature status ratio, the number of games played, the reserve, reservation 1, and reservation 2. The gaming machine performance information is transferred to the dedicated unit 350 and then further transmitted to the gaming machine information center (not shown). Here, MY represents the difference in tokens, with the lowest difference being 0, which is the difference between the number of electronic tokens inserted (bet amount) and the number of tokens paid out. Alternatively, or in addition to MY, the difference in tokens since the power was reset can also be used. Of this information, the byte order for total number of tokens inserted, total number of tokens paid out, MY, total number of tokens paid out by special features, total number of tokens paid out by consecutive special features, and number of games played is little-endian.

[0074] Furthermore, if the gaming machine information type is "01h", the gaming machine information is represented by 40 bytes of gaming machine installation information, which includes the main control chip ID number, main control chip manufacturer code, main control chip product code, medal count control chip ID number, medal count control chip manufacturer code, and medal count control chip product code, as shown in Figure 10. Here, the main control chip ID number (9 bytes) and medal count control chip ID number (9 bytes) are represented by the upper 4 bytes being 0, the following 4 bytes being the individual chip number or chip code, and the least significant byte being the identification code (LEM50A="21h", LES50A="22h", LEM7OA="23h", IDNAC8701="41h", IDNAC8702="42h", ​​IDNAC8703="43h"). However, if the medal CPU 204a is not installed, all 9 bytes are represented by 0. Note that the byte order of the main control chip ID number, main control chip manufacturer code, main control chip product code, medal count control chip ID number, medal count control chip manufacturer code, and medal count control chip product code is big-endian.

[0075] Furthermore, if the gaming machine information type is "02h", the hall computer / fraud monitoring information is represented as 12 to 16 bytes, and as shown in Figure 11, it includes the number of game tokens played, the number of tokens inserted, the number of tokens paid out, main control state 1, main control state 2, gaming machine error state, gaming machine fraud 1, gaming machine fraud 2, gaming machine fraud 3, number of game information, type information 1, count information 1, type information 2, and count information 2. Here, the relationship between the number of game tokens played, the number of tokens inserted, and the number of tokens paid out is "number of game tokens played" = "number of game tokens played" transmitted last time - "number of tokens inserted" + "number of tokens paid out" + "number of tokens lent" received after the number of game tokens transmitted last time - "number of tokens counted" transmitted after the number of game tokens transmitted last time. If this relationship is not satisfied, it can be determined that the hall computer / fraud monitoring information is abnormal. Furthermore, the setting change signal in bit 0 of the game machine fraud 1 indicates that the setting is being changed and that the setting change has been performed, and is output continuously from the time the setting is being changed until the end of one game after the setting change. In addition, the setting confirmation signal in bit 1 indicates that the setting is being confirmed, and as a countermeasure against cheating, it must be output for at least 3 seconds. If a power outage occurs while the setting confirmation signal is being output, the timer that was timing for 3 seconds may be reset and the setting confirmation signal may be output again for 3 seconds, or the timer value at the time of the power outage may be saved, and when the power is turned on (when the power is restored), timing may be restarted from the saved timer value and the setting confirmation signal may be output. In this case, the total time the setting confirmation signal is output before the power outage and after the power is restored will be 3 seconds. The game information consisting of a combination of type information 1 and count information 1, or a combination of type information 2 and count information 2, indicates by type information 1 and 2 whether it is a specified number (when the start switch 118 is operated) or the number of coins paid out (at the end of the game), and the number of coins is indicated by count information 1 and 2. During a replay, the specified number of times for replay activation will be notified. The number of game information items indicates the number of game information items; if the number of game information items is 0, the four items of type information 1, count information 1, type information 2, and count information 2 will not be transmitted.

[0076] Figure 12 is an explanatory diagram illustrating the format of the count notification. The count notification transmits the cumulative number of medals counted (described later) to the dedicated unit 350, and the message length is a fixed length of 7 bytes. Specifically, the first byte of the message indicates the message length (07h), and the second byte indicates the command type (in this case, count notification) as "02h". The third byte indicates a sequence number from 00h to FFh as the count serial number. This count serial number is notified as 00h when the power is turned on and is incremented by 1 each time a notification is made. However, the notification following FFh will be 01h instead of 00h. The fourth byte indicates the number of medals counted. The number of medals counted is the number of electronic medals counted at the time of the count notification. The fifth byte indicates the cumulative number of medals counted. The cumulative count of medals is the value accumulated from when the Smart Pachislo 100 is powered on, after being reset to 0000h. The value following FFFFh is 0000h. The 7th byte shows the checksum.

[0077] Figure 13 is an explanatory diagram illustrating the format of the loan receipt result response. The loan receipt result response is a response indicating the receipt result when a loan notification is received from the dedicated unit 350, and the message length is a fixed length of 5 bytes. Specifically, the first byte of the message indicates the message length (05h), and the second byte indicates "03h" indicating the command type (in this case, loan receipt result response). The third byte indicates a sequence number from 00h to FFh as the loan serial number. When the power is turned on, 00h is notified, and if the loan medal count receipt result described later is normal, the loan serial number received from the dedicated unit 350 is reflected as is. If the loan medal count receipt result is abnormal, the loan serial number from when the loan medal count receipt result was received normally from the dedicated unit 350 in the past is reflected. The fourth byte indicates the loan medal count receipt result (normal = 00h, abnormal = 01h). The fifth byte indicates the checksum.

[0078] Furthermore, the dedicated unit 350 sends the following loan notification to the smart pachislo 100 (in this case, for example, the medal CPU 204a).

[0079] Figure 14 is an explanatory diagram illustrating the format of the loan notification. The loan notification is transmitted from the Smart Pachislo 100 to the Smart Pachislo 100 when the dedicated unit 350 receives a counting notification from the Smart Pachislo 100. The message length is a fixed 5 bytes. Specifically, the first byte of the message indicates the message length (05h), and the second byte indicates the command type (in this case, loan notification) as "13h". The third byte indicates a sequence number from 00h to FFh as the loan serial number. This loan serial number is notified as 00h when the power is turned on and is incremented by 1 each time a notification is made. However, the notification following FFh will be 01h instead of 00h. The fourth byte indicates the number of loaned medals. The number of loaned medals indicates the number of electronic medals that have been loaned. If you have not received a gaming machine information notification, or if the gaming machine information type is not "02h: Hall Control / Fraud Monitoring Information", and the number of tokens counted in the counting notification is "1" or more, then the number of tokens dispensed will be notified as "0". The 5th byte will show the checksum.

[0080] Furthermore, if a specific abnormality occurs internally, the Smart Pachislo 100 may choose not to communicate with the dedicated unit 350. For example, if a specific abnormality occurs, such as a backup failure, a RAM (RWM) failure, or a manufacturer code mismatch, the medal CPU 204a of the Smart Pachislo 100 will issue an operation stop error without completing its startup process, and will restrict the initiation of communication with the dedicated unit 350.

[0081] Figure 15 is a timing chart showing the notification timings for game machine information notification, counting notification, loan notification, and loan receipt result response. As shown in Figure 15, the smart pachislo 100 (here, for example, the medal CPU 204a) sends game machine information notification to the dedicated unit 350 at a cycle of 300 msec (300 msec or more, but within 310 msec) from the completion of the smart pachislo 100's startup. The smart pachislo 100 also sends counting notification to the dedicated unit 350 100 msec (90 msec or more, but within 100 msec) from the start of game machine information notification. The dedicated unit 350 sends loan notification to the smart pachislo 100 within 170 msec from the start of receiving counting notification. After the smart pachislo 100 has completed receiving the loan notification, it notifies the dedicated unit 350 of the loan receipt result response within 10 msec. In this way, Smart Pachislo 100 can ensure a time of 20 msec or more between notifying the loan acceptance result response and sending the next gaming machine information notification.

[0082] Figure 16 is an explanatory diagram illustrating the transmission timing of gaming machine information notifications. As described above, gaming machine information notifications are sent to the dedicated unit 350 at 300 msec intervals. There are three types of gaming machine information notifications: gaming machine performance information, gaming machine installation information, and hall computer / fraud monitoring information. As shown in Figure 16, each has a different notification timing and priority. For example, gaming machine installation information is notified 60 seconds after the Smart Pachislo 100 has finished starting up, and thereafter at 60-second intervals. Similarly, gaming machine performance information is notified 180 seconds after the Smart Pachislo 100 has finished starting up, and thereafter at 180-second intervals. Hall computer / fraud monitoring information is notified at 300 msec intervals after the Smart Pachislo 100 has finished starting up. However, the transmission timings of the three notifications may overlap. If the transmission timings overlap, the gaming machine information notifications are sent sequentially according to priority. For example, if, within 180 seconds, the gaming machine performance information, gaming machine installation information, and hall control / fraud monitoring information overlap, and there is no update to the main control state in the hall control / fraud monitoring information and no game information, then the gaming machine installation information, which has a higher priority, will be notified first, followed by the gaming machine performance information 300 msec later, and then the hall control / fraud monitoring information 300 msec later. Also, if, within 60 seconds, the gaming machine installation information and hall control / fraud monitoring information overlap, and there is no update to the main control state in the hall control / fraud monitoring information and no game information, then the gaming machine installation information, which has a higher priority, will be notified first, followed by the hall control / fraud monitoring information 300 msec later. However, if there is an update to the main control state in the hall control / fraud monitoring information, or if there is game information, then the hall control / fraud monitoring information, which has a higher priority, will be notified first, followed by the gaming machine installation information and gaming machine performance information. With this configuration, the Smart Pachislo 100 and the dedicated unit 350 can exchange game machine information notifications (game machine performance information, game machine installation information, hall computer / fraud monitoring information), counting notifications, loan notifications, and loan receipt result responses at the appropriate timing and with the appropriate priority.

[0083] (VL connection signal) As explained using Figure 5, the game ball dispensing device connection terminal board 206 receives power from the dedicated unit 350, uses this power as input to an insulating element such as a photocoupler, generates a VL connection signal indicating the connection status with the dedicated unit 350, and outputs it to the medal CPU 204a of the medal count control board 204. The medal CPU 204a may or may not send a command to the main CPU 200a indicating that it has received the VL connection signal. If the medal CPU 204a sends a command to the main CPU 200a indicating that it has received the VL connection signal, the main CPU 200a may restrict (prohibit) the startup of only the main control board 200, only the medal count control board 204, or both the main control board 200 and the medal count control board 204, or stop the game from progressing, depending on whether the command indicates that the VL connection signal has been received or not. Furthermore, if the medal CPU 204a does not send a command to the main CPU 200a indicating that it has received the VL connection signal, the medal CPU 204a can individually restrict (prohibit) the activation of the medal count control board 204 or stop the game from progressing.

[0084] Here, if the VL connection signal is ON, the smart pachislo 100 can determine that it is properly connected to the dedicated unit 350 and that the dedicated unit 350 is powered on, so it can perform various processes targeting the main CPU 200a and the dedicated unit 350. On the other hand, if the VL connection signal is OFF, the smart pachislo 100 determines that it is not properly connected to the dedicated unit 350 (not connected) or that the dedicated unit 350 is powered off, and restricts the progress of the game. Specifically, if the VL connection signal is OFF, the smart pachislo 100 executes a game stop process. In this game stop process, the game is restricted as an error state of the main control board 200 (all processes for game progress based on betting electronic tokens, operation of the settlement switch 121, operation of the start switch 118, and counting processes are restricted (prohibited)). At this time, if the VL connection signal is OFF, the main CPU 200a and the token CPU 204a do not need to be started up.

[0085] Here, the counting process refers to the process of transferring some or all of the electronic medals held in the medal holder to the dedicated unit 350 in response to the player's operation of the counting switch 112. Specifically, if the counting switch 112 is not activated, if the number of game medals in the medal holder is 0, if the VL connection signal is OFF, or if counting is not possible, the number of medals to be counted (counting value) is set to "0". If a short press of the counting switch 112 is activated, the number of medals to be counted is set to "1". If a long press of the counting switch 112 is activated, if the number of game medals in the medal holder is less than 50, the number of electronic medals (game medals) is set to be counted, and if the number is 50 or more, the number of medals to be counted is set to "50". The number of medals to be counted is then added to the cumulative number of medals to be counted, and the counting serial number is updated. The Smart Pachislo 100 performs a checksum by treating the data sequence of the count notification message as a sequence of integer values ​​and calculating the sum, then sends the count notification to the dedicated unit 350. In parallel with this, the number of counted tokens is subtracted from the number of game tokens held in the token holding unit.

[0086] Here, if the counting switch 112 is operated while the game is playable, the counting process will always be executed. "While the game is playable" refers to the state in which the smart pachislo 100 and the dedicated unit 350 are connected and both are powered ON (a state in which a player can borrow electronic tokens, play a game on the smart pachislo 100, and count the results of the game). However, if the smart pachislo 100 is powered ON but the dedicated unit 350 is not powered ON, or if the smart pachislo 100 and the dedicated unit 350 are not connected, there is a risk that the counted tokens will be lost even if the smart pachislo 100 accepts the operation of the counting switch 112. In such cases, the operation of the counting switch 112 is disabled, and that period is not included in "while the game is playable". Furthermore, the period during which the Smart Pachislo 100 is unable to proceed with gameplay as a standalone unit, such as during the initialization process after power-on, during setting changes and setting confirmation, and during error states requiring recovery processing such as a reset, is not included in the "period during which gameplay is possible." During such initialization processes after power-on, during setting changes and setting confirmation, and during error states requiring recovery processing such as a reset, the counting process may or may not be performed.

[0087] Thus, if the VL connection signal is ON, the Smart Pachislo 100 will proceed with the game and accept counting processing as long as the game is playable. On the other hand, if the VL connection signal is OFF, the Smart Pachislo 100 will execute a game stop process and restrict (prohibit) all processes for proceeding with the game based on betting electronic tokens, operating the settlement switch 121, operating the start switch 118, and the counting processing described above. This is because, as mentioned above, if the VL connection signal is OFF, it can be determined that the Smart Pachislo 100 is not properly connected to the dedicated unit 350, or that the power to the dedicated unit 350 is OFF.

[0088] As explained using Figure 15, the smart pachislo 100 (for example, the medal CPU 204a) sends a counting notification containing information about the number of medals counted to the dedicated unit 350. However, if the smart pachislo 100 and the dedicated unit 350 are not properly connected (for example, not connected), or if the dedicated unit 350 is powered off, and the dedicated unit 350 is not properly prepared to receive the counting notification, then when the smart pachislo 100 receives an input operation (for example, a press operation) of the counting switch 112 and sends the counting notification to the dedicated unit 350, the number of medals counted based on that input operation may be lost. If the number of medals counted is lost, the total number of electronic medals decreases, resulting in an inconsistency in the electronic medals. In this embodiment, inconsistency refers to a situation where the total number of electronic medals, which is the sum of the number of game medals and the total number of acquired medals held by the dedicated unit 350, differs before and after the input operation of the counting switch 112, due to unintended loss or increase in the number of electronic medals. For example, if the total number of game medals is counted by the counting switch 112, and the number of game medals held in the smart pachislo 100 before counting differs from the number of acquired medals transferred to the dedicated unit 350 after counting, then an inconsistency occurs.

[0089] Therefore, before sending a counting notification to the dedicated unit 350, the smart pachislo 100 (for example, the medal CPU 204a) checks whether the dedicated unit 350 is connected by checking the ON / OFF status of the VL connection signal, which indicates the connection status with the dedicated unit 350. If the VL connection signal is OFF, indicating that the dedicated unit 350 is not connected, the smart pachislo 100 sets the counted medal count to "0" in order to limit the counting process itself.

[0090] When the counting number of tokens is set to "0", the Smart Pachislo 100 updates the number of tokens by subtracting the counting number "0" from the number of tokens in play. In other words, the updated number of tokens in play does not change in effect from before the update. The Smart Pachislo 100 displays the updated number of tokens in play on the token count display device 114. Since the number of tokens in play does not change in effect, the display on the token count display device 114 also does not change.

[0091] Furthermore, the Smart Pachislo 100 sends a counting notification to the dedicated unit 350 that includes information on the number of medals to be counted, which is set to "0". If the dedicated unit 350 is not connected, the dedicated unit 350 cannot properly receive the counting notification, and therefore the number of medals won does not change. Since the number of medals won does not change, the display on the medal count display device 374 also does not change.

[0092] In this way, by setting the counting number of medals to "0", both the number of game medals in the Smart Pachislo 100 and the number of medals acquired by the dedicated unit 350 remain unchanged, and therefore the total number of digitized medals also remains unchanged. For this reason, the Smart Pachislo 100 does not perform the counting process, and it is possible to avoid the loss of digitized medals in response to input operations on the counting switch 112. In other words, the Smart Pachislo 100 can avoid inconsistencies in the number of digitized medals.

[0093] Figure 17 is a flowchart showing the flow of the counting switch monitoring process in the medal CPU 204a. The counting switch monitoring process is executed when the counting switch 112 is pressed. Here, we will explain the processes related to this embodiment, and omit the processes not related to this embodiment. The numerical value of step S in this figure will be used only in the explanation of this figure.

[0094] As shown in Figure 17, when the medal CPU 204a detects pressure on the counting switch 112, specifically when it detects the ON edge of the counting switch 112 (YES in S1), it acquires a VL connection signal and determines whether the VL connection signal is ON or not (S2). If the VL connection signal is ON (YES in S2), the medal CPU 204a starts timing the timing counter of the smart pachislo 100 (S3). The timing counter starts timing in response to the detection of the ON edge of the counting switch 112 and counts from the ON edge to the OFF edge. Next, the medal CPU 204a determines whether it has detected the OFF edge of the counting switch 112 (S4). If the OFF edge of the counting switch 112 has not been detected (NO in S4), the medal CPU 204a determines whether a predetermined time (for example, 500 msec) has elapsed since the start of timing by the timing counter (S5). If the predetermined time has not elapsed (NO in S5), the medal CPU 204a returns to the process in step S4. If the predetermined time has elapsed (YES in S5), the medal CPU 204a sets the long press flag to ON (S6) and returns to the process in step S4. The long press flag is a flag for identifying a long press; when ON, it indicates a long press, and when OFF, it indicates that it is not a long press (i.e., a short press).

[0095] If the OFF edge of the counting switch is detected (YES in S4), the medal CPU 204a determines whether the long-press flag is OFF or OFF (S7). If the long-press flag is OFF (YES in S7), the medal CPU 204a sets the counting medal count to "1" and proceeds to step S9. The set counting medal count is stored in a predetermined register or RAM. If the long-press flag is ON (NO in S7), the medal CPU 204a proceeds to step S9. In step S9, the medal CPU 204a clears (turns OFF) the long-press flag. The medal CPU 204a clears the timing counter and terminates the counting switch monitoring process.

[0096] If the ON edge of the counting switch 112 is not detected (NO in S1), the counting switch monitoring process ends without performing any processing. If the VL connection signal is OFF (NO in S2), the medal CPU 204a sets the counted medal count to "0" (S11) and ends the counting switch monitoring process. The counted medal count of "0" is stored in a predetermined register or RAM. In other words, even if the counting switch 112 is pressed, if the VL connection signal is OFF, the counted medal count is set to "0", and the player's operation to count electronic medals is not accepted, or if accepted, is invalidated.

[0097] Figure 18 is a flowchart showing the counting process in the medal CPU 204a. The counting process is related to updating the count of the number of game medals, and is executed at interrupt timings that are repeated at a predetermined cycle (for example, 300ms), regardless of whether the counting switch 112 is pressed. Here, we will explain the processes related to this embodiment, and omit the processes that are not related to this embodiment. The numerical value of step S in this figure will be used only in the explanation of this figure.

[0098] As shown in Figure 18, when an interrupt timing occurs that repeats at a predetermined period, the medal CPU 204a acquires the VL connection signal and determines whether the VL connection signal is ON or OFF (S21). If the VL connection signal is ON (YES in S21), the medal CPU 204a proceeds to step S23. If the VL connection signal is OFF (NO in S21), the medal CPU 204a sets the counted medal count to "0" (S22) and proceeds to step S23. The counted medal count of "0" is stored in a predetermined register or RAM. In step S23, the medal CPU 204a acquires the current number of game medals from the medal holding unit (S23).

[0099] Next, the medal CPU 204a determines whether the long-press flag is ON or NOT ON (S24). If the long-press flag is ON (YES in S24), the medal CPU 204a determines whether the number of game medals acquired in step S23 is 50 or more (S25). If the number of game medals is 50 or more (YES in S25), the medal CPU 204a sets the counting number to 50 (S26) and proceeds to step S28. If the number of game medals is less than 50 (NO in S25), the medal CPU 204a sets the number of game medals to the counting number (S27) and proceeds to step S28. The counting number set in step S26 or step S27 is stored in a predetermined register or RAM. Also, if the long-press flag is OFF (NO in S24), the process proceeds to step S28.

[0100] In step S28, the medal CPU 204a retrieves the most recently stored number of counted medals from the register or RAM where the number of counted medals is stored (S28). For example, suppose that immediately before the current counting process, the counting switch monitoring process (see Figure 17) was performed and the number of counted medals was set to "1". In this case, in step S28 of the counting process (see Figure 18), the medal CPU 204a retrieves the number of counted medals "1" stored in a predetermined register or RAM. Also, if the number of counted medals was set to "50" in step S26 of the current counting process, the medal CPU 204a retrieves the number of counted medals "50" stored in a predetermined register or RAM. Furthermore, if the number of game medals less than "50" is set as the number of counted medals in step S27 of the current counting process, the medal CPU 204a retrieves the number of game medals less than "50" stored in a predetermined register or RAM as the number of counted medals. Furthermore, if the number of medals to be counted is set to "0" in step S11 of the counting switch monitoring process (see Figure 17) or step S22 of the counting process (see Figure 18), the medal CPU 204a retrieves the number of medals to be counted, "0," stored in a predetermined register or RAM.

[0101] Next, the medal CPU 204a updates the number of game medals by subtracting the acquired counted medals from the acquired number of game medals (S29). For example, if the acquired counted medals are "1", the updated (subtracted) number of game medals is the number obtained by subtracting "1" from the current acquired number of game medals. Also, if the acquired counted medals are "50", the updated number of game medals is the number obtained by subtracting "50" from the current acquired number of game medals. Furthermore, if a number of game medals less than "50" is acquired as the counted medals, all game medals less than "50" as counted medals are subtracted from the current acquired number of game medals, resulting in an updated number of game medals of "0". Also, if the acquired counted medals are "0", the updated number of game medals is the number obtained by subtracting "0" from the current acquired number of game medals. In other words, if the counted medals are "0", the number of game medals does not change in effect.

[0102] Next, the medal CPU 204a updates the display of the number of game medals on the game medal count display device 114 to the number of game medals derived in step S29 (S30). Next, the medal CPU 204a generates a counting notification containing the acquired counted medal information and sends it to the dedicated unit 350 (S31). Next, the medal CPU 204a clears the counted medal count in response to the completion of the counting notification (S32) and terminates the counting process.

[0103] In this way, the medal CPU 204a checks whether the VL connection signal is ON or OFF, and if the VL connection signal is OFF, it sets the counted number of medals to "0". Therefore, if the VL connection signal is OFF, even if the counting switch 112 is pressed, the number of game medals after the update will not substantially change from the number of game medals before the update. Also, if the VL connection signal is OFF, the dedicated unit 350 cannot properly receive the counting notification, so the number of acquired medals will not change either. Therefore, even if a counting notification is sent to the dedicated unit 350 before it has properly prepared to receive the counting notification, the Smart Pachislo 100 can avoid the loss or increase of electronic medals, thus preventing inconsistencies in the electronic medal count.

[0104] Furthermore, as shown in Figure 17, the medal CPU 204a sets the counted medal count to "0" immediately before updating the number of game medals, in other words, immediately before sending the counting notification. Therefore, in the Smart Pachislo 100, the counted medal count can be set to "0" more reliably, and inconsistencies in the electronic medal count can be avoided more reliably.

[0105] Furthermore, Smart Pachislo 100 determines whether the VL connection signal is ON or OFF in both the counting switch monitoring process and the counting process, and if the VL connection signal is OFF, it sets the counted number of medals to "0". As a result, for example, in the VL connection signal determination process in the counting switch monitoring process and the VL connection signal determination process in the counting process, the counted number of medals is set to "0" at the timing of the VL connection signal determination process that is executed before the VL connection signal turns OFF, so the counted number of medals can be set to "0" earlier. In addition, because Smart Pachislo 100 determines whether the VL connection signal is ON or OFF in both the counting switch monitoring process and the counting process, there are two opportunities to determine whether the VL connection signal is ON or OFF, which makes it possible to set the counted number of medals to "0" more reliably compared to a configuration where there is only one opportunity to determine whether the VL connection signal is ON or OFF.

[0106] Furthermore, in the Smart Pachislo 100, the medal CPU 204a performs the counting switch monitoring process and the counting process. The storage capacity of the ROM or RAM (storage unit) in the medal count control board 204 is smaller than that of the main ROM 200b or main RAM 200c (storage unit), but the processing load is low, resulting in a large amount of free space. Therefore, even if the program performs the ON / OFF determination of the VL connection signal and the process of setting the counted medal count to "0" when the VL connection signal is OFF in both the counting switch monitoring process and the counting process, it will not put pressure on the storage capacity of the medal count control board 204.

[0107] Furthermore, the Smart Pachislo 100 may determine whether the VL connection signal is ON or OFF in either the counting switch monitoring process or the counting process, while omitting the determination of whether the VL connection signal is ON or OFF in the other process. In this case, it is more preferable to omit the determination of whether the VL connection signal is ON or OFF in the counting switch monitoring process and to determine whether the VL connection signal is ON or OFF in the counting process. Also, in the Smart Pachislo 100, it is sufficient that the determination of whether the VL connection signal is ON or OFF is made before updating the number of game tokens or before counting notification, and if the VL connection signal is OFF, the number of tokens counted should be set to "0". The Smart Pachislo 100 is not limited to determining whether the VL connection signal is ON or OFF within the counting switch monitoring process or within the counting process.

[0108] Furthermore, when the Smart Pachislo 100 is powered on, if the dedicated unit 350 starts up slower than the Smart Pachislo 100, the VL connection signal may be delayed in turning ON, potentially resulting in an error. In this case, the impact of unintended error notifications can be reduced by temporarily lowering the output from the speaker 128, particularly the error notification level.

[0109] Furthermore, when the Smart Pachislo 100 is powered on, the main CPU 200a may wait for a predetermined waiting time (for example, 10 seconds) while waiting for the sub-CPU 202a and the medal count control board 204 to start up. This waiting time may be the CPU start-up time (for example, 0 to 100 msec) plus a time to ensure reliability (for example, 5 seconds).

[0110] (Counting) As described above, the medal CPU 204a of the Smart Pachislo 100 performs counting processing to transfer at least a portion of the electronic medals held in the medal holder to the dedicated unit 350 in response to the player's operation of the counting switch 112.

[0111] Figure 19 is a timing chart illustrating the counting process. Here, the medal CPU 204a measures the time the counting switch 112 is continuously operated in order to determine the counting method (short press or long press) desired by the player. For example, as shown in Figure 19(a), when a short press of the counting switch 112, i.e., an operation of less than 500 msec is received (time a), "1" is set as the counted medal count. When the 300 msec cycle (predetermined transmission cycle) caused by the timer interrupt shown in Figure 15 arrives (time b), "1" is subtracted from the number of game medals. Here, let's assume that the number of game medals has decreased from "30" to "29" after "1" is subtracted. Note that the counted medal count and the number of game medals are variables held in RAM by the medal CPU 204a. The smart pachislo 100 then sends a counting notification to the dedicated unit 350. When the dedicated unit 350 receives a counting notification, it adds the number of medals counted (in this case, "1") indicated in the counting notification to the number of medals won (for example, "0"), and displays the result of this addition (for example, "1") on the medals won display device 374.

[0112] Furthermore, for example, as shown in Figure 19(b), if the player continues to operate the counting switch 112 and a 300 msec cycle arrives (time c), and the counting switch 112 is pressed and held down, i.e., the operation is continued for 500 msec or more, then if the number of game tokens in the token holder is 50 or more, "50" is set as the number of tokens to be counted. If the number is less than 50, the total number of tokens is set as the number of tokens to be counted. Here, let's assume that the number of game tokens is "30", and the total number "30" is set as the number of tokens to be counted by pressing and holding the switch. Accordingly, the number of game tokens "30" is subtracted by the total number of tokens, and the number of game tokens becomes "0". The smart pachislo 100 then sends a counting notification to the dedicated unit 350 and clears the number of tokens to be counted (set to "0"). When the dedicated unit 350 receives a counting notification, it adds the number of medals counted in the counting notification (in this case, "30") to the number of medals won (for example, "0"), and displays the result of this addition (for example, "30") on the medals won display device 374.

[0113] As mentioned above, if the counting switch 112 is operated while the game is playable, the counting process will always be executed. Therefore, if a player operates the counting switch 112 while the game is in progress, the payout of electronic tokens during the game and the counting process may be executed in quick succession. For example, as shown in Figure 19(c), if the number of game tokens is "30", and a small win occurs during the game, and 15 electronic tokens are dispensed (time d), the token CPU 204a receives a payout completion command that includes the number of tokens dispensed, and adds the number of tokens dispensed "15" to the number of game tokens "30" to update the number of game tokens to "45" all at once. At the same time, the player continues to operate the counting switch 112, and when the 300 msec cycle arrives (time e), the medal CPU 204a, upon receiving a long press of the counting switch 112, i.e., an operation that continues for 500 msec or more, sets all the electronic medals (in this case, "45") as the counted medal count. Consequently, the number of game medals "45" is subtracted entirely, and the number of game medals becomes "0". The smart pachislo 100 then sends a counting notification to the dedicated unit 350 to clear the counted medal count. Upon receiving the counting notification, the dedicated unit 350 adds the counted medal count indicated in the counting notification (in this case, "45") to the number of acquired medals (for example, "0"), and displays the result of this addition (for example, "45") on the acquired medal count display device 374.

[0114] Here, the counting process is executed immediately after the electronic medals are dispensed, depending on the timing of the winning combination and the operation of the counting switch 112. Therefore, the number of game medals changes from "30" to "45" to "0" each time. However, if the electronic medal dispensing process and the counting process are executed consecutively within the 300 msec cycle in which the counting notification is sent, the counting notification will only notify the result. Therefore, regardless of the progression of the number of game medals from "30" to "45" to "0", the dedicated unit 350 will only display the change in the number of acquired medals from "0" to "45" on the acquired medal display device 374.

[0115] As shown in Figure 19, regardless of the timing of the change in the number of game tokens, that is, the timing of the payout or counting process of the electronic tokens, and without waiting for the change in the number of game tokens due to the payout process of the electronic tokens to be displayed on the game token display device 114, when the cycle for sending a count notification arrives, if the count switch 112 has been operated continuously for a predetermined time (for example, 500 msec) or longer, the medal CPU 204a sends a portion or all of the number of game tokens (in this case, all, "45") as the counted number of tokens. Therefore, even if the dispensing process and counting process of electronic medals overlap, depending on the timing, the cycle for sending a count notification may arrive, and with a long press, the number of game medals will change from "30" to "0", and "30" will be sent to the dedicated unit 350 as the counted number of medals. Then, due to the dispensing process of electronic medals, the number of game medals will change from "0" to "15", and again the cycle for sending a count notification will arrive, and with a long press, the number of game medals will change from "15" to "0", and "15" will be sent to the dedicated unit 350 as the counted number of medals. In that case, the display content of the acquired medal count display device 374 may change from "0" to "30" to "45", and as shown in Figure 19(c), the display content of the acquired medal count display device 374 may change from "0" to "45". However, since the player has already started counting the number of game tokens by pressing and holding the counting switch 112, it is sufficient to confirm that the display on the acquired token count display device 374, which was "0", has finally become "45" by adding the number of game tokens and the number of electronic tokens dispensed. Therefore, differences in the way the number of game tokens displayed on the acquired token count display device 374 changes do not affect the progress of the game.

[0116] Here, the medal CPU 204a transmits part or all of the number of game medals (in this case, "45") to the dedicated unit 350 when the counting switch 112 is operated continuously for a predetermined time (e.g., 500 msec) or longer, regardless of the timing of changes in the number of game medals. This configuration allows the player to quickly grasp the final number of acquired medals without unnecessarily waiting for the acquired medal display device 374 to update, and to quickly start the next operation, thereby improving the operability of the smart pachislo 100.

[0117] Furthermore, the medal CPU 204a always accepts input from the counting switch 112 regardless of the number of game medals (even if the number of game medals is "0"), and measures the time during which the counting switch 112 is continuously operated.

[0118] For example, if the number of game tokens is "0", the count notification will show the number of tokens as "0", regardless of whether the counting process is performed or not. Therefore, if the number of game tokens is "0", it is conceivable that the counting process would not be performed, or that the time during which the counting switch 112 is continuously operated would not be measured. However, as shown in Figure 19(c), if the electronic token payout process occurs, the counting process can be performed on the dispensed electronic tokens (number of game tokens) even if the number of game tokens before the payout process was "0". In this case, if the time during which the counting switch 112 is continuously operated is only measured after the number of game tokens becomes a number other than "0" (after the payout process is completed), the counting process will be delayed, and the operability will be worse.

[0119] Here, the medal CPU 204a measures the time the counting switch 112 is continuously operated, regardless of the number of game tokens. This configuration ensures that a long press is reliably detected when it is time to send a counting notification. As a result, players can quickly grasp the final number of tokens won and begin the next operation, improving the usability of the Smart Pachislo 100. Furthermore, since the program executed by the medal CPU 204a does not need to determine (branch) whether the number of game tokens is "0" or not, the processing load is reduced, and the memory capacity can be reduced.

[0120] Furthermore, the period during which the medal CPU 204a sends counting notifications (e.g., 300 msec) and the period during which the display of the game medal count display device 114 is updated (a predetermined display period by timer interrupt: e.g., 1 msec) are managed independently. Therefore, depending on the timing of the electronic medal payout and counting processes described above and the timing of the display update of the game medal count display device 114, the way the game medal count is displayed on the game medal count display device 114 will differ.

[0121] Figure 20 is a timing chart illustrating the display of the number of game tokens. Here, as shown in Figure 19(c), a small win occurs as the game progresses, and let's assume that 15 electronic tokens are dispensed. Simultaneously, the player continues to operate the counting switch 112, and when a 300 msec cycle arrives, the token CPU 204a, upon receiving a long press of the counting switch 112, i.e., an operation that continues for 500 msec or more, sets the total number of electronic tokens (in this case, "45") as the counted number of tokens. Here, the number of game tokens changes from "30" to "45" due to the electronic token dispensing process, and then changes from "45" to "0" due to the counting process. Also, in the dedicated unit 350, the number of acquired tokens changes from "0" to "45" due to the counting process.

[0122] For example, as shown in Figure 20(a), suppose the display content of the game token count display device 114 is updated (changed) between the dispensing process and the counting process of the electronic tokens. Then, when the cycle for updating the display of the game token count display device 114 arrives (time f) in response to the change in the number of game tokens from "30" to "45" due to the dispensing process of the electronic tokens, the token CPU 204a changes the display of the number of game tokens on the game token count display device 114 from "30" to "45". Similarly, when the cycle for updating the display of the game token count display device 114 arrives (time g) in response to the change in the number of game tokens from "45" to "0" due to the counting process, the token CPU 204a changes the display of the number of game tokens on the game token count display device 114 from "45" to "0".

[0123] Here, the display on the game token count display device 114 is updated after the electronic token payout process is executed and again after the counting process is executed. Therefore, as the number of game tokens changes from "30" to "45" to "0", the display on the game token count display device 114 also changes from "30" to "45" to "0". In this case, the player can understand that the number of game tokens has changed from "30" to "45" to "0" through the game token count display device 114.

[0124] Furthermore, for example, as shown in Figure 20(b), suppose that both the dispensing process and the counting process for electronic tokens are executed during the cycle in which the display of the game token count display device 114 is updated. In this case, the token CPU 204a will see that the number of game tokens changes from "30" to "45" due to the dispensing process for electronic tokens, and then changes from "45" to "0" due to the counting process. However, when the cycle for updating the display of the game token count display device 114 arrives (time h), the number of game tokens has already become "0", so the token CPU 204a directly changes the display of the number of game tokens on the game token count display device 114 from "30" to "0".

[0125] Here, the display on the game token count display device 114 is updated after both the dispensing and counting processes for the electronic tokens have been executed. Therefore, while the number of game tokens increases from "30" to "45" and then decreases to "0", the display on the game token count display device 114 immediately decreases from "30" to "0". In this case, the player understands that the number of game tokens has changed from "30" to "0" through the game token count display device 114.

[0126] Here, if we try to make the player aware that the number of game tokens has changed in stages, such as from "30" to "45" to "0", via the game token count display device 114, the token CPU 204a must wait for the display content of the game token count display device 114 to be updated before performing the counting process, which delays the counting process. Furthermore, in order for the player to recognize the update of the display on the game token count display device 114, the display time needs to be long enough for them to recognize it, which further delays the counting process and worsens the operability.

[0127] Here, as shown in Figure 20, the medal CPU 204a, regardless of whether the display content of the game medal count display device 114 has been updated in response to a change in the number of game medals, sends a portion or all of the number of game medals (in this case, all, "45") to the dedicated unit 350 as the counted number of game medals when the cycle for sending a count notification arrives. Therefore, when the number of game medals changes from "30" to "45" to "0", the number of game medals displayed on the game medal count display device 114 may change from "30" to "45" to "0", as shown in Figure 20(a), or it may change from "30" to "0", as shown in Figure 20(b). However, since the player has already started counting the number of game medals by long-pressing the count switch 112, it is sufficient for the player to confirm that the display content of the game medal count display device 114, which was "30", has finally become "0". Furthermore, the player only needs to confirm that the display on the acquired medal count display device 374, which initially showed "0," ultimately becomes "45" when the number of game medals played and the number of electronic medals dispensed are combined. Therefore, differences in the way the number of game medals displayed on the game medal count display device 114 changes do not affect the progress of the game.

[0128] Here, the medal CPU 204a transmits at least a portion of the number of game medals (in this case, "45") to the dedicated unit 350 when the counting switch 112 is operated continuously for a predetermined time (e.g., 500 msec) or longer, regardless of the timing of changes in the number of game medals. This configuration allows the player to quickly grasp the final number of game medals without unnecessarily waiting for the display on the game medal count display device 114 to update, and to quickly start the next operation, thereby improving the operability of the smart pachislo 100.

[0129] In this explanation, we have used Figures 19 and 20 to illustrate an example where the dispensing and counting processes for electronic tokens are executed consecutively. However, the change in the number of game tokens is not limited to these processes; it can also apply to various other processes, such as the insertion of electronic tokens.

[0130] Incidentally, as explained using Figure 15, the smart pachislo 100 (for example, the medal CPU 204a) transmits a game machine information notification to the dedicated unit 350 at a predetermined interval (for example, a 300 msec interval). Furthermore, the smart pachislo 100 transmits a counting notification to the dedicated unit 350 100 msec after transmitting the game machine information notification to the dedicated unit 350. In other words, the smart pachislo 100 transmits a counting notification containing information on the number of medals counted to the dedicated unit 350 at a predetermined interval (for example, a 300 msec interval), similar to the game machine information notification.

[0131] Furthermore, the counting switch 112 is an input operation unit that accepts a predetermined input operation (for example, a pressing operation) by the player. The smart pachislo 100 (for example, the medal CPU 204a) is capable of receiving a signal indicating the input operation from the counting switch 112 (input operation unit). Based on the signal received from the counting switch 112, the smart pachislo 100 sets the number of medals to be counted as described later. At the predetermined period described above (for example, 300 msec), the smart pachislo 100 subtracts the set number of medals to be counted from the current number of game medals to update the number of game medals, and at a different period than the predetermined period (for example, 1 msec), it updates the display of the game medal count display device 114 to the updated number of game medals as needed.

[0132] Once the update of the number of game tokens is complete, the display content of the game token count display device 114 is updated immediately, for example, in 1 msec. Therefore, the display content is updated at approximately a predetermined interval (for example, 300 msec). As a result, the smart pachislo 100 changes the display content of the game token count display device 114 (i.e., the number of game tokens displayed by the game token count display device 114) at a substantially predetermined interval (for example, 300 msec) based on the signal received from the counting switch 112.

[0133] Furthermore, the Smart Pachislo 100 transmits a count notification containing information on the set number of counted medals to the dedicated unit 350 at the predetermined interval (for example, 300 msec) mentioned above. In other words, the Smart Pachislo 100 outputs a count notification to the outside based on the signal received from the count switch 112 at the predetermined interval.

[0134] Furthermore, the dedicated unit 350 updates the number of acquired medals based on the received counting notification and updates the display of the acquired medal count display device 374 to the updated number of acquired medals at intervals different from a predetermined period (for example, 1 msec). In the dedicated unit 350, once the update of the number of acquired medals based on the counting notification is completed, the display content of the acquired medal count display device 374 is updated immediately, for example, in 1 msec, so the display content is updated at approximately a predetermined interval (for example, 300 msec). Thus, the dedicated unit 350 updates the display on the acquired medal count display device 374 at a predetermined interval (300 msec) based on the counting notification received from the smart pachislo 100.

[0135] In this case, the player may quickly press the counting switch 112 multiple times in a row. In such a case, the smart pachislo 100 may receive (receive input) multiple signals indicating the press operation within one cycle (for example, within 300 msec) of a predetermined cycle (for example, a 300 msec cycle). The smart pachislo 100 ensures that the display on the dedicated unit 350 is properly maintained even if such multiple press operations occur within one cycle.

[0136] Specifically, if the smart pachislo 100 (for example, the medal CPU 204a) receives multiple signals from the counting switch 112 during one cycle, it will only validate one of those signals. More specifically, even if the smart pachislo 100 receives multiple signals from the counting switch 112 during one cycle, it will fixate the number of medals to be counted corresponding to the press operation of the counting switch 112 to "1". Then, based on the single valid signal (more specifically, based on the number of medals counted "1"), the smart pachislo 100 updates the display on the game medal count display device 114 and outputs a signal (for example, a count notification) to the outside.

[0137] Figure 21 is a flowchart showing the counting switch processing flow in the medal CPU 204a. The counting switch processing is executed when the counting switch 112 is pressed. The counting switch processing corresponds to steps S3 to S10, which are performed when step S1 in Figure 17 is YES. Here, we will explain the processing related to this embodiment, and omit the processing unrelated to this embodiment. The numerical values ​​of step S in this figure will be used only in the explanation of this figure.

[0138] As shown in Figure 21, when the medal CPU 204a detects pressure on the counting switch 112 (specifically, when it detects the ON edge of the counting switch 112), it starts timing the timing counter of the smart pachislo 100 (S3). The medal CPU 204a determines whether or not it has detected the OFF edge of the counting switch 112 (S4). If the OFF edge of the counting switch 112 has not been detected (NO in S4), the medal CPU 204a determines whether or not a predetermined time (for example, 500 msec) has elapsed since the start of timing the timing counter (S5). If the predetermined time has not elapsed (NO in S5), the medal CPU 204a returns to the process of step S4. If the predetermined time has elapsed (YES in S5), the medal CPU 204a sets the long press flag to ON (S6) and returns to the process of step S4.

[0139] If the OFF edge of the counting switch is detected (YES in S4), the medal CPU 204a determines whether the long-press flag is OFF or OFF (S7). If the long-press flag is OFF (YES in S7), the medal CPU 204a sets the counted medal count to "1" and proceeds to step S9. The set counted medal count is stored in a predetermined register or RAM. If the long-press flag is ON (NO in S7), the medal CPU 204a proceeds to step S9. In step S9, the medal CPU 204a clears (turns OFF) the long-press flag. The medal CPU 204a clears the timing counter and terminates the counting switch processing. Here, in step S8, the counted medal count is set to "1" instead of being increased by "+1".

[0140] Figure 22 is a time chart illustrating the setting of the number of medals to be counted. As shown in Figure 22, for example, at time point a, the number of game medals is "50", and a counting notification containing the information that the number of medals to be counted is "0" is sent from the smart pachislo 100 to the dedicated unit 350, and the number of medals acquired is "50". Then, it is assumed that the counting switch 112 is pressed three times within 300 msec, which is one cycle, from time point a.

[0141] The counting switch processing described above begins at the ON edge of the pressing operation of the counting switch 112, and at the OFF edge of the pressing operation, if it is a short press, the number of counted medals is set to "1". Since the number of counted medals is repeatedly set to "1" each time the counting switch 112 is short-pressed, for example, even if it is the third short press in one cycle, the number of counted medals will not be set to "3" but to "1".

[0142] At time point b, 300 msec (one cycle) has elapsed from time point a, as described above using Figure 18, the smart pachislo 100 subtracts the set counting number of tokens "1" from the current number of game tokens "50" to derive the number of game tokens "49". The smart pachislo 100 updates the display of the number of game tokens on the game token display device 114 from "50" to "49". In this way, even if the press operation is performed three times during one cycle, if the number immediately before the display update of the game token display device 114 is, for example, "50", the display will be updated to "49" instead of "47".

[0143] Furthermore, at time b, the smart pachislo 100 sends a counting notification containing the information of the counted medals "1" to the dedicated unit 350. Upon receiving the counting notification, the dedicated unit 350 adds the received counted medals "1" to the acquired medals "50" to derive the acquired medals "51". The dedicated unit 350 updates the display of acquired medals on the acquired medals display device 374 from "50" to "51". In this way, even if the press operation is performed three times during one cycle, if the number immediately before the display update of the acquired medals display device 374 is, for example, "50", the display will be updated to "51" instead of "53".

[0144] In other words, even if the press operation is performed multiple times during one cycle, the medal CPU 204a can set the number of medals to count to "1", thereby updating the display of the acquired medal count display device 374 of the dedicated unit 350 to increase by 1 every predetermined cycle (for example, 300 msec). For example, the display content of the acquired medal count display device 374 will not jump from "50" to "53", but will change continuously by 1, such as from "50" to "51". Therefore, in the smart pachislo 100, the acquired medal count display device 374 of the dedicated unit 350 can display the acquired medal count appropriately, thereby suppressing the possibility of causing distrust among players.

[0145] In the Smart Pachislo 100 described above, if the counting switch 112 received (input) multiple signals (e.g., ON edge) during one cycle, only one of the signals was considered valid. However, if the Smart Pachislo 100 receives the counting switch 112 (e.g., ON edge) multiple times during one cycle, all of the received signals may be processed as valid.

[0146] Figure 23 is a flowchart showing the counting switch processing flow for a modified example that effectively processes multiple signals. The flowchart in Figure 23 differs from the flowchart in Figure 21 in that step S8 is changed to step S18, but the other steps are the same as in the flowchart in Figure 21.

[0147] As shown in Figure 23, when the long-press flag is OFF (YES in S7), the Smart Pachislo 100 increments the counted medal count by "+1" (by 1).

[0148] Figure 24 is a time chart illustrating the setting of the number of counting medals for a modified example that effectively processes multiple signals. As shown in Figure 24, it is assumed that the counting switch 112 is pressed three times within 300 msec, which is one cycle, from time c.

[0149] In this modified example, the counting switch processing begins at the ON edge of the counting switch 112's press operation, and at the OFF edge of that press operation, if it is a short press, the counted medal count is increased by "+1". Therefore, each time the counting switch 112 is short-pressed during one cycle, the counted medal count increases by "1". For example, at the second OFF edge during one cycle, the counted medal count is set to "2", and at the third OFF edge during one cycle, the counted medal count is set to "3".

[0150] At time point d, 300 msec has elapsed from time point c, as explained using Figure 18, the smart pachislo 100 subtracts the set counting number of medals "3" from the current number of game medals "50" to derive the number of game medals "47". The smart pachislo 100 updates the display of the number of game medals on the game medal display device 114 so that it decreases sequentially by "1" from "50" → "49" → "48" → "47".

[0151] Furthermore, at time d, the smart pachislo 100 transmits a count notification containing the information of the counted number of medals "3" to the dedicated unit 350 because it has been pressed three times during one cycle. Upon receiving the count notification, the dedicated unit 350 adds the received counted number of medals "3" to the acquired number of medals "50" to derive the acquired number of medals "53". The dedicated unit 350 updates the display of the acquired number of medals on the acquired number display device 374 so that it increases sequentially by "1" from "50" to "51" to "52" to "53".

[0152] Thus, even in this modified example where multiple signals are processed effectively, the number of acquired medals can be appropriately displayed in the acquired medal display device 374 of the dedicated unit 350.

[0153] (Counting sound) As described above, in the Smart Pachislo 100, when the counting switch 112 is operated and coefficient processing is performed, a counting sound is output from speaker 128 to notify that the counting switch 112 has been operated (notify that the electronic tokens have been moved). Similarly, in the Smart Pachislo 100, when the dispensing switch 366 is operated and dispensing processing is performed, a dispensing sound is output from speaker 128 to notify that the dispensing switch 366 has been operated (notify that the electronic tokens have been moved). Dispensing processing refers to the process of dispensing electronic tokens by transmitting information for dispensing some or all of the electronic tokens from the dedicated unit 350 to the Smart Pachislo 100 in response to the player's operation of the dispensing switch 366. Below, the output of counting sounds and dispensing sounds will be explained using counting sounds as an example.

[0154] As explained using Figure 19, the medal CPU 204a sets the number of medals to be counted to "0" if the counting switch 112 is not operated, sets the number of medals to be counted to "1" if the counting switch 112 is briefly pressed, and sets the number of medals to be counted to "50" (or the total number of medals if the number of game medals is 50 or less) if the counting switch 112 is long-pressed. Then, when the timing for sending a count notification, which occurs every 300 msec, arrives, the medal CPU 204a sends a count notification containing the set number of medals to be counted to the dedicated unit 350.

[0155] When the medal CPU 204a sends a count notification to the dedicated unit 350 that includes information on the number of medals to be counted ("1", "50", or any number between "1" and "50"), indicating that the counting switch 112 has been operated, it also sends a signal (count notification trigger signal) to the main control board 200 indicating that the counting process has been performed. When the main CPU 200a of the main control board 200 receives the count notification trigger signal from the medal control board 204, it sends a count sound notification to the sub-control board 202 instructing it to output a count sound. When the sub-CPU 202a of the sub-control board 202 receives the count sound notification through the main control board 200, it outputs a count sound through the speaker 128. As a result, the count sound is continuously output while the counting process is being performed in response to the operation of the counting switch 112.

[0156] Furthermore, the medal CPU 204a is not limited to transmitting a count notification trigger signal at the timing of transmitting a count notification that includes information on the number of counted medals indicating that the counting switch 112 has been operated. For example, it may transmit a count notification trigger signal at the timing when the number of game medals reflecting the set number of counted medals is displayed on the game medal display device 114, after the number of counted medals indicating that the counting switch 112 has been set.

[0157] The Smart Pachislo 100 may be equipped with a total of seven speakers as speaker 128: two upper speakers, two lower speakers, two tweeters, and one bass speaker. The upper speakers are, for example, provided one on each side of the symbol display window 108 in the front upper door 104. The upper speakers are installed on the back of the front upper door 104, and an opening is provided in front of the upper speakers in the front upper door 104. The lower speakers are, for example, provided one on each side of the front lower door 106. The lower speakers are installed on the back of the front lower door 106, and an opening is provided in front of the lower speakers in the front lower door 106. The tweeters are, for example, provided one near the left upper speaker and one near the right upper speaker. The tweeter is mounted on the back of the front upper door 104, and an opening is provided in the front of the front upper door 104 where the tweeter is located. The bass speaker is located, for example, near the reel 110 inside the housing 102. There is no opening in the front of the bass speaker inside the housing 102. The upper and lower speakers output, for example, mid-range sounds. The tweeter outputs, for example, high-range sounds. The bass speaker is, for example, a woofer and outputs low-range or sub-low-range sounds. The counting tone can be output from any of the upper speaker, lower speaker, tweeter, and bass speaker.

[0158] During gameplay, various sounds are output that effectively enhance the game, such as sound effects (e.g., background music), dialogue from characters in the game (e.g., "Bonus confirmed!"), and sound effects (SE). Hereafter, these various sounds related to gameplay will be collectively referred to as game sounds. When the counting switch 112 is operated during gameplay, in addition to the above-mentioned game sounds, a counting sound may also be output during gameplay in conjunction with the operation of the counting switch 112.

[0159] Figure 25 illustrates the operation when the game sound and the counting sound overlap. Figure 25(a) shows an example of the volume when there is no overlap between the game sound and the counting sound, and only the game sound is output. As shown in Figure 25(a), the game sound can be output from each speaker at the maximum settable volume (100%) for each speaker. Here, the louder the speaker volume, the greater the current flowing through the speaker's voice coil, and the greater the current flowing through the speaker's voice coil, the higher the speaker's temperature. When there is no overlap between the game sound and the counting sound, as shown in Figure 25(b), even when the game sound is output, the temperature of each speaker does not exceed the upper limit of the allowable temperature for each speaker (hereinafter referred to as the upper limit of the allowable temperature). Note that Figure 25(b) shows the temperature of any one speaker among the speakers as an example.

[0160] Figure 25(c) shows an example of the volume when the game sound and the counting sound overlap. In Figure 25(c), the game sound is output at the maximum configurable volume (100%) for each speaker, and the counting sound is also output at the maximum configurable volume (100%) for each speaker. When the game sound and the counting sound overlap in this way, and both are output at the maximum volume (maximum configurable volume), the temperature of each speaker may exceed the permissible temperature limit for each speaker, as shown in Figure 25(d). In some cases, this may cause damage to the speaker whose temperature exceeds the permissible temperature limit. Note that Figure 25(d) shows the temperature of any one speaker among the speakers as an example.

[0161] Therefore, as shown in Figure 25(e), when the game sound and the counting sound overlap, the volume of the game sound is reduced relative to the maximum volume, while the volume of the counting sound is output at the maximum volume (the maximum value of the configurable volume (100%)). For example, in the upper speaker, the volume of the game sound is reduced by 10% relative to the maximum volume, and the game sound is output at 90% of the maximum volume. In the lower speaker, tweeter, and bass speaker, the volume of the game sound is reduced by 50% relative to the maximum volume, and the game sound is output at 50% of the maximum volume.

[0162] As a result, as shown in Figure 25(f), even if the game sound and counting sound are output simultaneously, it is possible to prevent the temperature of each speaker from exceeding the permissible upper temperature limit for each speaker. Consequently, speaker damage can be prevented. In addition, although the volume of the game sound is reduced compared to the maximum volume, the game sound is still output, which helps to prevent players from feeling any discomfort regarding the progress of the game, and allows the game to proceed appropriately.

[0163] Furthermore, in the example shown in Figure 25(e), the decrease in volume of the game sounds output from the lower speaker, tweeter, and bass speaker is greater than the decrease in volume of the game sounds output from the upper speaker. Since the upper speaker outputs mid-range sounds close to the player's ears, players are sensitive to the sound from the upper speaker. If the decrease in volume of the game sounds output from the upper speaker is large, players are more likely to perceive the decrease in volume, potentially reducing the effectiveness of the game sounds. On the other hand, since the lower speaker, tweeter, and bass speaker are relatively far from the player's ears, even if the decrease in volume of the lower speaker, tweeter, and bass speaker is larger compared to the upper speaker, players are less likely to perceive the decrease in volume, and the reduction in the effectiveness of the game sounds is suppressed. Therefore, by making the reduction in volume of the game sounds output from the lower speaker, tweeter, and bass speaker greater than the reduction in volume of the game sounds output from the upper speaker, it is possible to suppress the reduction in the effectiveness of the game sounds while preventing damage to the speakers.

[0164] Furthermore, the reduction in volume of game sounds output from speakers other than the upper speaker among the upper speaker, lower speaker, tweeter, and bass speaker is not limited to the configuration in which the reduction in volume of game sounds output from the upper speaker is greater than the reduction in volume of game sounds output from the upper speaker. For example, among the multiple speakers arranged at multiple positions in the smart pachislo 100, the reduction in volume of game sounds output from speakers other than a specific speaker may be greater than the reduction in volume of game sounds output from a specific speaker. This configuration also prevents damage to the speakers and allows the game to proceed appropriately.

[0165] Furthermore, the reduction in the volume of the game sound may be made to the same extent for all speakers, including the upper speaker, lower speaker, tweeter, and bass speaker. This configuration also prevents damage to the speakers and allows the game to proceed properly.

[0166] Furthermore, in the Smart Pachislo 100, it is necessary to ensure that the total current value of the casing 102 (hereinafter referred to as the total current value of the casing 102), which is the sum of the currents flowing through each part of the Smart Pachislo 100, does not exceed the upper limit of the current that the casing 102 is allowed to handle (hereinafter referred to as the upper limit of the allowable current). When the game sound and the counting sound are output simultaneously, in addition to the current required to output the game sound, a current is also required to output the counting sound. Therefore, if the game sound and the counting sound overlap, the temperature of each speaker will rise, and the total current value of the casing 102 may exceed the upper limit of the allowable current.

[0167] As described above, when the game sound and the counting sound overlap, the volume of the game sound is reduced relative to the maximum volume, while the volume of the counting sound is output at the maximum volume, thereby preventing the total current value of the casing 102 from exceeding the allowable current limit. As a result, damage to various parts of the casing 102 can be prevented. In addition, by reducing the volume of the game sound, the total current value of the casing 102 can be suppressed, making it possible to miniaturize the power supply.

[0168] In Figure 25(e), the volume of the upper speaker was set to 90%, and the volumes of the lower speaker, tweeter, and bass speaker were set to 50%. However, the numerical values ​​for the volume of the game sounds are just examples, and the volume of the game sounds may be set to any value considering the temperature of each speaker and the total current value of the casing 102.

[0169] Figure 26 is a flowchart illustrating the counting sound processing performed by the performance control means 334. The numerical value of step S in this figure will be used only in the explanation of this figure. The counting sound processing is the process of outputting counting sounds from each speaker based on the reception of a counting sound notification.

[0170] The performance control means 334 determines, for example, whether a counting sound notification has been received at a predetermined interval (S1). If a counting sound notification is received (YES in S1), the performance control means 334 sets the volume of the game sounds to be reduced (S2). For example, the performance control means 334 sets the volume settings of the game sound tracks, such as the performance sound track, the dialogue track, and the SE track, to a predetermined volume value that is smaller than the volume setting value immediately before receiving the counting sound notification (under normal circumstances). As a result, the volume of the game sounds output from each speaker is reduced.

[0171] After the setting to reduce the volume of the game sounds is completed, the performance control means 334 outputs an audio signal indicating the counting sound to each speaker (S3). As a result, the counting sound is output from each speaker. The performance control means 334 outputs the counting sound each time it receives a counting sound notification. For example, if the counting switch 112 is pressed and held down, the counting sound is output for as long as it is pressed and held down.

[0172] Furthermore, if the system determines at predetermined intervals whether a counting tone notification has been received and finds that no counting tone notification has been received (NO in S1), the performance control means 334 determines whether a counting tone is being output (S4). If it determines that a counting tone is being output (YES in S4), the performance control means 334 stops outputting the sound signal indicating the counting tone to each speaker (S5). As a result, the output of the counting tone that was being output from each speaker is stopped. For example, if the long press on the counting switch 112 is released, the output of the counting tone is stopped in accordance with the release of the long press.

[0173] After the counting sound stops, the performance control means 334 sets the volume of the game sound to the volume immediately before receiving the counting sound notification (normal operation) (S4), and terminates the counting sound processing. As a result, the volume of the game sound output from each speaker returns to the normal volume.

[0174] As described above, the Smart Pachislo 100, an example of a gaming machine that can be connected to a specific unit (e.g., a dedicated unit 350) that lends out gaming value, includes a gaming value control means (e.g., a medal count control board 204) that manages gaming value (e.g., electronic medals) and an effect control means 334 that controls the effects. The effect control means 334 outputs gaming sounds according to the progress of the game through an audio output unit (e.g., each speaker). The gaming value control means (e.g., a medal count control board 204) may perform counting processing to transfer gaming value to the specific unit. In the Smart Pachislo 100, an example of a gaming machine, while counting processing is being performed, a counting sound is output to indicate that counting processing is taking place, and the volume of the gaming sounds is reduced. This makes it possible to proceed with the game appropriately and prevents damage to the speakers due to speaker temperature and damage to the casing 102 due to the total current value of the casing 102.

[0175] Furthermore, in cases where the game sound and the dispensing sound overlap, the volume of the game sound may be reduced and output from each speaker, as in the case where the game sound and the counting sound overlap. In this case as well, the amount of reduction in the volume of the game sound output from speakers other than a specific speaker among the multiple speakers arranged at multiple positions in the smart pachislo 100 may be greater than the amount of reduction in the volume of the game sound output from the specific speaker, or the amount of reduction in the volume of the game sound may be made to be the same for all speakers, including the upper speaker, lower speaker, tweeter, and bass speaker. In these embodiments as well, it is possible to proceed with the game appropriately and to prevent damage to the speakers due to speaker temperature and damage to the cabinet 102 due to the total current value of the cabinet 102.

[0176] Furthermore, the amount of reduction in the volume of the game sound when the game sound and the counting sound overlap, and the amount of reduction in the volume of the game sound when the game sound and the dispensing sound overlap, may be made to be the same (the reduction amounts may not differ), or they may be made different.

[0177] For example, the reduction in the volume of the game sound when the game sound and the dispensing sound overlap (e.g., a 25% reduction) may be less than the reduction in the volume of the game sound when the game sound and the counting sound overlap (e.g., a 50% reduction). Generally, it is assumed that the dispensing switch 366 is operated more frequently than the counting switch 112. Therefore, by making the reduction in the volume of the game sound when it overlaps with the dispensing sound less than the reduction in the volume of the game sound when it overlaps with the counting sound, it is possible to suppress the feeling of discomfort to the player regarding the progress of the game.

[0178] Furthermore, for example, the amount of reduction in the volume of the game sound when the game sound and the counting sound overlap (e.g., a 25% reduction) may be less than the amount of reduction in the volume of the game sound when the game sound and the dispensing sound overlap (e.g., a 50% reduction). When the counting switch 112 is operated with a relatively large number of game tokens, it is assumed that relatively long presses or relatively frequent short presses may occur, and that the frequency of operation of the counting switch 112 may increase or the operation time may increase instantaneously. For this reason, by making the amount of reduction in the volume of the game sound when it overlaps with the counting sound less than the amount of reduction in the volume of the game sound when it overlaps with the dispensing sound, it is possible to suppress the feeling of discomfort to the player regarding the progress of the game.

[0179] Furthermore, the counting tone and the lending tone may be the same or different. Different sounds may be, for example, different types of sounds (the sounds themselves), different pitches (intervals), different lengths, different rhythms, or different phrases. When the counting tone and the lending tone are different, for example, the counting tone may be an ascending phrase (ascending phrase) and the lending tone a descending phrase (descending phrase), or the counting tone may be a descending phrase (descending phrase) and the lending tone an ascending phrase (ascending phrase). An ascending phrase (ascending phrase) is a group of sounds consisting of multiple notes whose pitch rises as they are played. A descending phrase (descending phrase) is a group of sounds consisting of multiple notes whose pitch falls as they are played.

[0180] When the dispensing switch 366 is operated, the electronic tokens are generally moved from the dedicated unit 350 to the smart pachislo 100 in units of 50. However, when the dispensing switch 366 is operated, the entire amount of electronic tokens held in the dedicated unit 350 may be moved from the dedicated unit 350 to the smart pachislo 100.

[0181] Furthermore, if the game sound and the loan sound overlap, or regardless of whether there is an overlap with the game sound, even if the loan switch 366 is operated, the loan sound may be prevented from being output from each speaker. Since the loan notification sent from the dedicated unit 350 to the smart pachislo 100 is done at 300 msec intervals, there may be a time lag between the operation of the loan switch 366 and the smart pachislo 100 receiving the loan notification. If the time lag is relatively long, it may cause the player to feel uncomfortable regarding the loan. By preventing the output of the loan sound, it is possible to avoid causing the player to feel uncomfortable regarding the loan. Similarly, if the game sound and the counting sound overlap, or regardless of whether there is an overlap with the game sound, even if the counting switch 112 is operated, the counting sound may be prevented from being output from each speaker. By preventing the output of the counting sound, it is possible to avoid causing the player to feel uncomfortable regarding the counting.

[0182] Furthermore, in the Smart Pachislo 100, if various errors occur, such as a door opening error, an error sound will be output in conjunction with the occurrence of the error. If the error sound and the counting sound overlap, both the error sound and the counting sound may be output from each speaker without reducing the volume of the error sound. Similarly, if the error sound and the dispensing sound overlap, both the error sound and the counting sound may be output from each speaker without reducing the volume of the error sound. Since the error sound has a higher priority than the game sound, outputting the error sound without reducing its volume makes it easier for hall staff and others to recognize that an error has occurred.

[0183] Furthermore, if the error sound and the counting sound overlap, the error sound may be output from each speaker without reducing the volume of the error sound, the counting sound may be output from each speaker with reduced volume, or the counting sound may not be output from each speaker at all. Similarly, if the error sound and the rental sound overlap, the error sound may be output from each speaker without reducing the volume of the error sound, the rental sound may be output from each speaker with reduced volume, or the rental sound may not be output from each speaker at all. According to this embodiment, it is possible to make it easier for hall staff and others to recognize that an error has occurred while suppressing the temperature of each speaker and the total current value of the housing 102 from exceeding the upper limit.

[0184] Here, the main CPU 200a manages whether the difference in the number of tokens inserted (bet amount) and the number of tokens paid out since the power was reset has reached a first predetermined difference in tokens (predetermined value). If the first predetermined difference in tokens is reached, it may activate a so-called complete function that restricts the progress of the game. When such a complete function is activated, the performance control means 334 may output a complete activation sound from each speaker to indicate that the complete function is activated. The main CPU 200a also manages whether the difference in tokens has reached a second predetermined difference in tokens, which is a predetermined difference in tokens less than the first predetermined difference in tokens at which the complete function is activated. If the second predetermined difference in tokens is reached, it may indicate that the activation of the complete function is approaching (that the first predetermined difference in tokens may be reached). The performance control means 334 may output a complete activation indication sound from each speaker to indicate that the activation of the complete function is approaching. Hereinafter, the complete operation sound and the sound indicating complete operation will be collectively referred to as the complete function sound.

[0185] If the complete function sound and the counting sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, while the counting sound may also be output from each speaker. Similarly, if the complete function sound and the dispensing sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, while the dispensing sound may also be output from each speaker. Since the complete function sound has a higher priority than the game sound, outputting the complete function sound without reducing its volume makes it easier for players to recognize that the complete function is about to activate or that the complete function is already activated.

[0186] Furthermore, if the complete function sound and the counting sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, the counting sound may be output from each speaker with reduced volume, or the counting sound may not be output from each speaker at all. Similarly, if the complete function sound and the dispensing sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, the dispensing sound may be output from each speaker with reduced volume, or the dispensing sound may not be output from each speaker at all. According to this embodiment, it is possible to make it easier for players to recognize that the operation of the complete function is approaching or that the complete function is operating, while suppressing the temperature of each speaker and the total current value of the housing 102 from exceeding the upper limit.

[0187] Furthermore, if the complete function sound and the counting sound overlap, the volume of the complete function sound may be reduced and output from each speaker, or the complete function sound may not be output from each speaker and the counting sound may be output from each speaker. Similarly, if the complete function sound and the dispensing sound overlap, the volume of the complete function sound may be reduced and output from each speaker, or the complete function sound may not be output from each speaker and the dispensing sound may be output from each speaker. According to this embodiment, it is possible to make the counting sound or dispensing sound more easily recognizable to the player, etc., while suppressing the temperature of each speaker and the total current value of the housing 102 from exceeding the upper limit.

[0188] Furthermore, if the game sound and the complete function sound overlap, the volume of the game sound may be reduced and output from each speaker, while the complete function sound may be output from each speaker. This configuration makes it possible to appropriately advance or limit the game, and prevents damage to the speakers due to speaker temperature and damage to the housing 102 due to the total current value of the housing 102.

[0189] Furthermore, if the game sound and the complete function sound overlap, the game sound may be output from each speaker without reducing the volume of the game sound, and the complete function sound may also be output from each speaker. This configuration makes it possible to appropriately proceed with or limit the game.

[0190] Furthermore, if the game sound and the complete function sound overlap, the game sound may be output from each speaker without reducing the volume of the game sound, the complete function sound may be output from each speaker with reduced volume, or the complete function sound may not be output from each speaker. According to this embodiment, it is possible to appropriately proceed with or limit the game, and damage to the speakers due to speaker temperature and damage to the housing 102 due to the total current value of the housing 102 can be prevented.

[0191] The medal CPU 204a manages whether the number of game medals (the number of game value held) falls below a predetermined number, and may notify the player that the number of game medals has decreased if it falls below the predetermined number. In this case, the performance control means 334 may output a warning sound from each speaker to notify the player that the number of game medals has decreased.

[0192] If the counting sound and the possession warning sound overlap, the possession warning sound may be output from each speaker without reducing the volume of the possession warning sound, and the counting sound may also be output from each speaker. Similarly, if the dispensing sound and the possession warning sound overlap, the possession warning sound may be output from each speaker without reducing the volume of the possession warning sound, and the dispensing sound may also be output from each speaker. According to this embodiment, it is possible to make it easier for the player to recognize the possession warning sound and the counting sound, or the possession warning sound and the dispensing sound.

[0193] If the counting sound and the possession warning sound overlap, the volume of the possession warning sound may be reduced and output from each speaker, or the possession warning sound may not be output from each speaker and the counting sound may be output from each speaker. Similarly, if the dispensing sound and the possession warning sound overlap, the volume of the possession warning sound may be reduced and output from each speaker, or the possession warning sound may not be output from each speaker and the dispensing sound may be output from each speaker. According to this embodiment, it is possible to make the counting sound or dispensing sound more easily recognizable to the player while suppressing the temperature of each speaker and the total current value of the casing 102 from exceeding the upper limit.

[0194] If the counting sound and the possession warning sound overlap, the possession warning sound may be output from each speaker, the volume of the counting sound may be reduced and output from each speaker, or the counting sound may not be output from each speaker at all. Similarly, if the dispensing sound and the possession warning sound overlap, the possession warning sound may be output from each speaker, the volume of the dispensing sound may be reduced and output from each speaker, or the dispensing sound may not be output from each speaker at all. According to this embodiment, it is possible to make the possession warning sound more easily recognizable to the player while suppressing the temperature of each speaker and the total current value of the casing 102 from exceeding the upper limit.

[0195] If the error sound and the inventory count warning sound overlap, the error sound may be output from each speaker without reducing its volume, and the inventory count warning sound may be output from each speaker without reducing its volume. This configuration makes it easier for players to recognize both the error sound and the inventory count warning sound.

[0196] If the error sound and the inventory count warning sound overlap, the error sound may be output from each speaker without reducing its volume, the inventory count warning sound may be output from each speaker with reduced volume, or the inventory count warning sound may not be output from each speaker. Depending on the nature of the error, the error sound may have a higher priority than the inventory count warning sound. In such cases, it is possible to make the higher-priority error sound more easily recognizable to the player, etc., while suppressing the temperature of each speaker and the total current value of the casing 102 from exceeding the upper limit.

[0197] If the error sound and the inventory count warning sound overlap, the inventory count warning sound may be output to each speaker without reducing its volume, the error sound may be output to each speaker with reduced volume, or the error sound may not be output to each speaker at all. Depending on the nature of the error, the inventory count warning sound may have a higher priority than the error sound. In such cases, it is possible to make the higher-priority inventory count warning sound more easily recognizable to the player, etc., while suppressing the temperature of each speaker and the total current value of the casing 102 from exceeding the upper limit.

[0198] If the complete function sound and the inventory count warning sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, and the inventory count warning sound may be output from each speaker without reducing the volume of the inventory count warning sound. According to this embodiment, both the complete function sound and the inventory count warning sound can be easily recognized by the player or others.

[0199] If the complete function sound and the possession count warning sound overlap, the complete function sound may be output from each speaker without reducing the volume of the complete function sound, the possession count warning sound may be output from each speaker with reduced volume, or the possession count warning sound may not be output from each speaker. According to this embodiment, the complete function sound can be made more easily recognizable to the player, etc., while suppressing the temperature of each speaker and the total current value of the housing 102 from exceeding the upper limit.

[0200] If the complete function sound and the possession count warning sound overlap, the volume of the complete function sound may be reduced and output from each speaker, or the complete function sound may not be output from each speaker, and the possession count warning sound may be output from each speaker without reducing its volume. According to this embodiment, the possession count warning sound can be made more easily recognizable to the player, etc., while suppressing the temperature of each speaker and the total current value of the housing 102 from exceeding the upper limit.

[0201] (Volume of the counting sound) As mentioned above, the game state includes the bonus game state. The bonus game state is a more advantageous state for the player than other game states. In addition, the performance state includes the AT performance state. The AT performance state is a more advantageous state for the player than other performance states. Note that the advantageous state is not limited to the bonus game state and the AT performance state, but may also be any state that is advantageous to the player, such as the RT game state where the probability of winning a replay is set high, the ART game state where the AT performance state and the RT game state proceed simultaneously, or the chance zone (CZ).

[0202] The performance control means 334 outputs various sounds, such as game sounds, in accordance with the progress of the game. Thus, the performance control means 334 also functions as a sound control means that controls the output of sounds in accordance with the progress of the game.

[0203] The performance control means 334 (sound control means) outputs predetermined sounds, such as background music and character voices, at a first volume level through an audio output unit such as a speaker when the player is in an advantageous state. Here, the predetermined sounds also include system sounds corresponding to the operation of the bet switch 116, start switch 118, stop switch 120, etc. The first volume level represents the normal volume level without any restrictions. The first volume level can also be adjusted through the menu screen of the smart pachislo 100.

[0204] Here, if no game-playing operations are performed for a predetermined period of time while the player is in a favorable state (if no game-playing operations are performed for a predetermined period of time or longer), the Smart Pachislo 100 game machine may enter a volume adjustment state. The volume adjustment state indicates a state in which the volume of a predetermined sound is limited to a second volume that is lower than the first volume. The second volume may include zero volume, i.e., muted. In the case of muted sound, the predetermined sound will not be output from the audio output unit.

[0205] As described above, the medal count control board 204 is a game value control means that manages game value (e.g., electronic medals). The medal count control board 204 may perform counting processing to transfer game value to a specific unit (e.g., a dedicated unit 350). The medal count control board 204 may also perform lending processing to transfer game value from a specific unit (e.g., a dedicated unit 350). As described above, the counting processing and lending processing can be performed at any time, and may be performed, for example, during a favorable state, and may also be performed during the volume adjustment state described above while in a favorable state.

[0206] The performance control means 334, when in an advantageous state, outputs a counting sound at a third volume level through the audio output unit to indicate that counting processing is being performed, in response to the execution of counting processing. The third volume level is independent of the first and second volumes level of the predetermined sound described above. However, the third volume level may be louder than the first volume level, the same as the first volume level, or less than the first volume level but louder than the second volume level. The counting sound, dispensing sound, and settlement sound are included in the transfer sound for transferring electronic tokens and are distinguished from game sounds.

[0207] As described above, when the system transitions to the volume adjustment state while in an advantageous state, the performance control means 334 limits the volume of the predetermined sound from the first volume to the second volume. However, even when the system transitions to the volume adjustment state while in an advantageous state, the performance control means 334 outputs the counting sound at the third volume. In other words, there is no volume restriction on the counting sound.

[0208] The medal CPU 204a transmits a counting notification in accordance with the player's operation of the counting switch 112, and also transmits a signal (counting notification trigger signal) to the main control board 200 indicating that the counting process has been completed. When the main CPU 200a receives the counting notification trigger signal, it transmits a counting sound notification to the sub-control board 202 instructing the output of the counting sound. The sub-CPU 202a can receive the counting sound notification through the main control board 200. When the performance control means 334 receives the counting sound notification, it outputs the counting sound at a third volume level through the audio output unit.

[0209] Furthermore, as mentioned above, different tracks are assigned to each type of game sound, such as tracks for sound effects, character voices, and sound effects (SE). In addition, separate transfer sound tracks are assigned to the counting sound and the dispensing sound, in addition to the game sound tracks. Note that the counting sound and the dispensing sound may be assigned to the same track or to different tracks. Also, the settlement sound that notifies that settlement processing is being carried out in response to the operation of the settlement switch 121 may be assigned to a different track from the game sounds.

[0210] When the performance control means 334 transitions to the volume adjustment state, it limits the volume of the predetermined sound track (tracks other than the counting sound track) from the first volume to the second volume. At this time, the volume of the counting sound track is maintained at the third volume. Because the volume of the counting sound track is maintained at the third volume, even if counting processing is performed while the volume adjustment state is active, the performance control means 334 can output the counting sound at the third volume.

[0211] As a result, in the case of the Smart Pachislo 100, one example of a gaming machine, it becomes easier for players and hall staff to recognize that counting is taking place, allowing the game to proceed appropriately.

[0212] Furthermore, when the performance control means 334 is in a favorable state, it outputs a loan sound at a third volume level through the audio output unit to notify that a loan process is underway, in response to the execution of the loan process. Even if the performance control means 334 transitions to a volume adjustment state when in a favorable state, it outputs the loan sound at the third volume level. In other words, there is no volume restriction on the loan sound.

[0213] The medal CPU 204a, upon receiving a loan notification transmitted from the dedicated unit 350, transmits a signal (loan notification trigger signal) to the main control board 200 indicating that the loan process has been completed. When the main CPU 200a receives the loan notification trigger signal from the medal count control board 204, it transmits a loan sound notification to the sub-control board 202 instructing the output of the loan sound. The sub-CPU 202a can receive the loan sound notification through the main control board 200. When the performance control means 334 receives the loan sound notification, it outputs the loan sound at a third volume level through the audio output unit.

[0214] When the performance control means 334 transitions to the volume adjustment state, it limits the volume of the predetermined sound tracks (tracks other than the counting sound track) from the first volume to the second volume. At this time, the volume of the rental sound track is maintained at the third volume. Because the volume of the rental sound track is maintained at the third volume, even if the rental process is performed while the volume adjustment state is active, the performance control means 334 can output the rental sound at the third volume.

[0215] As a result, in the case of the Smart Pachislo 100, one example of a gaming machine, it becomes easier for players and hall staff to recognize that a loan process is underway, allowing the game to proceed appropriately.

[0216] Figure 27 is a flowchart illustrating the flow of the volume control process performed by the performance control means 334. The numerical value of step S in this figure will be used only in the explanation of this figure. The volume control process is the process of controlling the volume of the sound output from the sound output unit. In Figure 27, for the sake of explanation, the counting sound will be explained, and the lending sound will be omitted as it is explained in the same way as the counting sound.

[0217] The performance control means 334 determines at predetermined intervals whether the state is advantageous (S1). If the state is not advantageous (NO in S1), the performance control means 334 terminates the volume control process.

[0218] If the game is in an advantageous state (YES in S1), the performance control means 334 determines whether a predetermined time has elapsed since no game-playing operations were performed (S2). If the predetermined time has not elapsed (NO in S2), the performance control means 334 sets the volume of the predetermined sound to the first volume (S3). The performance control means 334 then outputs an audio signal indicating the predetermined sound to the audio output unit (S4). As a result, the predetermined sound is output from the audio output unit at the first volume.

[0219] If a predetermined time has elapsed (YES in S2), the performance control means 334 limits the volume of the predetermined sound to the second volume (S5), and enters a volume adjustment state. The performance control means 334 then outputs an audio signal indicating the predetermined sound to the audio output unit (S4). As a result, the predetermined sound is output from the audio output unit at the second volume.

[0220] After outputting the sound signal of the predetermined tone, the performance control means 334 determines whether a counting tone notification has been received (S10). If a counting tone notification has been received (YES in S10), the performance control means 334 outputs the sound signal of the counting tone to the audio output unit for a predetermined time (S11) and terminates the volume control process. As a result, regardless of whether the volume adjustment state is in place or not, the counting tone is output from the audio output unit at the third volume level.

[0221] If a counting sound notification has not been received (NO in S10), the performance control means 334 determines whether a counting sound is being output (S13). If it determines that a counting sound is not being output (NO in S12), the performance control means 334 terminates the volume control process.

[0222] If the system determines that a counting sound is being output (YES in S12), the performance control means 334 stops outputting the sound signal indicating the counting sound from the audio output unit (S13) and terminates the volume control process. As a result, the output of the counting sound that was being output from the audio output unit is stopped. For example, if the long press on the counting switch 112 is released, the output of the counting sound is stopped in accordance with the release of the long press.

[0223] In this way, by maintaining a third volume level without limiting the volume during counting and lending processes, it becomes easier for players and hall staff to recognize that counting and lending processes are taking place, allowing for the game to proceed appropriately.

[0224] (Communication between the main CPU and the medal CPU) The above describes the communication between the Smart Pachislo 100 and the dedicated unit 350. Specifically, in parallel with the serial communication between the medal CPU 204a and the dedicated unit 350 described above, the main CPU 200a and the medal CPU 204a communicate serially within the Smart Pachislo 100. The medal CPU 204a obtains information by sending and receiving commands with the main CPU 200a and notifies the dedicated unit 350 of this information. The serial communication has a communication speed of, for example, 125,000 bps, and each byte of data is represented by 1 start bit, 8 data bits, and 1 stop bit. Here, we will explain the relationship between the main CPU 200a and the medal CPU 204a, which precedes the notification between the medal CPU 204a and the dedicated unit 350, and detail the communication between them.

[0225] (Contents held in RAM) Here, using Figures 5(a) and 5(b), we have provided an example in which the main CPU 200a and the medal CPU 204a are provided separately, and each CPU has its own ROM and RAM, and processes based on an independent program. However, information such as the total number of coins inserted, the total number of coins paid out, MY (maximum MY), the total number of coins paid out by special features, the total number of coins paid out by consecutive special features, and the number of games played are all common to this system, and accumulation begins when the power is turned ON and is maintained until it is reset when the power is restored after an outage. If the main CPU 200a manages some of the information and the medal CPU 204a independently manages other information, the following problem arises. That is, if the power to either the main CPU 200a or the medal CPU 204a is turned OFF and the power to the other remains ON, for example, the total number of coins inserted and the total number of coins paid out may be counted from a reset state, but the total number of coins paid out by special features and the total number of coins paid out by consecutive special features may be counted in an accumulated state without being reset. Therefore, cumulative information such as the total number of tokens inserted, the total number of tokens paid out, MY (maximum MY), the total number of tokens paid out by special features, the total number of tokens paid out by consecutive special features, and the number of games played will be managed by one CPU. For example, in this case, the main CPU 200a manages all of this information. This configuration makes it possible to avoid inconsistencies in information and to proceed with the game appropriately.

[0226] (Error priority) The main CPU 200a, during betting, payout, settlement, and counting of electronic tokens, refers to the number of electronic tokens inserted, the number of tokens paid out, the total number of tokens inserted, the total number of tokens paid out, etc., to check for inconsistencies in these relationships, and may report an error if an inconsistency is found. In addition, the main CPU 200a may check that the number of electronic tokens inserted during betting is between 1 and 3, and that the number of tokens paid out during electronic token payout is between 0 and 15, and may report an error if it falls outside these ranges. Such processing may be performed in the used memory area or in the unused memory area. Furthermore, in addition to the above, the main CPU 200a may also check a predetermined number corresponding to the game state.

[0227] Here, let's assume that in addition to errors in the main CPU 200a, the medal CPU 204a is also configured to perform its own error detection process. In this configuration, if errors occur simultaneously in the main CPU 200a and the medal CPU 204a, the error occurring in the main CPU 200a may be given priority and reported by a device such as the speaker 128. Alternatively, specific errors that may occur simultaneously in the main CPU 200a and the medal CPU 204a (for example, errors that are judged to be serious problems, such as backup errors or errors indicating abnormal RAM read / write operations) may be set, and if errors occur simultaneously in the main CPU 200a and the medal CPU 204a, the device may report these specific errors. Furthermore, if multiple errors occur simultaneously in the medal CPU 204a, the most recently occurring error may be given priority and reported by a device such as the game medal count display device 114. In addition, not limited to this case, a priority order may be set in advance for multiple errors, and if multiple errors occur simultaneously in the medal CPU 204a, the errors may be reported based on the set priority order. By pre-determining the priority of error reporting in this way, it becomes possible to respond quickly and effectively according to the urgency and priority of the errors. For example, if multiple errors occur, the error with the highest priority (1) will be reported. When the cause of the error is removed and the error clearing operation is performed, the error report for error 1 at that time will be cleared, and the next highest priority error will be reported in sequence. In other words, the error report for error 1 will be cleared in response to the clearing operation for error 1. Furthermore, it is not only possible to control the system so that the error report for error 1 is cleared in response to the clearing operation for error 1, but it is also possible to control the system so that multiple error reports whose causes have been removed are cleared simultaneously in response to the clearing operation for error 1. In that case, when the error clearing operation is performed, multiple error reports whose causes have been removed will be cleared, and the error with the highest priority among the errors whose causes have not been removed will be reported.Furthermore, the medal count control board 204 may be equipped with separate individual devices such as a 7-segment display, and if an error occurs in the medal CPU 204a, the individual device may be used to notify the player in place of, or in addition to, the game medal count display device 114.

[0228] (RAM abnormality) Furthermore, the handling of RAM anomalies among the errors will be performed in the unused memory area by the main CPU 200a, and in the used memory area by the medal CPU 204a. This is because the main CPU 200a has limited capacity in the used memory area, while the medal CPU 204a has ample capacity in the used memory area. This configuration makes it possible to ensure that gameplay proceeds appropriately while suppressing an increase in the memory capacity of the main ROM 200b.

[0229] (Sending and receiving commands) The main CPU 200a sends predetermined commands to the medal CPU 204a. For example, when the bet switch 116 is operated, the main CPU 200a may send a game medal insertion command consisting of identification information, communication information indicating the number of medals to be inserted, and a checksum to the medal CPU 204a. Also, when the start switch is operated, the main CPU 200a may send a start lever press command consisting of identification information, communication information indicating the number of medals to be inserted, and a checksum to the medal CPU 204a. Also, when the payout is completed, the main CPU 200a may send a payout completion command consisting of identification information, communication information indicating the number of medals to be paid out, and a checksum to the medal CPU 204a. Also, when a game ends, the main CPU 200a may send a game completion command consisting of identification information, communication information related to the payout ratio, and a checksum to the medal CPU 204a. Furthermore, the main CPU 200a may send a startup command to the medal CPU 204a at startup, consisting of identification information, necessary transmission information at startup, transmission information related to the payout ratio, and a checksum. Also, the main CPU 200a may send a state transition command to the medal CPU 204a when the internal state changes, when an error occurs, or when an error is cleared, consisting of identification information and a checksum. The length of the above commands can be set arbitrarily. The main CPU 200a calculates and sends to the medal CPU 204a the transmission information related to the payout ratio (information related to the use of electronic medals (game value) and information related to the acquisition of electronic medals (game value)), namely, the total number of medals inserted, the total number of medals paid out, MY (maximum difference in medals), the total number of medals paid out by special features, the total number of medals paid out by consecutive special features, the special feature ratio, the consecutive special feature ratio, the advantageous section ratio, the special feature ratio including instructions, the special feature state ratio, and the number of games played. The medal CPU 204a extracts a portion of the communication information related to the payout ratio from the commands received from the main CPU 200a and stores it in the RAM of the medal count control board 204. The main CPU 200a may perform calculations of the communication information related to the payout ratio in the used area or in the unused area. The medal CPU 204a may also store the communication information related to the payout ratio in the used area of ​​RAM or in the unused area.Furthermore, the medal CPU 204a may transfer the performance ratio-related transmission information to RAM in the used area or in the unused area.

[0230] Of the above-mentioned commands—the command to insert a game token, the command to press the start lever, the command to finish payout, the command to end one game, the startup command, and the state transition command—the main CPU 200a sends the command to insert a game token, the command to press the start lever, the command to finish payout, the command to end one game, and the startup command within the main loop, while the main CPU 200a sends the state transition command within a timer interrupt (for example, with a period of 1.49 msec) to the medal CPU 204a.

[0231] Furthermore, the medal CPU 204a can determine errors based on commands received from the main CPU 200a. For example, the medal CPU 204a extracts the number of electronic medals inserted and dispensed in the game medal insertion command, the payout end command, and the game end command, and verifies that there is no inconsistency in the relationship with the total number of electronic medals inserted and dispensed. The medal CPU 204a also verifies that the number of electronic medals inserted is not 0 when it receives the start lever press command. The medal CPU 204a may also verify that there is no inconsistency in the prescribed number of electronic medals corresponding to the game state in the game medal insertion command. In addition, the main CPU 200a may control a 1-bit confirmation signal indicating that a payout end command should be sent in I / O other than serial communication, and if the confirmation signal does not indicate that a payout end command should be sent, the medal CPU 204a may discard the received command regardless of whether it is a payout end command or not.

[0232] Now, let's assume that the command sent from the main CPU 200a to the medal CPU 204a is of variable length. In this case, the medal CPU 204a does not know the length of the command when it starts receiving it, so it is unclear how long it should maintain the command reception state and when it should start analyzing the command. When the command is of variable length in this way, the medal CPU 204a can easily understand the command by indicating what kind of command it is and how many bytes long it is in the identification information.

[0233] Furthermore, for example, if there are bits in the identification information that have not been assigned information, those bits can be assigned to "re-play status," which is information required by the medal CPU 204a. In this way, the free area of ​​the transmission data can be effectively utilized, and it is not necessary to create a separate program to generate and transmit the 1-byte command for re-play status.

[0234] Furthermore, the medal CPU 204a sends predetermined commands to the main CPU 200a. For example, when the medal CPU 204a receives the above commands (game token insertion command, start lever press command, payout completion command, startup command) from the main CPU 200a, it may send a reply command to the main CPU 200a consisting of identification information, transmission information indicating the number of tokens that can be inserted and the number of game tokens, and a checksum. The main CPU 200a can determine an error by checking the checksum of the reply command received from the medal CPU 204a. Note that the medal CPU 204a does not send a reply command for the game completion command and the state transition command.

[0235] Here, let's assume that a predetermined bit in the identification information of the reply command is associated with an "ACK" indicating that the command sent from the main CPU 200a has been successfully received by the medal CPU 204a. Such an "ACK" is processed independently of the other bits. For example, if the predetermined bit in the identification information is 1, the main CPU 200a can proceed to the next processing of the game regardless of the contents of the other bits. Also, if any bits other than the predetermined bit are set, the main CPU 200a will continue the game while processing the bits that are set. This configuration makes effective use of the identification information area and improves the efficiency of information transfer.

[0236] Furthermore, this communication between the main CPU 200a and the medal CPU 204a may be performed continuously, or it may be subject to certain restrictions. For example, bidirectional communication between the main CPU 200a and the medal CPU 204a may be initiated when the winning type lottery or AT lottery is completed by operating the start switch 118, and restricted upon the end of a game. In this embodiment, when the start switch 118 is operated, a random number is obtained (latched) from the random number generator 200d and used as a winning type lottery random number for the winning type lottery or for the AT lottery. Here, communication between the main CPU 200a and the medal CPU 204a is not performed until the winning type lottery or AT lottery is completed by operating the start switch 118, and communication is initiated when the winning type lottery or AT lottery is completed by operating the start switch 118. This eliminates the risk that communication between the main CPU 200a and the medal CPU 204a will affect the latch timing of the random number, making it possible to obtain random numbers appropriately.

[0237] Furthermore, as shown in Figures 5(a) and 5(b), when the main CPU 200a and the medal CPU 204a are provided separately, they communicate information via the serial communication commands described above. On the other hand, as shown in Figure 5(c), when the main CPU 200a manages the electronic medals used for gameplay instead of the medal CPU 204a, it stores the information as a common internal variable in the main RAM 200c.

[0238] (Command management) As described above, the main CPU 200a sends multiple types of commands as information to the medal CPU 204a (command to insert game tokens, command to press the start lever, command to finish payout, command to end one game, startup command, and command to transition to a new state). In addition, the medal CPU 204a sends a reply command to the main CPU 200a. If the main CPU 200a successfully receives the reply command and its content indicates "ACK", it can proceed to the next process, considering that communication between the main CPU 200a and the medal CPU 204a has been completed successfully.

[0239] However, communication between the main CPU 200a and the medal CPU 204a does not always complete successfully. For example, the main CPU 200a may successfully send a command, but for some reason, the medal CPU 204a may not be able to receive the command properly. Also, the medal CPU 204a may successfully receive a command from the main CPU 200a and successfully send a reply command in response, but for some reason, the main CPU 200a may not be able to receive the reply command properly. However, in either case, the main CPU 200a cannot determine whether the medal CPU 204a has successfully received the command or not. Therefore, in order to proceed with processing, the main CPU 200a will resend the command it sent immediately before to the medal CPU 204a.

[0240] Here, we illustrate the case where the transmission of the payout completion command does not complete successfully. In the former case, that is, when the main CPU 200a successfully transmits the command but the medal CPU 204a fails to receive the command successfully, the medal CPU 204a has not effectively processed the payout completion command itself. Therefore, even if the main CPU 200a resends the payout completion command, no problem will occur as long as the medal CPU 204a successfully receives the resent payout completion command.

[0241] However, in the latter case, that is, when the medal CPU 204a successfully receives a command from the main CPU 200a and successfully sends a reply command in response to that command, but the main CPU 200a fails to successfully receive the reply command, there is a high probability that the medal CPU 204a has successfully processed the payout end command. For example, suppose the medal CPU 204a successfully receives the payout end command and adds the number of payouts included in the payout end command to the number of game medals. The medal CPU 204a sends a reply command successfully, but it cannot determine whether the main CPU 200a successfully received the reply command or not. If the main CPU 200a fails to successfully receive the reply command and resends the payout end command, and the medal CPU 204a successfully receives that payout end command, there is a risk that it will further add the number of payouts included in the payout end command to the number of game medals. In this case, for each instance of electronic medal payout, the number of medals dispensed will be added to the total number of medals played multiple times, resulting in the player unfairly gaining a profit from the game. Furthermore, if the harness between the main control board 200 and the medal count control board 204 is manipulated to fraudulently send the payout end command multiple times, the same phenomenon of the number of medals dispensed being added to the total number of medals played multiple times may occur.

[0242] Therefore, in this embodiment, commands sent from the main CPU 200a to the medal CPU 204a are appropriately valid only once. Specifically, if the medal CPU 204a receives the same type of command consecutively from the main CPU 200a (external), it invalidates the second and subsequent instances of the same type of command received and does not process those commands. Here, the commands refer to the aforementioned game medal insertion command, start lever press command, payout end command, 1 game end command, startup command, and state transition command. For example, if a payout end command is received after a payout end command without receiving any other commands, it is considered that the same type of command has been received consecutively. Note that if the same type of command is received two or more times consecutively from the main CPU 200a, it is not necessarily the case that subsequent instances of the same type of command will be invalidated. For example, if a predetermined command of the same type is received two or more times consecutively under predetermined circumstances that allow for consecutive command reception, such as when the 1-bet switch is operated two or more times consecutively, the medal CPU 204a may also process subsequent instances of the same type of command validly.

[0243] Furthermore, when the medal CPU 204a receives a predetermined command from the main CPU 200a, it may invalidate predetermined commands received after the first predetermined command received until it receives a specific command different from the predetermined command. For example, once the medal CPU 204a receives a payout end command from the main CPU 200a, it invalidates subsequent payout end commands until it receives a specific command, such as a start lever press command. In this case, predetermined commands received after the first predetermined command become valid only when the specific command is received, and even if commands or information other than the specific command are received between the first and second predetermined commands, the subsequently received payout end commands will be invalidated. For example, once the medal CPU 204a receives a payout end command as a predetermined command from the main CPU 200a, it invalidates subsequent payout end commands even if it receives other game token insertion commands, game end commands, startup commands, or state transition commands until it receives a start lever press command as a specific command.

[0244] In this explanation, we will describe an example where the medal CPU 204a, upon receiving a predetermined command from the main CPU 200a, effectively processes a predetermined command received after the first predetermined command received, provided that a specific command is received. However, the medal CPU 204a may also effectively process a predetermined command received after the first predetermined command, provided that it receives any command other than a predetermined command or any other information.

[0245] Figs. 28 to 30 are flowcharts showing the flow of command reception processing in medal CPU 204a. Here, the processing related to the present embodiment will be described, and the processing not related to the present embodiment, such as the generation processing of specific commands, etc., will be omitted. The numerical values of step S in such figures are used only in the description of this figure. Also, here, a 1-byte buffer (input request buffer, IN signal confirmation buffer, payout confirmation buffer, main reception command error buffer) is used as a flag, and the two values of "0h" and "FFh" are switched. Here, the reason for using a byte value instead of a bit value as a flag is that in the case of a bit value, after reading the byte value, a process of further determining the bit itself must be executed, and the total command size for determination becomes longer. Note that each of the above buffers used as a flag is backed up and is not initialized even when the power is turned off.

[0246] As shown in Fig. 28, when medal CPU 204a normally receives a command from main CPU 200a, it determines whether the received command (received command) is a startup command (S1). As a result, if the received command is a startup command (YES in S1), medal CPU 204a performs a game machine installation information reception process for receiving game machine installation information (S2), performs a manufacturer code confirmation process for confirming the main control chip manufacturer code (S3), and ends the command reception process. Also, if the received command is not a startup command (NO in S1), medal CPU 204a determines whether the received command is a payout end command (S4). As a result, if the received command is a payout end command (YES in S4), medal CPU 204a executes a payout number setting process (S5) and ends the command reception process. Such payout number setting process will be described in detail later.

[0247] Also, if the received command is not the payout end command (NO in S4), the medal CPU 204a determines whether the received command is a game end command for one game (S6). As a result, if the received command is a game end command for one game (YES in S6), the medal CPU 204a performs a game machine performance information setting process for setting game machine performance information (S7), and ends the command reception process. Also, if the received command is not a game end command for one game (NO in S6), the medal CPU 204a determines whether the received command is a state transition command (S8). As a result, if the received command is a state transition command (YES in S8), the medal CPU 204a executes a main control state reception process for receiving the main control state (S9), and ends the command reception process.

[0248] Also, if the received command is not a state transition command (NO in S8), the medal CPU 204a executes an input request number update process for updating the input request number of the electronic medals (S10), and determines whether the received command is a start lever press command (S11). As a result, if the received command is a start lever press command (YES in S11), the medal CPU 204a executes a game start process (S12), and ends the command reception process. Such a game start process will be described in detail later. Also, if the received command is not a start lever press command (NO in S11), the medal CPU 204a ends the command reception process.

[0249] In the flowchart shown in Figure 28, processing is performed exclusively and independently depending on which of the multiple types of commands is received. For example, if the received command is a payout end command, the payout quantity setting process (S5) is performed, but the game start process (S12) is not performed. Similarly, if the received command is a start lever press command, the game start process (S12) is performed, but the payout quantity setting process (S5) is not performed. In this embodiment, the payout quantity setting process (S5), which is executed in response to the receipt of a payout end command, and the game start process (S12), which is executed in response to the receipt of a start lever press command, are managed independently, and the commands received by the medal CPU 204a are appropriately managed by switching the payout confirmation buffer and the IN signal confirmation buffer.

[0250] In the payout quantity setting process (S5) shown in Figure 29, the medal CPU 204a sets the input request buffer to 0h (S5-1) and the IN signal confirmation buffer to 0h (S5-2). Here, by setting the IN signal confirmation buffer to 0h, the invalidation of the start lever press command received in the game start process (S12) described later is released. Next, the medal CPU 204a determines whether the payout confirmation buffer is 0h or not (S5-3). As a result, if the payout confirmation buffer is not 0h (NO in S5-3), it means that the payout end command has not been received for the first time, so the medal CPU 204a terminates the payout quantity setting process. On the other hand, if the payout confirmation buffer is 0h (YES in S5-3), it means that the payout end command has been received for the first time, so the medal CPU 204a sets the payout confirmation buffer to FFh (S5-4) and invalidates the second and subsequent payout end commands. Next, the medal CPU 204a determines whether the number of medals to be dispensed is 16 or more (S5-5). If the result is 16 or more (YES in S5-5), it sets FFh in the main received command error buffer (S5-6) and terminates the dispensed medal count setting process.

[0251] On the other hand, if the number of tokens dispensed is 15 or less (NO in S5-5), the token CPU 204a determines whether or not replay is activated (S5-7). If replay is not activated (NO in S5-7), the token CPU 204a determines whether or not the number of tokens dispensed is 0 (S5-8). If the number of tokens dispensed is 0 (YES in S5-8), the token CPU 204a terminates the token dispensed setting process. On the other hand, if the number of tokens dispensed is not 0 (NO in S5-8), the token CPU 204a adds the number of tokens dispensed to the number of tokens in play to update the number of tokens in play (S5-9), and sets the number of tokens dispensed to the number of tokens dispensed (S5-10). In this way, the number of tokens in play is updated appropriately. When the number of payouts is set to the number of medals to be paid out (S5-10), or if replay is activated (YES in S5-7), the medal CPU 204a performs a game information setting process to set game information (S5-11), and then terminates the payout number setting process.

[0252] In the game start process (S12) shown in Figure 30, the medal CPU 204a determines whether the IN signal confirmation buffer is 0h or not (S12-1). If the result is not 0h (NO in S12-1), it means that the start lever press command has not been received for the first time, so the medal CPU 204a terminates the game start process. On the other hand, if the IN signal confirmation buffer is 0h (YES in S12-1), it means that the start lever press command has been received for the first time, so the medal CPU 204a sets the IN signal confirmation buffer to FFh (S12-2), invalidates the start lever press command from the second time onward, performs the game information setting process to set game information (S12-3), sets the payout confirmation buffer to 0h (S12-4), and terminates the game start process. Here, by setting the payout confirmation buffer to 0h, the invalidation of the payout end command received in the payout amount setting process (S5) is released. In the above, step S12-4 is executed if the result in S12-1 is YES, but it may also be executed in a step prior to step S12-1.

[0253] Here, if the medal CPU 204a receives consecutive payout completion commands of the same type from the main CPU 200a, it invalidates the payout completion commands received from the second time onward. Specifically, in step S5-3 in Figure 29, if the payout confirmation buffer is 0h, the medal CPU 204a determines that it has received the first payout completion command, switches the payout confirmation buffer to FFh, and normally executes the processing from step S5-6 onward for the number of payouts. Subsequently, even if a payout completion command is received again, it is determined in step S5-3 that the payout confirmation buffer is not 0h (it is FFh), so the processing from step S5-6 onward for the number of payouts is not performed (the payout completion command is invalidated).

[0254] Furthermore, when the medal CPU 204a receives a start lever press command from the main CPU 200a while the received payout end command is invalidated, it undoes the invalidation of the payout end command. Specifically, in step S5-3 of Figure 29, if the payout confirmation buffer is 0h, the medal CPU 204a switches the payout confirmation buffer to FFh, invalidating any payout end commands received thereafter. However, if a start lever press command is received thereafter, the payout confirmation buffer is reset to 0h in step S12-4 of Figure 30. Therefore, when the next payout end command is received, the payout confirmation buffer is determined to be 0h in step S5-3 of Figure 29, meaning that the payout end command is the first to be received, and the processing from step S5-4 onwards for the number of medals to be paid out is executed normally.

[0255] Furthermore, if the medal CPU 204a receives consecutive start lever press commands of the same type from the main CPU 200a, it invalidates the start lever press commands received from the second time onward. Specifically, in step S12-1 in Figure 30, if the IN signal confirmation buffer is 0h, the medal CPU 204a determines that it has received the first start lever press command, switches the IN signal confirmation buffer to FFh, and successfully executes the game information setting process in step S12-3. Subsequently, even if a start lever press command is received again, it is determined in step S12-1 that the IN signal confirmation buffer is not 0h (it is FFh), so the game information setting process in step S12-3 is not performed (the start lever press command is invalidated).

[0256] Furthermore, when the medal CPU 204a has disabled the start lever press command it received in this manner, if it subsequently receives a payout completion command from the main CPU 200a, it will release the disablement of the start lever press command. Specifically, in step S12-1 of Figure 30, if the IN signal confirmation buffer is 0h, the medal CPU 204a switches the IN signal confirmation buffer to FFh, and disables the start lever press command received thereafter. However, when it receives a payout completion command, the IN signal confirmation buffer is reset to 0h in step S5-2 of Figure 29. Therefore, when the start lever press command is received next, the IN signal confirmation buffer is determined to be 0h in step S12-1 of Figure 30, meaning that the start lever press command is determined to be the first reception, and the game information setting process in step S12-3 is executed normally.

[0257] In this way, when a command is received multiple times in a row, the system is configured to invalidate the same type of command received from the second time onward. This prevents the execution of a process that should only be performed once in response to that command from being performed multiple times, ensuring that the game proceeds appropriately. Furthermore, even if an unauthorized circuit board is installed between the main control board 200 and the medal count control board 204, and this unauthorized circuit board sends commands fraudulently multiple times, those commands will be invalidated, preventing the unfair acquisition of game profits.

[0258] Here, if the payout end command is received multiple times in a row, the payout confirmation buffer is switched to invalidate the second and subsequent receptions. Similarly, if the start lever press command is received multiple times in a row, the IN signal confirmation buffer is switched to invalidate the second and subsequent receptions. Since the payout end command and the start lever press command are processed mutually exclusively, one buffer is normally sufficient. However, if two values ​​in one buffer are assigned to allow the payout end command and allow the start lever press command, then when one buffer allows either the payout end command or the start lever press command and not the other, if a backup error occurs in the medal CPU 204a or a setting change occurs in the main control board 200, the other command that should be allowed may not be allowed, potentially preventing the game from progressing. Therefore, buffers (payout confirmation buffer and IN signal confirmation buffer) are provided for both the payout completion command and the start lever press command. If predetermined initialization conditions such as a backup error or setting change are met, both buffers are set to 0h, thereby transitioning to a state where either command is acceptable. With this configuration, even if a backup error occurs in the medal CPU 204a or a setting change occurs in the main control board 200, the game can proceed appropriately.

[0259] Furthermore, this embodiment can also be implemented with a single buffer, for example, by providing a separate state in the command confirmation buffer that allows both the payout end command and the start lever press command. For example, the state that allows both the payout end command and the start lever press command can be set to 0h, the state that allows only the payout end command and not the start lever press command can be set to 1h, and the state that allows only the start lever press command and not the payout end command can be set to 2h. When the medal CPU 204a receives a payout end command, it switches the command confirmation buffer to 2h in order to invalidate the second and subsequent receptions if the payout end command is received multiple times in a row. Similarly, when it receives a start lever press command, it switches the command confirmation buffer to 1h in order to invalidate the second and subsequent receptions if the start lever press command is received multiple times in a row. When predetermined initialization conditions such as a backup error or setting change are met, the command confirmation buffer is set to 0h, transitioning to a state that allows both commands.

[0260] In this explanation, we have used commands as an example of information transmitted and received between the main CPU 200a and the medal CPU 204a, but the information can include various other contents such as data and signals.

[0261] (Monitoring for command infringement) Of the various types of commands (game token insertion command, start lever press command, payout completion command, game completion command, startup command, state transition command) sent from the main CPU 200a to the medal CPU 204a, some commands have a predetermined transmission order (the order in which the medal CPU 204a should receive them).

[0262] For example, the commands for inserting game tokens, pressing the start lever, ending payouts, and ending a game are sent sequentially according to the player's actions during a game. Specifically, when the player operates the bet switch 116 at the start of a game, the main CPU 200a sends the game token insertion command to the token CPU 204a. Next, when the player operates the start switch 118, the main CPU 200a sends the start lever press command to the token CPU 204a. Subsequently, the rotation-controlled reels 110a, 110b, and 110c stop according to the player's operation of the stop switches 120a, 120b, and 120c, and once a winning combination is determined, the main CPU 200a sends the payout end command to the token CPU 204a. Finally, when the payout ratio-related data is updated, the main CPU 200a sends the game ending command to the token CPU 204a. In this way, one game is completed.

[0263] However, betting can occur either by inserting an electronic medal held in the medal holder via the operation of the bet switch 116, or by automatically inserting an electronic medal based on the display of a replay symbol on an active line. If an electronic medal is automatically inserted based on the display of a replay symbol on an active line, the main CPU 200a does not send a game medal insertion command to the medal CPU 204a. In that case, of the game medal insertion command, start lever press command, payout end command, and game end command, the game medal insertion command is not necessarily sent by the main CPU 200a during a single game. Therefore, the commands whose transmission order by the main CPU 200a is fixed are the start lever press command, payout end command, and game end command. Note that the payout end command is sent even if the number of medals paid out is 0.

[0264] Here, as part of the command fraud monitoring, three commands are targeted: the start lever press command, the payout end command, and the game end command. The system determines whether the order in which the commands are received is a predetermined order. Specifically, when the medal CPU 204a receives any of the three commands (a limited number of commands), it determines whether the received command is one that should have been received. If it is different from the command that should have been received, it increments the error counter by 1. In this way, the medal CPU 204a counts the error counter when there is a risk of fraud, and when it reaches a predetermined value (for example, 10), it considers it a communication error and notifies the system of the communication error using a device such as the speaker 128. However, during a predetermined period after power-on, communication errors are likely to occur during the initialization process, so updating the error counter is prohibited to avoid unintended error notifications.

[0265] Here, we explained an example where the error counter is incremented by 1 when the order in which commands are received differs from the intended order. However, the error counter is not limited to these cases. For example, in addition to when the order in which commands are received differs from the intended order, the error counter is incremented by 1 when: the number of tokens inserted is inconsistent; the number of tokens paid out is inconsistent; a command indicating that reel 110 is spinning is received when no bet has been executed; a command to insert game tokens is received after a command to press the start lever; a command to press the start lever is received again after a command to press the start lever; or the checksum in the command is abnormal. Here, the number of tokens inserted is the total number of tokens inserted included in the communication information related to the payout ratio of the 1 game end command. The total number of tokens inserted received in the previous game is kept, and consistency is considered if the result of adding the current number of tokens inserted to the previous total number of tokens inserted is equal to the current total number of tokens inserted; otherwise, consistency is considered to exist. Similarly, the number of payouts uses the total number of payouts included in the payout ratio-related transmission information of the game end command. The total number of payouts received in the previous game is kept, and consistency is confirmed if the sum of the previous total payout and the current payout is equal; otherwise, consistency is not confirmed. In addition, if a game token insertion command is received after a start lever press command is received, and if a start lever press command is received again after a start lever press command is received, information to that effect is kept, for example by setting a flag, and when a payout end command is received, the information that a start lever press command was received is cleared.If the order in which commands are received differs from the intended order, if there is inconsistency in the number of tokens inserted, if there is inconsistency in the number of tokens dispensed, if a command indicating that reel 110 is spinning when no bet has been executed is received, if a command to insert game tokens is received after a start lever press command is received, or if a start lever press command is received again after a start lever press command is received, the error counter will be incremented, but the received command will be considered valid and the corresponding processing will be performed. On the other hand, if the checksum in the command is abnormal, the error counter will be incremented and the received command will be invalidated and discarded. Furthermore, if the error counter reaches a predetermined value and a communication error occurs, and that communication error is reported, the power must be turned back on and the error counter cleared in order to resolve the communication error. In addition, the cases in which the error counter is incremented may be expanded to include cases where the number of tokens inserted is outside a predetermined range (e.g., 1 to 3) and cases where the number of tokens dispensed is outside a predetermined range (e.g., 0 to 15). Furthermore, although examples were given here to increment the error counter when a game token insertion command is received after a start lever press command is received, and when a start lever press command is received again after a start lever press command is received, the medal CPU 204a may not perform any processing for the game token insertion command if a game token insertion command is received after a start lever press command is received, and the medal CPU 204a may not perform any processing for the second start lever press command if a start lever press command is received again after a start lever press command is received.

[0266] Figures 31 to 33 are flowcharts showing the flow of the command monitoring process. The command monitoring process is executed when the medal CPU 204a receives a command from the main CPU 200a. Figure 31 shows the case when a start lever press command is received, Figure 32 shows the case when a payout end command is received, and Figure 33 shows the case when a game end command is received. This section describes the processes related to this embodiment, and processes unrelated to this embodiment are omitted. The numerical value of step S in these figures will only be used in the explanation of each figure.

[0267] As shown in Figure 31, when the medal CPU 204a receives a command from the main CPU 200a, it determines whether the received command is a start lever press command (S1). If the received command is not a start lever press command (NO in S1), the medal CPU 204a terminates the command monitoring process for that start lever press command. If it is a start lever press command (YES in S1), the medal CPU 204a determines whether the identifier held in the next command (variable) is an identifier indicating a start lever press command (S2). Here, the next command is a variable (memory area) that holds the identifier of the next command to be received for the three commands: start lever press command, payout end command, and game end command. As a result, if the identifier held in the next command is not the identifier indicating the start lever press command, that is, if it is the identifier indicating the payout end command or the 1st game end command (NO in S2), the medal CPU 204a increments the error counter by 1, indicating that the order in which the commands were received is different from the original order (S3). If the identifier held in the next command is the identifier indicating the start lever press command (YES in S2), the medal CPU 204a does not increment the error counter. Then, the medal CPU 204a sets the identifier indicating the payout end command as the next command to be received after the start lever press command (S4). Here, regardless of whether the received start lever press command is the command that should be received, the payout end command is set as the command to be received after the start lever press command.

[0268] Thus, here, when receiving the start lever press command, it is determined whether the identifier held in the next command is the identifier indicating the start lever press command. Also, as will be described later, the identifier indicating the start lever press command is set in the next command when receiving the one-game end command. In other words, the medal CPU 204a determines whether the previously received command among the three commands of the restricted start lever press command, payout end command, and one-game end command is the one-game end command when receiving the start lever press command.

[0269] As shown in FIG. 32, when receiving a command from the main CPU 200a, the medal CPU 204a determines whether the received command is the payout end command (S1). As a result, if the received command is not the payout end command (NO in S1), the medal CPU 204a ends the command monitoring process regarding the payout end command. If it is the payout end command (YES in S1), the medal CPU 204a determines whether the identifier held in the next command is the identifier indicating the payout end command (S2). As a result, if the identifier held in the next command is not the identifier indicating the payout end command, that is, if it is the identifier indicating the one-game end command or the identifier indicating the start lever press command (NO in S2), the medal CPU 204a increments the error counter by 1 assuming that the reception order of the commands is different from the original reception order (S3). If the identifier held in the next command is the identifier indicating the payout end command (YES in S2), the medal CPU 204a does not increment the error counter. Then, the medal CPU 204a sets the identifier indicating the one-game end command as the command to be received next after the payout end command in the next command (S4). Here, regardless of whether the received payout end command is the command that should have been received originally, the one-game end command is set as the command to be received next after the payout end command.

[0270] As shown in Figure 33, when the medal CPU 204a receives a command from the main CPU 200a, it determines whether the received command is a game end command (S1). If the received command is not a game end command (NO in S1), the medal CPU 204a terminates the command monitoring process for that game end command. If it is a game end command (YES in S1), the medal CPU 204a determines whether the identifier held in the next command is an identifier indicating a game end command (S2). If the identifier held in the next command is not an identifier indicating a game end command, that is, an identifier indicating a start lever press command or an identifier indicating a payout end command (NO in S2), the medal CPU 204a increments the error counter by 1, indicating that the order in which the commands were received is different from the original order (S3). If the identifier held in the next command is an identifier indicating the "End Game" command (YES in S2), the medal CPU 204a does not increment the error counter. Then, the medal CPU 204a sets the identifier indicating the "Press Start Lever" command as the next command to be received after the "End Game" command (S4). Here, regardless of whether the received "End Game" command is the command that should be received, the "Press Start Lever" command is set as the command to be received after the "End Game" command.

[0271] Thus, when the medal CPU 204a receives a predetermined command from among the start lever press command, payout end command, and game end command, it determines whether the identifier held in the next command is equal to the identifier that indicates the received command. In other words, when the medal CPU 204a receives a predetermined command from among the start lever press command, payout end command, and game end command, it determines whether the previously received command was the game end command, the start lever press command, or the payout end command, respectively.

[0272] As described above, if an electronic medal is automatically inserted at the start of a game based on a replay symbol appearing on an active payline, the main CPU 200a does not send a game medal insertion command to the medal CPU 204a. In this case, the order of command reception is "payout end command" → "game end command" → "start lever press command", and the order of command reception is maintained. However, if the player operates the bet switch 116 at the start of a game, the medal CPU 204a will receive the "game medal insertion command" between the "game end command" and the "start lever press command", and there is a risk that it will determine that the order of command reception is different.

[0273] Here, as explained using Figures 31 to 33, the targets for monitoring the order of reception are limited to three commands: the start lever press command, the payout end command, and the game end command. For example, suppose that when a player operates the bet switch 116 at the start of a game, the medal CPU 204a receives commands in the order of "game end command" → "game token insertion command" → "start lever press command". In this case, upon receiving the game end command, the medal CPU 204a sets an identifier indicating the start lever press command as the next command to be received, as shown in Figure 33. Next, the medal CPU 204a receives the game token insertion command, but since the received game token insertion command is not one of the three commands (start lever press command, payout end command, or game end command), it does not determine or update the next command. Next, upon receiving the start lever press command, the medal CPU 204a determines, as shown in Figure 31, whether the identifier held in the next command is the identifier indicating the start lever press command. Since the next command holds the identifier indicating the start lever press command, the error counter is not updated. Therefore, even if the medal CPU 204a receives a "game token insertion command" between the "game end command" and the "start lever press command," no problem arises.

[0274] Furthermore, as mentioned above, within the main loop, the main CPU 200a sends the command to insert a game token, the command to press the start lever, the command to finish payout, the command to end one game, and the startup command to the token CPU 204a, and within the timer interrupt, it sends the command to change states to the token CPU 204a. In this case, between the three commands mentioned above—the command to press the start lever, the command to finish payout, and the command to end one game—the token CPU 204a receives the command to change states at the timing of the timer interrupt, which may lead it to mistakenly determine that the order in which the commands were received is incorrect.

[0275] Even in such cases, the command monitoring process only targets three commands: the start lever press command, the payout end command, and the game end command. Therefore, even if a state transition command is received between the start lever press command, the payout end command, and the game end command, the main CPU 200a will not execute the command monitoring process itself. Thus, the medal CPU 204a excludes commands other than the start lever press command, the payout end command, and the game end command from its command monitoring process, and only determines the order in which these three commands are received. Consequently, even if the medal CPU 204a receives a state transition command at the timing of a timer interrupt between the start lever press command, the payout end command, and the game end command, the error counter will not be updated.

[0276] This command monitoring process makes it possible to appropriately identify errors even if commands are tampered with through fraudulent means, such as inserting an unauthorized circuit board between the main control board 200 and the medal count control board 204.

[0277] Here, we have provided an example in which the medal CPU 204a receives a start lever press command, a payout end command, and a game end command as second commands, and determines whether the identifier held in the next command is an identifier indicating the start lever press command, a payout end command, or a game end command, respectively; that is, whether the previously received command was the game end command, the start lever press command, or the payout end command as the first command. However, the commands to be judged are not limited to this case; it is sufficient to have at least two commands with a predetermined reception order, and the medal CPU 204a only needs to determine whether the first and second commands were received in a predetermined reception order. In this case, when the medal CPU 204a receives a second command, it may determine that the received command is the first command among a limited number of commands.

[0278] In addition to the command monitoring process described above, the medal CPU 204a manages timeouts to confirm whether command transmission from the main CPU 200a to the medal CPU 204a is being performed stably. Specifically, the main CPU 200a sends a transmission confirmation command at the timing of a timer interrupt (for example, every 1.49 msec). The transmission confirmation command is a fixed 1-byte value "AAh" consisting of alternating 1s and 0s bits, without an identifier or checksum. The medal CPU 204a confirms that command transmission is being performed stably by periodically receiving such transmission confirmation commands. If it fails to receive the transmission confirmation command that it should receive within a predetermined timeout (for example, 100 msec), it clears the information in the medal RAM 204c used when receiving commands such as the game token insertion command, start lever press command, payout end command, and game end command, such as pointers. Here, since the transmission and reception frequency of the transmission confirmation command is high, we have only cleared the information in medal RAM204c to account for the effects of noise, etc. However, if the transmission confirmation command that should have been received is not received within a predetermined timeout period, the error counter may be incremented by 1.

[0279] However, for some commands, the time it takes to complete sending command 1 may be longer than the timer interrupt period (e.g., 1.49 msec). For example, the game end command and the startup command take more than 4 msec to complete sending command 1. In this case, there is a risk of a conflict between the game end command or startup command and the transmission confirmation command.

[0280] Here, as will be explained later, the main CPU 200a temporarily holds each command in the transmit FIFO 380 for serial transmission. The transmit FIFO 380 only transmits data at transmit-enabled timings (for example, every 80 μsec), but the main CPU 200a can set each command in the transmit FIFO 380 at once. In addition, the main CPU 200a disables timer interrupts while setting the 1-game end command and the startup command in the transmit FIFO 380. With this configuration, the timing at which the main CPU 200a sets the 1-game end command and the startup command in the transmit FIFO 380 does not overlap with the timing at which the transmission confirmation command is set in the transmit FIFO 380. Therefore, the 1-game end command and the startup command do not conflict with the transmission confirmation command.

[0281] However, if a transmission confirmation command is set after a game end command or startup command has been set, the transmission confirmation command will be output from the transmission FIFO 380 after the game end command or startup command. In that case, depending on the setting timing of the transmission FIFO 380, the transmission confirmation command may overlap with the game end command or startup command within the transmission FIFO 380, resulting in two or more transmission confirmation commands being output consecutively. In this case, the medal CPU 204a will receive the transmission confirmation commands consecutively. However, even in this case, the interval between receiving the transmission confirmation commands will average to the timer interrupt period, so the error counter will not be updated.

[0282] By managing timeouts using such transmission confirmation commands, it becomes possible to appropriately identify errors even if commands are tampered with through fraudulent means, such as inserting an unauthorized board between the main control board 200 and the medal count control board 204 or inputting an unauthorized command by some means.

[0283] In this example, the medal CPU 204a manages the timeout using a transmission confirmation command. However, it is not limited to this case; both the main CPU 200a and the medal CPU 204a may periodically output transmission confirmation commands, and the main CPU 200a may also manage the timeout using transmission confirmation commands (mutual management).

[0284] Furthermore, the means for confirming whether command transmission from the main CPU 200a to the medal CPU 204a is being performed stably is not limited to managing timeouts using transmission confirmation commands. For example, a command permission signal may be provided as a connection confirmation signal, and when either the main CPU 200a or the medal CPU 204a prohibits command transmission by turning OFF the command permission signal, and the other transmits a command, the information in the medal RAM 204c used when receiving each command, such as pointers, may be cleared. Alternatively, when either the main CPU 200a or the medal CPU 204a prohibits command transmission by turning OFF the command permission signal, and the other transmits a command, the error counter may be updated, similar to the transmission confirmation command.

[0285] Furthermore, this explanation uses an example of sending a command from the main CPU 200a, which acts as the first control unit, to the medal CPU 204a, which acts as the second control unit, in the Smart Pachislo 100. However, this is not limited to such cases; it can be applied to serial communication between various independent CPUs, such as when sending and receiving commands between other boards within the Smart Pachislo 100, acting as the first and second control units.

[0286] Furthermore, in this explanation, assuming that the main CPU 200a does not send a game token insertion command to the medal CPU 204a when an electronic token is automatically inserted based on the display of a replay symbol on an active line, we have listed and explained three commands whose transmission order is fixed by the main CPU 200a: the start lever press command, the payout end command, and the 1st game end command. However, even if an electronic token is automatically inserted based on the display of a replay symbol on an active line, the main CPU 200a may still send a game token insertion command to the medal CPU 204a. In that case, the commands whose transmission order is fixed by the main CPU 200a would be four commands: the game token insertion command, the start lever press command, the payout end command, and the 1st game end command. In this case, when the main CPU 200a receives any of the four commands—a command to insert a game token, a command to press the start lever, a command to finish paying out, or a command to end one game—it determines whether the received command is one that it should have received. If it is different from the command it should have received, it increments the error counter by 1.

[0287] Furthermore, here, assuming that the payout end command is sent even when the number of payouts is 0, we have listed and explained three commands—the start lever press command, the payout end command, and the 1st game end command—as commands whose transmission order is fixed by the main CPU 200a. However, not limited to this case, the main CPU 200a may choose not to send the payout end command to the medal CPU 204a when the number of payouts is 0. In that case, the commands whose transmission order is fixed by the main CPU 200a would be the start lever press command and the 1st game end command. In this case, when the main CPU 200a receives either the start lever press command or the 1st game end command, it will determine whether the received command is one that it should have received, and if it is different from one that it should have received, it will increment the error counter by 1. Furthermore, the main CPU 200a can also choose not to send a payout end command to the medal CPU 204a when the number of payouts is 0, and can send a game token insertion command to the medal CPU 204a when an electronic token is automatically inserted based on a replay symbol appearing on an active line. In this case, the commands that the main CPU 200a sends in a fixed order are the game token insertion command, the start lever press command, and the 1st game end command. When the main CPU 200a receives any of these three commands, it determines whether the received command is the one it should have received, and if it is different from the command it should have received, it increments the error counter by 1.

[0288] (Connection confirmation using VL connection signal) As described above, when checking the connection between the Smart Pachislo 100 and the dedicated unit 350, if the VL connection signal is ON, the Smart Pachislo 100 will proceed with the game and accept counting processing as long as the game is playable. On the other hand, if the VL connection signal is OFF, the Smart Pachislo 100 will execute a game stop process and restrict (prohibit) all processes for proceeding with the game based on betting electronic tokens, operating the settlement switch 121, operating the start switch 118, and the counting processing described above. This is because if the VL connection signal is OFF, it can be determined that the Smart Pachislo 100 is not properly connected to the dedicated unit 350, or that the power to the dedicated unit 350 is OFF.

[0289] However, even if the VL connection signal is ON, that is, even if the smart pachislo 100 and the dedicated unit 350 are properly connected and the power of the dedicated unit 350 is recognized as ON, there are cases where it is better not to immediately execute the counting process. For example, when the VL connection signal is ON, communication between the main control board 200 and the medal count control board 204 has not been established, or when it was established but then the communication connection was disconnected. In this case as well, the counting process cannot be executed normally, so even if the smart pachislo 100 accepts the operation of the counting switch 112 and transmits information to the dedicated unit 350, there is a risk that the counted medals will be lost. Therefore, in this modified embodiment, not only the VL connection signal but also the establishment status of communication between the main control board 200 and the medal count control board 204 is determined, and a decision is made as to whether or not to execute the game stop process. If communication is not established, the game stop process is performed to restrict the progress of the game. In this explanation, we have described the case where the game stop process is performed in both cases: when the VL connection signal is ON and communication between the main control board 200 and the medal count control board 204 has not been established, and when communication has been established but subsequently disconnected. However, the game stop process is not limited to these cases. In any case where the VL connection signal is ON and communication between the main control board 200 and the medal count control board 204 has not been established, the game stop process is performed. However, if communication has been established but subsequently disconnected, the game stop process may only restrict the processing for game progression based on betting electronic medals, operating the settlement switch 121, and operating the start switch 118, while maintaining the ability to perform the counting process.

[0290] Figure 34 is a flowchart showing the communication specifications when the power is turned on. The numerical value of step S in this figure will be used only in the explanation of this figure. For example, when the smart pachislo 100 is powered on, the main CPU 200a of the main control board 200 sends and receives predetermined commands (startup command, reply command) to and from the medal CPU 204a of the medal count control board 204 and determines the status of communication establishment.

[0291] First, the main CPU 200a sets its own registers (S1), checks the backup from the previous power outage (S2), and then enters a signal waiting state. In this waiting state, the main CPU 200a checks that the power outage warning signal, which indicates that a power outage will occur after a predetermined time, is OFF, and that the command permission signal received from the medal count control board 204 is ON (S3). If the power outage warning signal is ON, or the command permission signal is OFF (NO in S3), the waiting state is maintained.

[0292] In parallel with this, the medal CPU 204a sets its own registers (S4), checks the backup from the previous power outage (S5), performs the initial startup processing (S6), and enters a state of waiting for startup commands. In this state of waiting for startup commands, the medal CPU 204a checks whether it has received a startup command (S7), and if it has received one (YES in S7), it checks whether the startup command is normal (S8). If it has not received a startup command (NO in S7) or if the startup command is abnormal (NO in S8), it maintains the state of waiting for startup commands. Note that startup commands and reply commands consist of serial signals: a start bit, 1 byte (8 bits) of information indicating the type of command, a stop bit, and a parity bit. Therefore, the medal CPU 204a determines that a startup command is normal if the type of command indicates a startup command and the parity bit is normal.

[0293] If the power outage warning signal is OFF and the command permission signal is ON (YES in S3), the main CPU 200a sends a startup command to the medal CPU 204a (S9). Then, the main CPU 200a sets a communication timer (S10) and enters a state of waiting for a reply command. In this state of waiting for a reply command, the main CPU 200a checks whether a reply command has been received (S11). If it has been received (YES in S11), it checks whether the reply command is normal (S12). If a reply command has not been received (NO in S11) or if the reply command is abnormal (NO in S12), it maintains the state of waiting for a reply command. The main CPU 200a determines that a reply command is normal if the command type indicates a reply command and the parity bits are normal.

[0294] When the main CPU 200a sends a startup command (S9), the medal CPU 204a receives the startup command (YES in S7). If the medal CPU 204a determines that the startup command is normal (YES in S8), it enters a signal waiting state. In this waiting state, the medal CPU 204a checks that the command permission signal received from the main control board 200 is ON (S13). If the command permission signal is OFF (NO in S13), it maintains the waiting state. On the other hand, if the command permission signal is ON (YES in S13), the medal CPU 204a sends a reply command to the main CPU 200a (S14), starts communication with the dedicated unit 350, and enters a counting-ready state.

[0295] When medal CPU 204a sends a reply command (S14), main CPU 200a receives the reply command (YES in S11). If main CPU 200a determines that the reply command is valid (YES in S12), it proceeds to the configuration change process or the power-off recovery process. Here, we have explained an example where main CPU 200a receives a reply command and determines that it is valid before proceeding to the configuration change process or power-off recovery process. However, even if this is not the case, main CPU 200a may proceed to the configuration change process or power-off recovery process without waiting for a reply command after sending the startup command (S9), and after the configuration change process or power-off recovery process is completed, it may check the status of the reply command reception, and if the reply command has not been received, or if the reply command has been received but is not valid, it may proceed to the error state.

[0296] Furthermore, while waiting for a reply command, the communication timer set in step S10 is set, and after a predetermined time has elapsed, it times out and transitions to an error state, displaying the contents on the game token count display device 114 and terminating the communication process. This communication process is set not to resume unless the power is turned back on. Through such a timeout, the main CPU 200a determines that communication between the main CPU 200a and the token CPU 204a has not been established, or that it was established but the communication connection was subsequently disconnected, and performs a game stop process to restrict the progress of the game.

[0297] Figure 35 is a flowchart showing the communication specifications during operation. The numerical value of step S in this figure will be used only in the explanation of this figure. For example, when the bet switch 116, settlement switch 121, start switch 118, etc. are operated, the main CPU 200a of the main control board 200 sends and receives commands (start lever press command, reply command) to and from the medal CPU 204a of the medal count control board 204 and determines the status of communication establishment.

[0298] For example, when the start switch 118 is operated, the main CPU 200a enters a signal waiting state. In this waiting state, the main CPU 200a checks that the power outage warning signal is OFF and the command permission signal is ON (S1). If the power outage warning signal is ON or the command permission signal is OFF (NO in S1), the CPU maintains the waiting state.

[0299] On the other hand, if the power outage warning signal is OFF and the command permission signal is ON (YES in S1), the main CPU 200a sends a start lever press command to the medal CPU 204a (S2) and sets the communication timer (S3).

[0300] When the main CPU 200a sends a start lever press command (S2), the medal CPU 204a determines whether the received start lever press command is normal (S4). If it is not normal (NO in S4), it does not perform the processing for that operation. On the other hand, if the received start lever press command is normal (YES in S4), the medal CPU 204a enters a waiting state until the command permission signal received from the main control board 200 turns ON. In this waiting state, the medal CPU 204a confirms that the command permission signal is ON (S5). If the command permission signal is OFF (NO in S5), it maintains the waiting state. On the other hand, if the command permission signal is ON (YES in S5), the medal CPU 204a sends a reply command to the main CPU 200a (S6) and terminates the processing for that operation.

[0301] When the main CPU 200a receives a reply command, it checks if the reply command is valid (S7). If it is valid (YES in S7), it checks if the game is permitted to proceed (S8). If the reply command is abnormal (NO in S7) or if the game is not permitted to proceed (NO in S8), it maintains a waiting state for the reply command. If the reply command is valid (YES in S7) and the game is permitted to proceed (YES in S8), the main CPU 200a proceeds with the game.

[0302] Furthermore, similar to the communication specifications when the power is turned on, while waiting for a reply command, the communication timer set in step S3 is set to count down. After a predetermined time has elapsed, it times out, and the operation information for the bet switch 116, settlement switch 121, start switch 118, etc., is discarded (becomes invalid). By disabling the operations in this way, the game is set not to proceed.

[0303] Figure 36 is a flowchart showing the communication specifications at the end of the game. The numerical value of step S in this figure will be used only in the explanation of this figure. For example, when all reels 110 have stopped and the winning determination is complete, the main CPU 200a of the main control board 200 sends and receives commands (payout completion command, reply command) to and from the medal CPU 204a of the medal count control board 204 and determines the status of communication establishment.

[0304] Once all reels 110 have stopped and the prize determination is complete, the main CPU 200a enters a signal waiting state. In this waiting state, the main CPU 200a checks that the power outage warning signal is OFF and the command permission signal is ON (S1). If the power outage warning signal is ON or the command permission signal is OFF (NO in S1), the CPU 200a maintains the waiting state.

[0305] On the other hand, if the power outage warning signal is OFF and the command permission signal is ON (YES in S1), the main CPU 200a sends a payout completion command to the medal CPU 204a (S2) and sets the communication timer (S3).

[0306] When the main CPU 200a sends a payout termination command (S2), the medal CPU 204a determines whether the received payout termination command is valid (S4). If it is not valid (NO in S4), it does not execute the processing at the end of the game. On the other hand, if the received payout termination command is valid (YES in S4), the medal CPU 204a enters a waiting state until the command permission signal received from the main control board 200 turns ON. In this waiting state, the medal CPU 204a confirms that the command permission signal is ON (S5). If the command permission signal is OFF (NO in S5), it maintains the waiting state. On the other hand, if the command permission signal is ON (YES in S5), the medal CPU 204a sends a reply command to the main CPU 200a (S6) and terminates the processing at the end of the game.

[0307] When the main CPU 200a receives a reply command, it checks whether the reply command is valid (S7). If the reply command is abnormal (NO in S7), it maintains a waiting state for the reply command. If the reply command is valid (YES in S7), the update process of the main RAM 200c is executed, and the game proceeds.

[0308] Furthermore, similar to the communication specifications when the power is turned on, while waiting for a reply command, the communication timer set in step S3 is set to count down, and after a predetermined time has elapsed, it times out and the main RAM 200c is not updated.Even if a timeout does not occur here, as explained using Figure 35, the operation information of the bet switch 116, settlement switch 121, start switch 118, etc. is discarded (becomes invalid), so in any case the game will not proceed.

[0309] Here, the system also determines the status of communication between the main CPU 200a and the medal CPU 204a. If communication is not established, it executes a game stop process. This configuration prevents inconsistencies between the number of game medals and the number of counted medals, enabling proper counting.

[0310] (Bet processing) As described above, by operating the bet switch 116, the player can bet any number of electronic tokens (number of game tokens) held in the token holder managed by the token CPU 204a via the bet switch 116 managed by the main CPU 200a. The player can also settle the bet electronic tokens and return them to the token holder by operating the settlement switch 121.

[0311] At this time, the main CPU 200a transmits the number of tokens to be inserted to the medal CPU 204a via a game token insertion command or a start lever press command. The number of tokens to be inserted indicates the total number of electronic tokens that the player wishes to bet in one game. For example, when the player operates the bet switch 116, the number of tokens to be inserted becomes the predetermined number required for one game, for example, 3 tokens. When the player operates the 1-bet switch, the number of tokens to be inserted increases by 1 each time it is operated, up to the predetermined limit. For example, each time the player operates the 1-bet switch, the number of tokens to be inserted changes from "0" → "1" → "2" → "3", and thereafter, even if the 1-bet switch is operated again, the number of tokens to be inserted remains at "3". Each time the bet switch 116 or the 1-bet switch is operated, the main CPU 200a transmits a game token insertion command including the number of tokens to be inserted to the medal CPU 204a, regardless of whether the number of tokens to be inserted has changed or not.

[0312] Then, the medal CPU 204a transmits the number of insertable medals and the number of game medals to the main CPU 200a via a reply command. The number of insertable medals indicates the total number of electronic medals that can be bet from the medal holder in one game. The number of game medals indicated in the reply command is the remaining number of game medals (updated number of game medals) after the number of insertable medals has been bet (after the bet has been made). The main CPU 200a bets the number of electronic medals that can be inserted, as received from the medal CPU 204a, and updates the number of game medals.

[0313] In this explanation, we have described an example where the main CPU 200a waits for the number of digitized tokens that can be inserted and the number of game tokens to be played via a reply command from the medal CPU 204a, and then bets the number of digitized tokens that can be inserted. However, the main CPU 200a may also adopt a specification in which it pre-executes betting of digitized tokens in response to the operation of the bet switch 116 or the 1-bet switch, and then aligns the bets based on the reply command from the medal CPU 204a. For example, the main CPU 200a stores information in the main RAM 200c, such as the total number of digitized tokens that have already been bet by the main CPU 200a (number of tokens inserted (value of tokens inserted)), the number of tokens to be inserted, and the number of game tokens to be played, so it can determine the number of digitized tokens that can be bet. Therefore, the main CPU 200a bets the number of digitized tokens that can be inserted in response to the operation of the bet switch 116 or the 1-bet switch, and sends a game token insertion command including the number of tokens to be inserted to the medal CPU 204a. In response, the medal CPU 204a sends a reply command to the main CPU 200a indicating the number of medals that can be inserted and the number of game medals to be played. The main CPU 200a then confirms that the received number of medals that can be inserted and the number of electronic medals that have been bet are the same (if they are different, it resends the game medal insertion command as described later or generates an error), and terminates the bet process. By adopting this configuration, the main CPU 200a can immediately place a bet with electronic medals in response to the operation of the bet switch 116 or the 1-bet switch, and for example, activate the start switch 118, thereby avoiding delays in the progress of the game.

[0314] Thus, the main CPU 200a sends the requested number of tokens to bet to the medal CPU 204a, and the medal CPU 204a replies with the number of tokens that can be bet. Therefore, the number of tokens that can be bet and the requested number of tokens should basically be equal.

[0315] However, since the number of operations for the bet switch 116 and the 1-bet switch is not limited, they can be operated multiple times before a game starts. If we simply assume that the number of tokens that can be inserted equals the number of tokens requested, then each time the bet switch 116 or the 1-bet switch is operated, the number of tokens requested is sent to the medal CPU 204a, and each time, the number of tokens requested is deducted from the number of game tokens, and electronic tokens exceeding the specified number are bet. Also, if we simply assume that the number of tokens requested is added to the number of game tokens during settlement, then each time the settlement switch 121 is operated, the number of tokens requested is sent to the medal CPU 204a, and each time, the number of tokens requested is added to the number of game tokens. Furthermore, even if the number of game tokens is less than the number of tokens that can be inserted, if we simply assume that the number of tokens that can be inserted equals the number of tokens requested, there is a risk that the number of game tokens will become negative due to betting.

[0316] Therefore, the medal CPU 204a appropriately manages the number of electronic medals. Specifically, here, not only the main CPU 200a but also the medal CPU 204a stores the number of inserted medals as information in RAM and controls both CPUs to ensure that the number of inserted medals is equal. The medal CPU 204a then derives the number of medals that can be inserted based on the number of inserted medals. For example, assuming that electronic medals have already been bet, the medal CPU 204a derives the number of medals that can be inserted by subtracting the number of inserted medals from the number of requested inserts. Furthermore, if the derived number of medals that can be inserted is greater than the number of game medals, transmitting the derived number of medals that can be inserted would result in a negative number of game medals. Therefore, to prevent this from happening, the total number of game medals is set as the number of medals that can be inserted.

[0317] Figure 37 is a flowchart showing the flow of betting in the medal CPU 204a. Here, we will explain the processes related to this embodiment, and omit processes not related to this embodiment, such as the generation of specific commands. The numerical value of step S in this figure will be used only in the explanation of this figure. Here, the medal CPU 204a stores not only the number of game tokens but also the number of tokens inserted in the RAM belonging to the medal CPU 204a.

[0318] If the main CPU 200a successfully receives a command and that command includes the number of tokens to be inserted (a token insertion command, a start lever press command), the token CPU 204a determines whether the number of tokens to be inserted is 0 or greater and 3 or less, as shown in Figure 37 (S1). If the result is that the number of tokens to be inserted is less than 0 or 4 or greater (NO in S1), error processing is performed, such as sending an error command to the main CPU 200a indicating that the number of tokens to be inserted is not within the acceptable range (S2), and the bet process is terminated. Note that although the acceptable range of the number of tokens to be inserted is determined here, the process can proceed to step S3 only if various acceptable conditions are met, such as the VL connection signal being ON, and if the acceptable conditions are not met, error processing such as sending an error command to the main CPU 200a may be performed. Furthermore, in this embodiment, if the number of requested inserts is 0, settlement processing is performed. However, in other embodiments, if the settlement processing does not adopt a specification that limits the number of requested inserts to 0, then if the number of requested inserts is 0, error processing such as sending an error command to the main CPU 200a may be performed.

[0319] On the other hand, if the number of requested tokens to be inserted is 0 or greater and 3 or less (YES in S1), the medal CPU 204a subtracts the number of requested tokens to be inserted from the number of tokens inserted to obtain the increase / decrease amount (S3). Here, the number of tokens inserted can be between 0 and 3, and the number of requested tokens to be inserted can be between 0 and 3, so the increase / decrease amount will be between -3 and 3. In this case, if the increase / decrease amount is a negative value, it indicates a bet of electronic tokens from the medal CPU 204a to the main CPU 200a, and if the increase / decrease amount is a positive value, it indicates a settlement of electronic tokens from the main CPU 200a to the medal CPU 204a. Therefore, for example, if the number of requested tokens to be inserted is 0, the entire number of tokens inserted will be subject to settlement.

[0320] Next, the medal CPU 204a adds the increase or decrease in the number of game medals to the number of game medals, and the result is the summation result (S4). This summation result is the updated number of game medals when there is no restriction on the number of game medals being negative.

[0321] Next, the medal CPU 204a determines whether the addition result is negative (S5). If the addition result is negative (YES in S5), the medal CPU 204a adds the current number of game medals to the number of medals to be inserted to derive the number of medals that can be inserted (S6). A negative addition result means that even if all of the current number of game medals is bet, it will not be enough to meet the number of medals that need to be inserted. Therefore, in this case, in order to bet as many electronic medals as possible, the entire current number of game medals is added to the number of medals to be inserted to obtain the number of medals that can be inserted. Then, the medal CPU 204a sets the remaining number after betting all of them, i.e., 0, to the updated number of game medals (S7).

[0322] On the other hand, if the sum is not a negative value (NO in S5), the medal CPU 204a uses the requested number of medals to be inserted as the number of medals that can be inserted (S8), and uses the sum as the updated number of game medals (S9). In this case, since the number of game medals is sufficient to meet the requested number of medals to be inserted, the number of medals that can be inserted equals the requested number of medals to be inserted, and it becomes possible to use the sum as the updated number of game medals.

[0323] Next, the medal CPU 204a updates the number of medals to be inserted, which it manages, to the number of medals that can be inserted (S10), sets the updated number of medals that can be inserted and the updated number of medals to be played in the reply command (S11), and terminates the bet process. In this way, the reply command is sent to the main CPU 200a.

[0324] The main CPU 200a can obtain the number of tokens that can be inserted via a reply command and start a game. However, in a specification where the start condition for a game is the maximum number of tokens bet, the main CPU 200a stores information on the number of tokens inserted and the number of tokens to be played in the main RAM 200c, so it can determine whether the number of tokens that can be inserted will fall short of the maximum number even if all the tokens to be played are bet, and if it does not fall short, it may restrict the start of a game. For example, if the main CPU 200a determines that the number of tokens that can be inserted is short of the maximum number, it may not send a command including the requested number of tokens to insert to the token CPU 204a, or even if it does send a command, the token CPU 204a may send an error command instead of a reply command (so-called "optimal max bet" control). In this way, it is possible to avoid the game proceeding with a number of electronic tokens that is short of the maximum number to bet. For example, even if the allowed number of tokens is 2 or 3, and one game can be played regardless of the number of tokens inserted, the game can be restricted if the number of tokens that can be inserted is less than the maximum allowed number of 3 (for example, if only 2 tokens are inserted). Therefore, if the number of game tokens is 0, it is possible to specify that the main CPU 200a does not send a command to the token CPU 204a that includes the number of tokens to be inserted.

[0325] Figure 38 is an explanatory diagram showing an actual calculation example of betting. For example, as shown in Figure 38(a), suppose the number of game tokens held in the RAM of the medal CPU 204a is "10" and the number of tokens inserted is "0". Then, suppose the main CPU 200a receives a command including the number of tokens to be inserted, and that the number of tokens to be inserted is "3". The medal CPU 204a subtracts the number of tokens to be inserted "3" from the number of tokens inserted "0" to derive an increase / decrease of "-3", adds the increase / decrease of "-3" to the number of game tokens "10", and derives an addition result of "7". Since the addition result "7" is not a negative value, the number of tokens that can be inserted becomes "3", which is equal to the number of tokens to be inserted. The updated number of game tokens becomes "7", which is equal to the addition result, and the number of tokens inserted becomes the number of tokens that can be inserted "3". The number of tokens that can be inserted, "3," and the updated number of game tokens, "7," are set in the reply command, and the updated number of tokens inserted, "3," is stored in the RAM of the token CPU 204a.

[0326] Furthermore, as shown in Figure 38(b), if the number of game tokens held in the RAM of the medal CPU 204a is "1" and the number of tokens inserted is "1", then the main CPU 200a receives a command including the number of tokens to be inserted, and the number of tokens to be inserted is "3". The medal CPU 204a subtracts the number of tokens to be inserted "3" from the number of tokens inserted "1" to derive an increase / decrease of "-2", and adds the increase / decrease of "-2" to the number of game tokens "1" to derive an addition result of "-1". Since the addition result "-1" is a negative value, the number of tokens that can be inserted becomes "2", which is the number of tokens inserted "1" plus the current number of game tokens "1", so the number of game tokens after the update becomes "0", and the number of tokens inserted becomes "2", which is equal to the number of tokens that can be inserted. The number of tokens that can be inserted, "2," and the updated number of tokens to play, "0," are set in the reply command, and the updated number of tokens inserted, "2," is stored in the RAM of the token CPU 204a.

[0327] Furthermore, as shown in Figure 38(c), if the number of game tokens held in the RAM of the medal CPU 204a is "3" and the number of tokens inserted is "3", then the main CPU 200a receives a command including the number of tokens to be inserted, and the number of tokens to be inserted is "0". This event can occur when the settlement switch 121 is operated. The medal CPU 204a subtracts the number of tokens to be inserted "0" from the number of tokens inserted "3" to derive an increase / decrease of "3", adds the increase / decrease of "3" to the number of game tokens "3", and derives an addition result of "6". Since the addition result "6" is not a negative value, the number of tokens that can be inserted becomes "0", which is equal to the number of tokens to be inserted, the updated number of game tokens becomes "6", which is equal to the addition result, and the number of tokens inserted becomes the number of tokens that can be inserted "0". The number of tokens that can be inserted, "0," and the updated number of tokens to be played, "6," are set in the reply command, and the updated number of tokens inserted, "0," is stored in the RAM of the token CPU 204a.

[0328] Furthermore, as shown in Figure 38(d), if the number of game tokens held in the RAM of the medal CPU 204a is "2" and the number of tokens inserted is "3", then the main CPU 200a receives a command including the number of tokens to be inserted, and that number of tokens to be inserted is "3". Such an event can occur, for example, when the bet switch 116 is operated multiple times. It can also occur if the main CPU 200a sends a command including the number of tokens to be inserted to the medal CPU 204a, and the medal CPU 204a receives it normally, but for some reason the main CPU 200a is unable to normally receive the reply command from the medal CPU 204a, and the main CPU 200a resends the command including the number of tokens to be inserted to the medal CPU 204a. The medal CPU 204a subtracts the number of tokens to be inserted "3" from the number of tokens inserted "3" to derive an increase / decrease of "0", and adds the increase / decrease of "0" to the number of game tokens "2" to derive an addition result of "2". Since the sum result "2" is not a negative value, the number of tokens that can be inserted becomes "3", which is equal to the number of tokens requested to be inserted. The updated number of game tokens becomes "2", which is equal to the sum result, and the number of tokens inserted becomes the number of tokens that can be inserted, "3". This number of tokens that can be inserted, "3", and the updated number of game tokens, "2", are set in the reply command, and the updated number of tokens inserted, "3", is stored in the RAM of the token CPU 204a.

[0329] Furthermore, as shown in Figure 38(e), if the number of game tokens held in the RAM of the medal CPU 204a is "3" and the number of tokens inserted is "0", then the main CPU 200a receives a command including the number of tokens to be inserted, and that number of tokens to be inserted is "0". Such an event can occur, for example, when the settlement switch 121 is operated multiple times. It can also occur if the main CPU 200a sends a command including the number of tokens to be inserted to the medal CPU 204a, and the medal CPU 204a receives it normally, but for some reason the main CPU 200a is unable to normally receive the reply command from the medal CPU 204a, and the main CPU 200a resends the command including the number of tokens to be inserted to the medal CPU 204a. The medal CPU 204a subtracts the number of tokens to be inserted "0" from the number of tokens inserted "0" to derive an increase / decrease of "0", adds the increase / decrease of "0" to the number of game tokens "3", and derives an addition result of "3". Since the sum result "3" is not a negative value, the number of tokens that can be inserted becomes "0", which is equal to the number of tokens requested to be inserted. The updated number of game tokens becomes "3", which is equal to the sum result, and the number of tokens inserted becomes the number of tokens that can be inserted, "0". This number of tokens that can be inserted, "0", and the updated number of game tokens, "3", are set in the reply command, and the updated number of tokens inserted, "0", is stored in the RAM of the token CPU 204a.

[0330] In this way, both the main CPU 200a and the medal CPU 204a store the number of inserted medals as information in their respective RAMs, and the configuration controls both CPUs to ensure that the number of inserted medals is equal. As a result, the medal CPU 204a can grasp the number of inserted medals, which would normally only be managed by the main CPU 200a. Therefore, based on the number of game medals managed by the medal CPU 204a, the number of inserted medals, and the number of requested inserts obtained from the main CPU 200a, it becomes possible to appropriately derive the number of insertable medals, the updated number of game medals, and the updated number of inserted medals through calculations such as "number of inserted medals - number of requested inserts" and "number of game medals + increase / decrease."

[0331] Thus, even if the bet switch 116 or the 1-bet switch is operated multiple times, the medal CPU 204a appropriately derives the number of medals to be inserted based on the number of medals inserted and subtracts the required number of digitized medals from the number of game medals. Therefore, in the betting process, digitized medals will not be bet in excess of the specified number, and in the settlement process, digitized medals will not be unnecessarily added to the number of game medals. In addition, if the number of game medals is less than the number of medals that can be inserted, the medal CPU 204a will bet up to the number of game medals held in the medal holder, so the number of game medals will never become negative due to betting.

[0332] When a setting change occurs in the main control board 200, both the number of inserted tokens and the number of game tokens held in the RAM of the main CPU 200a and the RAM of the medal CPU 204a are cleared to 0. Specifically, when a setting change occurs, the main CPU 200a clears the number of inserted tokens and the number of game tokens held in its own RAM to 0. The main CPU 200a then transmits a command to the dedicated unit 350 via the medal CPU 204a indicating that a setting change has been performed. When the medal CPU 204a receives this command indicating that a setting change has been performed, it clears the number of inserted tokens to 0. Furthermore, since the number of game tokens held in the token holder is not cleared except when the "game token count clear button" is operated, the medal CPU 204a sends the current number of game tokens to the main CPU 200a in a reply command to the startup command, and the main CPU 200a updates the number of game tokens held in its own RAM based on the received number of game tokens. This ensures the same number of inserted tokens and the same number of tokens played between the main CPU 200a and the token CPU 204a. Furthermore, if a backup error occurs in the token CPU 204a, the RAM belonging to the token CPU 204a is cleared to 0. Even in this case, the main CPU 200a can ensure the same number of inserted tokens by sending the number of inserted tokens held in the main RAM 200c of the main CPU 200a to the token CPU 204a via a startup command at startup.

[0333] Alternatively, or in addition to the above configuration, the medal CPU 204a may periodically send various calculated values, such as the number of medals inserted, the number of medals played, the number of medals requested to be inserted, and the number of medals that can be inserted, as commands to the main CPU 200a at predetermined intervals.

[0334] (Settings change / Settings confirmation) As described above, in this embodiment, the setting is changed by the setting value setting means. When attempting to change the setting, first the power of the smart pachislo 100 is turned OFF. Then, when a predetermined operation key is inserted into the setting door key (not shown) and rotated from the OFF position to the ON position, the power is turned on via the power switch (not shown), and the system enters setting change mode, becoming capable of changing the setting, and the setting change status becomes ON. Here, the setting change status is ON while the setting change is being performed, and OFF otherwise. If the main RAM 200c is abnormal at the start of the setting change mode, all variables in the main RAM 200c are cleared, and if the main RAM 200c is normal, only the setting change area of ​​the main RAM 200c is cleared. When the main CPU 200a transmits the setting change status to the dedicated unit 350, the medal CPU 204a can acquire the setting change status, but does not clear the number of game tokens managed by the medal CPU 204a in response to this setting change status. When the setting change switch is pressed while the setting can be changed, the setting value is incremented by 1 each time, repeating in ascending order from 1 to 6: 1→2→3→4→5→6→1→…. Here, the setting is updated to one of the six setting values, and when the start switch 118 is operated, the setting value is confirmed. Then, by returning the setting door key to its original position (OFF position), the setting change mode ends and gameplay becomes possible. The setting change status is turned OFF after the setting change mode ends and after one game is completed.

[0335] Furthermore, in the setting change mode, the main CPU 200a generates a setting change signal to transmit the setting change status to the dedicated unit 350. The setting change signal indicates the ON / OFF status of the setting change and is set to bit 0 in the "Gaming Machine Fraud 1" section of the Hall Computer Fraud Monitoring Information (Gaming Machine Information) in the Gaming Machine Information Notification shown in Figure 11. As shown in Figure 16, it is notified to the dedicated unit 350 at a 300 msec cycle.

[0336] Here, assuming that two CPUs (main CPU 200a and medal CPU 204a) are installed independently as shown in Figures 5(a) and 5(b), and that the main CPU 200a manages the setting change status, the main CPU 200a turns on the setting change signal when the power switch is turned on with a predetermined operation key inserted into the setting door key and rotated from the OFF position to the ON position, indicating that the setting change status is ON, and sends a game machine information notification to the dedicated unit 350 via the medal CPU 204a. On the other hand, after the setting door key is returned to its original position (OFF position), and after one game has finished, the main CPU 200a turns off the setting change signal to indicate that the setting change status has turned OFF, and sends a game machine information notification to the dedicated unit 350 via the medal CPU 204a. In other words, the setting change signal must remain ON until the end of one game. If we were to implement this process using the main CPU 200a, it would require a program that not only sets the setting change signal but also waits for the end of one game to finish before turning off the setting change signal. This could strain the memory usage, especially the control area. Therefore, in this example, the process of setting the setting change signal and the process of waiting for the end of one game to finish before turning off the setting change signal are implemented using the medal CPU 204a instead of the main CPU 200a.

[0337] Figure 39 is a flowchart showing the update process of the setting change signal. The numerical value of step S in this figure will be used only in the explanation of this figure. When the power switch is turned ON with a predetermined operation key ON, the main CPU 200a executes a setting change process to change the setting value (S1). Then, when the initialization process including the setting change is completed, the main CPU 200a executes a bet process to bet electronic tokens in response to the player's operation of the bet switch 116 (S2). Subsequently, the main CPU 200a executes a lottery process in response to the player's operation of the start switch 118 (S3). Then, the main CPU 200a starts the rotation of reels 110a, 110b, and 110c and executes a reel rotation process (S4). Next, in response to the player's operation of stop switches 120a, 120b, and 120c, the main CPU 200a executes a reel stop process to control the stopping of reels 110a, 110b, and 110c corresponding to the operated stop switches 120a, 120b, and 120c (S5). When reels 110a, 110b, and 110c stop, the main CPU 200a executes a determination process to determine whether the combination of symbols displayed on active line A corresponds to any winning combination (S6). Based on the determination result, if a combination of symbols corresponding to a minor win is displayed on active line A, the main CPU 200a executes a payout process for the medals corresponding to that minor win (S7). In this way, one game is executed through a series of processes from step S2 to step S7. Thereafter, steps S2 to S7 are repeated.

[0338] Furthermore, at the start of the setting change process (S1), the main CPU 200a sends a state transition command (first command) to the medal CPU 204a indicating that the setting change has started. Upon receiving this state transition command, the medal CPU 204a turns ON the setting change signal by setting bit 0 in the game machine fraud 1 of the hall computer fraud monitoring information shown in Figure 11 to 1 (S11). Also, in the payout process (S7), when the payout of medals is completed, the main CPU 200a sends a payout completion command (second command) to the medal CPU 204a. Upon receiving this payout completion command, the medal CPU 204a turns OFF the setting change signal by setting bit 0 in the game machine fraud 1 of the hall computer fraud monitoring information to 0 (S12). Thus, the function unit that turns on a setting change signal at the start of a setting change and sends it to the dedicated unit 350, and then turns off the setting change signal at the end of a game and sends it to the dedicated unit 350 after the setting change is complete, is sometimes called the setting change signal update unit. The first command is not limited to a state transition command, but can be any command as long as it is specified that a setting change is starting, and the second command is not limited to a payout end command, but can be any command as long as it is specified that a game is completed each time a game is finished.

[0339] In this way, by implementing the process of setting the setting change signal in the medal CPU 204a instead of the main CPU 200a, the increase in the program in the main ROM 200b can be suppressed. Therefore, the used memory area, especially the control area, is not strained. Furthermore, since the ROM of the medal CPU 204a has ample memory capacity (2.5K bytes), there is no problem in implementing the program in the medal CPU 204a.

[0340] In this configuration, the main CPU 200a sends a payout completion command to the medal CPU 204a during each game and payout process (S7), and the medal CPU 204a turns off the setting change signal in response to this payout completion command (S12). In this configuration, the medal CPU 204a repeatedly turns off the setting change signal. However, the setting change signal remains OFF and, once turned OFF, is appropriately notified to the dedicated unit 350 at 300 msec intervals. Therefore, it is not a problem for the medal CPU 204a to repeatedly turn off the setting change signal. In this configuration, when sending the payout completion command to the medal CPU 204a, the main CPU 200a does not need to determine the condition that it is the first game after the setting change process has finished, so a program to determine the condition that it is the first game after the setting change process has finished is unnecessary, and the increase in the program in the main ROM 200b can be further suppressed.

[0341] In this explanation, we have used an example where the main CPU 200a sends a command to the medal CPU 204a during the payout process (S7). However, commands may also be sent during the reel stop process (S5) or the judgment process (S6) as long as one game has finished.

[0342] In addition to changing settings, the Smart Pachislo 100 also allows users to check the set settings. To attempt a setting check, the designated operation key is first inserted into the setting door key and rotated from the OFF position to the ON position. This switches the machine to setting check mode, making it possible to check the setting values, and the setting check status is turned ON. The setting check status remains ON while the setting check is being performed, and is OFF otherwise. The bet switch 116, payout switch 121, and start switch 118 may be disabled while the setting check status is active. The set values ​​are then displayed, and the status timer begins counting. The status timer measures the time the setting check status is maintained. Returning the operation key to its original position (OFF position) ends the setting check mode, and gameplay becomes possible. The setting check status is turned OFF when the setting door key is OFF and the status timer has elapsed for 5 seconds or more.

[0343] Furthermore, in the setting confirmation mode, the main CPU 200a generates a setting confirmation signal to transmit the setting confirmation status to the dedicated unit 350. The setting confirmation signal indicates the ON / OFF status of the setting confirmation and, as shown in Figure 11, is set to bit 1 in the game machine fraud 1 of the hall computer fraud monitoring information (game machine information) in the game machine information notification, and is notified to the dedicated unit 350 at a 300 msec cycle, as shown in Figure 16.

[0344] Here, as shown in Figures 5(a) and 5(b), if two CPUs are installed independently (main CPU 200a and medal CPU 204a), managing the setting confirmation status with the main CPU 200a would require a program that not only sets the setting confirmation signal but also measures 5 seconds using the status timer, which could strain the memory usage, especially the control area. Therefore, similar to the setting change mode, the process of setting the setting confirmation signal and measuring 5 seconds using the status timer is implemented by the medal CPU 204a instead of the main CPU 200a.

[0345] Figure 40 is a flowchart showing the update process of the setting confirmation signal. The numerical value of step S in this figure will be used only in the explanation of this figure. While one game is being executed through the series of processes shown in Figure 40, the payout process of the previous game (S1) is completed and the electronic tokens are in a waiting state. When a predetermined operation key is turned ON, the main CPU 200a starts a setting confirmation process to check the set value (S2). Once the setting confirmation is complete, the predetermined operation key is turned OFF and the main CPU 200a ends the setting confirmation process (S3). In this way, the main CPU 200a can perform the bet process (S4).

[0346] Furthermore, at the start of the setting confirmation process (S2), the main CPU 200a sends a state transition command (third command) to the medal CPU 204a in response to the start of the setting confirmation. Upon receiving this state transition command, the medal CPU 204a turns on the setting confirmation signal by setting bit 1 in the game machine fraud 1 of the hall computer fraud monitoring information shown in Figure 11 to 1 (S11). Also, at the end of the setting confirmation process (S3), the main CPU 200a sends a state transition command (fourth command) to the medal CPU 204a. Upon receiving this state transition command, the medal CPU 204a sets the status timer to 5 seconds and starts timing (S12). Then, the medal CPU 204a determines whether 5 seconds have elapsed in the status timer (S13), waits until 5 seconds have elapsed (NO in S13), and when 5 seconds have elapsed (YES in S13), it turns off the setting confirmation signal by setting bit 1 in the game machine fraud 1 of the hall computer fraud monitoring information to 0 (S14). In this way, the function unit that turns on the setting confirmation signal at the start of setting value confirmation and sends it to the dedicated unit 350, and after the confirmation of the setting value is completed, waits for a predetermined time to elapse, turns off the setting confirmation signal and sends it to the dedicated unit 350, is sometimes called the setting confirmation signal update unit. Note that the third command is not limited to the above and can be any command as long as it is specified at the start of setting value confirmation, and the fourth command is not limited to the above and can be any command as long as it is specified at the completion of setting value confirmation.

[0347] In this way, by having the medal CPU 204a perform the process of setting the setting confirmation signal and timing 5 seconds with the status timer, instead of the main CPU 200a, the program size in the main ROM 200b can be reduced, and the control area in particular will not be strained.

[0348] As mentioned above, the setting confirmation signal indicates that the machine is in setting confirmation mode and must be output for at least 3 seconds as a countermeasure against cheating. However, the game machine information notification, including the setting confirmation signal, is only transmitted to the dedicated unit 350 at 300 msec intervals. In that case, for example, if the medal CPU 204a receives a state transition command immediately after the game machine information notification is transmitted, the time between the ON and OFF states of the setting confirmation signal may be reduced by about 300 msec. Here, by setting the waiting time in the status timer to 5 seconds, the time between the ON and OFF states of the setting confirmation signal can be made 3 seconds or more, regardless of the transmission timing of the game machine information notification. Furthermore, since the start of the 5-second timer is set to the reception of the command indicating the end of the setting confirmation, rather than the reception of the command indicating the start of the setting confirmation, the time between the command indicating the start of the setting confirmation and the command indicating the end of the setting confirmation is added to the 5 seconds, thus ensuring that the time between the ON and OFF states of the setting confirmation signal is 3 seconds or more.

[0349] (Winner of the replay role) Furthermore, by generating the setting change signal and setting confirmation signal in the medal CPU 204a instead of the main CPU 200a, the processing load on the main CPU 200a and the memory capacity of the main ROM 200b are reduced. However, not limited to this case, the amount of information transmitted from the main CPU 200a to the medal CPU 204a can be kept to a minimum, and information requiring notification to the dedicated unit 350 may be generated by the medal CPU 204a. This configuration also reduces the burden on the main CPU 200a. For example, the smart pachislo 100 must transmit the hall computer / fraud monitoring information and game information shown in Figure 11 to the dedicated unit 350 every 300 msec, and as part of the game information, it must transmit the number of medals inserted and the number of medals paid out when the start switch 118 is operated and when the game ends. Here, for example, if the game result is a replay win, the main CPU 200a sends only the information of a replay flag and payout amount "0" to the medal CPU 204a. The medal CPU 204a then sends the necessary information to the dedicated unit 350, for example, when the start switch 118 is operated, it generates the predetermined number of medals to be inserted (the predetermined number bet in that game) as the number of medals to be inserted, and when the game ends, it generates the predetermined number of medals to be paid out and notifies the dedicated unit 350. This configuration reduces the processing load of the main CPU 200a and the memory capacity of the main ROM 200b.

[0350] Furthermore, by assigning the replay flag that the main CPU 200a sends to the medal CPU 204a to a predetermined bit of the identification information, "replay status" (1 bit), instead of a 1-byte command, it becomes unnecessary to prepare a 1-byte command called "replay status," thereby consolidating commands and reducing the processing load.

[0351] (Data transmission control from main CPU 200a to medal CPU 204a) As shown in Figures 5(a) and 5(b), when two CPUs are installed independently (main CPU 200a and medal CPU 204a), serial communication is performed between the main CPU 200a and the medal CPU 204a. For example, the main CPU 200a sends a predetermined command to the medal CPU 204a via serial communication. The medal CPU 204a then sends a game machine information notification to the dedicated unit 350, as shown in Figures 8 to 16.

[0352] Figure 41 is an explanatory diagram illustrating a comparative example of communication processing between the main CPU 200a and the medal CPU 204a. Here, we will explain an example in which the main CPU 200a sends a 5-byte (fixed-length) command containing a checksum to the medal CPU 204a.

[0353] As shown in Figure 41, the main control board 200 is provided with a transmit FIFO 380 for serial transmission. The transmit FIFO 380 has a memory capacity of 64 bytes and has a buffer function that holds the first byte of data input and outputs that byte of data first at the transmittable timing (for example, every 80 μsec). In addition, the main RAM 200c corresponding to the main CPU 200a is provided with a transmit candidate buffer 382 that holds 4 bytes of command (data).

[0354] When the main CPU 200a receives a command (4 bytes excluding the checksum) to send to the medal CPU 204a, it first checks whether the command is already held in the transmission candidate buffer 382. If the command is already held, the main CPU 200a waits for the transmission candidate buffer 382 to become free. If the command is not already held, the main CPU 200a places the 4-byte command, indicated by cross-hatching, into the transmission candidate buffer 382, ​​as shown in Figure 41(a). Next, the main CPU 200a checks whether there are 10 bytes free in the transmission FIFO 380, depending on whether the command is now held in the transmission candidate buffer 382. Here, 10 bytes free means that the data held in the 64-byte buffer of the transmission FIFO 380 is 54 (64-10) or less, and that at least 10 bytes of data can be held. The reason for checking for 10 bytes free here is that there are cases where two 5-byte commands, including the checksum, are sent consecutively. If the transmit FIFO380 does not have 10 bytes free, the main CPU200a waits for 10 bytes to become free in the transmit FIFO380. Then, if 10 bytes are free in the transmit FIFO380, the main CPU200a has the transmit FIFO380 hold the command, as shown in Figure 41(b).

[0355] Furthermore, as shown in Figure 41(c), when the main CPU 200a has the transmit FIFO 380 hold a command, it calculates a checksum of the 4-byte command held in the transmit candidate buffer 382, ​​and has the transmit FIFO 380 hold the checksum, shown in black, in addition to the 4-byte command. In this way, a 5-byte command is set in the transmit FIFO 380. Then, as shown in Figure 41(d), the transmit FIFO 380 sends the 5-byte command to the medal CPU 204a at 80 μsec intervals.

[0356] Figure 41 illustrates an example where the command is of fixed length, but commands can also be of variable length. For example, the main CPU 200a sends a variable-length command, such as 3 to 80 bytes, to the medal CPU 204a. When a command is of variable length, the following problems arise. For example, a 3-byte command can be held at once in the 4-byte transmission candidate buffer 382 or the 64-byte transmission FIFO 380, but an 80-byte command cannot be held at once in either. Therefore, the command to be sent is divided into multiple parts, and the command is sent in units of a small number of bytes (e.g., 1 byte). In this example, the configuration of the transmission candidate buffer 382 is removed, and the checksum generation process is modified.

[0357] Figure 42 is a flowchart illustrating the concept of sending a single byte of a command, along with a diagram showing the command. The numerical value of step S in this diagram will be used only in the explanation of this diagram.

[0358] As shown in Figure 42(a), the main CPU 200a first obtains information about the transmit FIFO 380 (S1). Specifically, the command "PUSH AF" on the first line of Figure 42(b) saves the value of the AF register to the stack area, and the command "IN A,(@S0ST__)" on the third line uses the value of the U register as the upper byte of the address and the address "@S0ST__" as the lower byte, and reads the value of the multiplication result register indicated by that address into the A register. In this way, information about the transmit FIFO 380 is obtained from "@S0ST__". Next, as shown in Figure 42(a), the main CPU 200a determines whether there is one or more bytes free in the transmit FIFO 380 (S2), and repeats the process of step S1 until one or more bytes become free in the transmit FIFO 380 (NO in S2). Specifically, the command "JBIT Z,6,A,MCD_SND01" on the fourth line of Figure 42(b) indicates that if bit 6 of the A register is 0, that is, if there is no free space of 1 byte or more in the transmit FIFO380, the process from the indicator "MCD_SND01" on the second line is repeated, and if bit 6 is not 0, the next command on the fifth line is executed.

[0359] Next, as shown in Figure 42(a), if there is one or more bytes of free space in the transmit FIFO 380 (YES in S2), the main CPU 200a sends one byte of data to the transmit FIFO 380 (S3). Specifically, the command "POP AF" on the 5th line of Figure 42(b) restores the data that had been saved in the stack area to the AF register. The command "OUT (@S0DT__),A" on the 6th line uses the value of the U register as the upper byte of the address and the address "@S0DT__" as the lower byte, and outputs the value of the A register that was restored to the transmit FIFO 380 indicated by that address. Subsequently, as shown in Figure 42(a), the one-byte checksum is updated (S4). Specifically, the command "ADD A,E" on line 7 of Figure 42(b) adds the value of the E register, which holds the checksum, to the value of the A register, the command "LD E,A" on line 8 returns the result of the addition (the value of the A register) to the E register, and the command "RET" on line 9 returns to the routine one level up.

[0360] Figure 43 is an explanatory diagram illustrating the communication process between the main CPU 200a and the medal CPU 204a. Here, we will explain using an example where the main CPU 200a sends an 80-byte command from among variable-length commands to the medal CPU 204a.

[0361] As shown in Figure 43, the main CPU 200a is equipped with a transmit FIFO 380 for serial transmission. Similar to Figure 41, the transmit FIFO 380 has a memory capacity of 64 bytes and has a buffer function that holds the first byte of data input and outputs that byte of data first at the transmission timing (e.g., every 80 μsec). In addition, the main RAM 200c, which belongs to (corresponds to) the main CPU 200a, is equipped with a checksum buffer 384 that holds a 1-byte checksum.

[0362] When the main CPU 200a receives a command (76 bytes excluding the checksum) to send to the medal CPU 204a, it clears the checksum buffer 384 (setting it to 0) and checks whether there is 1 byte free in the transmit FIFO 380. If there is not 1 byte free in the transmit FIFO 380, the main CPU 200a waits for 1 byte to become free in the transmit FIFO 380. If there is 1 byte free in the transmit FIFO 380, as shown in Figure 43(a), the main CPU 200a has the transmit FIFO 380 hold the 1 byte of data at the beginning of the command.

[0363] Furthermore, when the main CPU 200a stores one byte of data in the transmit FIFO 380, it calculates a checksum between the data in the checksum buffer 384 and the one-byte data, and overwrites the checksum buffer 384 with the checksum (calculated result) shown in black. In this way, the checksum is updated each time one byte of data is transmitted.

[0364] Then, as shown in Figure 43(b), if there is one byte free in the transmit FIFO 380, the main CPU 200a has the transmit FIFO 380 hold the command one byte at a time, and the transmit FIFO 380 sends the command one byte at a time at 80 μsec intervals. In this way, if there is one or more bytes free in the transmit FIFO 380, the main CPU 200a has the transmit FIFO 380 sequentially hold the command divided into one byte portions. However, as mentioned above, the number of bytes in the command to be transmitted is larger than the capacity of the transmit FIFO 380, so a situation may occur where there is no free space in the transmit FIFO 380, as shown in Figure 43(c). In this case, the main CPU 200a will wait until the transmit FIFO 380 has one byte free.

[0365] Once the main CPU 200a has stored all the commands in the transmit FIFO 380, it stores the checksum held in the checksum buffer 384 in the transmit FIFO 380, as shown in Figure 43(d). In this way, an 80-byte command is set in the transmit FIFO 380. The transmit FIFO 380 then sends the 80-byte command to the medal CPU 204a at 80 μsec intervals.

[0366] In this configuration, where commands are divided and stored in the transmission FIFO380, the main CPU200a can appropriately send commands to the medal CPU204a regardless of the command length, even if the command length exceeds the capacity of the transmission FIFO380.

[0367] Furthermore, regardless of the number of bytes in a command, for example, even if the command is 3 bytes, the main CPU 200a uniformly divides the command and stores it in the transmit FIFO 380, which simplifies the program and suppresses the increase in the program in the main ROM 200b. Therefore, the used area, especially the control area, is not strained. Also, unlike the configuration in Figure 41, the transmit candidate buffer 382 is reduced, so the capacity of the main RAM 200c can be secured.

[0368] Furthermore, in this case, the main CPU 200a uniformly updates the checksum each time it stores one byte of data in the transmit FIFO 380, so the checksum calculation is completed at the time the command transmission is finished. Therefore, a separate program to calculate the checksums of multiple data at once is unnecessary, which not only prevents the use of memory, especially the control area, from being strained, but also reduces processing time.

[0369] In this explanation, we have used an example where the main CPU 200a divides the command into 1-byte chunks and stores them in the transmission FIFO 380. However, the command can be divided into predetermined byte units less than the maximum command length, such as 2-byte chunks. If the unit of division is not a common divisor of the command length, the main CPU 200a repeatedly sends the command in chunks of the divided length, and sends the remaining data in the final transmission. For example, if the command length is 80 bytes and the byte unit is 5 bytes, the main CPU 200a divides the command into 5-byte chunks and repeatedly (16 times) stores them in the transmission FIFO 380.

[0370] Furtherm...

Claims

[Claim 1] A gaming machine that can be connected to a specific unit that provides gaming value, A game control means for controlling the progress of the game, A game value management means for managing the game value, A sound control means that controls the output of sound according to the progress of the game, Equipped with, The sound control means is In some cases, the first sound may be output based on the processing related to the progress of the aforementioned game. In some cases, a second sound may be output based on the process related to the transfer of the game value with the aforementioned specific unit. In some cases, a third tone may be output if certain conditions are met. In some cases, the second tone may be superimposed and output during the output of the first tone. A gaming machine capable of not outputting the second sound while the third sound is being output.

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