Indication device

Abstract

To provide a display device that can reduce optical leakage from switching elements. [Solution] The display device comprises an array substrate, a counter substrate, a liquid crystal layer between the array substrate and the counter substrate, and a light source positioned so that light enters the side surface of the array substrate or the side surface of the counter substrate. The array substrate has a plurality of signal lines spaced apart in a first direction, a plurality of scan lines spaced apart in a second direction, and switching elements connected to the scan lines and signal lines. The switching element has a semiconductor layer having a first side surface on the side closer to the direction of incidence of light from the light source, and a second side surface opposite to the first side surface. The semiconductor layer has a first width in the direction intersecting the direction of incidence that is smaller than the second width in the direction parallel to the direction of incidence, and the source electrode connected to the signal line covers the first side surface of the semiconductor layer.

Description

Technical Field

[0001] The present invention relates to a display device.

Background Art

[0002] Patent Documents 1 and 2 describe a display device including a first light-transmissive substrate, a second light-transmissive substrate disposed opposite the first light-transmissive substrate, a liquid crystal layer having a polymer-dispersed liquid crystal encapsulated between the first light-transmissive substrate and the second light-transmissive substrate, and a plurality of light-emitting elements (light-emitting modules) disposed opposite at least one side surface of the first light-transmissive substrate and the second light-transmissive substrate. In the display devices described in Patent Documents 1 and 2, the background on the other side surface can be visually recognized from one surface of the display panel.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In such a display device, since a light source (described as a light-emitting module in Patent Documents 1 and 2) is disposed opposite at least one side surface of the first light-transmissive substrate and the second light-transmissive substrate, it is necessary to reduce the light leakage of the switching element due to the light source.

[0005] An object of the present invention is to provide a display device capable of reducing the light leakage of a switching element.

Means for Solving the Problems

[0006] A display device according to one aspect of the present disclosure comprises an array substrate, a counter substrate, a liquid crystal layer between the array substrate and the counter substrate, and a light source positioned such that light enters the side surface of the array substrate or the side surface of the counter substrate, wherein the array substrate has a plurality of signal lines spaced apart in a first direction, a plurality of scan lines spaced apart in two directions, and switching elements connected to the scan lines and the signal lines, the switching elements having a semiconductor layer having a first surface on the side closer to the direction of incidence of light from the light source and a second surface on the opposite side to the first surface, the semiconductor layer having a first width in a direction intersecting the incidence direction less than a second width in a direction parallel to the incidence direction, and a source electrode connected to the signal line covers the first surface of the semiconductor layer. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a perspective view showing an example of a display panel according to this embodiment. [Figure 2] Figure 2 is a block diagram representing the display device of the first embodiment. [Figure 3] Figure 3 is a timing chart illustrating the timing of light emission from the light source in the field sequential method of the first embodiment. [Figure 4] Figure 4 is an explanatory diagram showing the relationship between the voltage applied to the pixel electrode and the scattering state of the pixel. [Figure 5] Figure 5 is a cross-sectional view showing an example of a cross-section of a display device. [Figure 6] Figure 6 is a plan view showing the top view of the display device shown in Figure 1. [Figure 7] Figure 7 is an enlarged cross-sectional view of the liquid crystal layer portion shown in Figure 5. [Figure 8] Figure 8 is a cross-sectional view illustrating the non-scattering state in the liquid crystal layer. [Figure 9] Figure 9 is a cross-sectional view illustrating the scattering state in the liquid crystal layer. [Figure 10] Figure 10 is a plan view showing scan lines, signal lines, and switching elements in a pixel. [Figure 11] FIG. 11 is a plan view showing a holding capacitance layer in a pixel. [Figure 12] FIG. 12 is a plan view showing a switching element in a pixel. [Figure 13] FIG. 13 is a plan view showing a pixel electrode in a pixel. [Figure 14] FIG. 14 is a plan view showing a light shielding layer in a pixel. [Figure 15] FIG. 15 is a cross-sectional view taken along line XV-XV' of FIG. 12. [Figure 16] FIG. 16 is a cross-sectional view taken along line XVI-XVI' of FIG. 14. [Figure 17] FIG. 17 is a cross-sectional view taken along line XVII-XVII' of FIG. 14. [Figure 18] FIG. 18 is a cross-sectional view showing a switching element according to a first modification. [Figure 19] FIG. 19 is a plan view showing a switching element of a display device according to a second embodiment. [Figure 20] FIG. 20 is a cross-sectional view taken along line XX-XX' of FIG. 19. [Figure 21] FIG. 21 is a plan view showing a switching element according to a second modification. [Figure 22] FIG. 22 is a cross-sectional view taken along line XXII-XXII' of FIG. 21. [Figure 23] FIG. 23 is a plan view showing a switching element according to a third modification.

MODE FOR CARRYING OUT THE INVENTION

[0008] Embodiments for implementing the present disclosure will be described in detail with reference to the drawings. The present disclosure is not limited by the content described in the following embodiments. Further, the components described below include those that can be easily assumed by those skilled in the art and substantially identical ones. Furthermore, the components described below can be combined as appropriate. Note that the disclosure is merely an example, and for those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the present disclosure, they are naturally included in the scope of the present disclosure. In addition, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but this is merely an example and does not limit the interpretation of the present disclosure. Also, in the present disclosure and each figure, the same reference numerals are given to the same elements as those described above with respect to the previously shown figures, and detailed descriptions may be omitted as appropriate.

[0009] In the present disclosure, when expressing the aspect of arranging another structure on a certain structure, when simply described as "on", unless otherwise specified, it includes both the case of arranging another structure directly above so as to contact a certain structure and the case of arranging another structure above a certain structure via yet another structure.

[0010] (First Embodiment) FIG. 1 is a perspective view showing an example of the display panel according to the present embodiment. FIG. 2 is a block diagram showing the display device of the first embodiment. FIG. 3 is a timing chart for explaining the timing at which the light source emits light in the field sequential method of the first embodiment.

[0011] As shown in Figure 1, the display device 1 comprises a display panel 2, a light source 3 (see Figure 5), and a drive circuit 4. The array substrate 10 has a larger PX-PY plane area than the opposing substrate 20, and the drive circuit 4 is provided on the protruding portion of the array substrate 10 that is exposed from the opposing substrate 20. The drive circuit 4 includes at least a gate drive circuit 43 and a source drive circuit 44, which will be described later. Here, one direction of the plane of the display panel 2 is defined as the first direction PX, the direction perpendicular to the first direction PX is defined as the second direction PY, and the direction perpendicular to the PX-PY plane is defined as the third direction PZ. Furthermore, "planar view" refers to the positional relationship when viewed from the third direction PZ.

[0012] The display panel 2 comprises an array substrate 10, a counter substrate 20, and a liquid crystal layer 50 (see Figure 5). The array substrate 10 is a first translucent substrate, and the counter substrate 20 is a second translucent substrate. The counter substrate 20 faces the surface of the array substrate 10 in a direction perpendicular to it (the third direction PZ shown in Figure 1). The liquid crystal layer 50 (see Figure 5) is sealed with a polymer-dispersed liquid crystal LC, which will be described later, between the array substrate 10, the counter substrate 20, and the sealing portion 18.

[0013] As shown in Figure 1, the display panel 2 has an active area AA on which an image can be displayed, and a peripheral area FR outside the active area AA. Multiple pixels Pix are arranged in a matrix in the active area AA. In this disclosure, a row refers to a pixel row having m pixels Pix arranged in one direction. A column refers to a pixel column having n pixels Pix arranged in a direction orthogonal to the direction in which the rows are arranged. The values ​​of m and n are determined according to the vertical display resolution and the horizontal display resolution. Multiple scan lines GL are wired for each row, and multiple signal lines SL are wired for each column.

[0014] As shown in Figure 2, the light source 3 is equipped with a plurality of light-emitting units 31. The light source control unit 32 is provided on a wiring board 93. The wiring board 93 is a flexible printed circuit board or PCB board. The light source control unit 32 receives a light source control signal LCSA from the image output unit 91 of an external higher-level control unit 9. The light source control signal LCSA is a signal that includes information about the amount of light emitted by the light-emitting units 31, which is set according to the input grayscale value to the pixel Pix, for example.

[0015] As shown in Figure 1, the drive circuit 4 is fixed to the surface of the array substrate 10. As shown in Figure 2, the drive circuit 4 includes a signal processing circuit 41, a pixel control circuit 42, a gate drive circuit 43, a source drive circuit 44, and a common potential drive circuit 45.

[0016] The signal processing circuit 41 receives a first input signal (such as an RGB signal) VS from the image output unit 91 of the external higher-level control unit 9 via the flexible printed circuit board 92.

[0017] The signal processing circuit 41 includes an input signal analysis unit 411, a storage unit 412, and a signal adjustment unit 413. The input signal analysis unit 411 generates a second input signal VCS based on a first input signal VS input from an external source.

[0018] The second input signal VCS is a signal that determines what grayscale value to assign to each pixel Pix of the display panel 2 based on the first input signal VS. In other words, the second input signal VCS is a signal that contains grayscale information regarding the grayscale value of each pixel Pix.

[0019] The signal adjustment unit 413 generates a third input signal VCSA from the second input signal VCS. The signal adjustment unit 413 sends the third input signal VCSA to the pixel control circuit 42.

[0020] The pixel control circuit 42 then generates a horizontal drive signal HDS and a vertical drive signal VDS based on the third input signal VCSA. In this embodiment, since it is driven in a field sequential manner, the horizontal drive signal HDS and the vertical drive signal VDS are generated for each color that the light-emitting unit 31 can emit light.

[0021] The gate drive circuit 43 sequentially selects scan lines GL of the display panel 2 within one vertical scanning period based on the horizontal drive signal HDS. The order of selection of scan lines GL is arbitrary. The gate drive circuit 43 and scan lines GL are electrically connected by a second wiring GPL located in the peripheral region FR (see Figure 1) outside the active region AA.

[0022] Based on the vertical drive signal VDS, the source drive circuit 44 supplies a grayscale signal to each signal line SL of the display panel 2 within one horizontal scanning period, corresponding to the output grayscale value of each pixel Pix.

[0023] In this embodiment, the display panel 2 is an active matrix type panel. Therefore, in a plan view, there is a signal (source) line SL extending in the second direction PY and a scan (gate) line GL extending in the first direction PX, and a switching element Tr is located at the intersection of the signal line SL and the scan line GL.

[0024] A thin-film transistor is used as the switching element Tr. Examples of thin-film transistors include bottom-gate transistors and top-gate transistors. A single-gate thin-film transistor is used as an example of the switching element Tr, but a double-gate transistor may also be used. One of the source and drain electrodes of the switching element Tr is connected to the signal line SL, the gate electrode is connected to the scan line GL, and the other of the source and drain electrodes is connected to one end of the capacitance of the polymer-dispersed liquid crystal (LC) described later. One end of the polymer-dispersed liquid crystal (LC) capacitance is connected to the switching element Tr via the pixel electrode PE, and the other end is connected to the common potential wiring COML via the common electrode CE. Furthermore, a retaining capacitance HC is generated between the pixel electrode PE and the retaining capacitance electrode IO, which is electrically connected to the common potential wiring COML. The common potential wiring COML is supplied by the common potential drive circuit 45.

[0025] The light-emitting unit 31 includes a first-color (e.g., red) light-emitting element 33R, a second-color (e.g., green) light-emitting element 33G, and a third-color (e.g., blue) light-emitting element 33B. The light source control unit 32 controls the first-color light-emitting element 33R, the second-color light-emitting element 33G, and the third-color light-emitting element 33B to emit light in a time-division manner based on the light source control signal LCSA. In this way, the first-color light-emitting element 33R, the second-color light-emitting element 33G, and the third-color light-emitting element 33B are driven in a field-sequential manner.

[0026] As shown in Figure 3, in the first subframe (first predetermined time) RF, the first color emitter 33R emits light during the first color emission period RON, and the pixels Pix selected within one vertical scanning period GateScan scatter light to display the image. In the entire display panel 2, if the pixels Pix selected within one vertical scanning period GateScan are supplied with gradation signals corresponding to the output gradation values ​​of each pixel Pix to the respective signal lines SL described above, then only the first color is lit during the first color emission period RON.

[0027] Next, in the second subframe (second predetermined time) GF, the second color emitter 33G emits light during the second color emission period GON, and the pixels Pix selected within one vertical scanning period GateScan scatter light to display. In the entire display panel 2, if the pixels Pix selected within one vertical scanning period GateScan are supplied with gradation signals corresponding to the output gradation values ​​of each pixel Pix to the respective signal lines SL mentioned above, then only the second color is lit during the second color emission period GON.

[0028] Furthermore, in the third subframe (third predetermined time) BF, the third color emitter 33B emits light during the third color emission period BON, and the pixels Pix selected within one vertical scan period GateScan scatter light to display the image. In the entire display panel 2, if the pixels Pix selected within one vertical scan period GateScan are supplied with gradation signals corresponding to the output gradation values ​​of each pixel Pix to the respective signal lines SL mentioned above, only the third color will be lit during the third color emission period BON.

[0029] The human eye has limitations in temporal resolution, resulting in afterimages; therefore, a composite image of three colors is perceived within a single frame (1F). In the field sequential method, color filters are unnecessary, and absorption losses due to color filters are reduced, resulting in high transmittance. In the color filter method, one pixel is created by dividing the pixel Pix into subpixels for the first, second, and third colors, whereas in the field sequential method, such subpixel division is not necessary. Furthermore, a fourth subframe may be included, emitting a fourth color different from the first, second, and third colors.

[0030] Figure 4 is an explanatory diagram showing the relationship between the voltage applied to the pixel electrode and the scattering state of the pixel. Figure 5 is a cross-sectional view showing an example of a cross-section of a display device. Figure 6 is a plan view showing the top view of the display device in Figure 1. Figure 7 is an enlarged cross-sectional view of the liquid crystal layer portion of Figure 5. Figure 8 is a cross-sectional view illustrating the non-scattering state in the liquid crystal layer. Figure 9 is a cross-sectional view illustrating the scattering state in the liquid crystal layer.

[0031] If a grayscale signal corresponding to the output grayscale value of each pixel Pix is ​​supplied to each signal line SL described above for each pixel Pix selected within one vertical scanning period (GateScan), the voltage applied to the pixel electrode PE changes according to the grayscale signal. When the voltage applied to the pixel electrode PE changes, the voltage between the pixel electrode PE and the common electrode CE changes. Then, as shown in Figure 4, the scattering state of the liquid crystal layer 50 for each pixel Pix is ​​controlled according to the voltage applied to the pixel electrode PE, and the scattering ratio within the pixel Pix changes.

[0032] As shown in Figure 4, when the voltage applied to the pixel electrode PE exceeds the saturation voltage Vsat, the change in the scattering rate within the pixel Pix becomes smaller. Therefore, the drive circuit 4 changes the voltage applied to the pixel electrode PE in accordance with the vertical drive signal VDS in the voltage range Vdr which is lower than the saturation voltage Vsat.

[0033] As shown in Figure 5, the display device 1 comprises a light-transmitting first substrate 25, a display panel 2, and a light-transmitting second substrate 27. A protective layer 75 is provided on one surface of the light-transmitting first substrate 25. A protective layer 76 is provided on one surface of the light-transmitting second substrate 27.

[0034] The display panel 2 comprises an array substrate 10, a counter substrate 20, and a liquid crystal layer 50. The counter substrate 20 faces the surface of the array substrate 10 in a direction perpendicular to it (the third direction PZ shown in Figure 1). The liquid crystal layer 50 is sealed with a polymer-dispersed liquid crystal, which will be described later, between the array substrate 10, the counter substrate 20, and the sealing portion 18.

[0035] As shown in Figures 5 and 6, the array substrate 10 comprises a first main surface 10A, a second main surface 10B, a first side surface 10C, a second side surface 10D, a third side surface 10E, and a fourth side surface 10F. The first main surface 10A and the second main surface 10B are parallel planes. The first side surface 10C and the second side surface 10D are also parallel planes. The third side surface 10E and the fourth side surface 10F are also parallel planes.

[0036] As shown in Figures 5 and 6, the opposing substrate 20 comprises a first main surface 20A, a second main surface 20B, a first side surface 20C, a second side surface 20D, a third side surface 20E, and a fourth side surface 20F. The first main surface 20A and the second main surface 20B are parallel planes. The first side surface 20C and the second side surface 20D are parallel planes. The third side surface 20E and the fourth side surface 20F are parallel planes.

[0037] As shown in Figures 5 and 6, the first substrate 25 comprises a first main surface 25A, a second main surface 25B, a first side surface 25C, a second side surface 25D, a third side surface 25E, and a fourth side surface 25F. The first main surface 25A and the second main surface 25B are parallel planes. The first side surface 25C and the second side surface 25D are parallel planes. The third side surface 25E and the fourth side surface 25F are parallel planes.

[0038] The first substrate 25 is bonded to the first main surface 20A of the opposing substrate 20 via an optical resin 23. The first substrate 25 is a protective substrate for the opposing substrate 20 and is formed of, for example, glass or a light-transmitting resin. When the first substrate 25 is formed of a glass substrate, it is also called a cover glass. When the first substrate 25 is formed of a light-transmitting resin, it may be flexible. In addition, the same substrate as the first substrate 25 may be bonded to the first main surface 10A of the array substrate 10 via an optical resin.

[0039] As shown in Figures 5 and 6, the second substrate 27 comprises a first main surface 27A, a second main surface 27B, a first side surface 27C, a second side surface 27D, a third side surface 27E, and a fourth side surface 27F. The first main surface 27A and the second main surface 27B are parallel planes. The first side surface 27C and the second side surface 27D are parallel planes. The third side surface 27E and the fourth side surface 27F are parallel planes.

[0040] The second substrate 27 is bonded to the first main surface 10A of the array substrate 10 via an optical resin 26. The second substrate 27 is a protective substrate for the array substrate 10 and is formed of, for example, glass or a light-transmitting resin. When the second substrate 27 is formed of a glass substrate, it is also called a cover glass. When the second substrate 27 is formed of a light-transmitting resin, it may be flexible.

[0041] As shown in Figures 5 and 6, the light source 3 faces the second side surface 25D of the first substrate 25. The light source 3 is sometimes called a side light source. As shown in Figure 5, the light source 3 irradiates the second side surface 25D of the first substrate 25 with light from the light source 3. The second side surface 25D of the first substrate 25 facing the light source 3 becomes the light incident surface. Alternatively, the light incident surface facing the light source 3 may be the second side surface 25D of the opposing substrate 20 or the second side surface 27D of the second substrate 27.

[0042] The light source 3 comprises a light-emitting section 31 and a light guide 33L. The light-emitting section 31 includes a first-color (e.g., red) light-emitting element 33R, a second-color (e.g., green) light-emitting element 33G, and a third-color (e.g., blue) light-emitting element 33B. The light guide 33L irradiates the second side surface 25D of the first substrate 25 with the light emitted by the first-color light-emitting element 33R, the second-color light-emitting element 33G, and the third-color light-emitting element 33B. The light guide 33L simultaneously receives light from multiple light-emitting sections 31, diffuses it internally, and emits it to the display panel 2. As a result, the distribution of light per unit area irradiated onto the second side surface 25D of the first substrate 25 is made uniform.

[0043] Furthermore, the light guide 33L is a single light guide 33L integrally formed from the third side surface 25E to the fourth side surface 25F. The light guide 33L may also be constructed by arranging multiple divided light guides from the third side surface 25E to the fourth side surface 25F. The light guide 33L may also be constructed by arranging multiple divided light guides from the third side surface 25E to the fourth side surface 25F and connecting adjacent light guides.

[0044] The light-emitting section 31 and the light guide 33L are fixed with adhesive or the like and assembled onto the support 33M to form a light source module. The support 33M is mounted so as to overlap the first main surface 25A of the first substrate 25 and is fixed to the first substrate 25 with adhesive or the like.

[0045] The wiring board 93 (flexible printed circuit board or PCB board) is equipped with an integrated circuit for the light source control unit 32, and the light source control unit 32 is connected to the light source 3 via the wiring board 93 (flexible printed circuit board or PCB board). The wiring board 93 is fixed to the support 33M with adhesive or the like.

[0046] As shown in Figure 5, the light emitted from the light source 3 propagates in a direction away from the second side surface 20D (second direction PY) while being reflected by either the first substrate 25, the array substrate 10, the opposing substrate 20, or the second substrate 27.

[0047] As shown in Figure 5, light from a light source propagating through the interior of the first substrate 25, the array substrate 10, the opposing substrate 20, or the second substrate 27 is scattered by a pixel Pix containing liquid crystal in a scattering state. When the incident angle of the scattered light becomes smaller than the critical angle, synchrotron radiation 68 and 68A are emitted to the outside from the first main surface 20A of the opposing substrate 20 (the first main surface 25A of the first substrate 25) and the first main surface 10A of the array substrate 10, respectively. The synchrotron radiation 68 and 68A emitted to the outside from the first main surface 20A of the opposing substrate 20 and the first main surface 10A of the array substrate 10 are observed by an observer.

[0048] Therefore, as shown in Figure 6, multiple light-emitting units 31 are arranged at a predetermined pitch in the region corresponding to the second direction PY of the active region AA.

[0049] As shown in Figure 6, the drive circuit 4 described above comprises multiple integrated circuits for the gate drive circuit 43 and multiple integrated circuits for the source drive circuit 44.

[0050] Below, Figures 7 to 9 will be used to explain polymer-dispersed liquid crystals in a scattering state and polymer-dispersed liquid crystals in a non-scattering state.

[0051] As shown in Figure 7, the array substrate 10 is provided with a first alignment film AL1. The opposing substrate 20 is provided with a second alignment film AL2. When the alignment films are subjected to alignment processing, for example, the orientation direction of the first alignment film AL1 is one side of the first direction PX, and the orientation direction of the second alignment film AL2 is directed toward the other side of the first direction PX. The first alignment film AL1 and the second alignment film AL2 may be, for example, vertical alignment films, or alignment films directed toward the first direction PX where the multiple light-emitting units 31 are arranged. The alignment processing is performed by rubbing processing or optical alignment processing.

[0052] The polymer-dispersed liquid crystal LC of the liquid crystal layer 50 shown in Figure 7 is encapsulated between the array substrate 10 and the opposing substrate 20. Next, with the monomer and liquid crystal aligned by the first alignment film AL1 and the second alignment film AL2, the monomer is polymerized by ultraviolet light or heat to form a three-dimensional mesh-like polymer network 51. This forms a liquid crystal layer 50 having reverse-mode polymer-dispersed liquid crystal LC in which liquid crystal molecules 52 are dispersed in the gaps of the mesh-like three-dimensional mesh-like polymer network 51.

[0053] Thus, the polymer-dispersed liquid crystal (LC) has a three-dimensional mesh-like polymer network 51 and liquid crystal molecules 52.

[0054] The orientation of the liquid crystal molecules 52 is controlled by the voltage difference between the pixel electrode PE and the common electrode CE. The orientation of the liquid crystal molecules 52 changes depending on the voltage applied to the pixel electrode PE. This change in the orientation of the liquid crystal molecules 52 changes the degree of light scattering as it passes through the pixel Pix.

[0055] For example, as shown in Figure 8, when no voltage is applied between the pixel electrode PE and the common electrode CE, the orientations of the optical axis Ax1 of the polymer network 51 and the optical axis Ax2 of the liquid crystal molecule 52 are approximately equal to each other. The optical axis Ax2 of the liquid crystal molecule 52 is parallel to the first direction PX (Figure 1) of the liquid crystal layer 50. Furthermore, the optical axis Ax1 of the polymer network 51 is parallel to the first direction PX of the liquid crystal layer 50 regardless of the presence or absence of voltage.

[0056] The ordinary refractive indices of the polymer network 51 and the liquid crystal molecules 52 are equal. When no voltage is applied between the pixel electrode PE and the common electrode CE, the refractive index difference between the polymer network 51 and the liquid crystal molecules 52 is almost zero in all directions. The liquid crystal layer 50 is in a non-scattering state and does not scatter light from the light source. The light from the light source propagates in the direction away from the light source 3 (light-emitting part 31). When the liquid crystal layer 50 is in a non-scattering state and does not scatter light from the light source, the background on the side of the first main surface 20A of the opposing substrate 20 is visible from the first main surface 10A of the array substrate 10, and the background on the side of the first main surface 10A of the array substrate 10 is visible from the first main surface 20A of the opposing substrate 20.

[0057] As shown in Figure 9, between the pixel electrode PE to which a voltage is applied and the common electrode CE, the optical axis Ax2 of the liquid crystal molecule 52 is tilted by the electric field generated between the pixel electrode PE and the common electrode CE. Since the optical axis Ax1 of the polymer network 51 does not change due to the electric field, the orientations of the optical axis Ax1 of the polymer network 51 and the optical axis Ax2 of the liquid crystal molecule 52 are different from each other. In a pixel Pix where the pixel electrode PE to which a voltage is applied is located, the light from the light source is scattered. As described above, a portion of the scattered light source is emitted to the outside from the first main surface 10A of the array substrate 10 or the first main surface 20A of the opposing substrate 20, and this light is observed by the observer.

[0058] In pixels Pix where no voltage is applied to the pixel electrode PE, the background on the side of the first main surface 20A of the opposing substrate 20 is visible from the first main surface 10A of the array substrate 10, and the background on the side of the first main surface 10A of the array substrate 10 is visible from the first main surface 20A of the opposing substrate 20. When the first input signal VS is input from the image output unit 91 of the display device 1 of this embodiment, a voltage is applied to the pixel electrode PE of the pixel Pix on which the image is displayed, and the image based on the third input signal VCSA is visible together with the background. In this way, when the polymer-dispersed liquid crystal LC is in a scattering state, an image is displayed in the display area.

[0059] In a pixel Pix where a voltage is applied to a pixel electrode PE, the image displayed by the light scattered from the light source and emitted to the outside is superimposed on the background and displayed. In other words, the display device 1 of this embodiment can display an image superimposed on the background by combining the synchrotron radiation 68 or synchrotron radiation 68A with the background.

[0060] In the GateScan vertical scan period shown in Figure 3, the potential of each written pixel electrode PE (see Figure 7) must be maintained during at least one of the emission periods following each GateScan: the first color emission period RON, the second color emission period GON, and the third color emission period BON. If the potential of each written pixel electrode PE (see Figure 7) cannot be maintained during at least one of the emission periods following each GateScan vertical scan period, such as flicker is likely to occur. In other words, in order to shorten the GateScan vertical scan period, which is the selection time for the scan lines, and to improve visibility in the so-called field sequential method, there is a need to make it easier to maintain the potential of each written pixel electrode PE (see Figure 7) during each of the emission periods following each of the first color emission period RON, the second color emission period GON, and the third color emission period BON.

[0061] Figure 10 is a plan view showing the scan lines, signal lines, and switching elements in a pixel. Figure 11 is a plan view showing the retention capacitance layer in a pixel. Figure 12 is a plan view showing the switching elements in a pixel. Figure 13 is a plan view showing the pixel electrodes in a pixel. Figure 14 is a plan view showing the light-shielding layer in a pixel. Figure 15 is a cross-sectional view of Figure 12 from XV-XV'. Figure 16 is a cross-sectional view of Figure 14 from XVI-XVI'. Figure 17 is a cross-sectional view of Figure 14 from XVII-XVII'.

[0062] As shown in Figures 1, 2, and 10, the array substrate 10 has a grid of multiple signal lines SL and multiple scan lines GL arranged in a planar configuration. In other words, one surface of the array substrate 10 has a plurality of signal lines SL arranged at intervals in the first direction PX, and a plurality of scan lines GL arranged at intervals in the second direction PY.

[0063] As shown in Figure 10, the region enclosed by adjacent scan lines GL and adjacent signal lines SL is a pixel Pix. Each pixel Pix is ​​provided with a pixel electrode PE and a switching element arrangement region SW for a switching element Tr (see Figure 2).

[0064] As shown in Figure 10, the scan lines GL are wiring made of metals such as molybdenum (Mo) and aluminum (Al), laminates thereof, or alloys thereof. The signal lines SL are wiring made of metals such as aluminum or alloys.

[0065] As shown in Figure 12, the switching element Tr comprises a semiconductor layer SC, a gate electrode GE integrated with the scan line GL, a source electrode SE integrated with the signal line SL, and a drain electrode DE. In this embodiment, the switching element Tr is a bottom-gate thin-film transistor. The source electrode SE and the drain electrode DE each extend along the first direction PX and are spaced apart and aligned along the second direction PY. The source electrode SE is in contact with one end of the semiconductor layer SC of the switching element Tr. The drain electrode DE is in contact with the other end of the semiconductor layer SC. The contact electrode DEA is connected to the drain electrode DE on the opposite side of the semiconductor layer SC in the second direction PY.

[0066] The semiconductor layer SC is, for example, an oxide semiconductor. The semiconductor layer SC may be polycrystalline silicon or amorphous silicon. Multiple semiconductor layers SC are arranged at intervals in the first direction PX. For example, four semiconductor layers SC are superimposed on the gate electrode GE and arranged at intervals along the first direction PX. Each of the multiple semiconductor layers SC is rectangular in shape with its longitudinal direction in the second direction PY. Furthermore, the semiconductor layers SC are provided so as not to extend beyond the gate electrode GE in a plan view.

[0067] As shown in Figure 12, the light source L emitted from the light source 3 (see Figure 5) is incident with the second direction PY as the incident direction. The incident direction is the direction from the second side surface 20D, which is closest to the light source 3 (see Figure 5), toward the first side surface 20C, which is opposite to the second side surface 20D. Each of the semiconductor layers SC of the switching element Tr has a first width Wx in the first direction PX, which intersects with the incident direction of light from the light source 3, which is smaller than the second width Wy in the second direction PY, which is parallel to the incident direction. As a result, the display device 1 of this embodiment is less affected by light leakage from the switching element Tr.

[0068] The contact electrode DEA at one end of the drain electrode DE is connected to the pixel electrode PE via connecting electrodes CN1 and CN3 (see Figure 15).

[0069] As shown in Figure 15, the array substrate 10 has a first translucent substrate 19 made of, for example, glass. The first translucent substrate 19 may be made of any resin, such as polyethylene terephthalate, as long as it is translucent.

[0070] As shown in Figure 15, a scanning line GL (see Figure 10) and a gate electrode GE are provided on the first translucent substrate 19.

[0071] As shown in Figure 15, a first insulating layer 11 (gate insulating layer) is also provided covering the scan line GL and the gate electrode GE. The first insulating layer 11 is formed of a transparent inorganic insulating material such as silicon nitride.

[0072] A semiconductor layer SC is laminated on the first insulating layer 11. The semiconductor layer SC has a first side surface S1 on the side closer to the incident direction and a second side surface S2 on the opposite side of the first side surface S1, which is further away from the incident direction. In a plan view, the first side surface S1 and the second side surface S2 correspond to the short side of the semiconductor layer SC.

[0073] A second insulating layer 12 is provided on the first insulating layer 11, covering the semiconductor layer SC. The second insulating layer 12 is formed of a transparent inorganic insulating material such as silicon nitride, similar to the first insulating layer 11. The second insulating layer 12 covers most of the semiconductor layer SC and the first insulating layer 11. A contact hole CH1 (opening) is provided in the region of the second insulating layer 12 that overlaps with the first side surface S1 of the semiconductor layer SC. A contact hole CH2 (opening) is provided in the region of the second insulating layer 12 that overlaps with the second side surface S2 of the semiconductor layer SC. As shown in Figure 12, the contact hole CH1 extends in the first direction PX and is provided across the first side surface S1 of multiple semiconductor layers SC. Similarly, the contact hole CH2 extends in the first direction PX and is provided across the second side surface S2 of multiple semiconductor layers SC.

[0074] As shown in Figure 15, a source electrode SE, a signal line SL, and a drain electrode DE are provided on the second insulating layer 12. The drain electrode DE is made of the same material as the signal line SL. The source electrode SE is connected to one end of the semiconductor layer SC through a contact hole CH1. More specifically, the source electrode SE covers the side surface of the contact hole CH1 formed in the second insulating layer 12, and also covers a portion of the upper surface and a first side surface S1 of the semiconductor layer SC located inside the contact hole CH1, and is in contact with the first insulating layer 11.

[0075] The drain electrode DE is connected to the other end of the semiconductor layer SC through the contact hole CH2. More specifically, the drain electrode DE covers the side surface of the contact hole CH2 formed in the second insulating layer 12, and also covers a portion of the upper surface and the second side surface S2 of the semiconductor layer SC located inside the contact hole CH2, and is in contact with the first insulating layer 11.

[0076] As shown in Figure 12, the source electrode SE extends in the first direction PX and is provided covering the first side surface S1 of the multiple semiconductor layers SC in the region overlapping with the contact hole CH1. Similarly, the drain electrode DE extends in the first direction PX and is provided covering the second side surface S2 of the multiple semiconductor layers SC in the region overlapping with the contact hole CH2.

[0077] With this configuration, the source electrode SE is provided covering the first side surface S1 located on the incident side of the semiconductor layer SC, thereby blocking the light source L incident on the first side surface S1 of the semiconductor layer SC. Furthermore, the drain electrode DE is provided covering the second side surface S2 of the semiconductor layer SC, thereby blocking the light incident on the second side surface S2 of the semiconductor layer SC. As a result, the display device 1 of this embodiment is less affected by light leakage from the switching element Tr.

[0078] Furthermore, the second insulating layer 12 covers the semiconductor layer SC and is provided between the source electrode SE and the drain electrode DE and the semiconductor layer SC. Therefore, in the process of patterning the source electrode SE (signal line SL) and the drain electrode DE by dry etching or the like, the semiconductor layer SC is covered by the second insulating layer 12 except for the areas where contact holes CH1 and CH2 are formed, thus suppressing damage to the semiconductor layer SC.

[0079] As shown in Figure 15, a third insulating layer 13 is provided on the signal line SL and the drain electrode DE. The third insulating layer 13 is formed of a transparent inorganic insulating material such as silicon nitride, similar to the first insulating layer 11.

[0080] The contact electrode DEA at one end of the drain electrode DE is located in a region that does not overlap with the aperture AP of the pixel Pix and is superimposed on the connecting electrode CN3. A contact hole CH3 is formed in the third insulating layer 13 interposed between the drain electrode DE and the connecting electrode CN3. The drain electrode DE is in contact with the connecting electrode CN3 at the contact hole CH3.

[0081] The connecting electrode CN1 is in contact with the connecting electrode CN3. This electrically connects the connecting electrode CN1 to the switching element Tr, and then electrically connects to the pixel electrode PE shown in Figure 13 through the contact hole CH4 formed in the fifth insulating layer 15. The connecting electrode CN1 is a translucent electrode made of the same material as the retaining capacitance electrode IO, which will be described later, while the drain electrode DE and the connecting electrode CN3 are made of metallic material.

[0082] A fourth insulating layer 14 is formed on the third insulating layer 13, covering a portion of the third insulating layer 13. The fourth insulating layer 14 is an organic insulating layer formed from a light-transmitting organic insulating material, such as acrylic resin. The fourth insulating layer 14 has a thicker film thickness compared to other insulating films formed from inorganic materials.

[0083] As shown in Figures 15, 16, and 17, there are regions where the fourth insulating layer 14 is present and regions where it is not. As shown in Figures 16 and 17, the regions where the fourth insulating layer 14 is present are above the scan line GL and above the signal line SL. The fourth insulating layer 14 forms a grid that covers the area above the scan line GL and signal line SL, along the scan line GL and signal line SL. Also, as shown in Figure 15, the regions where the fourth insulating layer 14 is present are above the semiconductor layer SC, that is, above the switching element Tr. Therefore, the switching element Tr, scan line GL, and signal line SL are relatively far from the retaining capacitance electrode IO, making them less susceptible to the influence of the common potential from the retaining capacitance electrode IO. Furthermore, in the array substrate 10, a region without the fourth insulating layer 14 is created in the region surrounded by the scan line GL and signal line SL, so a region is created where the thickness of the insulating layer is smaller than the thickness of the insulating layer overlapping the signal line SL and scan line GL in a plan view. In the region enclosed by the scan line GL and the signal line SL, the light transmittance is relatively higher and the light transmission is improved compared to the areas above the scan line GL and above the signal line SL.

[0084] As shown in Figure 15, a retaining capacitance electrode IO is provided on the fourth insulating layer 14. The retaining capacitance electrode IO is formed of a translucent conductive material such as ITO (Indium Tin Oxide). The retaining capacitance electrode IO is also called the third translucent electrode. As shown in Figure 11, the retaining capacitance electrode IO has a region IOX in which there is no translucent conductive material in the region surrounded by the scan line GL and the signal line SL. The retaining capacitance electrode IO is provided across multiple pixels Pix, spanning adjacent pixels Pix. In the retaining capacitance electrode IO, the region with translucent conductive material overlaps with the scan line GL or the signal line SL and extends to the adjacent pixel Pix.

[0085] The connecting electrode CN1 is spaced apart from the retaining capacitance electrode IO and is positioned on the third insulating layer 13 at an opening in the fourth insulating layer 14 or at an opening in the retaining capacitance electrode IO (region IOX (see Figure 11)). The retaining capacitance electrode IO and the connecting electrode CN1 are located in substantially the same layer and are formed of the same material. The connecting electrode CN1 is positioned on and in contact with the connecting electrode CN3.

[0086] As shown in Figure 15, a metal layer TM is provided on the fourth insulating layer 14 and on the retaining capacitance electrode IO. The conductive metal layer TM is a wiring of metals such as molybdenum (Mo) and aluminum (Al), laminates thereof, or alloys thereof. Since the metal layer TM has lower resistance than the retaining capacitance electrode IO, the variation in retaining capacitance for each pixel Pix is ​​reduced. In a plan view, the metal layer TM is provided in the region that overlaps with the signal line SL, scan line GL, and switching element Tr. As a result, the metal layer TM forms a grid, creating an opening surrounded by the metal layer TM. In this way, the metal layer TM becomes a power supply line that supplies the potential of the retaining capacitance.

[0087] The retention capacitance electrode IO is a grid that covers the area above the scan line GL and signal line SL, along the scan line GL and signal line SL. As a result, the retention capacitance HC between the pixel electrode PE and the electrode decreases in the region IOX where there is no translucent conductive material, so the retention capacitance HC is adjusted by the size of the region IOX where there is no translucent conductive material.

[0088] As shown in Figures 12 and 15, a switching element Tr is provided connected to the scan line GL and the signal line SL. At least the switching element Tr is covered with a fourth insulating layer 14, which is an organic insulating layer, and above the fourth insulating layer 14 is a metal layer TM with a larger area than the switching element Tr. This makes it possible to suppress optical leakage from the switching element Tr.

[0089] More specifically, the array substrate 10 includes a fourth insulating layer 14, which is an organic insulating layer covering at least the switching element Tr, and a metal layer TM superimposed on the fourth insulating layer 14, with a larger area than the switching element Tr. In the region surrounded by the scan line GL and the signal line SL, there is a region whose thickness is smaller than the thickness of the fourth insulating layer 14 that overlaps the scan line GL and the signal line SL in a plan view. As a result, a slope is created in which the thickness of the fourth insulating layer 14 changes on the side closer to the light source 3 than the switching element Tr in a plan view.

[0090] As shown in Figures 13, 15, 16, and 17, a portion of the pixel electrode PE overlaps the slope where the thickness of the fourth insulating layer 14 changes. This stabilizes the behavior of liquid crystal molecules between adjacent pixels Pix.

[0091] As shown in Figure 16, in a plan view, the width of the metal layer TM overlapping the signal line SL is greater than the width of the signal line SL. This suppresses the emission of reflected light from the display panel 2 that is reflected at the edge of the signal line SL. Here, the width of the metal layer TM and the width of the signal line SL are lengths in the direction intersecting the direction in which the signal line SL extends.

[0092] Furthermore, as shown in Figure 17, the width of the metal layer TM overlapping the scan line GL is greater than the width of the scan line GL. Here, the width of the metal layer TM and the width of the scan line GL are the lengths in the direction intersecting the direction in which the scan line GL extends.

[0093] As shown in Figure 15, a fifth insulating layer 15 is provided on the retaining capacitance electrode IO and the metal layer TM. The fifth insulating layer 15 is an inorganic insulating layer formed of a transparent inorganic insulating material such as silicon nitride.

[0094] As shown in Figure 15, a pixel electrode PE is provided on the fifth insulating layer 15. The pixel electrode PE is formed of a translucent conductive material such as ITO. The pixel electrode PE is electrically connected to the contact electrode DEA via a contact hole CH4 provided in the fifth insulating layer 15 and a contact hole CH3 provided in the third insulating layer 13. As shown in Figure 13, the pixel electrode PE is partitioned for each pixel Pix. A first orientation film AL1 is provided on top of the pixel electrode PE.

[0095] As shown in Figure 16, in the display device 1 of the first embodiment, a light-shielding layer GS, which is in the same layer as the scan line GL, extends along the signal line SL and is provided in a position that overlaps with a part of the signal line SL. The light-shielding layer GS is made of the same material as the scan line GL. The light-shielding layer GS is not provided in the portion where the scan line GL and the signal line SL intersect in a plan view.

[0096] As shown in Figure 10, the light-shielding layer GS and the signal line SL are electrically connected by a contact hole CHG. This reduces the wiring resistance of the light-shielding layer GS and the signal line SL compared to the wiring resistance of the signal line SL alone. As a result, the delay of the grayscale signal supplied to the signal line SL is suppressed. Note that the contact hole CHG may be absent, and the light-shielding layer GS and the signal line SL may not be connected.

[0097] As shown in Figure 16, the light-shielding layer GS is provided on the side opposite to the metal layer TM with respect to the signal line SL. The width of the light-shielding layer GS is greater than the width of the signal line SL and less than the width of the metal layer TM. The widths of the light-shielding layer GS, the metal layer TM, and the signal line SL are the lengths in the direction intersecting the direction in which the signal line SL extends. In this way, since the light-shielding layer GS is wider than the signal line SL, it suppresses the emission of reflected light reflected from the edge of the signal line SL from the display panel 2. As a result, the visibility of the image in the display device 1 is improved.

[0098] As shown in Figure 15, the opposing substrate 20 has a second translucent substrate 29 made of, for example, glass. The second translucent substrate 29 may be made of any resin, such as polyethylene terephthalate, as long as it is translucent.

[0099] As shown in Figures 14 and 15, a light-shielding layer LS is provided on the opposing substrate 20. The light-shielding layer LS is provided in the region that overlaps with the signal line SL, scan line GL, and switching element Tr in a plan view. The light-shielding layer LS is made of a black resin or metal material.

[0100] As shown in Figures 14, 15, 16, and 17, the light-shielding layer LS has a wider width than the metal layer TM. This suppresses the emission of reflected light from the display panel 2 that is reflected at the edges of the signal line SL, scan line GL, and metal layer TM. As a result, the visibility of the image in the display device 1 is improved.

[0101] A common electrode CE is provided on the second main surface 20B of the second translucent substrate 29, covering a light-shielding layer LS. The common electrode CE is formed of a translucent conductive material such as ITO. A second orientation film AL2 is provided on the surface of the common electrode CE facing the pixel electrode PE.

[0102] As shown in Figures 16 and 17, the display device 1 of the first embodiment has a protective film 21 on the opposing substrate 20. Note that the protective film 21 is not shown in Figure 15. The protective film 21 is formed of an inorganic insulating material such as silicon nitride or silicon oxide, which has insulating and light-transmitting properties, and covers the array substrate 10 side of the common electrode CE. A second orientation film AL2 is provided on the array substrate 10 side of the protective film 21.

[0103] The protective film 21 is formed in a position that overlaps the fourth insulating layer 14. In the region that overlaps the opening AP, the common electrode CE and the second orientation film AL are directly laminated without the protective film 21 in between. As a result, the planar shape of the protective film 21 becomes lattice-like, and a non-overlapping region NOI of the protective film 21 is created. Furthermore, the protective film 21 is not formed on the opening AP. However, the protective film 21 may be omitted.

[0104] As described above, the display device 1 of this embodiment comprises an array substrate 10, a counter substrate 20, a liquid crystal layer 50 between the array substrate 10 and the counter substrate 20, and a light source 3 arranged so that light enters the side surface of the array substrate 10 or the side surface of the counter substrate 20. The array substrate 10 has a plurality of signal lines SL arranged at intervals in a first direction PX, a plurality of scan lines GL arranged at intervals in a second direction PY, and switching elements Tr connected to the scan lines GL and the signal lines SL. The switching element Tr has a semiconductor layer SC having a first side surface S1 on the side closer to the incident direction of light from the light source 3, and a second side surface S2 on the opposite side of the first side surface S1. The semiconductor layer SC has a first width Wx in the direction intersecting the incident direction that is smaller than the second width Wy in the direction parallel to the incident direction. The source electrode SE connected to the signal line SL covers the first side surface S1 of the semiconductor layer SC.

[0105] As a result, in the display device 1, the first width Wx of the semiconductor layer SC of the switching element Tr in the direction intersecting the incident direction is smaller than the second width Wy, thus suppressing the penetration of light into the semiconductor layer SC. Furthermore, since the source electrode SE is provided covering the first side surface S1 of the semiconductor layer SC, it effectively blocks the light source L incident on the first side surface S1 of the semiconductor layer SC. Therefore, the display device 1 of this embodiment can reduce light leakage from the switching element Tr.

[0106] (First variation) Figure 18 is a cross-sectional view showing a switching element according to the first modified example. As shown in Figure 18, in the first modified example, a step is formed in the first insulating layer 11 on the side of the semiconductor layer SC that is closer to the incident direction (second direction PY side) than the first side surface S1. That is, the upper surface of the first insulating layer 11 has a first upper surface 11a on which the semiconductor layer SC is provided, and a second upper surface 11b that is provided in the third direction PZ and is closer to the first translucent substrate 19 than the first upper surface 11a.

[0107] The source electrode SE covers a portion of the upper surface and the first side surface S1 of the semiconductor layer SC in the region overlapping with the contact hole CH1 formed in the second insulating layer 12, and also covers the stepped portion of the first insulating layer 11. More specifically, the source electrode SE is in contact with a portion of the first upper surface 11a and a portion of the second upper surface 11b of the first insulating layer 11 in the region overlapping with the contact hole CH1. As a result, in the third direction PZ, the source electrode SE is provided to a position closer to the first translucent substrate 19 than to the lower surface of the semiconductor layer SC, and covers the first side surface S1 of the semiconductor layer SC. As a result, in the first modified example, the source electrode SE effectively blocks the light source L incident on the first side surface S1 of the semiconductor layer SC.

[0108] The stepped portion of the first insulating layer 11 can be formed by removing a part of the first insulating layer 11 by etching or the like. Alternatively, the stepped portion of the first insulating layer 11 may be formed following the side surface of the gate electrode GE by arranging the gate electrode GE and the contact hole CH1 such that the side surface of the gate electrode GE is located in a region that overlaps with the contact hole CH1.

[0109] (Second Embodiment) Figure 19 is a plan view showing the switching elements of the display device according to the second embodiment. Figure 20 is a cross-sectional view taken along the line XX-XX' in Figure 19.

[0110] As shown in Figures 19 and 20, in the display device 1A according to the second embodiment, the switching element Tr has an auxiliary gate electrode AG. The auxiliary gate electrode AG is superimposed on the gate electrode GE and the semiconductor layer SC. The semiconductor layer SC is located in the third direction PZ between the gate electrode GE and the auxiliary gate electrode AG. The auxiliary gate electrode AG is further superimposed on the scan line GL.

[0111] As shown in Figure 20, the auxiliary gate electrode AG is provided on the third insulating layer 13. The auxiliary gate electrode AG and the semiconductor layer SC face each other in the third direction PZ via the second insulating layer 12 and the third insulating layer 13. The auxiliary gate electrode AG also extends to the side of the semiconductor layer SC closer to the incident direction (the second direction PY side) than the first side surface S1. On the first side surface S1 side of the semiconductor layer SC, the auxiliary gate electrode AG is electrically connected to the gate electrode GE through contact holes CH5 provided in the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13. As a result, the auxiliary gate electrode AG is electrically connected to the scan line GL, just like the gate electrode GE. Consequently, the gate electrode GE and the auxiliary gate electrode AG are at the same potential as the scan line GL.

[0112] In the second embodiment, in addition to the source electrode SE, an auxiliary gate electrode AG is also provided covering the first side surface S1 of the semiconductor layer SC. As a result, the source electrode SE and the auxiliary gate electrode AG block the light source L incident on the first side surface S1 of the semiconductor layer SC.

[0113] Note that the connection configuration between the auxiliary gate electrode AG and the gate electrode GE shown in Figures 19 and 20 is merely schematic and can be modified as appropriate. For example, the number of contact holes CH5 is not limited to four, but may be three or fewer, or five or more. Also, the contact holes CH5 are not limited to a configuration that penetrates the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13, and connecting electrodes may be provided between each insulating layer as needed.

[0114] (Second variation) Figure 21 is a plan view showing a switching element according to a second modified example. Figure 22 is a cross-sectional view taken along line XXII-XXII' in Figure 21. In the second embodiment described above, the auxiliary gate electrode AG is electrically connected to the gate electrode GE on the first side surface S1 side of the semiconductor layer SC, that is, the side closer to the incident direction. However, the connection configuration between the auxiliary gate electrode AG and the gate electrode GE is not limited to this.

[0115] As shown in Figures 21 and 22, in the display device 1B according to the second modified example, the auxiliary gate electrode AG is electrically connected to the gate electrode GE on at least one of the third side surface S3 and the fourth side surface S4 of the semiconductor layer SC in a direction intersecting the incident direction.

[0116] More specifically, each of the multiple semiconductor layers SC aligned in the first direction PX has a third side surface S3 and a fourth side surface S4 located between the first side surface S1 and the second side surface S2. As shown in Figure 21, in the direction intersecting the incident direction (first direction PX), a contact hole CH6 is provided between the multiple semiconductor layers SC aligned in the first direction PX and the signal line SL. In addition, a contact hole CH7 is provided on the side of the multiple semiconductor layers SC aligned in the first direction PX that is opposite to the contact hole CH6.

[0117] As shown in Figure 22, contact holes CH6 and CH7 penetrate the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13, respectively. As a result, the auxiliary gate electrode AG is electrically connected to the gate electrode GE through contact hole CH6 on the third side surface S3 side of the multiple semiconductor layers SC. The auxiliary gate electrode AG is electrically connected to the gate electrode GE through contact hole CH7 on the fourth side surface S4 side of the multiple semiconductor layers SC.

[0118] The auxiliary gate electrode AG is provided to cover the third side surface S3 and the fourth side surface S4 of the multiple semiconductor layers SC. More specifically, the auxiliary gate electrode AG is provided to cover the multiple semiconductor layers SC aligned in the first direction PX. The auxiliary gate electrode AG is provided to cover the fourth side surface S4 of the semiconductor layer SC located on one side of the first direction PX (right side in Figure 22) among the multiple semiconductor layers SC. Furthermore, the auxiliary gate electrode AG is provided to cover the third side surface S3 of the semiconductor layer SC located on the other side of the first direction PX (left side in Figure 22) among the multiple semiconductor layers SC. As a result, the auxiliary gate electrode AG blocks the light source L incident on the third side surface S3 and the fourth side surface S4 of the multiple semiconductor layers SC.

[0119] (Third variation) Figure 23 is a plan view showing a switching element according to a third modified example. As shown in Figure 23, the display device 1C according to the third modified example has a gate connection electrode GCN. The gate connection electrode GCN is provided on a first translucent substrate 19 in the same layer as the gate electrode GE, and is positioned with a gap between it and the gate electrode GE in the first direction PX. The gate connection electrode GCN also extends along the second direction PY and is connected to the scan line GL on the same side as the gate electrode GE.

[0120] The auxiliary gate electrode AG extends in the first direction PX from the region overlapping with the multiple semiconductor layers SC to the region overlapping with the gate connection electrode GCN. On the first direction PX side of the multiple semiconductor layers SC, the auxiliary gate electrode AG is electrically connected to the gate connection electrode GCN through contact holes CH8 provided in the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13. As a result, the auxiliary gate electrode AG is electrically connected to the scan line GL, similar to the gate electrode GE.

[0121] In the third modification, the auxiliary gate electrode AG is connected to the gate connection electrode GCN at a position that does not overlap with the gate electrode GE and the scan line GL. Therefore, in the third modification, the degree of freedom of connection between the auxiliary gate electrode AG and the scan line GL can be improved.

[0122] While preferred embodiments of this disclosure have been described above, this disclosure is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of this disclosure. Any modifications made without departing from the spirit of this disclosure will naturally fall within the technical scope of this disclosure. At least one of various omissions, substitutions, and modifications of components can be made without departing from the gist of each embodiment and each modification described above. [Explanation of symbols]

[0123] 1, 1A, 1B, 1C display device 2 Display Panel 3 light source 4. Drive Circuit 10 Array substrates 11. First insulating layer 12. Second insulating layer 13. Third insulating layer 14. Fourth insulating layer 15. Fifth insulating layer 19 First translucent base material 20 Opposing substrate 29 Second translucent base material 31 Light-emitting part 50 liquid crystal layers DE drain electrode GE Terminal GL scan lines LC Polymer dispersed liquid crystal PE pixel electrode SC semiconductor layer S1 1st side S2 2nd side S3 3rd side S4 4th side SE Source Electrode SL signal line Tr switching element

Claims

1. Array substrate and Opposite substrate and, The liquid crystal layer between the array substrate and the opposing substrate, The array includes a light source positioned so as to illuminate the side surface of the array substrate or the side surface of the opposing substrate, The aforementioned array substrate is Multiple signal lines arranged at intervals in the first direction, Multiple scan lines arranged at intervals in the second direction, It has a switching element connected to the scan line and the signal line, The switching element has a semiconductor layer having a first side surface on the side closer to the direction of incidence of light from the light source, and a second side surface on the opposite side to the first side. The semiconductor layer has a first width in a direction intersecting the incident direction that is smaller than the second width in a direction parallel to the incident direction. The source electrode connected to the signal line covers the first side surface of the semiconductor layer. Display device.

2. It has a drain electrode that connects the semiconductor layer and the pixel electrode, The drain electrode covers the second side surface of the semiconductor layer. The display device according to claim 1.

3. The insulating layer covers the semiconductor layer and has openings provided at positions that overlap with the first and second sides of the semiconductor layer, respectively. The source electrode covers the side surface forming the opening of the insulating layer and the first side surface of the semiconductor layer. The display device according to claim 1.

4. A gate electrode connected to the scan line, The gate electrode and the semiconductor layer are provided with a gate insulating layer, A stepped portion is formed in the gate insulating layer on the side of the first side surface of the semiconductor layer that is closer to the incident direction, The source electrode covers the first side surface of the semiconductor layer and the stepped portion of the gate insulating layer. The display device according to claim 1.

5. The gate electrode and auxiliary gate electrode connected to the scan line are provided, In a direction perpendicular to the array substrate, the semiconductor layer is arranged between the gate electrode and the auxiliary gate electrode. The auxiliary gate electrode is electrically connected to the gate electrode on the incident side of the first side surface of the semiconductor layer, The auxiliary gate electrode covers the first side surface of the semiconductor layer. The display device according to claim 1.

6. The gate electrode and auxiliary gate electrode are connected to the scan line. In a direction perpendicular to the array substrate, the semiconductor layer is arranged between the gate electrode and the auxiliary gate electrode. The semiconductor layer has a third side and a fourth side located between the first side and the second side, The auxiliary gate electrode is electrically connected to the gate electrode on at least one of the third and fourth sides of the semiconductor layer. The auxiliary gate electrode covers at least one of the third and fourth sides of the semiconductor layer. The display device according to claim 1.

7. The liquid crystal layer includes polymer-dispersed liquid crystal, The background of the opposing substrate is visible from the array substrate, and the background of the array substrate is visible from the opposing substrate. The display device according to any one of claims 1 to 6.

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