Photonic integrated circuits, and optoelectronic systems including photonic integrated circuits

Abstract

During the use of photonic integrated circuits, an electrical grounding shield minimizes or prevents the overlap between the RF signal and the electric fields generated by the doped epitaxial semiconductor layer. [Solution] The present invention relates to a photonic integrated circuit (1) comprising a bond pad (19), an RF component (20), a first layer stack (4) having a doped epitaxial semiconductor layer (5), a second layer stack (8) associated with the first layer stack, and a first set of long tracks (18a, 18b) of conductive material associated with the second layer stack and capable of transmitting RF signals between the bond pad and the RF component during use of the photonic integrated circuit (1). The second layer stack includes an electrical ground shield (12) sandwiched between a first dielectric layer (9) and a second dielectric layer (15).

Description

[Technical Field]

[0001] This invention relates to a photonic integrated circuit. The invention also relates to an optoelectronic system comprising a photonic integrated circuit according to the present invention. The optoelectronic system according to the present invention may, but is not limited to, applications such as telecommunications, light detection and ranging (LIDAR), or sensor applications. [Background technology]

[0002] The ongoing development of new and improved optoelectronic systems, which may, but are not limited to, applications such as telecommunications, optical detection and ranging (lidar), or sensor applications, is primarily driven by the optimization of module bandwidth (bitrate) to meet market demand, and by the increasing complexity of photonic chips to reduce costs and utilize smaller module form factors. As a result, interesting challenges arise in designing required radio frequency (RF) photonic integrated circuits and associated optoelectronic systems. For example, in the case of a typical traveling wave modulator system, it is not enough to simply design the RF modulator, the electronics for the driver circuit, and the RF termination. To maximize the performance of the entire traveling wave modulator system, it is also important to carefully consider the impedance of on-chip electrical interconnects or long metal tracks used as feed lines. Failure to consider such factors will result in electrical reflections and losses that hinder the achievement of the desired maximum performance of the entire traveling wave modulator system.

[0003] In the case of photonic integrated circuits, on-chip electrical interconnects or feed lines typically consist of long (elongated) metal tracks positioned along the surface of the photonic integrated circuit for interconnecting adhesive pads (bond pads) and RF components. Unlike off-chip electrical interconnects, which are often designed for low-loss printed circuit boards, on-chip electrical interconnects or feed lines must be designed to account for the adverse effects that doped semiconductor layers placed beneath the on-chip electrical interconnect have on the RF signals transmitted by the on-chip electrical interconnect during use, due to the overlap of the RF signals and the electric fields generated by the doped semiconductor layers. As a result, on-chip electrical interconnects or feed lines for high-bandwidth photonic integrated circuits are preferably kept as short as possible to reduce electrical insertion losses.

[0004] This design method may work for photonic integrated circuits with simple layouts, but it becomes impractical for photonic integrated circuits with increasingly complex layouts. For example, in more complex photonic integrated circuits, on-chip electrical interconnects or feed lines may have to be implemented as long metal tracks as a result of constraints on the location of the electrical interface around the photonic integrated circuit with respect to the electrical interface and the RF components that need to be electrically connected. Furthermore, due to constraints on optical routing, on-chip electrical interconnects or feed lines may need to cross on-chip optical waveguides. This can lead to increased loss of RF signals transmitted by the on-chip electrical interconnects during use of the photonic integrated circuit.

[0005] Typical methods to mitigate the aforementioned problems associated with the design of on-chip electrical interconnects or feed lines for photonic integrated circuits with increasingly complex layouts include depositing thick electrical insulating polymer layers, removing doped semiconductor layers, and applying air bridges.

[0006] Insertion loss can be reduced by depositing a thick layer of electrically insulating polymer with a low dielectric constant between on-chip electrical interconnects or feed lines and the doped semiconductor layer of the photonic integrated circuit beneath them. However, a disadvantage of this method is that there is a limited number of suitable polymers that can withstand semiconductor manufacturing processes, such as dry etching, wet etching, temperature ranges, etc. As a result, the range of suitable dielectric constants is limited. Another disadvantage is that if the polymer layer is extremely thick, the topology that the on-chip electrical interconnect or feed line must traverse to enable the establishment of electrical contacts with the underlying photonic elements increases. Yet another disadvantage of thick polymer layers is that they can induce tension in the photonic integrated circuit. The aforementioned disadvantages lead to yield and reliability challenges for the photonic integrated circuit and the associated optoelectronic systems in which the photonic integrated circuit is applied. The aforementioned disadvantages of applying thick polymer layers become increasingly pronounced as the feed line length increases, as the surface area of ​​the feed line increases and the adverse effects increase.

[0007] The doped semiconductor layer beneath on-chip electrical interconnects or feed lines can be removed by etching trenches in the doped semiconductor layer that provide access to the underlying semi-insulating substrate of the photonic integrated circuit. While this method can reduce the aforementioned loss to RF signals transmitted by the on-chip electrical interconnects during use of the photonic integrated circuit, it introduces manufacturing problems. For example, a disadvantage of this method is that providing large trenches can negatively impact etching loading between processes. Additionally, providing large trenches can lead to resist pooling, which can negatively affect lithography resolution. Removing the doped semiconductor layer is not an option in areas of the photonic integrated circuit where on-chip electrical interconnects or feed lines need to cross on-chip optical waveguides.

[0008] To enable on-chip electrical interconnects or feed lines to cross on-chip optical waveguides, at least a portion of the on-chip electrical interconnects or feed lines crossing the on-chip optical waveguides may be arranged as an air bridge, i.e., a floating conductive structure. A disadvantage associated with air bridges is that, for their manufacture, the electrically insulating sacrificial support material initially placed beneath, for example, at least a portion of the on-chip electrical interconnects that need to cross the on-chip optical waveguides must be removed in order to obtain the at least partially floating on-chip electrical interconnects or feed lines called air bridges. Another disadvantage associated with air bridges is that, due to the structural constraints of air bridges, the distance that can be bridged is extremely short. Yet another disadvantage of the application of air bridges is that, for example, due to damage to the air bridge during the removal of the electrically insulating sacrificial support material, air bridges can cause yield and reliability problems. [Overview of the project] [Problems that the invention aims to solve]

[0009] In light of the above, it is clear that each of the typical methods for mitigating the aforementioned problems associated with the design and implementation of on-chip electrical interconnects or feed lines for photonic integrated circuits with increasingly complex layouts is advantageous in specific situations and therefore does not provide a so-called "universal solution." In addition, these typical methods can cause yield and reliability problems in the photonic integrated circuits to which they are applied. Therefore, there is a need to provide photonic integrated circuits that include structural features capable of proactively avoiding or at least mitigating the aforementioned and / or other disadvantages associated with the design and implementation of on-chip electrical interconnects or feed lines in increasingly complex high-bandwidth photonic integrated circuits.

[0010] An object of the present invention is to provide a photonic integrated circuit that includes structural features capable of proactively avoiding or at least mitigating at least one of the aforementioned and / or other disadvantages associated with the design and implementation of on-chip electrical interconnects or feed lines in increasingly complex high-bandwidth photonic integrated circuits.

[0011] Another object of the present invention is to provide an optoelectronic system including a photonic integrated circuit according to the present invention. The optoelectronic system according to the present invention may, but is not limited to, be used in applications such as telecommunications, lidar, or sensors.

[0012] Aspects of the present invention are described in the appended independent and dependent claims. Features of the dependent claims may be combined with features of the independent claims as appropriate, not only as expressly described in those claims. Furthermore, all features may be replaced by other technically equivalent features. [Means for solving the problem]

[0013] At least one of the above objectives is a photonic integrated circuit, An InP-based substrate having a first surface, A first layer stack comprising a doped epitaxial semiconductor layer, configured and arranged to provide optical functionality during use of a photonic integrated circuit, A second surface associated with the first surface of the InP base substrate, and A third surface positioned so as not to be related to the second surface (so as to face away from the second surface), A first layer stack including, and A second layer stack configured and arranged to provide electrical functionality during the use of a photonic integrated circuit, A fourth surface associated with the third surface of the first layer stack, and A fifth surface positioned so as not to be related to the fourth surface, A first dielectric layer having, A sixth surface relating to the fifth surface of the first dielectric layer, and A seventh surface positioned so as not to be related to the sixth surface, An electrical grounding shield having, The eighth surface relating to the seventh surface of the electrical earth shield, and A ninth surface positioned so as not to be related to the eighth surface, A second dielectric layer having, A second layer stack including, A first set of long (elongated) tracks of conductive material associated with the ninth surface of the second dielectric layer of the second layer stack, the first set configured and arranged to transmit RF signals during use of a photonic integrated circuit, and It includes at least one adhesive pad (bond pad) and at least one RF component, which are electrically related to each other via a first set of long tracks of conductive material, The first dielectric layer of the second layer stack is configured and positioned to provide DC (direct current) electrical isolation between the electrical ground shield and the first layer stack during use of the photonic integrated circuit, and the electrical ground shield is configured and positioned to minimize or prevent the overlap between the RF signal and the electric field generated by the doped epitaxial semiconductor layer of the first layer stack during use of the photonic integrated circuit, as achieved by the photonic integrated circuit.

[0014] Thus, the photonic integrated circuit according to the present invention includes an on-chip electrical interconnect or feed line that is implemented using a shielded on-chip electrical interconnect or feed line method. From the above-described embodiments of the photonic integrated circuit according to the present invention, it should be noted that the long tracks of a first set of long tracks of conductive material that electrically interconnect at least one adhesive pad and at least one RF component of the photonic integrated circuit should be interpreted as an on-chip electrical interconnect or feed line.

[0015] The shielded on-chip electrical interconnect or feed line method applied to photonic integrated circuits according to the present invention minimizes or prevents the overlap between the doped epitaxial semiconductor layer of the photonic integrated circuit and the electric field of the RF signal transmitted by the on-chip electrical interconnect or feed line during use of the photonic integrated circuit, without requiring the application of at least one of the aforementioned dividing insulating trenches, unrealistically thick polymer layers, and fragile air bridges. The shielded on-chip electrical interconnect or feed line method enables low-loss on-chip electrical interconnects or feed lines with desirable impedance in lengths ranging from 0.5 mm to 5 mm for use in photonic integrated circuits with increasingly complex layouts. Long shielded on-chip electrical interconnects or feed lines can be routed on photonic components such as on-chip optical waveguides without any performance loss. It should be noted that the shielded on-chip electrical interconnects or feed lines of the photonic integrated circuit according to the present invention are suitable for application to any type of RF component, such as Mach-Zehnder modulators (MZMs), field absorption modulators (EAMs), and RF photodiodes (RF PDs).

[0016] The conductive material used for the long tracks of the first set of long tracks can be any type of conductive material having any suitable composition and dimensions as long as a high-quality RF signal can be transmitted between the adhesive pads of the photonic integrated circuit and the RF components during the use of the photonic integrated circuit. It should be noted that the composition and dimensions of the long tracks of the first set of long tracks of the conductive material are determined by the desired electrical impedance of the on-chip electrical interconnects or feedlines and the tolerances in the manufacturing process. In a practical example, the long tracks of the first set of long tracks are manufactured using electroplated gold as the conductive material. The electroplated gold tracks of the first set of long tracks can have a first width (W1) of 10 μm and a first thickness (T1) of 3 μm when viewed in a direction parallel to the InP-based substrate to achieve an on-chip electrical interconnect or feedline with an impedance of 55 ohms. It should be noted that any other dimensions and compositions of the conductive material can be assumed according to the specific technical requirements of the photonic integrated circuit. It should be noted that the shielding performance of the electrical ground shield is not affected by the dimensions and / or composition of the long tracks of the first set of long tracks of the conductive material. The electrical ground shield can have a second thickness (T2) when viewed in a direction orthogonal to the InP-based substrate. The second thickness (T2) can be within the range of 50 nm to 4 μm. The disadvantage of an electrical ground shield having a second thickness (T2) exceeding 4 μm is that topological and / or reliability problems can occur without any increase in performance. The disadvantage of an electrical ground shield having a second thickness (T2) less than 50 nm is that the performance is impaired by too high resistivity.

[0017] It should be noted that the degree of coupling between the electrical ground shield and the electric field associated with the RF signal transmitted by the first set of long tracks of conductive material during use of the photonic integrated circuit may be influenced by the composition of the second dielectric layer and its third thickness (T3) as viewed in the direction perpendicular to the InP base substrate, in the arrangement of the electrical ground shield, second dielectric layer, and long tracks of the first set of long tracks of conductive material according to the above-described embodiment of the photonic integrated circuit according to the present invention. For example, if the long tracks of the first set of long tracks of conductive material have a first thickness (T1) of, for example, 3 μm and the second dielectric layer contains benzocyclobutene (BCB) with a third thickness (T3) of, for example, 3 μm, the electric field associated with the RF signal transmitted by the first set of long tracks of conductive material during use of the photonic integrated circuit may be considered to be strongly coupled to the electrical ground shield. In addition, it should be noted that the composition of the second dielectric layer and its third thickness (T3) may affect the impedance of the on-chip electrical interconnect or feed lines. Therefore, the composition and third thickness (T3) of the second dielectric layer must be carefully selected and / or controlled. The above example of a second dielectric layer containing benzocyclobutene (BCB) and having a third thickness (T3) of 3 μm can be used to achieve an on-chip electrical interconnect or feed wire with an impedance of 55 ohms. It will be evident that the value for the impedance of the on-chip electrical interconnect or feed wire depends on the actual use case of the photonic integrated circuit 1, and therefore the composition and dimensions of the second dielectric layer also depend on the actual use case of the photonic integrated circuit.

[0018] As described above, during the use of the photonic integrated circuit, the first dielectric layer provides electrical insulation for DC between the first layer stack including the electrical ground shield and the doped epitaxial semiconductor layer. The first dielectric layer need only have a fourth thickness, for example 20 nm, when viewed in a direction orthogonal to the InP-based substrate, but for planarization, it is advantageous for the first dielectric layer to have a fourth thickness (T4) of, for example, 3 μm. As such, the first dielectric layer may also have a planarization function that can improve the yield and reliability of the photonic integrated circuit.

[0019] Based on all of the above, it is clear that the photonic integrated circuit according to the invention, including an on-chip electrical interconnect or feedline implemented according to the method of shielded on-chip electrical interconnects or feedlines, anticipates and avoids the above-mentioned problems associated with the implementation of on-chip electrical interconnects or feedlines in a photonic integrated circuit having an increasingly complex layout. In particular, it is understood that the method of shielded on-chip electrical interconnects or feedlines can facilitate the processing of the photonic integrated circuit. In addition, the method of shielded on-chip electrical interconnects or feedlines provides a universal solution for the above-mentioned specific situations, such as on-chip electrical interconnects that need to be disposed on, for example, a doped epitaxial semiconductor layer and / or cross on-chip optical waveguides.

[0020] In an embodiment of the photonic integrated circuit according to the invention, the electrical ground shield of the second layer stack is configured as a continuous sheet of conductive material.

[0021] A continuous sheet of conductive material is the simplest implementation of an electrical grounding shield according to the present invention, providing desired electrical shielding for long tracks of conductive material from a first set of long tracks of conductive material from a doped epitaxial semiconductor layer of a first layer stack of a photonic integrated circuit, i.e., on-chip electrical interconnects or feed lines. However, the application of conductive material constituting an electrical grounding shield as a continuous sheet can lead to reliability issues. In particular, if the continuous sheet has an area that covers most or all of the underlying layer, the incorporation of material emitted from the underlying layer beneath the continuous sheet can lead to failure points that sacrifice the yield and reliability of the photonic integrated circuit.

[0022] It should be noted that, as long as the conductive material can achieve electromagnetic shielding, any type of conductive material with any suitable composition and dimensions can be used to establish an electrical grounding shield as a continuous sheet. Examples of suitable materials include metals, degenerate semiconductors, conductive polymers, organometallic frames (metal-organic structures, MOFs), and coordination polymers. Organometallic frames are defined as crystalline compounds consisting of metal ions or clusters that are often coordinately bonded to rigid organic molecules to form a one-dimensional, two-dimensional, or three-dimensional structure that may be porous. Coordination polymers are inorganic or organometallic polymer structures containing metal cation centers bonded by ligands.

[0023] In an embodiment of the photonic integrated circuit according to the present invention, the electrical grounding shield of the second layer stack is configured as a mesh-like grid of conductive material.

[0024] It should be noted that the aforementioned disadvantages of establishing the electrical grounding shield as a continuous sheet of conductive material can be overcome by configuring the electrical grounding shield as a mesh grid of conductive material. In addition, since a continuous sheet of conductive material is more prone to delamination during the manufacturing process than a mesh grid of conductive material, a mesh grid of conductive material can lead to improved tolerances in manufacturing. Furthermore, a mesh grid of conductive material can help reduce additional stress or tension that accumulates on the electrical grounding shield during reliability testing of photonic integrated circuits.

[0025] A mesh-like grid can be established by providing continuous layers of conductive material with through-holes. The through-holes may be configured and arranged such that the mesh-like grid has areas of uniform mesh size, areas of non-uniform mesh size, or areas of uniform mesh size and areas of non-uniform mesh size. It is also possible to interconnect long tracks of conductive material using a mesh pattern to establish a mesh-like grid. Long tracks of conductive material may be arranged relative to one another to establish areas of uniform mesh size, areas of non-uniform mesh size, or areas of uniform mesh size and areas of non-uniform mesh size.

[0026] It should be noted that any type of conductive material with any suitable composition and dimensions can be used to establish a mesh-like grid, as long as the conductive material can achieve electromagnetic shielding. Examples of suitable materials include metals, degenerate semiconductors, conductive polymers, organometallic frames, and coordination polymers.

[0027] In an embodiment of the photonic integrated circuit according to the present invention, the mesh grid of the conductive material is configured to have a maximum mesh size equal to one-tenth the wavelength of the RF signal transmitted by a first set of long tracks of the conductive material during use of the photonic integrated circuit. Typically, the maximum mesh size is on the order of a few millimeters. The minimum mesh size is usually determined by the processing limits. A minimum mesh size equal to zero would actually lead to a continuous sheet of conductive material.

[0028] In an embodiment of the photonic integrated circuit according to the present invention, the electrical ground shield of the second layer stack is configured as a second set of long tracks of conductive material interconnected via a mesh-like grid of conductive material.

[0029] In this way, the electrical grounding shield is established in a hybrid manner, namely by using continuous tracks of conductive material interconnected by a mesh-like grid of conductive material. It should be noted that any type of conductive material with any suitable composition and dimensions can be used to establish a second set of long tracks interconnected by a mesh-like grid, as long as the conductive material can achieve electromagnetic shielding. Examples of suitable materials include metals, degenerate semiconductors, conductive polymers, organometallic frames, and coordination polymers.

[0030] In an embodiment of the photonic integrated circuit according to the present invention, the long tracks of a second set of long tracks of conductive material are positioned below the long tracks of a first set of long tracks of conductive material. It should be noted that the long tracks of the second set of long tracks of conductive material may also be positioned to accommodate the intersection of optical waveguides.

[0031] In an embodiment of the photonic integrated circuit according to the present invention, each long track of a second set of long tracks of conductive material, positioned below each long track of a first set of long tracks of conductive material, has a second width W2 when viewed in a direction parallel to the InP base substrate, and each long track of the first set of long tracks of conductive material has a first width W1 when viewed in a direction parallel to the InP base substrate, the second width W2 is greater than the first width W1.

[0032] The second width (W2) may be at least 75% larger than the first width (W1). The first width (W1) may be in the range of 5 μm to 15 μm depending on specific requirements regarding the desired impedance of the long tracks of the first set of long tracks of the conductive material and other factors.

[0033] In embodiments of the photonic integrated circuit according to the present invention, the conductive material includes a metal. It should be noted that any highly conductive metal can be used, provided that it is suitable for InP processing and does not lead to yield and / or reliability problems.

[0034] In embodiments of the photonic integrated circuit according to the present invention, the metal includes gold. It should be noted that the gold-containing metal alloy should be suitable for InP treatment and should not lead to yield and / or reliability problems.

[0035] In an embodiment of the photonic integrated circuit according to the present invention, the conductive material is gold. Gold is advantageous due to its high conductivity and suitability for InP treatment.

[0036] In an embodiment of the photonic integrated circuit according to the present invention, the first layer stack includes an unintentionally doped epitaxial semiconductor layer, which is arranged in relation to a doped epitaxial semiconductor layer to provide optical waveguides to the photonic integrated circuit.

[0037] In an embodiment of the photonic integrated circuit according to the present invention, an unintentionally doped epitaxial semiconductor layer is in the optical waveguide.x Ga 1-x As y P 1-y The core layer, which is also a doped epitaxial semiconductor layer, is a p-type doped InP-based cladding layer of the optical waveguide.

[0038] In an embodiment of the photonic integrated circuit according to the present invention, the fourth surface of the first dielectric layer of the second layer stack is related to the third surface of the first layer stack via the third dielectric layer, wherein the first dielectric layer and the third dielectric layer each contain different materials.

[0039] The first dielectric layer may be a polymer layer, such as benzocyclobutene (BCB). The fourth thickness (T4) of the first dielectric layer may be in the range of 500 nm to 3 μm, for example, 1.5 μm. The third dielectric layer may be an oxide-containing material, such as silicon dioxide (SiO2) with a fifth thickness (T5) when viewed in a direction perpendicular to the InP base substrate. The fifth thickness (T5) may be in the range of 20 nm to 300 nm, for example, 150 nm.

[0040] In an embodiment of the photonic integrated circuit according to the present invention, the eighth surface of the second dielectric layer of the second layer stack is related to the seventh surface of the electrical ground shield of the second layer stack via the fourth dielectric layer, wherein the second dielectric layer and the fourth dielectric layer each contain different materials.

[0041] The second dielectric layer may be a polymer layer, such as benzocyclobutene (BCB). The third thickness (T3) of the second dielectric layer may be in the range of 1 μm to 5 μm, for example, 3 μm. The fourth dielectric layer may be an oxide-containing material, for example, silicon dioxide (SiO2) with a sixth thickness (T6) when viewed in a direction perpendicular to the InP base substrate. The sixth thickness (T6) may be in the range of 50 nm to 500 nm, for example, 300 nm.

[0042] According to another aspect of the present invention, an optoelectronic system is provided, comprising a photonic integrated circuit, wherein the optoelectronic system is one of a transmitter, receiver, transceiver, coherent transmitter, coherent receiver, and coherent transceiver. The optoelectronic system may, but is not limited to, be used for telecommunications, lidar, or sensor applications. Based on the above, those skilled in the art will understand that any of the aforementioned transmitters, receivers, and transceivers may benefit from the advantages provided by the photonic integrated circuit according to the present invention. [Brief explanation of the drawing]

[0043] Further features and advantages of the present invention will become apparent from the description of exemplary and non-limiting embodiments of the photonic integrated circuit and optoelectronic system according to the present invention.

[0044] Those skilled in the art will understand that the embodiments described for the photonic integrated circuit and optoelectronic system are illustrative in nature and should not be construed as limiting the scope of protection in any way. Those skilled in the art will also understand that alternative and equivalent embodiments of the photonic integrated circuit and optoelectronic system may be conceived and put into practice without departing from the scope of protection of the present invention.

[0045] The diagrams in the attached drawings are referenced. The diagrams are inherently schematic and therefore not necessarily drawn to exact proportions. Furthermore, the same reference number refers to the same or similar part. [Figure 1] This is a schematic cross-sectional view of a first exemplary and non-limiting embodiment of a photonic integrated circuit according to the present invention. [Figure 2] This is a schematic cross-sectional view of a second exemplary and non-limiting embodiment of a photonic integrated circuit according to the present invention. [Figure 3] This is a schematic cross-sectional view of a third exemplary and non-limiting embodiment of a photonic integrated circuit according to the present invention. [Figure 4]This is a schematic cross-sectional view of a fourth exemplary and non-limiting embodiment of a photonic integrated circuit according to the present invention. [Figure 5] This figure is a schematic top view of a portion of a photonic integrated circuit according to the present invention, in which two long tracks of a first set of long tracks of conductive material are arranged in relation to a first exemplary and non-limiting embodiment of an electrical earth shield, and any dielectric layers arranged between the two long tracks and the electrical earth shield are omitted for clarity of representation. [Figure 6] This figure is a schematic top view of a portion of a photonic integrated circuit according to the present invention, in which two long tracks of a first set of long tracks of conductive material are arranged in relation to a second exemplary and non-limiting embodiment of an electrical earth shield, and any dielectric layers arranged between the two long tracks and the electrical earth shield are omitted for clarity of representation. [Figure 7] This figure is a schematic top view of a portion of a photonic integrated circuit according to the present invention, in which two long tracks of a first set of long tracks of conductive material are arranged in relation to a third exemplary and non-limiting embodiment of an electrical earth shield, and any dielectric layers arranged between the two long tracks and the electrical earth shield are omitted for clarity of representation. [Figure 8] This is a schematic top view of a first exemplary and non-limiting embodiment of an optoelectronic system according to the present invention, which includes a photonic integrated circuit according to the present invention. [Modes for carrying out the invention]

[0046] Figure 1 is a schematic cross-sectional view of a first exemplary and non-limiting embodiment of a photonic integrated circuit 1 according to the present invention. The photonic integrated circuit 1 includes an InP-based substrate 2 having a first surface 3, and a first layer stack including a doped epitaxial semiconductor layer 5. The first layer stack 4 is configured and arranged to provide optical functionality during use of the photonic integrated circuit 1. The first layer stack 4 has a second surface 6 associated with the first surface 3 of the InP-based substrate 2, and a third surface 7 arranged so as not to be associated with the second surface 6 (so as to face away from the second surface).

[0047] The photonic integrated circuit 1 also includes a second layer stack 8 configured and arranged to provide electrical functionality during use of the photonic integrated circuit 1. The second layer stack 8 includes a first dielectric layer 9 having a fourth surface 10 related to a third surface 7 of the first layer stack 4 and a fifth surface 11 arranged not to be related to the fourth surface 10. The second layer stack 8 also includes an electrical grounding shield 12 having a sixth surface 13 related to the fifth surface 11 of the first dielectric layer 9 and a seventh surface 14 arranged not to be related to the sixth surface 13. The second layer stack 8 further includes a second dielectric layer 15 having an eighth surface 16 related to the seventh surface 14 of the electrical grounding shield 12 and a ninth surface 17 arranged not to be related to the eighth surface 16.

[0048] The photonic integrated circuit 1 also includes a first set of long (elongated) tracks 18a, 18b of conductive material associated with the ninth surface 17 of the second dielectric layer 15 of the second layer stack 8. The first set of long tracks 18a, 18b of conductive material is configured and arranged to transmit RF signals during use of the photonic integrated circuit 1. Those skilled in the art will understand that the first set of long tracks of conductive material may include any suitable number of long tracks. The two long tracks 18a, 18b shown in Figure 1 are merely non-limiting examples.

[0049] The photonic integrated circuit 1 also includes at least one electrobonding pad (bond pad) 19 and at least one RF component 20 that are electrically related to each other via a first set of long tracks 18a, 18b of conductive material. Those skilled in the art will understand that the photonic integrated circuit 1 may include any suitable number of electrobonding pads 19 and RF components 20 that can be electrically related using the long tracks of the first set of any suitable number of long tracks of conductive material. One electrobonding pad 19, one RF component 20, and two long tracks 18a, 18b of conductive material configured and arranged to electrically relate the electrobonding pad 19 and the RF component 20 to each other are merely non-limiting examples.

[0050] It should be noted that the first dielectric layer 9 of the second layer stack 8 of the photonic integrated circuit 1 illustrated in Figure 1 is configured and positioned to provide DC electrical isolation between the electrical ground shield 12 and the first layer stack 4 during use of the photonic integrated circuit 1. In addition, the electrical ground shield 12 is configured and positioned to minimize or prevent the overlap of electric fields caused by RF signals and the doped epitaxial semiconductor layer 5 of the first layer stack 4 during use of the photonic integrated circuit 1. Thus, the photonic integrated circuit 1 includes on-chip electrical interconnects or feed lines 18a, 18b that are implemented using the method of shielded on-chip electrical interconnects or feed lines. From the above-described first exemplary and non-limiting embodiment of the photonic integrated circuit 1, it is evident that the long tracks 18a, 18b of the first set of long tracks of conductive material should be interpreted as on-chip electrical interconnects or feed lines.

[0051] The shielded on-chip electrical interconnect or feed line method, applicable to all exemplary and non-limiting embodiments of the photonic integrated circuit 1 according to the present invention illustrated in Figures 1, 2, 3, and 4, minimizes or prevents the overlap between the doped epitaxial semiconductor layer 5 of the photonic integrated circuit 1 and the electric field of the RF signals transmitted by the on-chip electrical interconnect or feed lines 18a, 18b during use of the photonic integrated circuit 1, without requiring the application of at least one of the dividing insulating trenches, unrealistically thick polymer layers, and fragile air bridges described above in relation to the prior art. The shielded on-chip electrical interconnect or feed line method enables low-loss on-chip electrical interconnect or feed lines 18a, 18b with desired impedance in lengths ranging from 0.5 mm to 5 mm for use in photonic integrated circuits with increasingly complex layouts. The shielded on-chip electrical interconnect or feed line can be routed on photonic components such as on-chip optical waveguides without any performance loss. It should be noted that the shielded on-chip electrical interconnects or feed lines of the photonic integrated circuit according to the present invention are suitable for application to any type of RF component, such as Mach-Zehnder modulators (MZMs), field absorption modulators (EAMs), and RF photodiodes (RF PDs).

[0052] The conductive material used for the long tracks 18a and 18b of the first set of long tracks can be any type of conductive material with any suitable composition and dimensions, as long as high-quality RF signals can be transmitted between the adhesive pads 19 and RF components 20 of the photonic integrated circuit 1 during use. It should be noted that the composition and dimensions of the long tracks 18a and 18b of the first set of long tracks of conductive material are determined by the desired electrical impedance of the on-chip electrical interconnect or feed wire and the tolerances in the manufacturing process.

[0053] In a practical example, the long track 18a of the first set of long tracks is manufactured using electroplated gold as the conductive material. To achieve an on-chip electrical interconnect or feed wire with an impedance of 55 ohms, the electroplated gold track 18a of the first set of long tracks may have a first width (W1) of 10 μm when viewed in a direction parallel to the InP base substrate 2 (see Figures 5 to 7) and a first thickness (T1) of 3 μm when viewed in a direction perpendicular to the InP base substrate 2 (see Figures 1 to 4). It should be noted that any other dimensions and composition of the conductive material may be assumed depending on the specific technical requirements of the photonic integrated circuit 1.

[0054] It should be noted that the shielding performance of the electrical earth shield 12 is not affected by the dimensions and / or composition of the long tracks 18a, 18b of the first set of long tracks of conductive material. The electrical earth shield 12 may have a second thickness (T2) in the range of 50 nm to 4 μm. The disadvantage of the electrical earth shield 12 having a second thickness (T2) greater than 4 μm is that topology and / or reliability problems may arise without any improvement in performance. The disadvantage of the electrical earth shield 12 having a second thickness (T2) less than 50 nm is that performance is impaired due to excessively high resistivity.

[0055] It should be noted that the degree of coupling between the electrical grounding shield 12 and the electric field associated with the RF signal transmitted by the first set of long tracks 18a, 18b of the first set of long tracks of conductive material during use of the photonic integrated circuit may be influenced by the composition and thickness of the second dielectric layer 15. For example, if the long tracks 18a, 18b of the first set of long tracks of conductive material have a first thickness (T1) of, for example, 3 μm, and the second dielectric layer 15 contains benzocyclobutene (BCB) with a third thickness (T3) of, for example, 3 μm when viewed in a direction orthogonal to the InP base substrate 2, then the electric field associated with the RF signal transmitted by the first set of long tracks 18a, 18b of conductive material during use of the photonic integrated circuit 1 may be considered to be strongly coupled to the electrical grounding shield 12. In addition, it should be noted that the composition and third thickness (T3) of the second dielectric layer 15 may affect the impedance of the on-chip electrical interconnect or feed lines 18a, 18b. Therefore, the composition of the second dielectric layer 15 and the third thickness (T3) must be carefully selected and / or controlled.

[0056] The above example of a second dielectric layer 15 containing benzocyclobutene (BCB) and having a third thickness (T3) of 3 μm can be used to achieve an on-chip electrical interconnect or feed wire with an impedance of 55 ohms. The values ​​for the impedance of the on-chip electrical interconnect or feed wires 18a, 18b will depend on the actual use case of the photonic integrated circuit 1, and therefore it will be clear that the composition and dimensions of the second dielectric layer 15 will also depend on the actual use case of the photonic integrated circuit.

[0057] As described above, during use of the photonic integrated circuit 1, the first dielectric layer 9 provides DC electrical insulation between the first layer stack 4, which includes the electrical ground shield 12 and the doped epitaxial semiconductor layer 5. It is sufficient for the first dielectric layer 9 to have a fourth thickness of, for example, 20 nm when viewed in the direction orthogonal to the InP base substrate 2, but for planarization, it is advantageous for the first dielectric layer 9 to have a fourth thickness (T4) of, for example, 3 μm. In such a case, the first dielectric layer 9 may also have a planarization function that can improve the yield and reliability of the photonic integrated circuit 1.

[0058] It should be noted that the conductive material used in the long tracks 18a and 18b may include any metal that has high conductivity, is suitable for InP treatment, and does not lead to yield and / or reliability problems. Such metal may be a pure metal or an alloy. The pure metal may be gold or a gold-containing alloy due to its high conductivity and suitability for InP treatment.

[0059] In relation to Figures 1 to 4, it should be noted that the first thickness (T1) of the long tracks 18a, 18b of the first set of long tracks of the conductive material can be in the range of 0.5 μm to 8 μm. In addition, it should be noted that the second thickness (T2) of the electrical grounding shield 12 can also be in the range of 0.5 μm to 8 μm. Although the second thickness (T2) is selected to be equal to the first thickness (T1) according to the exemplary and non-limiting embodiments of the photonic integrated circuit 1 shown in Figures 1 to 4, it should be noted that the second thickness (T2) may differ from the first thickness (T1) depending on the specific requirements of the photonic integrated circuit 1.

[0060] Figure 2 shows a schematic cross-sectional view of a second exemplary and non-limiting embodiment of the photonic integrated circuit 1 according to the present invention, in which the fourth surface 10 of the first dielectric layer 9 of the second layer stack 8 is related to the third surface 7 of the first layer stack 4 via the third dielectric layer 26. It should be noted that the first dielectric layer 9 and the third dielectric layer 26 each contain different materials. The first dielectric layer 9 may be a polymer layer, for example, benzocyclobutene (BCB). The fourth thickness (T4) of the first dielectric layer 9 may be in the range of 500 nm to 3 μm, for example, 1.5 μm. The third dielectric layer 26 may be an oxide-containing material, for example, silicon dioxide (SiO2) with a fifth thickness (T5) when viewed in a direction perpendicular to the InP base substrate 2. The fifth thickness (T5) may be in the range of 20 nm to 300 nm, for example, 150 nm.

[0061] According to a second exemplary and non-limiting embodiment of the photonic integrated circuit 1 shown in Figure 2, the eighth surface 16 of the second dielectric layer 15 of the second layer stack 8 is related to the seventh surface 14 of the electrical ground shield 12 of the second layer stack 8 via a fourth dielectric layer 27. It should be noted that the second dielectric layer 15 and the fourth dielectric layer 27 may each comprise different materials. The second dielectric layer 15 may be a polymer layer, for example, benzocyclobutene (BCB). The third thickness (T3) of the second dielectric layer 15 may be in the range of 1 μm to 5 μm, for example, 3 μm. The fourth dielectric layer 27 may be an oxide-containing material, for example, silicon dioxide (SiO2) with a sixth thickness (T6) when viewed in a direction perpendicular to the InP base substrate 2. The sixth thickness (T6) may be in the range of 50 nm to 500 nm, for example, 300 nm. It should be noted that the 55-ohm MZM feed lines 18a and 18b can be obtained by applying a second dielectric layer 15 containing a BCB with a third thickness (T3) of 3 μm and a fourth dielectric layer 27 containing SiO2 with a sixth thickness (T6) of 300 nm. It is obvious that the third thickness (T3) of the second dielectric layer 15 and the sixth thickness (T6) of the fourth dielectric layer 27 depend on the specific requirements for the photonic integrated circuit 1. However, for the yield and / or reliability of the photonic integrated circuit 1, it is recommended that the sum of the third thickness (T3) and the sixth thickness (T6) be at least 50 nm.

[0062] Figure 3 shows a schematic cross-sectional view of a third exemplary and non-limiting embodiment of the photonic integrated circuit 1 according to the present invention. Compared with the first exemplary and non-limiting embodiment of the photonic integrated circuit 1 shown in Figure 1, the first layer stack 4 of the photonic integrated circuit 1 shown in Figure 3 includes an unintentionally doped epitaxial semiconductor layer 24 arranged relative to the doped epitaxial semiconductor layer 5 of the first layer stack 4 to provide the photonic integrated circuit 1 with optical waveguides 25. The unintentionally doped epitaxial semiconductor layer 24 provides the optical waveguides 25 with respect to the optical waveguides 25. x Ga 1-x Asy P 1-y can be the core layer of, and the doped epitaxial semiconductor layer 5 can be the p-type doped InP-based cladding layer of the optical waveguide 25.

[0063] FIG. 4 is a schematic cross-sectional view of a fourth exemplary and non-limiting embodiment of the photonic integrated circuit 1 according to the present invention. Compared with the second exemplary and non-limiting embodiment of the photonic integrated circuit 1 illustrated in FIG. 2, the first layer stack 4 of the photonic integrated circuit 1 illustrated in FIG. 4 includes an unintentionally doped epitaxial semiconductor layer 24 disposed with respect to the doped epitaxial semiconductor layer 5 of the first layer stack 4 to provide the optical waveguide 25 to the photonic integrated circuit 1. The unintentionally doped epitaxial semiconductor layer 24 is In x Ga 1-x As y P 1-y can be the core layer of, and the doped epitaxial semiconductor layer 5 can be the p-type doped InP-based cladding layer of the optical waveguide 25.

[0064] Based on all of the above, it is clear that a photonic integrated circuit 1, including on-chip electrical interconnects or feed lines 18a, 18b that have been implemented according to a shielded on-chip electrical interconnect or feed line method, according to any of the above-described exemplary and non-limiting embodiments shown in Figures 1 to 4, proactively avoids the above-described problems associated with typical methods known from the prior art, in order to reduce the above-described problems associated with the implementation of on-chip electrical interconnects or feed lines in photonic integrated circuits with increasingly complex layouts. In particular, it is understood that the shielded on-chip electrical interconnect or feed line method can make the processing of the photonic integrated circuit 1 according to the present invention easier. In addition, the shielded on-chip electrical interconnect or feed line method provides a universal solution for the above-described specific situations, such as on-chip electrical interconnects that need to be placed on a doped epitaxial semiconductor layer and / or cross on-chip optical waveguides.

[0065] Figure 5 is a schematic top view of a portion of the photonic integrated circuit 1 according to the present invention, in which two long tracks 18a, 18b of a first set of long tracks of conductive material are arranged in relation to a first exemplary and non-limiting embodiment of the electrical grounding shield 12. For clarity of representation, it should be noted that any dielectric layers arranged between the two long tracks 18a, 18b and the electrical grounding shield 12, viewed in a direction orthogonal to the InP base substrate 2 (see Figures 1 to 4), have been omitted.

[0066] As shown in Figure 5, the electrical grounding shield 12 of the second layer stack 8 is configured as a continuous sheet of conductive material. A continuous sheet of conductive material is the simplest implementation of the electrical grounding shield 12, providing desired electrical shielding for two long tracks 18a, 18b, i.e., on-chip electrical interconnects or feed lines, from the doped epitaxial semiconductor layer 5 of the first layer stack 4 of the photonic integrated circuit 1 (see Figures 1 to 4). However, the application of conductive material to constitute the electrical grounding shield 12 as a continuous sheet can lead to reliability issues. In particular, if the continuous sheet has an area that covers most or all of the underlying layer, the incorporation of material emitted from the underlying layer beneath the continuous sheet can lead to failure points that sacrifice the yield and reliability of the photonic integrated circuit 1.

[0067] It should be noted that any type of conductive material with any suitable composition and dimensions can be used to establish an electrical grounding shield as a continuous sheet, as long as the conductive material can achieve electromagnetic shielding. Examples of suitable materials include metals, degenerate semiconductors, conductive polymers, organometallic frames, and coordination polymers. Organometallic frames are defined as crystalline compounds consisting of metal ions or clusters that are often coordinated to rigid organic molecules to form a one-dimensional, two-dimensional, or three-dimensional structure that may be porous. Coordination polymers are inorganic or organometallic polymer structures containing metal cation centers bonded by ligands.

[0068] Figure 6 is a schematic top view of a portion of the photonic integrated circuit 1 according to the present invention, in which two first sets of long tracks 18a, 18b of conductive material are arranged in relation to a second exemplary and non-limiting embodiment of the electrical grounding shield 12. As described above in relation to Figure 5, any dielectric layers arranged between the two long tracks 18a, 18b and the electrical grounding shield 12 when viewed in a direction orthogonal to the InP base substrate 2 (see Figures 1 to 4) are omitted for clarity of representation.

[0069] As shown in Figure 6, the electrical grounding shield 12 of the second layer stack 8 is configured as a mesh grid of conductive material. By configuring the electrical grounding shield 12 as a mesh grid of conductive material, the aforementioned disadvantages of establishing the electrical grounding shield 12 as a continuous sheet of conductive material can be overcome. In addition, since a continuous sheet of conductive material is more prone to peeling during the manufacturing process than a mesh grid of conductive material, a mesh grid of conductive material can lead to improved tolerances in manufacturing. Furthermore, a mesh grid of conductive material can help reduce additional stress or tension that accumulates on the electrical grounding shield 12 during reliability testing of the photonic integrated circuit 1.

[0070] A mesh-like grid can be established by providing continuous layers of conductive material with through-holes. The through-holes may be configured and arranged such that the mesh-like grid has a uniform mesh size, i.e., through-holes with equal width (W) and length (L) as shown in Figure 6, non-uniform mesh size (not shown), or regions with uniform mesh size and regions with non-uniform mesh size (not shown). Another method of establishing a mesh-like grid is by interconnecting long tracks of conductive material using a mesh pattern. Long tracks of conductive material may be arranged relative to one another to establish a uniform mesh size, i.e., through-holes with equal width (W) and length (L), non-uniform mesh size (not shown), or regions with uniform mesh size and regions with non-uniform mesh size (not shown).

[0071] A mesh grid of conductive material can have a maximum mesh size equal to one-tenth the wavelength of the RF signal transmitted by at least one of the two tracks 18a, 18b during the use of the photonic integrated circuit 1. Typically, the maximum mesh size is on the order of a few millimeters. The minimum mesh size is usually determined by the processing limits. A minimum mesh size equal to zero would actually lead to a continuous sheet of conductive material.

[0072] As described above, any type of conductive material with any suitable composition and dimensions can be used to establish a mesh-like grid, as long as the conductive material can achieve electromagnetic shielding. Examples of suitable materials include metals, degenerate semiconductors, conductive polymers, organometallic frames, and coordination polymers.

[0073] Figure 7 is a schematic top view of a portion of the photonic integrated circuit 1 according to the present invention, in which two first sets of long tracks 18a, 18b of conductive material are arranged in relation to a third exemplary and non-limiting embodiment of the electrical grounding shield 12. As described above in relation to Figures 5 and 6, any dielectric layers arranged between the two long tracks 18a, 18b and the electrical grounding shield 12 when viewed in a direction orthogonal to the InP base substrate 2 (see Figures 1 to 4) are omitted for clarity of representation.

[0074] As shown in Figure 7, the electrical grounding shield 12 of the second layer stack 8 is configured as a second set of long tracks 23a, 23b of conductive material interconnected via a mesh-like grid of conductive material. In this way, the electrical grounding shield 12 is established in a hybrid manner, that is, by using continuous tracks 23a, 23b of conductive material interconnected by a mesh-like grid of conductive material.

[0075] It should be noted that any type of conductive material with any suitable composition and dimensions can be used to establish long tracks 23a, 23b of a second set of long tracks interconnected by a mesh-like grid of conductive materials, as long as the conductive material can achieve electromagnetic shielding. Examples of suitable materials include metals, degenerate semiconductors, conductive polymers, organometallic frames, and coordination polymers.

[0076] As shown in Figure 7, the first long track 23a of the second set of conductive material long tracks is positioned below the first long track 18a of the first set of conductive material long tracks, and the second long track 23b of the second set of conductive material long tracks is positioned below the second long track 18b of the first set of conductive material long tracks. It should be noted that the configuration in which the first long track 23a and the second long track 23b of the second set of conductive material long tracks are positioned below the first long track 18a and the second long track 18b of the first set of conductive material long tracks, as shown in Figure 7, is by its nature exemplary and non-limiting. According to the third exemplary and non-limiting embodiment of the electrical earthing shield 12 shown in Figure 7, the first long track 23a and the second long track 23b of the second set of conductive material long tracks are positioned entirely below the first long track 18a and the second long track 18b of the first set of conductive material long tracks. As described above, the advantage of the first long track 23a and the second long track 23b of the second set of long tracks of conductive material is that they can be arranged such that the first long track 18a and the second long track 18b of the first set of long tracks of conductive material can intersect, for example, an optical waveguide.

[0077] Figure 7 illustrates that the first long track 18a of the first set of conductive material long tracks has a first width (W1) when viewed in a direction parallel to the InP base substrate 2, and that the first long track 23a of the second set of conductive material long tracks, located below the first long track 18a of the first set of conductive material long tracks, has a second width (W2) when viewed in a direction parallel to the InP base substrate 2. The second width (W2) is greater than the first width (W1). It should be noted that the second width (W2) can be at least 75% larger than the first width (W1). The first width (W1) can be in the range of 5 μm to 15 μm depending on specific requirements regarding the desired impedance of the first long track 18a of the first set of conductive material long tracks and other factors. Although not shown in Figure 7, it will be understood by those skilled in the art that the same applies to the second long track 18b of the first set of conductive material long tracks and the second long track 23b of the second set of conductive material long tracks.

[0078] Figure 8 is a schematic diagram of a first exemplary and non-limiting embodiment of an optoelectronic system 100 according to the present invention, which includes a photonic integrated circuit 1 according to the present invention. The optoelectronic system 100 may, but is not limited to, be used for, for example, telecommunications applications, lidar or sensor applications. The optoelectronic system 100 may be, for example, one of a transmitter, receiver, transceiver, coherent transmitter, coherent receiver, and coherent transceiver. Based on the above, those skilled in the art will understand that the optoelectronic system 100 according to the present invention may benefit from the advantages provided by the photonic integrated circuit 1 according to the present invention.

[0079] The present invention can be summarized as relating to a photonic integrated circuit 1 comprising an adhesive pad 19, an RF component 20, a first layer stack 4 having a doped epitaxial semiconductor layer 5, a second layer stack 8 associated with the first layer stack 4, and a first set of long tracks 18a, 18b of conductive material associated with the second layer stack 8 and capable of transmitting RF signals between the adhesive pad 19 and the RF component 20 during use of the photonic integrated circuit 1. The second layer stack 8 includes an electrical grounding shield 12 sandwiched between a first dielectric layer 9 and a second dielectric layer 15. During use of the photonic integrated circuit 1, the electrical grounding shield 12 minimizes or prevents the overlap between the RF signal and the electric fields generated by the doped epitaxial semiconductor layer 5. The present invention also relates to an optoelectronic system 100 comprising the photonic integrated circuit 1.

[0080] It will be apparent to those skilled in the art that the scope of the present invention is not limited to the examples described above, and that many amendments and modifications thereto are possible without departing from the scope of the invention as defined in the appended claims. In particular, various combinations of specific features of different embodiments of the invention are possible. Embodiments of the invention can be further advantageously enhanced by adding features described in other embodiments of the invention. Although the present invention has been illustrated and described in detail in the drawings and specification, such illustrations and descriptions should be construed as being for illustrative or illustrative purposes only and not limiting.

[0081] The present invention is not limited to the embodiments disclosed. By examining the features, descriptions, and appended claims, modifications to the embodiments disclosed can be understood and achieved by those skilled in the art in carrying out the invention described in the claims. In the claims, the word "including" does not exclude other steps or elements, nor does it exclude the case that a component is plural when described singly. The fact that certain means are described in different claims does not mean that combinations of these means cannot be used advantageously. No reference numeral in the claims should be construed as limiting the scope of the present invention.

Claims

1. A photonic integrated circuit (1), An InP base substrate (2) having a first surface (3), A first layer stack (4) comprising a doped epitaxial semiconductor layer (5), configured and arranged to provide optical functionality during use of the photonic integrated circuit (1), A second surface (6) associated with the first surface (3) of the InP base substrate (2), A third surface (7) is positioned so as to face away from the second surface (6), A first layer stack (4) having, A second layer stack (8) configured and arranged to provide electrical functionality during use of the aforementioned photonic integrated circuit (1), A fourth surface (10) associated with the third surface (7) of the first layer stack (4), A fifth surface (11) is positioned so as to face away from the fourth surface (10), A first dielectric layer (9) having, A sixth surface (13) associated with the fifth surface (11) of the first dielectric layer (9), A seventh surface (14) is positioned so as to face away from the sixth surface (13), An electrical grounding shield (12) having, The eighth surface (16) associated with the seventh surface (14) of the electrical grounding shield (12), A ninth surface (17) is positioned so as to face away from the eighth surface (16), A second dielectric layer (15) having, A second layer stack (8) including, A first set of elongated tracks (18a, 18b) of conductive material associated with the ninth surface (17) of the second dielectric layer (15) of the second layer stack (8), wherein the first set of elongated tracks (18a, 18b) of conductive material is configured and arranged to transmit RF signals during use of the photonic integrated circuit (1), At least one bond pad (19) and at least one RF component (20) are electrically linked to each other via the first set of long tracks (18a, 18b) of conductive material, Includes, The first dielectric layer (9) of the second layer stack (8) is configured and positioned to provide DC electrical insulation between the electrical ground shield (12) and the first layer stack (4) during use of the photonic integrated circuit (1), and the electrical ground shield (12) is configured and positioned to minimize or prevent the overlap between the RF signal and the electric field generated by the doped epitaxial semiconductor layer (5) of the first layer stack (4) during use of the photonic integrated circuit (1). The aforementioned photonic integrated circuit (1).

2. A photonic integrated circuit (1) according to claim 1, The electrical grounding shield (12) of the second layer stack (8) is configured as a continuous sheet of conductive material. The aforementioned photonic integrated circuit (1).

3. A photonic integrated circuit (1) according to claim 1, The electrical grounding shield (12) of the second layer stack (8) is configured as a mesh grid of conductive material. The aforementioned photonic integrated circuit (1).

4. A photonic integrated circuit (1) according to claim 3, The mesh grid of the conductive material is configured to have a maximum mesh size equal to one-tenth of the wavelength of the RF signal transmitted by the first set of elongated tracks (18a, 18b) of the conductive material during use of the photonic integrated circuit (1). The aforementioned photonic integrated circuit (1).

5. A photonic integrated circuit (1) according to claim 1, The electrical grounding shield (12) of the second layer stack (8) is configured as a second set of elongated tracks (23a, 23b) of conductive material interconnected via a mesh-like grid of conductive material. The aforementioned photonic integrated circuit (1).

6. A photonic integrated circuit (1) according to claim 5, The elongated tracks of the second set of conductive material (23a, 23b) are positioned below the elongated tracks of the first set of conductive material (18a, 18b). The aforementioned photonic integrated circuit (1).

7. A photonic integrated circuit (1) according to claim 6, Each of the elongated tracks (23a, 23b) of the conductive material, positioned below each of the elongated tracks (18a, 18b) of the first set of conductive material, has a second width W when viewed in a direction parallel to the InP base substrate (2). ２ The first set of elongated tracks (18a, 18b) of conductive material has a first width W when viewed in the direction parallel to the InP base substrate (2). １ It has the second width W ２ The first width W １ Larger, The aforementioned photonic integrated circuit (1).

8. A photonic integrated circuit (1) according to claim 1, The conductive material includes a metal. The aforementioned photonic integrated circuit (1).

9. A photonic integrated circuit (1) according to claim 8, The aforementioned metal includes gold. The aforementioned photonic integrated circuit (1).

10. A photonic integrated circuit (1) according to claim 1, The conductive material is gold. The aforementioned photonic integrated circuit (1).

11. A photonic integrated circuit (1) according to claim 1, The first layer stack (4) includes an unintentionally doped epitaxial semiconductor layer (24) arranged in relation to the doped epitaxial semiconductor layer (5) to provide an optical waveguide (25) to the photonic integrated circuit (1), The aforementioned photonic integrated circuit (1).

12. A photonic integrated circuit (1) according to claim 11, The unintentionally doped epitaxial semiconductor layer (24) is in the In of the optical waveguide (25). ｘ Ga １－ｘ As ｙ P １－ｙ The core layer, and the doped epitaxial semiconductor layer (5), is a p-type doped InP-based cladding layer of the optical waveguide (25). The aforementioned photonic integrated circuit (1).

13. A photonic integrated circuit (1) according to claim 1, The fourth surface (10) of the first dielectric layer (9) of the second layer stack (8) is associated with the third surface (7) of the first layer stack (4) via the third dielectric layer (26), and the first dielectric layer (9) and the third dielectric layer (26) each contain different materials. The aforementioned photonic integrated circuit (1).

14. A photonic integrated circuit (1) according to claim 1, The eighth surface (16) of the second dielectric layer (15) of the second layer stack (8) is associated with the seventh surface (14) of the electrical ground shield (12) of the second layer stack (8) via the fourth dielectric layer (27), and the second dielectric layer (15) and the fourth dielectric layer (27) each contain different materials. The aforementioned photonic integrated circuit (1).

15. An optoelectronic system (100) comprising the photonic integrated circuit (1) described in claim 1, The aforementioned optoelectronic system (100) is one of a transmitter, receiver, transceiver, coherent transmitter, coherent receiver, and coherent transceiver. The aforementioned optoelectronic engineering system (100).

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