Optical Multi-Die Interconnect Bridge (OMIB)

Abstract

This relates to a device and method for optical interconnection using an integrated circuit and / or an external chiplet. [Solution] The package includes a bridge element (OMIB) and first and second photonic paths that form a bidirectional photonic path. The OMIB has first and second interconnection regions that connect to one or more dies. Third and fourth unidirectional photonic paths may connect the first interconnection region to an optical interface (OI). The photonic transceiver has a first portion in the OMIB and a second portion in one of the dies. The first and second portions may be connected via an electrical interconnection less than 2 mm in length. The die includes a computing element around a central region adjacent to the second portion.

Description

Technical Field

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 448,585, filed on February 27, 2023, entitled "Optical, Multi-Die Interconnect Bridge (OMIB)"; U.S. Provisional Patent Application No. 63 / 420,330, filed on October 28, 2022, entitled "Thermally Stable Optical Modulation Elements Coupled to Electronic Elements"; and U.S. Provisional Patent Application No. 63 / 321,453, filed on March 18, 2022, entitled "Photonic Memory Fabric for System Memory Interconnection". These priority applications are hereby incorporated by reference in their entirety as if fully set forth herein.

[0002] Each publication, patent, and / or patent application mentioned in this specification is hereby incorporated by reference in its entirety to the same extent as if each individual publication and / or patent application was specifically and individually indicated to be incorporated by reference.

[0003] The disclosed implementations generally relate to devices and methods for interconnecting semiconductor dies, and more particularly, to devices and methods for optical interconnects using integrated circuits and / or external chiplets.

Background Art

[0004] The subject matter discussed in this section should not be assumed to be prior art merely as a result of its mention in this section. Similarly, problems associated with the subject matter mentioned or provided as background in this section should not be assumed to have been recognized in the prior art. The subject matter in this section merely represents various approaches, and in itself, may also correspond to the implementation of the claimed technology.

[0005] Integrated circuits (ICs) with processors, particularly those used to perform artificial intelligence and machine learning functions, move large amounts of data between one or more processor ICs and one or more memory ICs. Chiplets can help interconnect processor dies, memory dies, and other circuits to increase bandwidth and reduce latency and power consumption during the process. [Overview of the project]

[0006] Processing AI workloads often requires dedicated hardware. Typical hardware bridges two chips with an electrical interconnect. Electrical interconnects consume high power, have pin count limitations, and can only bring data to the edge of the chip. If memory is located in the central region of the chip, each time the processor accesses memory by sending a request from outside the chip to the edge of the chip, the signal needs to travel an extra distance. This is highly inefficient and makes it difficult for AI computing hardware to meet the demands required by AI applications.

[0007] In a first embodiment, the implementation provides a package comprising a bridge element, a first unidirectional photonic path, and a second unidirectional photonic path. The bridge element includes a first interconnection region and a second interconnection region, both configured to be electrically connected on one or more dies. The unidirectional photonic path is coupled in opposite directions between the two interconnection regions. Third and fourth unidirectional photonic paths may be coupled bidirectionally between the first interconnection region and an optical interface (OI). A first portion of the photonic transceiver may be coupled to the first interconnection region to transmit a first optical signal via the first unidirectional photonic path and to receive a second optical signal via the second unidirectional photonic path. A first portion of the photonic transceiver may further be configured to transmit a third optical signal via a third unidirectional photonic path and to receive a fourth optical signal via a fourth unidirectional photonic path. The first part of the photonic transceiver may reside in a photonic integrated circuit (PIC), and the second part of the photonic transceiver may reside in an electrical integrated circuit (EIC). The first and second parts may be coupled via an electrical interconnection less than 2 mm in length. The modulator may be an electro-absorption modulator made of germanium, silicon, a germanium alloy, a silicon alloy, an indium phosphide (InP)-based III-V material, or a gallium arsenide (GaAs)-based III-V material. The EIC may include two or more computing elements around a central region. The second part is adjacent to one of the computing elements.

[0008] A further understanding of the nature and advantages of the specific implementations disclosed herein can be achieved by referring to the remainder of this specification and the accompanying drawings.

[0009] The present invention will be described with reference to the drawings. [Brief explanation of the drawing]

[0010] [Figure 1]This is a top view of a wafer and die, including or potentially including one or more microelectronic packages having OMIBs, relating to various mounting configurations. [Figure 2] An exemplary OMIB with two dies bridging is shown. [Figure 3] This shows an exemplary package in which two dies can be coupled via an electrical interconnect. [Figure 4] This shows an exemplary package in which two dies can be coupled via an electrical interconnect. [Figures 5A-5E] This document presents an exemplary package that uses an optical engine to provide optical signals for use by a photonic network. [Figure 6] An exemplary perspective view of the OMIB, which bridges two dies and is coupled to the optical engine, is shown. [Figure 7A] An exemplary perspective view of an OMIB that bridges two dies and receives unmodulated light from a chiplet optical engine (CLE) is shown. [Figure 7B] This shows an example package that can use CLE. [Figure 8A] This figure shows an exemplary OMIB having a photonic link capable of connecting two dies within a package, relating to several implementation configurations. [Figure 8B] This shows one implementation configuration having two OMIBs coupled between a first die and a second die. [Figure 9] This figure shows an exemplary system of a link that uses WDM for communication from a die to an external device, relating to several implementation configurations. [Figure 10] Figure 9 shows an exemplary inverse channel for the WDM system relating to several implementation configurations. [Figure 11] This shows an exemplary one-way logic channel with multiple photonic links. [Figure 12] Figure 11 shows an example of 8-word message transfer in a one-way logical channel. [Figure 13]Show an exemplary AMS block in detail. [Figure 14A] Show the arrangement of three OMIBs bridging a part of two dies. [Figure 14B] Show an exemplary arrangement of five dies bridged by an OMIB. [Figure 14C] Show an exemplary arrangement of dies bridged by both an OMIB and an electrical bridge. [Figure 14D] Show an exemplary offset checkerboard of an OMIB bridging dies in two dimensions. [Figure 15] It is a flowchart showing an exemplary method of manufacturing an OMIB according to various implementation modes. [Figure 16] Show the components of an exemplary system in which one or more OMIBs can be used. [Figures 17A-17D] Show an example of a combination of EIC / OMIB using temperature compensation to expand the temperature range of a modulator in an OMIB. [Figure 18] Show an exemplary method 1800 of manufacturing a system.

Mode for Carrying Out the Invention

[0011] In the figures, like reference numerals may indicate functionally similar elements. The systems and methods shown in the figures and described in the following detailed description can be configured and designed in a variety of different implementations. Neither the drawings nor the detailed description are intended to limit the scope of the claimed subject matter. Rather, they merely represent examples of various implementation modes of the present invention.

[0012] AI workload processing often uses dedicated hardware. Typical hardware bridges two chips with an electrical interconnect. The electrical interconnect consumes high power, has pin count limitations, and can only bring data to the edges of the chips. When memory is in the central region of the chip, each time the processor accesses the memory by sending a request from outside the chip to the edge of the chip, the signal has to travel an extra distance. This is very inefficient and makes it difficult for AI computing hardware to meet the demands required by AI applications.

[0013] This book discloses an optical multi-die interconnect bridge element (OMIB). The OMIB can be used as a bridge between semiconductor dies, such as electrical integrated circuits (EICs). The bridge can include the OMIB alone, or the OMIB combined with a substrate to which the OMIB is coupled or in which the OMIB is embedded. By using the OMIB for a multi-die processing system, many of the problems associated with the processing of AI workloads, including latency, power, and bandwidth, are solved. The photonic receiver may comprise a first part within the OMIB that includes two parts, such as a modulator and / or a photodetector, and a second part within the EIC that includes an AMS block as described later in this specification.

[0014] In various configurations, the OMIB can transmit or receive photonic signals to carry data. For example, memory such as a cache may be located in the central region of the EIC die within 2 millimeters (2 mm) of the AMS block, and the photonic transmitter within the OMIB is located close to the memory edge directly above or below the portion of the die where the memory edge is located. The central region may intersect with the center of the EIC die. Computing elements such as a central processing unit (CPU), graphics processing unit (GPU), and tensor processing unit (TPU) may also be advantageously located in the central region of the die within 2 millimeters (2 mm) of where the photonic transmitter is located, or spatially coupled with the memory. The photonic IC is designed to avoid reaching the center of the die of the connected chip due to the heat generated by the connected chip. The photonic chip may have a limited temperature range, within which the modulator functions within specifications. One reason why the OMIB in the disclosed technology can reach the center of the die is that it uses a temperature-stabilized modulator, such as the one described in U.S. Provisional Patent Application No. 63 / 420,330, entitled “Thermally Stable Optical Modulation Elements Coupled to Electronic Elements”.

[0015] As a result, OMIB is faster and more power-efficient than conventional systems. Latency is improved by photon-transporting data to the computation point rather than the die edge. This allows the die to conserve electrical pipeline stages and use fewer electrical connections to transport data from the chip edge to the interior where the memory is located. Electrical data movement from the die edge to the interior requires a slower and more power-intensive data path. When a typical system is used to train an AI model, the advantages of photon-transporting data to the computation point are continuously repeated, resulting in substantial savings and / or the feasibility of this type of complex AI system. term

[0016] This specification may use perspective-based descriptions, such as top / bottom, inside / outside, or upward / downward views. Such descriptions are used solely for the purpose of facilitating discussion and are not intended to restrict the application of the implementations described herein to any particular orientation.

[0017] Where used herein, the expression "one of ~" should be interpreted as meaning only one of the listed items. For example, the expression "one of A, B, and C" should be interpreted as meaning either A only, B only, or C only.

[0018] Where used herein, the expression "at least one of ~" should be interpreted as meaning one or more items. For example, the expression "at least one of A, B, and C" or "at least one of A, B, or C" should be interpreted as meaning any combination of A, B, and / or C.

[0019] Unless otherwise specified, the use of ordinal adjectives such as "first," "second," and "third" to describe an object simply refers to a different example or class of the object, and does not indicate rank or order.

[0020] The term “to be coupled” is used in an operational sense and is not limited to direct or indirect coupling. “To be coupled to ~” generally means to be directly coupled, while “to be coupled with ~” generally means to be directly or indirectly coupled. In electronic systems, “coupling” may refer to a configuration that enables the flow of information, signals, data, or physical quantities such as electrons between two elements that are coupled to or coupled with each other. In some cases, this flow may be unidirectional; in other cases, the flow may be bidirectional or multidirectional. Coupling may be galvanic (meaning the presence of a direct electrical connection in this context), capacitive, inductive, electromagnetic, optical, or any other process permitted by physics.

[0021] The term "connected" is used to describe a direct connection between connected things without any intermediaries or devices, such as an electrical connection, optical connection, electromagnetic connection, or mechanical connection.

[0022] The term “configured to perform” one or more tasks is a broad description of a structure that “has a circuit” that performs one or more tasks while in operation. Thus, the described item may be configured to perform tasks even when the unit / circuit / component is not currently on or active. Generally, the circuit forming the structure corresponding to “configured” may include hardware circuitry and may further be controlled by switches, fuses, bond wires, metal masks, firmware, and / or software. Similarly, for convenience in this specification, various items may be described as performing one or more tasks. Such descriptions should be interpreted as including the expression “configured.”

[0023] As used herein, the term “based on” is used to describe one or more factors that influence a decision. This term does not exclude the possibility that additional factors may influence the decision. That is, a decision may be based on the specified factors alone, or on the specified factors and other unspecified factors. Consider the expression “Determine A on B.” This expression specifies that B is a factor used to determine A, or a factor that influences the determination of A. This expression does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This expression is also intended to cover implementations in which A is determined solely on B. Thus, the expression “based on” is synonymous with the expression “based at least in part.”

[0024] "Processor" includes any suitable hardware system, mechanism, or component that processes data, signals, or other information. A processor may include a general-purpose central processing unit, multiple processing units, dedicated circuits for implementing a function, or other systems. Examples of processing systems may include servers, clients, end-user devices, routers, switches, network storage, etc. "Computer" may be any processor that communicates with memory. Memory may be any suitable processor-readable storage medium, such as random access memory (RAM), read-only memory (ROM), magnetic or optical disks, or other tangible media suitable for storing instructions to be executed by the processor.

[0025] The terms "effectively," "almost," "approximately," "around," and "about" refer to a range of plus or minus 10% of the given value, unless otherwise specified.

[0026] The following terms or acronyms are defined, at least in part, as follows:

[0027] AI-Artificial Intelligence

[0028] AMS - Analog / Mixed Signal

[0029] BGA - Ball Grid Array

[0030] A channel is one or more lanes that can be joined to each other.

[0031] Chiplet - An integrated circuit with simple or special functions used in combination with other ICs or chiplets in a multichip assembly.

[0032] CLE-Chiplet Light Engine

[0033] CPU - Central Processing Unit

[0034] CW (Continuous Wave)

[0035] DDR memory - Double Data Rate Memory

[0036] DFB-Distributed Fiber Bragg

[0037] DIMM - Dual Inline Memory Module

[0038] DRV-Driver

[0039] DSP - Digital Signal Processor

[0040] EAM (Earth Absorption Modulator)

[0041] EIC - Electronic Integrated Circuits

[0042] EW - Evanescent Wave

[0043] FAU - Fiber Array Unit

[0044] FBG - Fiber Bragg Grating

[0045] FPGA - Field-Programmable Gate Array

[0046] GC - Grating Coupler - Coupler between optical fiber and on-chip photonic waveguide

[0047] GPU - Graphics Processing Unit

[0048] GRIN Lane - Refractive Index Distribution Lens

[0049] HBM - High Bandwidth Memory

[0050] IC – Integrated Circuit – Monolithic integrated circuit, i.e., a single semiconductor die that can be supplied as a bare die or packaged circuit. For the purposes of this specification, the term integrated circuit also includes packaged circuits comprising multiple semiconductor dies, stacked dies, or multiple die substrates. Such structures are now common in the industry, produced by the same supply chain, and are often indistinguishable from monolithic circuits to the average user.

[0051] A lane includes a serializer, a link, and a deserializer.

[0052] LED - Light-emitting diode

[0053] LDSU - Load / Store Unit

[0054] In this patent document, a link is a combination of a modulator, a photonic path (within the optical transmission medium), and a photodetector.

[0055] LGA Land Grid Array

[0056] ML (Machine Learning)

[0057] MLA - Microlens Array

[0058] MOD Modulator

[0059] MZI-Mach-Zehnder Interferometer

[0060] OI - Optical Interface - An interface that uses any means to connect a fiber and a photonic IC via an optical interface.

[0061] OMIB - Optical Multi-die Interconnection Bridge

[0062] PCB - Printed Circuit Board

[0063] PCIe - PCI Express - High-Speed ​​Serial Computer Expansion Bus.

[0064] PCM - Phase-Change Memory

[0065] PD - Photodetector, for example, a photodiode.

[0066] PGA-Pingrid Array

[0067] PIC - Photonic Integrated Circuit

[0068] QR-Quick Response

[0069] A processing device, processor, computing device, or computing element may refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory.

[0070] RAM stands for Random Access Memory. There are several types, including Static RAM (SRAM), Dynamic RAM (DRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), and Conductive Bridge RAM (CBRAM).

[0071] RDL - Redistribution Layer - An extra metal layer on the IC to make bond pads available at other locations on the die.

[0072] SCM-Storage Class Memory

[0073] SLD - Superluminescent Diode

[0074] SSD - Solid State Drive

[0075] SOA - Semiconductor Optical Amplifier

[0076] TPU-Tensor Processing Unit

[0077] UCIe - Universal Chiplet Interconnection: An open specification for express-die interconnects and serial buses between chiplets.

[0078] VCSEL - Vertical Cavity Surface Emitting Laser

[0079] Waveguides are implementations of unidirectional photonic paths in optical transmission media.

[0080] WDM - Wavelength Division Multiplexing. Implementation Method

[0081] The implementation embodiments described herein relate to addressing concerns regarding power, latency, or pin count by providing various OMIB configurations and various packages containing at least one OMIB. Figure 1 is a top view of a wafer 100 and a die 102 that may contain, or be contained in, one or more microelectronic packages having an OMIB, relating to various implementation embodiments. The wafer 100 may be composed of a semiconductor material and may contain one or more dies 102 having an IC structure formed on the surface of the wafer 100. Each die 102 may be a unit of a semiconductor product containing a suitable IC. After the manufacturing of the semiconductor product is complete, the wafer 100 may undergo a unitization process in which the dies are separated from each other to provide individual “chips” of the semiconductor product. The dies 102 and at least one other die may be contained in a microelectronic package having an OMIB.

[0082] The OMIB may be formed in a second process using a second wafer (not shown) in a manner similar to the manufacturing of the die 102. The OMIB is an electronic integrated circuit (EIC) and, in contrast to the die 102 which generally has internally manufactured electronic elements, is a photonic integrated circuit (PIC) and has internally manufactured optical components. The OMIB may be embedded in a package substrate. The package substrate may be a cored or coreless substrate. The package substrate may include one or more layers of dielectric material which may be organic or inorganic. The package substrate may further include one or more conductive elements such as vias, pads, traces, microstrips, or striplines. The conductive elements may be inside or on the surface of the package substrate. Generally, the conductive elements may enable the routing of signals through the package substrate or between elements coupled to the package substrate. In some implementation embodiments, the package substrate may be, for example, a printed circuit board (PCB), an interposer, a motherboard, or any other type of substrate.

[0083] Figure 2 shows an example of an OMIB having two bridged dies. The OMIB 200, formed in the second stage of the manufacturing process, may share dimensions (horizontal or vertical) with each die 102 formed in the first stage of the manufacturing process. The dies may be as large as possible within the size limitations of the reticle used in manufacturing. In Figure 2, die 102 has a width corresponding to the maximum reticle width MRW1 of the EIC reticle and a height corresponding to the maximum reticle height MRH1 of the EIC reticle, and OMIB 200 has a width corresponding to the maximum reticle width MRW2 of the PIC reticle. This may be for convenience and cost reduction during manufacturing and is not limited to various mounting configurations.

[0084] In some implementation embodiments, wafer 100 or die 102 may include memory devices, computing devices, or both (e.g., random access memory (RAM) devices (e.g., static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, or conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, NOR, or EXOR gates), NAND flash memory, solid-state device (SSD) memory, NOR flash memory, CMOS memory, thin-film transistor-based memory, phase-change memory (PCM), storage class memory (SCM), magnetoresistive memory (MRAM), resistive RAM, DRAM, high-bandwidth memory (HBM), DDR-based DRAM, DIMM memory, CPU, GPU, MPU, tensor engine, load / store unit (LDSU), neural computing engine, dot product and / or convolution engine, field-programmable gate array (FPGA), AI accelerator, or any other suitable circuit elements). Multiple of these devices may be combined on a single die 102. For example, die 102 includes multiple memory arrays, one or more processors, other logic, communication circuits, and memory with power management functions, and may execute instructions stored in the memory arrays or interact with the memory arrays in other ways using the processors on die 102.

[0085] Figure 3 shows an exemplary package 300 in which dies 310 and 320 may be coupled via an electrical interconnect. The package 300 includes an OMIB 330 that acts as a bridge between dies 310 and 320. An optional substrate 340 is coupled to the OMIB 330 such that the OMIB 330 is embedded in the substrate 340. Although shown as coplanar in Figure 3, the OMIB 330 may not be coplanar with the surface of the substrate 340, but rather may protrude at least partially from the substrate 340 or be embedded in the inner layers of the substrate 340. The various elements shown may be on the surface of the OMIB 330 or dies 310 and / or 320, or may protrude at least partially from there. Also, the specific number of elements, interconnects, dies, and other devices may differ in other mounting embodiments. In some mounting embodiments, the package may include adhesives, sealants, underfill materials, molding materials, overmolding materials, or any other structural or dielectric materials. In some implementation embodiments, certain elements may be positioned at different locations in the signal path relative to other elements. The optical interface (OI) 350 is included on the surface of the OMIB 330. The optical interface 350 may couple with the optical engine 370 to receive unmodulated light via fiber 360 and / or with an external device optical interface to exchange modulated and / or unmodulated light in either direction. In addition to the optical interface 350, one or more electrical interfaces for interfacing with external electrical devices may be present on the surface of the OMIB 330.

[0086] Various implementations can utilize different types of optical engines. The optical engine may be external to the OMIB or integrated into the OMIB. Exemplary implementations may use the following optical engines in a package containing the OMIB330, and to bring signals from the package: Laser diodes – these are highly coherent light sources that produce narrower beams of light and are widely used in photonic chips for data communication and sensing applications; Light-emitting diodes (LEDs) – a type of diode that emits light when current passes through it (widely used for photonic chips due to their low cost, small size, and long lifespan); Superluminescent diodes (SLDs) – SLDs are similar to LEDs but emit a broader, widerband optical spectrum (SLDs are used, for example, for optical amplification, These are used in applications such as wavelength division multiplexing and optical fiber sensing; vertical cavity surface-emitting lasers (VCSELs) – these are lasers that emit light perpendicular to the chip surface and are ideal for photonics applications (VCSELs are widely used in data communication and sensing applications such as 3D sensing, LiDAR, and data center interconnects); and silicon photonics – devices that generate light sources on silicon chips using the optical propagation properties of silicon (silicon photonics have the potential to revolutionize photonics by reducing the size, cost, and power consumption of photonic components). These are some of the most commonly used light sources, along with packages including the OMIB330. The choice of optical engine depends on the specific requirements of the implementation, such as wavelength, power, and modulation rate.

[0087] The optical engine may be located locally in the OMIB330 or connected to the OMIB330 via fiber 360. When integrated on the PIC, a distributed fiber Bragg (DFB) laser or quantum dot laser may be mounted during processing or, where possible, integrated into the native technology. For remote applications, any packaged continuous wave (CW) with a suitable power and spectrum for modulation techniques may be used. In one implementation embodiment, the light source is a set of DFB lasers mounted on a silicon interposer and connected to the PIC via optical fiber.

[0088] The optical interface 350 is used to terminate the optical fiber at the edge or top of the OMIB330 so that optical input and / or output from an external processor or device communicably coupled to the package 300 via the fiber occurs. The choice of OI depends on the specific requirements of the implementation, such as the wavelength of light, coupling efficiency, and cost. The optical interface 350 and any other optical interfaces within the OMIB330 may include any means for optical interface connection between the fiber and the photonic IC, such as edge couplers, grating couplers (CG), distributed refractive index (GRIN) lens couplers, fiber Bragg grating (FBG) couplers, microlens array (MLA) couplers, evanescent wave (EW) couplers, adiabatic couplers, wavelength division multiplexing (WDM) couplers, prism couplers, butt couplers, end-fire couplers, and V-groove couplers.

[0089] In one implementation embodiment, the optical interface 350 includes a fiber array unit (FAU) for optically connecting the OMIB to a light source and / or optical I / O unit. A FAU is a device used in optical communication systems to couple or separate optical signals from multiple fibers into a single optical signal. FAUs can be used in a variety of applications, such as wavelength division multiplexing (WDM), parallel optical interconnects, and photosensing. There are two main types of fiber array units that can be used: linear and circular. A linear FAU couples or separates optical signals along a straight line, while a circular fiber array unit couples or separates optical signals in a circular configuration. Both types of fiber array units are typically made of precision-molded optical plastic or ceramic material and may have several to several hundred fibers arranged in a specific pattern. The choice of FAU depends on the specific requirements of the application, such as the number of fibers, the arrangement of the fibers, the wavelength of light used, and the desired coupling efficiency. Each die may have an associated analog / mixed-signal (AMS) block related to the portion of the OMIB it is coupled to, and one or more transistors or support circuits, or any other IC components, for routing electrical signals to transistors.

[0090] The OMIB330 may further include one or more electrical interfaces (EIs). The OI and EIs may be mounted between bridged dies 102, or on the surface of the OMIB offset to areas in the x or y direction where the dies 102 do not extend. The EIs function similarly to the OI, except that they grant the OMIB the ability to transmit data to and from the dies via electrical connections rather than optical connections, and that external I / O blocks can be connected to the OMIB via wires from the EI to the external I / O blocks, for example. Different types of electrical connections are possible, including wires, RDLs, etc. Electrical connections generally transmit and receive data electrically across the electrical interconnects between the EIs and any of the dies bridged by the OMIB, or between the EIs and external I / O blocks, using known standards or bus protocols. The electrical path between the EIs and the dies may be routed through the OMIB, through the substrate, or both (or, in the case of RDLs, through one of the layers of the OMIB and / or the substrate).

[0091] Figure 4 shows an exemplary package 400 in which dies 410 and 420 can be coupled via an electrical interconnect. Package 400 is similar to package 300 in Figure 3 and has a similar number of elements, but in addition, it shows a first photonic transceiver 432 and a second photonic transceiver 434. Part of the first transceiver 432 is in die 410, and part of the second photonic transceiver 434 is in die 420. Another part of the first transceiver 432 is in OMIB 430, and another part of the second transceiver 434 is in OMIB 430. Figure 4 shows bidirectional photonic paths 481, 482, and 483. Bidirectional photonic path 483 connects the first photonic transceiver 432 and the second photonic transceiver 434. The bidirectional photonic path 483 may include two or more unidirectional photonic paths in opposite directions to create a bidirectional path between two transceivers and enable optical communication and / or data movement through the photonic channel in both directions between the two dies 410 and 420. The bidirectional photonic path 481 links the photonic transceiver 432 to the optical interface 450, and the bidirectional photonic path 482 links the photonic transceiver 434 to the optical interface 450. The optical interface 450 is coupled to the optical engine via fiber 460. The bidirectional photonic paths 481-483 may form a photonic network within the OMIB 430. The optical interface 450 may include any means for interface connection between the fiber and the photonic IC. The substrate 400 is optional.

[0092] Photonic paths can be implemented on optical transmission media. Optical transmission media may include waveguides on a PIC, optical fibers or other optical transmission media (e.g., free-space optics or glass-etched waveguides), or a combination of several of the above. Examples of optical modulators include, but are not limited to, field absorption modulators (EAMs), microring resonators, or any suitable optical component with sufficient thermal stability.

[0093] Figures 5A–E show exemplary packages that use an optical engine to provide optical signals for use by a photonic network. The optical engine may include a laser diode, an optical system, and / or control electronics. The laser diode is the laser light source, and the optical system is used to shape and control the laser output. Control electronics (not shown) provide the laser diode with the power and modulation required to produce the desired output. In the implementation embodiments of Figures 5A–E, the optical engine provides optical signals to a splitter, a modulator (MOD) adjacent to the AMS block on the first die, and ultimately a photodetector (PD) adjacent to the AMS block on the second die, via an optical interface such as a FAU and GC. If the laser is a chiplet optical engine (as described with reference to Figure 7A), the FAU is not required, and the light can be directed directly into the GC. The photonic network within the OMIB in Figures 5A–E allows for multiple optical paths. Figures 5A–E show a GC and FAU that band together to form an optical interface, but in implementations, any means may be used to interface the fiber with the photonic IC.

[0094] Figure 5A shows an example of an OMIB internal connection 500, illustrating the optical path starting from the optical engine 570. Figure 5A includes a first die 510 divided into a general-purpose section 510B which may include various processing, storage, and communication functions, and an AMS section 510A which includes analog / mixed signaling circuits for interfacing with the OMIB 530. Figure 5A further includes an optional substrate 540 and an optical engine 570. The AMS section 510A of the first die 510 may include a driver (DRV1) and a transimpedance amplifier (TIA1). The AMS section 520A of the second die 520 may include a driver (DRV2) and a transimpedance amplifier (TIA2).

[0095] The optical engine 570 transmits light into a splitter SP in the OMIB 530 via a fiber array unit FAU and a grating coupler GC (or any other OI configured to receive light at an OI input and pass the received light at an OI output). The splitter SP distributes the light to modulators MOD1 and MOD2 via two different photonic paths 531 and 532. In some implementation embodiments, the splitter or splitter tree distributes light via more than two different photonic paths to supply additional modulators. The photonic paths may be implemented in any suitable optical transmission medium and may include a mixture of waveguides and fibers.

[0096] Modulator MOD1 modulates the light received from splitter SP with information from driver DRV1 and transmits the modulated light to photodetector PD2 via photonic path 533. Photodetector PD2 converts the received light into an electrical signal for the second die 520. Modulator MOD2 modulates the light received from splitter SP with information from driver DRV2 and transmits the modulated light to photodetector PD1 via photonic path 534. Photodetector PD1 converts the received light into an electrical signal for the first die 510. In conjunction with the serializer (not shown) in the first die 510, driver DRV1, transimpedance amplifier TIA2, and deserializer (not shown) in the second die 520, modulator MOD1, photonic path 533, and photodetector PD1 form a data channel from the first die 510 to the second die 520.

[0097] The photonic IC OMIB530 includes a first interconnection region, a second interconnection region, and an offset region. The first interconnection region includes bond pad patterns located above MOD1 and PD1 that match bond pad patterns on the first die 510 located below DRV1 and TIA1, or otherwise are configured to form electrical connections between the respective components. The second interconnection region includes bond pad patterns located above PD2 and MOD2 that match bond pad patterns on the second die 520 located below TIA2 and DRV2, or otherwise are configured to form electrical connections between the respective components. The offset region, shown in detail in Figure 6, includes, for example, an optical interface such as GC / FAU. Two or more bond pads in the bond pad pattern on the first die 510 are physically and electrically coupled to two or more bond pads in the bond pad pattern within the first interconnection region, and two or more bond pads in the bond pad pattern on the second interconnection circuit are physically and electrically coupled to two or more bond pads in the bond pad pattern within the second interconnection region. One or more of the two or more bond pads on the first die 510 may be located more than 100 microns (100 μm) away from the edge of the first die 510. One or more of the two or more bond pads on the second die 520 may be located more than 100 microns (100 μm) away from the edge of the second die 520. The distance between the (bottom) surface of the first die 510 and the (top) surface of the OMIB 530 is less than 2 mm, and in many cases less than 50 microns. The distance between the (bottom) surface of the second die 520 and the (top) surface of OMIB530 is less than 2 mm, and in many cases less than 50 microns.

[0098] Figure 5B shows the same example, but with only the signal path visible. The path for unmodulated light is omitted. In Figure 5B, one signal path is shown in thick line as follows: The interface I / F in the first die 510 sends a digital signal carrying the information transmitted from the general-purpose section 510B of the first die 510 to the driver DRV1. The driver DRV1 converts the digital signal into an analog electrical signal suitable for driving a photonic modulator and sends the analog electrical signal to the modulator MOD1 in the OMIB530. The modulator MOD1 transmits the light modulated with the transmitted information to the photodetector PD2 via the photonic path 533. The photodetector PD2 converts the modulated light into a current signal and sends the current signal to the transimpedance amplifier TIA2, which amplifies the signal and converts it into a voltage signal suitable for the digital interface I / F2. The interface I / F2 converts the voltage into a digital signal suitable for processing in the general-purpose section 520B of the second die 520. Similarly, information transmitted from the general-purpose section 520B of the second die 520 to the general-purpose section 510B of the first die 510 travels via I / F2, DRV2, MOD2, photonic path 534, photodetector PD1, transimpedance amplifier TIA1, and interface I / F1.

[0099] Photonic paths 533 and 534 include waveguides or other suitable optical transmission media to carry optical signals from the modulator to the photodetector. The modulator in OMIB 530 is coupled to a driver in the AMS section of the first or second die via a copper column or other suitable electrical interconnect. The photodetector in OMIB 530 is coupled to a transimpedance amplifier in the AMS section of the first or second die via a copper column or other suitable electrical interconnect. The photonic paths in OMIB 530 may be unidirectional, and a pair of photonic paths in opposite directions may be included within a single bidirectional information channel.

[0100] An electrical interconnection is shown as providing coupling (or adjacent coupling) between elements in the AMS section and corresponding elements in the OMIB530. In one implementation embodiment, the interconnection is a copper column with a length of 2 millimeters or less. In other implementation embodiments, the electrical interconnection may be a solder bump formed of a material such as tin, silver, or copper. When a solder bump is used for the interconnection, the solder bump may be a flip-chip bump. In yet another implementation embodiment, the interconnection may be an element of a ball grid array (BGA), a pin grid array (PGA), a land grid array (LGA), or any other type of interconnection. In general, the interconnection can physically and electrically couple the AMS block to the OMIB530. For example, one or more interconnections may physically couple the pads of the die and the pads of the substrate 540 and / or the OMIB530, allowing electrical signals to pass between them. The interconnections 525 do not have to have a uniform size, shape, or pitch. To enable dense communication paths between elements coupled to an OMIB, fine-pitch interconnects may be desirable. In implementations, one or more sizes, shapes, pitches, or types of interconnects may differ from those shown in the figures or from other interconnects. The specific type, size, shape, or pitch of an interconnect may be based on one or more factors, such as use cases, materials used, design considerations, and manufacturing considerations.

[0101] Figure 5C shows an example of an OMIB interconnection. The unmodulated optical path is omitted. The first die 510 and the second die 520 can photonically communicate with the external device optical interface 571 via OMIB 580 and fiber 561. For example, the first die 510 may transmit to the external device optical interface 571 via I / F1, DRV1, MOD1, photonic path 581, an optional multiplexer MUX (if wavelength division multiplexing is desired), GC, FAU, and fiber 561. Conversely, the first die 510 may receive from the external device optical interface 571 via fiber 561, FAU, GC, photonic path 583, an optional demultiplexer DEMUX (if wavelength division multiplexing is desired), PD1, TIA1, and I / F1.

[0102] Figure 5D shows an example of a stacked die configuration. The AMS circuits (DRV1 and TIA1) are contained in the first AMS die 511A, and the general-purpose / digital circuits are contained in the first general-purpose die 511B. The first AMS die 511A is stacked on top of the OMIB 580 via an electrical interconnect 526A, and the first general-purpose die 511B is stacked on top of the first AMS die 511A via an electrical interconnect 526B. The OMIB 580 interfaces with the optical engine 570 and / or an external device optical interface 571 via a fiber 560, and may further interface with a second die 520.

[0103] Figure 5E shows a configuration in which the first general-purpose die 512B and the first AMS die 512A are stacked separately on the OMIB590 and arranged side by side. Signal transmission between the first general-purpose die 512B and the first AMS die 512A is possible (e.g., using UCIe, PCIe, or any suitable protocol) by an electrical interconnect, such as a bus. The electrical interconnect may include an electrical path 527A from TIA1 to I / F1 and an electrical path 527B from I / F1 to DRV1.

[0104] Figure 6 shows a perspective view 600 of an exemplary OMIB630 bridging two dies (a first die 610 and a second die 620) and coupled to an optical engine 670. The substrate 640 is optional. Each of the first die 610 and the second die 620 has an AMS block (first AMS section 610A and second AMS section 620A) in a region overlapping the OMIB630, such that the AMS block is adjacent to and / or stacked on the OMIB630, with the first die 610 coupled to the OMIB630 and the second die 630 coupled to the OMID630 via electrical connections. The interconnections can be made by copper columns or any other suitable electrical interconnections. The offset portion of the OMIB provides an offset region in which an OI and / or an external optical engine 670 may be located. The external optical engine 670 provides a light source for the photonic network via the OI. The external device optical interface 671 provides bidirectional communication with the die via a fiber between the OI and the external device optical interface 671. In Figure 6, the top surface of the OMIB 630 and the substrate 640 are shown as being substantially coplanar, but as previously stated, the OMIB 630 does not need to be coplanar with the surface of the substrate 640. The bottom surface of the first die 610 or the second die 620 may be physically and electrically coupled with the top surface of the OMIB 630. If the first part of the transceiver (modulator and / or PD in the OMIB 630) coincides with the second part of the transceiver (AMS section 610A or AMS section 620A), the OMIB 630 and the first die 610 or the second die 620 form an adjacent coupling.

[0105] Figure 7A shows a perspective view of an exemplary OMIB730 that bridges two dies and receives unmodulated light from a chiplet optical engine (CLE). The substrate 740 is optional. Each of the first die 710 and the second die 720 includes an AMS block (710A, 720A) in a region overlapping the OMIB730, such that the AMS block is on top of the OMIB730 and / or stacked on top of the OMIB730 in a configuration that couples the two dies to the OMIB730 via appropriate electrical interconnects (e.g., with the modulator located directly above the driver and the TIA located directly above the PD). The CLE is located in an offset region of the OMIB730. The CLE includes a laser which may be positioned parallel to the surface of the OMIB 730, a first optical component (e.g., a mirror 701 for reflecting the laser beam downward or to the side), and a second optical component (e.g., a lens 702 for focusing the laser beam into a small area), the first and second optical components which may be configured to rotate the light substantially by 90 degrees so that the light from the laser can be directed into the OMIB. Within the OMIB, the light can be incident on a waveguide running parallel to the surface of the OMIB, since it can be incident on a GC which includes a 90-degree mirror. An external device optical interface 771 communicates bidirectionally with the die via a fiber between the OI and the external device optical interface 771.

[0106] Figure 7B shows an exemplary package 700 in which the CLE775 can be used. The substrate 741 is optional. Optical signals are provided from the CLE775 via OMIB731 to a grating coupler CG1 (or any other means of interfacing between the fiber and the photonic IC) and a splitter SP, from where they are led to a first die 711 and a second die 721. OMIB731 also provides a bidirectional optical path between the dies. A second grating coupler CG2 and FAU, or other associated fiber connectors using any other means of interfacing between the fiber and the photonic IC, provide access to and from an external device optical interface 771. In some implementation embodiments, the CLE775 may be included in a CLE array. In further implementation embodiments, the CLE775 may include a semiconductor optical amplifier (SOA) or SOA array for amplifying the power of unmodulated light.

[0107] Figure 8A shows an exemplary OMIB830 having a photonic link capable of connecting two dies within a package, relating to several implementation configurations. The OMIB830 provides optical communication from each modulator (MOD1-4) in the first die 810 to each photodetector (PD1-4) in the second die 820. A waveguide system within the OMIB may bridge and / or enable connection between a transmitting unit (not shown) in the first die 810 and a receiving unit (not shown) in the second die 820. An optical engine 870, which may be inside or outside the OMIB830, outputs carrier light of a single wavelength ·a1. A splitter tree SPT can split the light having wavelength ·a1 through multiple optical paths (four are shown) leading to modulators MOD1-4. The modulators modulate the light having a single wavelength ·a1 and transmit the modulated light to the photodetectors PD1-4 through their respective waveguides. Figure 8A shows four links, each containing a modulator, a photonic path, and a photodetector. Each link may be part of a lane further containing a serializer and a deserializer. Multiple lanes may be combined into a single channel, which may be unidirectional or bidirectional.

[0108] Figure 8B shows one implementation configuration having two OMIBs 831 and 832 coupled between a first die 811 and a second die 821. The optical engine 870 outputs carrier light to a splitter tree SPT, which may split the light between multiple optical paths leading to modulators MOD1-4 associated with one or more photonic channels. For example, the first bidirectional photonic channel may include links MOD1 / PD1 and MOD2 / PD2, and the second bidirectional photonic channel may include links MOD3 / PD3 and MOD4 / PD4.

[0109] Figure 9 shows an exemplary system of a link using WDM for communication from a die to an external device, relating to several implementation configurations. In this example, the first die 910 and the external device are coupled via grating couplers GC and FAU in an OMIB 930 (or any other means for optical interface connection between the fiber and the photonic IC), an optical fiber 991, and an external device optical interface 971.

[0110] An optical engine 970, which may be internal or external, provides light of multiple wavelengths (e.g., 2 to 16 wavelengths) to the OMIB 930, for example, four wavelengths ·b1, ·b2, ·b3, ·b4 as shown. A splitter tree SPT (similar to the splitter tree SPT in Figure 8A, for example) may split the light of multiple wavelengths between multiple different channels or different links (e.g., two links, only one fully shown here), which may be in different OMIBs or different PICs. The carrier light of wavelengths ·b1, ·b2, ·b3, ·b4 is provided to optical modulators MOD1-4, which can modulate the four light beams with different portions of the information to be transmitted, and a WDM multiplexer (MUX) combines the four light beams into a single beam containing four different wavelengths. The single light beam is then transmitted to an external device optical interface 971 via the GC, FAU, and optical fiber 991.

[0111] Figure 10 shows an exemplary inverse channel for the WDM system of Figure 9, relating to several implementation configurations. An external device optical interface 971 provides the optical signal to a WDM demultiplexer (DEMUX) in the OMIB 930 via fiber 991, FAU, and GC. The WDM demultiplexer separates the optical signal into four separate modulated signals having wavelengths ·b1, ·b2, ·b3, and ·b4. These four signals are provided via their respective optical waveguides to photodetectors PD1-4, which are electrically interfaced with the first die 910 to provide information from the external device to the first die 910.

[0112] The above-described implementation is directed towards a photonic channel representing a WDM multiplexer receiving four unidirectional optical links and four different wavelengths; however, in other implementations, a WDM multiplexer receiving two or more optical links and two or more different wavelengths may be used. Accordingly, the WDM demultiplexer outputs two or more different wavelengths corresponding to these alternative implementations.

[0113] For example, as mentioned above, using intra-OMIB and inter-OMIB photonic channels, which generally include one or more links per direction, processors within an EIC (or more) in a single package can be connected within an electrophotonic network. The resulting network topology generally depends on the selection of pairs of dies coupled via the relevant photonic channels, and various topological examples are known in the art. However, this document generally refers to bidirectional photonic channels, which provide a network structure with greater flexibility for implementing ML and other computational models compared to unidirectional photonic channels, although it should be noted that electrophotonic networks can also be formed with unidirectional photonic channels, and such networks may retain any of the advantages discussed herein (e.g., power reduction through long-distance photonic data transfer).

[0114] As previously mentioned, a photonic channel can include at least two unidirectional sets of one or more links, and it is possible to create a bidirectional channel. Examples of such channels include, but are not limited to, a photonic channel between two dies when bridged by an OMIB, and a photonic channel between an OI on the OMIB and an external device optical interface. The nature of the external device optical interface may vary, as long as it has the optical capability to receive messages transmitted from the OMIB and / or transmit messages that can be received and used by the OMIB or any die using the OMIB as a bridge.

[0115] The message may be in the form of a variable-size packet. Figure 11 shows an exemplary one-way logical channel 1100 with multiple photonic links. The logical channel 1100 has an input link 1101, a transmit bonding engine 1102, photonic paths 1103A-D, a receive bonding engine 1104, and an output link 1105. The transmit bonding engine 1102 may split incoming data packets across the active photonic links and add sequence information. The receive bonding engine 1104 reassembles the data packets using the sequence information. In the illustrated example, the data reaches the receive bonding engines via four links.

[0116] Figure 12 shows the transmission of an exemplary 8-word message in the one-way logical channel 1100 of Figure 11. The message comprises words W0 to W7. The transmit bonding engine 1102 divides the word across four active photonic links. For example, the first link transmits words W0 and W4. The second link transmits words W1 and W5, and so on. The transmit bonding engine 1102 adds sequence information to each of the partial messages, and the receive bonding engine 1104 reassembles the entire message at its output. Bonding can enable the construction of a high-bandwidth, low-latency channel from multiple low-bandwidth links and may provide the ability to avoid non-functional links.

[0117] Figure 13 shows an exemplary AMS block in detail. Figure 13 shows the AMS transmit block 1310A for the first die and the AMS receive block 1320A for the second die. The AMS receive block 1315 for the first die and the AMS transmit block 1328 for the second die are not detailed in order to simplify the figure. Each of the AMS blocks 1310A and 1320A may be connected to the OMIB 1330 via one or more electrical interconnects (only interconnection 1314 for the AMS transmit block 1310A and interconnection 1321 for the AMS receive block 1320A are shown here). As shown in Figure 13, each link in the photonic channel comprises an optical transmit unit Tx, an optical receive unit Rx, and an optical transmission medium (e.g., an optical waveguide or fiber) connecting the transmit unit to the receive unit, in which case the AMS transmit block 1310A is coupled to the AMS receive block 1320A, and the AMS transmit block 1335 is coupled to the AMS receive block 1336. The transmit unit (e.g., transmit unit 1331) includes an optical modulator (e.g., optical modulator 1333) that modulates the carrier light output by the optical engine 1370 to add a message to the optical signal, and an electrical serializer (e.g., serializer 1313) that converts the electronic message received in parallel data words into a signal suitable for driving the optical modulator. The receiving unit (e.g., receiving unit 1332) includes a photodetector (e.g., photodetector 1334) for converting the optical signal received through the transmission medium back into an electrical signal, and associated electronic equipment including a transimpedance amplifier (e.g., TIA 1322) and gain controller (e.g., gain controller 1323) for normalizing the signal level, a slicer (e.g., slicer 1324) for extracting the bitstream, and a deserializer (e.g., deserializer 1325) for converting the received message back into parallel data.The AMS transmit block 1310A further includes a transmit bonding engine 1312 that can split messages from the first interface 1311 as detailed with reference to Figure 11, and the AMS receive block 1320A includes a receive bonding engine 1326 that reassembles messages for the second interface 1327 as detailed with reference to Figure 12. The OMIB 1330 may further include a receive block 1336 interfaced with the AMS receive block 1315, a transmit block 1335 interfaced with the AMS transmit block 1328, an optical engine 1370, an optical interface OI1, and an optical interface OI2.

[0118] In one implementation embodiment, the information is modulated at 56 Gb / s with a non-zero return (NRZ) code, but more spectrally efficient modulation schemes, such as PAM-4 or PAM-8 or higher-order pulse amplitude modulation, may be used to enable high-bandwidth, low-latency links.

[0119] Figure 14A shows the configuration of three OMIBs bridging parts of two dies. OMIB1430A bridges two computing elements 1411 in the first die 1410, the first portion of the central region 1412 in the first die 1410, two computing elements 1421 in the second die 1420, and the first portion of the memory region 1422 in the second die 1420. OMIB1430B bridges two computing elements 1421 in the second die 1420 and the second portion of the memory region 1422 in the second die 1420. OMIB1430C bridges two computing elements 1411 in the first die 1410, the second portion of the central region 1412 in the first die 1410, two computing elements 1421 in the second die 1420, and the third portion of the memory region 1422 in the second die 1420. The central region 1412 is located in the center of the first die 1410 to equalize latency between the computing elements 1411 and the central region 1412. The central region 1412 may include memory, cache memory, other shared memory, a network-on-chip crossbar, a switch, a routing mechanism, and a memory controller. The memory region 1422 is located in the center of the second die 1420 to equalize latency between the computing elements 1421 and the memory region 1422. The memory region 1422 may include cache memory, other shared memory, and a memory controller. The portion of the die bridged by the OMIB has 10 computing elements and 2 memory regions. Additional OMIBs (not shown) are located on the opposite side of the first die 1410 and the second die 1420 and may bridge additional dies, computing elements, and portions of memory regions. This configuration allows for the photonic routing of packets from the external device optical interface 1471 to an AMS block that is close to the memory being used or accessed and close to a location where the computing elements 1411 or 1421 can perform one or more calculations on the data in the memory area.The ability of OMIB to carry instructions from any computing element or external device, for example, to load or store data into memory region 1412 or 1422 using packets carried as photonic signals via OMIB into one of the dies 1410 or 1420, and / or to process the data on computing elements 1411 or 1421 adjacent to the central region 1412 or 1422, addresses many of the problems of strand memory and / or latency introduced when optical signals cannot extend beyond the edges of the die.

[0120] The AMS transmit and receive blocks can capture optical signals into the central region of any die (for example, to a memory controller to access memory in the central region) from any external device optical interface connected to the OMIB by an inter-OMIB link, or from AMS transmit and receive blocks having inter-OMIB connections in a bridge. The OI of each OMIB may, but is not required, be connected by fiber. A first side (e.g., the right side) of the AMS transmit block 1413 or AMS receive block 1414 is aligned with a first side (e.g., the left side) of the central region (e.g., central region 1412). The first side of the central region is in close proximity to and / or in contact with a computing element 1411, such as a CPU, GPU, or TPU. A second side (e.g., the left side) of the AMS transmit block 1413 or AMS receive block 1414 is aligned with the left side of the OMIB. Lateral alignment is approximate and does not need to be precise, but typically it is at least two-dimensional to allow for proximity between optical and electrical elements within the OMIB and AMS blocks, respectively.

[0121] Figure 14B shows an exemplary configuration of five dies 1410–1414 bridged by OMIBs. Using this configuration of package 1440, bridges can be added infinitely in two dimensions as needed. In this configuration, each OMIB has two interconnection regions for mounting dies. Since the L2 cache or other memory regions can be located and / or manufactured in the center of the die, the memory regions can be photonically reached into the interior of the die (rather than the edges), reducing latency. It is also possible to provide an optical channel between OMIBs by linking two OMIBs, for example, via optical fiber. The OI can be located within the offset region of the OMIB. The configuration in Figure 14B can be extended infinitely in the x and y directions. Furthermore, the configuration in Figure 14B can be routed through multiple hops in the diagonal direction, resulting in a further significant reduction in routing latency.

[0122] Figure 14C shows an exemplary configuration of dies 1413-1417 bridged by both the OMIB and the electrical bridge 1419. In some implementation embodiments, the OMIB and the electrical bridge are coupled to a single die.

[0123] As shown below, one OMIB can bridge four dies. For example, an OMIB can be used to bridge dies both vertically and horizontally, resulting in four interconnection areas in each OMIB corresponding to the four AMS blocks on each die. In this configuration, the OMIB can provide channels in six directions, including two horizontal, two vertical, and two diagonal directions.

[0124] Figure 14D shows an exemplary offset checkerboard of OMIBs bridging dies (1410, 1418) in two dimensions. Each OMIB has four interconnection areas, and it is possible to bridge the four dies using six links (two vertical links, two horizontal links, and two diagonal links) representing the six die-internal connections on each OMIB. Some dies, such as die 1418, may include a memory area. The AMS block may interface with the memory area, as well as any processing elements and other logic. However, Figure 14D may not be to a constant scale. An OMIB with dimensions similar to those of the dies being bridged can reach an AMS block near the center of the die. Also, the AMS block may be much smaller relatively than that shown in this example, and each die and each OMIB may have more than four interconnection areas.

[0125] Figure 15 is a flowchart illustrating an exemplary method 1500 for manufacturing an OMIB in various configurations. Method 1500 comprises the following operations.

[0126] Operation 1510 - Manufacturing a bridge including a photonic link from a first interconnection region to a second interconnection region, the photonic link including a first electrical interconnection, a modulator coupled to the first electrical interconnection, an optical transmission medium coupled to the modulator, a photodetector coupled to the optical transmission medium, and a second electrical interconnection. In some implementation embodiments, the modulator is configured to be thermally stabilized by applying a stabilization voltage to the modulator, the stabilization voltage being related to the die temperature, and the stabilization voltage inducing a change in dielectric absorption in the modulator.

[0127] Operation 1520 - Arrange interconnection regions to enable electrical interconnection and / or adjacent coupling with the AMS block within the die.

[0128] Operation 1530 - Manufactures an OMIB intra-connection between interconnection regions.

[0129] Operation 1540 - Manufactures an OMIB interconnection between two interconnection regions and an optical interface.

[0130] Figure 16 shows the components of an exemplary system 1600 in which one or more OMIBs may be used. Each component or group of components may include AMS blocks and interfaces for coupling with one or more OMIBs. For example, system 1600 may include a display device interface circuit, such as a connector, and a driver to which a display device 1606 may be coupled. In this case, the display device 1606 does not need to be integrated into system 1600 or be a component of system 1600. Similarly, system 1600 may not have an audio input device 1624 or an audio output device 1608, but may have an audio input or output device interface circuit, such as a connector and support circuit, for coupling with an external audio input device or an external audio output device.

[0131] System 1600 may include one or more processing devices 1602. Processing devices 1602 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), tensor processing units (TPUs), AI accelerators, fixed-gate programmable arrays (FPGAs), load / store units (LDSUs), neural computing engines (NCEs), dot product and / or convolution engines, server processors, or any other suitable processing devices. System 1600 may include memory 1604 which itself may include one or more memory devices, such as random access memory (RAM) devices (e.g., static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, or conductive bridge RAM (CBRAM) devices), logic devices (e.g., AND, OR, NAND, or NOR gates), NAND flash memory, solid state drive (SSD) memory, NOR flash memory, CMOS memory, thin-film transistor-based memory, phase-change memory (PCM), storage class memory (SCM), magnetoresistive memory (MRAM), resistive RAM, DRAM, high-bandwidth memory (HBM), DDR-based DRAM, and DIMM memory, but is not limited thereto. In some implementation embodiments, memory 1604 may include memory that shares a die with processing device 1602. This memory may be used as cache memory and may include embedded dynamic RAM or spin-shift torque magnetic RAM.

[0132] In some implementation embodiments, the system 1600 may include a communication chip 1612. For example, the communication chip 1612 may be configured to manage wireless communication for transferring data to and from a device.

[0133] The communication chip 1612 may implement any of a number of wireless standards or protocols, including, but not limited to, Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 group), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), the Long-Term Evolution (LTE) project, and any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compliant broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed conformity and interoperability testing related to the IEEE 802.16 standard. The communication chip 1612 may operate in accordance with Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Next Generation HSPA (E-HSPA), or LTE networks. The communication chip 1612 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Next Generation UTRAN (E-UTRAN). The communication chip 1612 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and their derivatives, as well as any other radio protocol designated as 3G, 4G, 5G, and later. The communication chip 1612 may operate in accordance with other radio protocols in other implementation embodiments. System 1600 may include an antenna 1622 for facilitating wireless communication and / or receiving other wireless communications (such as AM or FM radio transmissions).

[0134] In some implementations, the communication chip 1612 may manage wired communication, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet or USB). As described above, the communication chip 1612 may include multiple communication chips. For example, the first communication chip 1612 may be dedicated to short-range wireless communication, such as Wi-Fi or Bluetooth, and the second communication chip 1612 may be dedicated to long-range wireless communication, such as EDGE, GPRS, CDMA, WiMAX, LTE, or EV-DO. In some implementations, the first communication chip 1612 may be dedicated to wireless communication, and the second communication chip 1612 may be dedicated to wired communication.

[0135] System 1600 may include a battery / power supply circuit 1614. The battery / power supply circuit 164 may include one or more energy storage devices (e.g., batteries or capacitors) and / or a circuit for coupling components of System 1600 to an external energy source (e.g., an AC line power supply). System 1600 may include a display device 1606 (or a corresponding interface circuit as described above). The display device 1606 may include any visual indicator, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, flat panel display, virtual reality headset, augmented reality headset, etc. System 1600 may include an audio output device 1608 (or a corresponding interface circuit as described above). The audio output device 1608 may include any device that generates an audible indicator, such as a speaker, headset, earphone, vibrator, piezoelectric crystal, etc. System 1600 may include an audio input device 1624 (or a corresponding interface circuit as described above). The audio input device 1624 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (for example, an instrument with a pickup or instrument digital interface (MIDI) output).

[0136] System 1600 may include a positioning device 1618 (or a corresponding interface circuit) such as one compliant with a Global Positioning System (GPS), Galileo, GLONASS, BeiDou, IRNSS, NavIC, and / or QZSS. The positioning device 1618 may communicate with a satellite-based system as known in the art and may receive the position of System 1600. System 1600 may include another output device 1610 (or a corresponding interface circuit as described above). Examples of the other output device 1610 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. System 1600 may include another input device 1620 (or a corresponding interface circuit as described above). Other examples of input devices 1620 include accelerometers, gyroscopes, compasses, image acquisition devices, keyboards, cursor control devices such as mice, styluses, touchpads, barcode readers, quick response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0137] System 1600 may have any desired form factor, such as a handheld or mobile device (e.g., a mobile phone, smartphone, tablet computer, laptop computer, Internet of Things (IoT) device, netbook computer, ultrabook computer, mobile internet device, music player, personal digital assistant (PDA), ultramobile personal computer, etc.), a desktop electrical device, a server device or other network computing component, a printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable electrical device. In some implementation embodiments, System 1600 may be any other electronic device that processes data. Thermal behavior

[0138] The close spacing (less than 2 millimeters, often within 50 microns) between the EIC and PIC chiplets creates thermal challenges for the OMIB. Depending on the type of modulator used, the operating temperature range within specifications can be below 30 degrees Celsius. However, the die temperature of the EIC can vary more significantly depending on ambient temperature, load conditions, supply voltage, and other factors. Modulator types include Mach-Zehnder interferometers (MZI), ring modulators, and field absorption modulators (EAM). Ring modulators have a very narrow temperature range (less than 1 degree Celsius), while MZI and EAMs can have operating ranges exceeding 30 degrees Celsius. Both modulator temperature and bias voltage can affect the frequency (wavelength) at the modulator's efficiency peak. The laser wavelength may or may not be affected by these parameters. Therefore, temperature changes can create a difference between the laser wavelength and the modulator's efficiency peak wavelength, affecting the modulation depth.

[0139] The implementation may include a modulator that is essentially optimal over a desired temperature range. Alternatively, the implementation may provide temperature compensation, including temperature sensing or predictive capability. The temperature compensation may be fully integrated into the OMIB, or partially integrated into the OMIB and partially into the connecting die.

[0140] Figures 17A–D show examples of EIC / OMIB combinations that use temperature compensation to extend the temperature range of the modulator in the OMIB. Figure 17A shows the EIC1710 physically and electrically coupled to the PIC1720 (e.g., OMIB) via a metal interconnect such as a bump or copper column. The EIC1710 includes a driver DRV1711 and a temperature element TE1712. The TE1712 may include a temperature sensor, a temperature predictor, or both (the temperature predictor predicts the die or PIC temperature based on processor load conditions known in software or firmware). In some implementation embodiments, the temperature sensor is located less than 2 millimeters (2 mm) from the DRV1711. In further implementation embodiments, the temperature sensor is located within 50 microns (50 μm) from the DRV1711. The driver DRV1711 feeds a high data-rate modulated signal to the modulator 1721 in the PIC1720. The TE1712 supplies a low-frequency (relative to the data rate) temperature-dependent bias voltage to the MOD1721. If the temperature dependence of the bias voltage is inversely proportional to the temperature dependence of the modulator over an extended temperature range, the effect of temperature on modulator performance over the extended temperature range is canceled out. In a further implementation embodiment, the TE1712 includes a lookup table for converting measured or predicted temperatures into temperature-compensated modulator bias voltages.

[0141] In Figure 17B, the EIC1730 is physically and electrically coupled to the PIC1740 (e.g., OMIB). The EIC1730 includes a driver DRV1731, a temperature element TE1732, and an adder 1733. The PIC1740 includes a modulator MOD1741. The adder 1733 adds a low-frequency temperature-dependent bias voltage from the TE1732 to a high-data-rate modulated signal from the DRV1731 and transfers it to the MOD1741. In some implementation embodiments, the TE1732 includes a lookup table for converting a measured or predicted temperature to a temperature-compensated modulator bias voltage.

[0142] In Figure 17C, the EIC1750 is physically and electrically coupled to the PIC1760 (e.g., OMIB). The EIC1750 includes a driver 1751, and the PIC1760 (e.g., OMIB) includes a modulator MOD1761 and a temperature sensor TS1762. The TS1762 is located near the MOD1761 and supplies a temperature-dependent bias voltage to the MOD1761. The temperature dependence of the bias voltage is inversely proportional to the temperature dependence of the MOD1761 over an extended temperature range, thereby extending its operating temperature range.

[0143] In Figure 17D, the EIC1770 is physically and electrically coupled to the PIC1780 (e.g., OMIB). The PIC1780 includes a modulator MOD1781 and a temperature sensor TS1782. The TS has a temperature sensor output configured to be coupled to external circuitry (e.g., the EIC1770) of the PIC1780. The EIC1770 includes a driver DRV1771, a temperature controller TC1772, and an adder 1733. The TC1772 is configured to receive a first temperature-dependent signal from external circuitry (e.g., from TS1782 in the PIC1780). The TC1772 converts the first temperature-dependent signal into a temperature-dependent bias voltage whose temperature dependence is inversely proportional to the temperature dependence of the MOD1781 over an extended temperature range. The TC1772 may perform the conversion using temperature-linear and temperature-nonlinear analog circuits. Alternatively or additionally, the TC1772 may use digital circuitry to perform conversions to access memory 1774, which stores temperature profiles. The TC1772 may be included in a temperature element TE, such as the TE1732 in Figure 17B. In some implementation embodiments, the TC1772 includes a lookup table for converting measured or predicted temperatures into temperature-compensated modulator bias voltages.

[0144] Some modulators, when incorporated into, for example, an OMIB, can provide stable operation over a wide temperature range for the modulator for optical components without the need for additional temperature compensation. The modulator may utilize the Franz-Keldisch effect for electrically induced changes in light absorption. Various materials can be used for the modulator, including Group III-V materials such as germanium and its alloys, silicon and its alloys, and materials based on materials such as indium phosphide (InP) or gallium arsenide (GaAs). For example, one or more implementation embodiments described herein include chip hardware that includes features and functions to provide thermally stable optical modulators (or more) coupled to electronic elements (or more) (e.g., drivers in an AMS transmitter block). In one or more implementation embodiments, the hardware is a device including an electronic integrated circuit (EIC) and a photonic integrated circuit (PIC). The PIC may be electrically interconnected with the EIC by coupling or adjacent coupling. Each transmitter unit may include a thermally stable optical modulator in the portion residing within the PIC. Data may be optically transported within the PIC via an optical carrier between one of the thermally stable optical modulators in the first part of the OMIB and one of the receiving units located in or interconnected with the second part of the OMIB. In one or more implementation embodiments, the thermally stable optical modulators operate in a temperature range above 30 degrees Celsius. In this example, the thermally stable optical modulators may further include materials selected from the group including germanium, silicon, germanium alloys, silicon alloys, indium phosphide (InP)-based III-V materials, and gallium arsenide (GaAs)-based III-V materials. In one or more implementation embodiments, the optical modulator is an electric field absorption modulator (EAM) that utilizes the Franz-Keldisch effect for electrically induced changes in light absorption.

[0145] In one or more implementation embodiments, the thermally stable optical modulator is an EAM operating in a temperature range below 30 degrees Celsius. In this example, the thermally stable optical modulator may include (for example) germanium, silicon, germanium alloys, silicon alloys, indium phosphide (InP)-based Group III-V materials, and gallium arsenide (GaAs)-based Group III-V materials. In one or more implementation embodiments, the thermally stable optical modulator utilizes the quantum confinement Stark effect (QCSE) for electrically induced changes in light absorption. In one or more implementation embodiments, the thermally stable optical modulator has an output with a high optical modulation amplitude. In this example, the thermally stable optical modulator may include a material selected from the group including germanium, silicon, germanium alloys, silicon alloys, indium phosphide (InP)-based Group III-V materials, and gallium arsenide (GaAs)-based Group III-V materials. In one or more implementation embodiments, the thermally stable optical modulator utilizes the quantum confinement Stark effect (QCSE) for electrically induced changes in light absorption. In one or more implementation embodiments, the thermally stable optical modulator is configured for stable operation over a wide temperature range. In this example, the thermally stable optical modulator may include a material selected from the group including germanium, silicon, germanium alloys, silicon alloys, indium phosphide (InP)-based III-V materials, and gallium arsenide (GaAs)-based III-V materials. In one or more implementation embodiments, the modulator utilizes the Franz-Keldisch effect for electrically induced changes in light absorption. manufacturing

[0146] Figure 18 shows an exemplary method 1800 for manufacturing a system. Method 1800 comprises step 1810 of manufacturing a system including a first die (integrated circuit), a second die (integrated circuit), a photonic IC providing bridging functionality, a light source, and a data channel. The photonic IC includes a first interconnection region, a second interconnection region, and an offset region. Bond pad patterns on the first integrated circuit coincide with bond pad patterns in the first interconnection region, and bond pad patterns on the second integrated circuit coincide with bond pad patterns in the second interconnection region. Two or more bond pads on the first integrated circuit are physically and electrically coupled with two or more bond pads in the first interconnection region, and two or more bond pads on the second integrated circuit are physically and electrically coupled with two or more bond pads in the second interconnection region. The light source is optically coupled to a first optical interface (first OI) in the offset region. The data channel comprises a serializer and driver in the first integrated circuit, a modulator, a photonic path, and a photodetector in the photonic IC, and a transimpedance amplifier and deserializer in the second integrated circuit. The distance between the surface of the first integrated circuit and the surface of the photonic IC is less than 2 mm, and the distance between the surface of the second integrated circuit and the surface of the photonic IC is also less than 2 mm. Often, this distance is less than 50 microns (50 μm). At least one of two or more bond pads on the first integrated circuit may be located within 100 microns (100 μm) of the edge of the first integrated circuit. At least one of two or more bond pads on the second integrated circuit may be located within 100 microns (100 μm) of the edge of the second integrated circuit. The modulator may be an electric field absorption modulator (EAM). The modulator may be a Mach-Zehnder interferometer (MZI). The first die or photonic IC may include a temperature sensor or temperature predictor capable of supplying a temperature-dependent bias signal. Consideration

[0147] This description describes specific implementations, which are illustrative and not limiting. This description may refer to specific structural implementations and methods, and is not intended to limit the Art to the specifically disclosed implementations and methods. The Art may be carried out using other features, elements, methods, and implementations. The implementations are described for illustrative purposes and do not limit their scope as defined by the claims. Those skilled in the art will recognize various equivalent modifications to the above description.

[0148] For example, many examples in this book use grating couplers to couple the fiber to the photonic IC. However, many implementations function adequately using other means for optical interface connection between the fiber and the photonic IC, as illustrated with reference to Figure 3, for example. Many examples show only OMIBs bridging a first die and a second die, but OMIBs may bridge any number of dies. Many examples show AMS functionality contained in the first die and / or the second die, but AMS functionality may be partially or completely contained in separately stacked ICs, as shown, for example, in Figures 5D-E. All such implementations are within the scope and domain of the disclosed technology.

[0149] All features disclosed herein, including the claims, summary of the invention, and drawings, and all steps in any disclosed method or process, may be combined in any combination, except for any combination in which at least a portion of such features and / or steps are mutually exclusive. Each feature disclosed herein, including the claims, summary of the invention, and drawings, may be replaced by an alternative feature that serves the same, equivalent, or similar purpose, unless otherwise expressly stated.

[0150] This description has described specific implementations, but these specific implementations are merely illustrative and not limiting. For example, many of the operations may be implemented on a printed circuit board (PCB) using off-the-shelf devices, in a system-on-a-chip (SoC), application-specific integrated circuit (ASIC), programmable processor, coarse-grained reconfigurable architecture (CGRA), or programmable logic device such as a field-programmable gate array (FPGA), eliminating the need for at least some of any dedicated hardware. The implementation may be as a single chip or as a multi-chip module (MCM) that packages multiple semiconductor dies in a single package. All such variations and modifications are considered to be within the scope of the disclosed art, and their nature is determined from the above description.

[0151] Any suitable technique for manufacturing electronic devices may be used to implement circuits of specific implementation configurations, including CMOS, FinFET, BiCMOS, bipolar, JFET, MOS, NMOS, PMOS, HBT, MESFET, etc. Various semiconductor materials may be used, for example, silicon, germanium, SiGe, GaAs, InP, GaN, SiC, graphene, etc. The circuit may have single-ended or operating inputs and single-ended or operating outputs. The terminals of the circuit may function as inputs, outputs, or both, or may be in a high-impedance state, or may function to receive power supplies, ground references, reference voltages, reference currents, etc. The physical processing of signals may be presented in a specific order, but this order may be changed in different specific implementation configurations. In some specific implementation configurations, multiple elements, devices, or circuits shown sequentially herein may operate in parallel.

[0152] Specific implementations may be implemented using programmed general-purpose digital computers, application-specific integrated circuits, programmable logic devices, field-programmable gate arrays, optical, chemical, biological, quantum, or nanoengineering systems, etc. Other components and mechanisms may be used. In general, the functionality of a particular implementation may be realized by any means known in the art. Distributed, networked systems, components, and / or circuits may be used. Communication, data transmission, or transfer may be by wired, wireless, or any other means.

[0153] One or more of the elements shown in the drawings / figures may be implemented in a further divided or integrated manner to be useful according to a particular application, or may be excluded or made inoperable in a particular example.

[0154] Therefore, although specific implementations have been described herein, a degree of freedom for modification, various changes, and substitutions is intended in the above disclosure, and it is understood that in some cases, certain features of a particular implementation may be used without the use of corresponding other features without departing from the scope and intent described above. Accordingly, many modifications may be made to adapt a particular situation or material to its essential scope and intent.

Claims

1. Package substrate and A bridge element disposed within the package substrate that provides an optical bridge to the die, An analog / mixed signal (AMS) block coupled to the bridge element implements a data serialization and deserialization interface between the die and the bridge element, A photonic network arranged within the bridge element, including multiple photonic paths, One or more modulators located within the bridge element, which are optically coupled to the photonic network and electrically coupled to the AMS block via a first set of one or more electrical interconnections, One or more photodetectors, positioned within the bridge element, are optically coupled to the photonic network and electrically coupled to the AMS block via a second set of one or more electrical interconnections. A multiplexer located within the bridge element, optically coupled to one or more modulators via the photonic network and further optically coupled to an optical interface via the photonic network, configured to multiplex a first group of individual signals received from one or more modulators into a first group of data channels and transmit them to the optical interface via a first optical path, wherein each data channel in the first group of data channels is defined by the multiplexer by its own wavelength, A demultiplexer located within the bridge element, optically coupled to one or more photodetectors via the photonic network and further optically coupled to the optical interface via the photonic network, configured to demultiplex a multiplexed signal received from the optical interface via a second photonic path, the multiplexed signal comprising a second group of data channels, demultiplexing the multiplexed signal into a second group of individual signals, the individual signals being transmitted to one or more photodetectors via the photonic network, and each data channel of the second group of data channels being defined by a unique wavelength, The AMS block is aligned with the bridge element, and the length of each electrical interconnect of the first and second electrical interconnect group is less than 2 mm, in the package.

2. The package according to claim 1, wherein the AMS block includes a serializer and a deserializer, the serializer and the deserializer are each connected to a die via a digital interface.

3. The package according to claim 2, wherein the digital interface includes either UCIe (Universal Chiplet Interconnect Express) or PCIe (Peripheral Component Interconnect Express).

4. The package according to claim 2, wherein the digital interface includes an electrical path located at least partially within the AMS block or the bridge element.

5. The package according to claim 1, wherein the optical interface includes any of the following: edge couplers, grating couplers, distributed refractive index lens couplers, fiber Bragg grating couplers, microlens array couplers, evanescent wave couplers, adiabatic couplers, wavelength division multiplexing couplers, prism couplers, butt couplers, end-fire couplers, or V-groove couplers.

6. The package according to claim 5, wherein the optical interface further includes a fiber array unit optically coupled to the grating coupler.

7. The package according to claim 5, wherein the optical interface provides an optical connection to an external device.

8. The package according to claim 7, wherein the external device includes either an optical engine or an electrical device.

9. The package according to claim 1, wherein the bridge element further includes a redistribution layer.

10. The package according to claim 9, wherein the redistribution layer includes one or more electrical interconnects or through-glass vias provided between the die and the bridge element.

11. The package according to claim 1, wherein the AMS block is aligned with the die, and the data serialization and deserialization interface is accessible from an arithmetic element or memory area located in the central region of the die.

12. The package according to claim 1, wherein the package substrate includes one of a printed circuit board, an interposer, or a motherboard.

13. The package according to claim 1, wherein the central region of the die is located at a distance of less than 2 mm from the AMS block.

14. The package according to claim 1, wherein the one or more modulators include one of a Mach-Zehnder interferometer, an electric field absorption modulator, or a ring modulator.

15. The package according to claim 1, wherein one or more modulators are configured to modulate using either a non-zero return method or a pulse amplitude modulation method.

16. The package according to claim 1, wherein the AMS block further includes a modulator driver.

17. The package according to claim 1, wherein the AMS block further includes a transmit bonding engine and a receive bonding engine.

18. The package according to claim 1, wherein the AMS block further includes a transimpedance amplifier.

19. The package according to claim 1, wherein the AMS block further includes a slicer.

20. The package according to claim 1, wherein the AMS block further includes a gain controller.

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