Imaging device

Abstract

To provide an imaging device with improved signal-to-noise ratio and dynamic range. [Solution] The imaging device comprises a pixel, an amplification circuit electrically connected to the pixel which amplifies the pixel signal and reset signal, each of which are analog signals read from the pixel, at one of a plurality of amplification rates and outputs the result, an AD conversion circuit electrically connected to the amplification circuit which converts the output from the amplification circuit into a digital signal, and a determination circuit electrically connected to the pixel which compares the level of the pixel signal with at least one threshold. Based on the comparison result between the level of the pixel signal and at least one threshold, the determination circuit sets the amplification rate of the amplification circuit to one of a plurality of amplification rates. The amplification circuit amplifies the pixel signal and the reset signal at the set single amplification rate.

Description

[Technical Field]

[0001] This disclosure relates to an imaging device. [Background technology]

[0002] In recent years, proposals have been made to achieve a wide dynamic range in imaging devices such as CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal-Oxide-Semiconductor) image sensors.

[0003] Patent Document 1 discloses a photoelectric converter having a plurality of analog signal output units that output analog signals based on a plurality of pixels, and a plurality of signal processing units. Each of the plurality of signal processing units is provided in correspondence with one of the plurality of analog signal output units and includes a gain application unit that applies a gain to the analog signal and an AD conversion unit. The gain application unit outputs either a first amplified signal obtained by applying a first gain of 1 or less to the analog signal, or a second amplified signal obtained by applying a second gain lower than the first gain to the analog signal. The AD conversion unit performs AD conversion on the first amplified signal or the second amplified signal output from the gain application unit. The signal processing unit has a determination unit. Based on the result of comparing the first amplified signal with a threshold, the determination unit provides either the first amplified signal or the second amplified signal to the AD conversion unit. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2014-131147 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] Imaging devices require improvements in signal-to-noise ratio (S / N) and dynamic range. [Means for solving the problem]

[0006] In one exemplary, non-limiting embodiment, the imaging apparatus of the present disclosure includes: a pixel; an amplification circuit electrically connected to the pixel, which amplifies and outputs a pixel signal and a reset signal, each being an analog signal, read from the pixel, at one of a plurality of amplification rates; an AD conversion circuit electrically connected to the amplification circuit, which converts the output from the amplification circuit into a digital signal; and a determination circuit electrically connected to the pixel, which compares the level of the pixel signal with at least one threshold, wherein the determination circuit sets the amplification rate of the amplification circuit to one of the plurality of amplification rates based on the comparison result between the level of the pixel signal and the at least one threshold, and the amplification circuit amplifies the pixel signal and the reset signal at the set one amplification rate.

[0007] In one other exemplary embodiment, not limited thereto, the imaging apparatus of the present disclosure comprises: a pixel; an AD conversion circuit electrically connected to the pixel, which converts a pixel signal and a reset signal, each being an analog signal, read from the pixel, into digital signals; a reference signal generation circuit for generating and outputting a lamp signal, which is a reference signal; an amplification circuit electrically connected to the reference signal generation circuit for amplifying the lamp signal at one of a plurality of amplification factors and outputting it; and a determination circuit electrically connected to the pixel for comparing the level of the pixel signal with at least one threshold, wherein the AD conversion circuit includes a comparison circuit for comparing the levels of the pixel signal and the reset signal with the amplified lamp signal output from the amplification circuit; the determination circuit sets the amplification factor of the amplification circuit to one of the plurality of amplification factors based on the comparison result of the level of the pixel signal with the at least one threshold; and the amplification circuit amplifies the lamp signal at the one amplification factor set by the determination circuit during the period for converting the pixel signal and the reset signal into digital signals.

[0008] In yet another exemplary aspect, which is not limiting, the imaging device of the present disclosure includes a pixel, an AD conversion circuit that converts an analog signal output from the pixel into a digital signal, a determination circuit electrically connected to the pixel that compares the level of the analog signal with at least one threshold value, and a holding circuit that holds the comparison result between the level of the analog signal and the at least one threshold value.

Advantages of the Invention

[0009] According to one aspect of the present disclosure, an imaging device with improved S / N and dynamic range is provided.

Brief Description of the Drawings

[0010] [Figure 1] FIG. 1 is a block diagram schematically showing an example of the configuration of an imaging device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram schematically showing an example of the configuration of a pixel. [Figure 3] FIG. 3 is a circuit diagram showing an example of the circuit configuration of a pixel. [Figure 4] FIG. 4 is a circuit diagram showing another example of the circuit configuration of a pixel. [Figure 5] FIG. 5 is a block diagram schematically showing the configuration of a conversion circuit according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is a block diagram schematically showing another configuration of the conversion circuit according to the first embodiment of the present disclosure. [Figure 7A] FIG. 7A is a circuit diagram showing a comparator according to the first configuration example at the functional block level. [Figure 7B] FIG. 7B is a circuit diagram showing a comparator according to the first configuration example at the symbol level. [Figure 7C] FIG. 7C is a circuit diagram showing a comparator according to the first configuration example at the transistor level. [Figure 7D] FIG. 7D is a diagram showing the relationship between a pixel signal, which is an input signal to the comparator, and an output signal. [Figure 8A]Figure 8A is a circuit diagram showing the comparator according to the second configuration example at the functional block level. [Figure 8B] Figure 8B is a circuit diagram showing the comparator according to the second configuration example at the symbol level. [Figure 8C] Figure 8C is a circuit diagram showing the comparator according to the second configuration example at the transistor level. [Figure 8D] Figure 8D shows the relationship between the pixel signal, which is the input signal of the comparator, and the output signal. [Figure 9A] Figure 9A is a circuit diagram showing the comparator according to the third configuration example at the functional block level. [Figure 9B] Figure 9B is a circuit diagram showing the comparator according to the third configuration example at the symbol level. [Figure 9C] Figure 9C is a circuit diagram showing the comparator according to the third configuration example at the transistor level. [Figure 9D] Figure 9D shows the relationship between the pixel signal, which is the input signal of the comparator, and the output signal. [Figure 10A] Figure 10A is a circuit diagram showing an attenuator according to the first configuration example. [Figure 10B] Figure 10B is a circuit diagram showing an attenuator according to the second configuration example. [Figure 11A] Figure 11A is a schematic diagram showing a first configuration example of the holding circuit. [Figure 11B] Figure 11B shows the truth table for a latch circuit. [Figure 12] Figure 12 is a schematic diagram showing a second configuration example of the holding circuit. [Figure 13] Figure 13 is a timing chart showing an example of the operation procedure of an imaging device equipped with the conversion circuit shown in Figure 5. [Figure 14] Figure 14 is a timing chart illustrating another example of the operation procedure of an imaging device equipped with the conversion circuit shown in Figure 5. [Figure 15] Figure 15 is a schematic diagram showing the relationship between the range, threshold, and attenuation rate of the pixel signal of an imaging device according to the first embodiment of this disclosure. [Figure 16]Figure 16 is a schematic diagram showing the relationship between the pixel signal range, threshold, attenuation rate, and non-operating range of the source follower circuit of an imaging device according to the first embodiment of this disclosure. [Figure 17] Figure 17 is a schematic block diagram showing a modified example of the conversion circuit according to the first embodiment of this disclosure. [Figure 18A] Figure 18A is a circuit diagram showing an example of the configuration of an attenuator in a modified example of the conversion circuit according to the first embodiment of this disclosure. [Figure 18B] Figure 18B is a circuit diagram showing another configuration example of an attenuator in a modified example of the conversion circuit according to the first embodiment of this disclosure. [Figure 19] Figure 19 is a schematic diagram showing the relationship between the range, threshold, and attenuation rate of the pixel signal in a modified example of the conversion circuit according to the first embodiment of this disclosure. [Figure 20] Figure 20 is a schematic block diagram showing the configuration of a conversion circuit according to the second embodiment of this disclosure. [Figure 21A] Figure 21A is a circuit diagram showing an example configuration of an attenuator according to the second embodiment of this disclosure. [Figure 21B] Figure 21B is a circuit diagram showing another configuration example of an attenuator according to the second embodiment of this disclosure. [Figure 22] Figure 22 is a timing chart showing an example of the operation procedure of the imaging device according to the second embodiment of this disclosure. [Figure 23] Figure 23 is a timing chart showing another example of the operation procedure of the imaging apparatus according to the second embodiment of this disclosure. [Figure 24] Figure 24 is a schematic diagram showing the relationship between the pixel signal range, threshold, and AD conversion gain of an imaging device according to the second embodiment of this disclosure. [Figure 25] Figure 25 is a schematic block diagram showing a modified example of the conversion circuit according to the second embodiment of this disclosure. [Figure 26] Figure 26 is a schematic diagram showing the relationship between the pixel signal range, threshold, and AD conversion gain in a modified example of the conversion circuit according to the second embodiment of this disclosure. [Figure 27]Figure 27 schematically shows an example of the configuration of a camera system according to the third embodiment of this disclosure. [Modes for carrying out the invention]

[0011] <Knowledge that forms the basis of this disclosure> Generally, the pixel signal output from a pixel is an analog signal. If the range of the analog-to-digital (AD) conversion is smaller than the maximum range (or full range) of the pixel signal, the pixel signal needs to be attenuated to fit within the AD conversion range. On the other hand, attenuating the pixel signal increases the noise in the post-AD conversion processing relative to the pixel signal. Therefore, using an attenuator can reduce the signal-to-noise ratio (S / N) for subjects in darkness or low light. Here, the ratio of the noise level to the voltage level of the pixel signal is generally called the "S / N ratio" or simply "S / N".

[0012] To address the above issues, the inventors of this invention focused on a configuration that switches the attenuation rate of an attenuator according to the magnitude of the voltage level of the pixel signal (hereinafter referred to as "pixel signal level"), and arrived at a novel imaging device that can attenuate both the pixel signal and the reset signal at the same attenuation rate according to the magnitude of the pixel signal level. According to one aspect of the imaging device of this disclosure, it is possible to perform AD conversion of the pixel signal at the maximum range of the pixel signal while avoiding S / N degradation in low light conditions. As a result, the dynamic range can be improved. Furthermore, since the time required for AD conversion is also shortened, the technology of this disclosure can also contribute to increased speed.

[0013] From another perspective, in a typical single-slope AD conversion circuit, the resolution of the AD conversion is controlled by the slope of the reference signal Vramp. For example, when the signal level is relatively high, AD conversion is performed using a reference signal Vramp that changes by 1V in a predetermined time, and when the signal level is relatively low, AD conversion is performed using a reference signal Vramp that changes by 250mV in a predetermined time. In the former case, the AD conversion gain is 0dB, and in the latter case, the AD conversion gain is 12dB. By changing the AD conversion gain according to the signal level in this way, AD conversion is performed appropriately with a constant bit width.

[0014] When the AD conversion gain is low, large signals can be converted using the AD converter, but the resolution decreases. As a result, quantization noise increases. Conversely, when the AD conversion gain is high, quantization noise can be suppressed. However, the signal range that can be handled becomes smaller.

[0015] To address the above challenges, the inventors focused on a configuration in which AD conversion is performed with a relatively low AD conversion gain when the pixel signal level is greater than a threshold, and with a relatively high AD conversion gain when the pixel signal is less than a threshold. With such a configuration, it is possible to perform AD conversion of the pixel signal over its maximum range while suppressing quantization noise and avoiding S / N degradation in low light conditions. As a result, the dynamic range can be improved.

[0016] An overview of one aspect of this disclosure is as follows:

[0017] [Item 1] Pixels and An amplification circuit electrically connected to the aforementioned pixel, which amplifies the pixel signal and reset signal, each of which are analog signals, read from the pixel, by one of a plurality of amplification rates and outputs the result. An AD conversion circuit electrically connected to the aforementioned amplification circuit, which converts the output from the amplification circuit into a digital signal, A determination circuit electrically connected to the pixel and comparing the level of the pixel signal with at least one threshold, Equipped with, The determination circuit sets the amplification factor of the amplification circuit to one of the plurality of amplification factors based on the comparison result between the level of the pixel signal and the at least one threshold. The amplification circuit amplifies the pixel signal and the reset signal with the set amplification factor. Imaging device.

[0018] [Item 2] Pixels and An AD conversion circuit electrically connected to the aforementioned pixel, which converts the pixel signal and reset signal, each of which are analog signals, read from the aforementioned pixel into digital signals; A reference signal generation circuit that generates and outputs a lamp signal, which is a reference signal, An amplification circuit electrically connected to the aforementioned reference signal generation circuit, which amplifies the lamp signal at one of a plurality of amplification rates and outputs it, A determination circuit electrically connected to the pixel and comparing the level of the pixel signal with at least one threshold, Equipped with, The AD conversion circuit includes a comparison circuit that compares the levels of the pixel signal and the reset signal with the amplified ramp signal output from the amplification circuit. The determination circuit sets the amplification factor of the amplification circuit to one of the plurality of amplification factors based on the comparison result between the level of the pixel signal and the at least one threshold. The amplification circuit amplifies the lamp signal by the single amplification factor set by the determination circuit during the period in which the pixel signal and the reset signal are converted into digital signals. Imaging device.

[0019] [Item 3] The imaging device according to item 1 or 2, wherein the determination circuit includes an inverter circuit.

[0020] [Item 4] The inverter circuit includes an N-type MOS transistor and a P-type MOS transistor. The imaging apparatus according to item 3, wherein the W / L ratio of the N-type MOS transistor is 1 / 2 or more of the W / L ratio of the P-type MOS transistor.

[0021] [Item 5] The imaging apparatus according to any one of items 1 to 4, further comprising a holding circuit for holding the comparison result of the determination circuit.

[0022] [Item 6] The imaging apparatus according to item 5, wherein the holding circuit includes a switch electrically connected between the pixel and the inverter circuit.

[0023] [Item 7] The imaging apparatus according to item 5, wherein the holding circuit includes a latch electrically connected downstream of the inverter circuit.

[0024] [Item 8] The imaging apparatus according to item 1 or 2, wherein the determination circuit includes a differential amplifier.

[0025] [Item 9] The system further comprises a signal processing circuit that receives the digital signal output from the AD conversion circuit, The imaging apparatus according to any one of items 1 to 8, wherein the signal processing circuit applies a correction process to the digital signal according to the comparison result of the determination circuit.

[0026] [Item 10] The aforementioned determination circuit is a first determination circuit, A second determination circuit electrically connected to the pixel compares the level of the pixel signal with at least one other threshold different from the at least one threshold, A first holding circuit is electrically connected to the first determination circuit and the amplification circuit, and holds the comparison result of the first determination circuit, A second holding circuit is electrically connected to the second determination circuit and the amplification circuit, and holds the comparison result of the second determination circuit, The imaging apparatus described in item 1 or 2, further comprising:

[0027] [Item 11] The imaging apparatus according to any one of items 1 to 10, wherein the pixel includes a pixel electrode, a counter electrode facing the pixel electrode, and a photoelectric conversion layer located between the pixel electrode and the counter electrode.

[0028] [Item 12] The imaging device according to any one of items 1 to 11, wherein the pixel outputs the reset signal after outputting the pixel signal during a 1-frame period.

[0029] [Item 13] Pixels and A determination circuit electrically connected to the pixel compares the level of the analog signal output by the pixel with at least one threshold value. A holding circuit that holds the result of comparing the level of the analog signal with the at least one threshold, An imaging device equipped with the following features.

[0030] Embodiments of this disclosure will be described in detail below with reference to the drawings. The embodiments described below are either comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, processing content, and processing sequence shown in the following embodiments are examples only and are not intended to limit this disclosure. The various embodiments described herein can be combined with each other as long as they do not conflict. Furthermore, components in the following embodiments that are not described in an independent claim representing the highest-level concept will be described as optional components. In the following description, components having substantially the same function will be indicated by a common reference numeral and their description may be omitted.

[0031] <Overall configuration of the imaging device> First, the overall configuration of the imaging device according to the embodiment of this disclosure will be described with reference to Figure 1. Figure 1 is a schematic block diagram showing an example of the configuration of the imaging device according to the embodiment of this disclosure. The imaging device 200 shown in Figure 1 is, for example, a solid-state imaging device having a so-called stacked configuration, which will be described later. However, the imaging device 200 may be a solid-state imaging device such as a CMOS image sensor. The imaging device 200 includes a pixel unit 201, a vertical scanning circuit 202, a horizontal transfer scanning circuit 203, a reference signal generation circuit 204, a drive control circuit 205, a column processing unit 206, a plurality of vertical signal lines 212, a horizontal signal line 213, and an amplifier circuit 214.

[0032] The pixel unit 201 includes a plurality of pixels 10 arranged in a matrix. Each pixel 10 generates a signal charge of a magnitude corresponding to the intensity of the incident light by photoelectric conversion of the incident light, and generates pixel signals VSIG0 to VSIGp (where p is an integer of 1 or more), which are electrical signals, based on the signal charge. The pixel signals are an example of signals dealt with in the embodiments of this disclosure. Details of the pixels 10 will be described later.

[0033] The vertical scanning circuit 202 is configured to control row address and row scanning. The vertical scanning circuit 202 generates pixel control signals such as VSEL or VRST, which will be described later, and outputs them to the pixel unit 201.

[0034] Each of the multiple vertical signal lines 212 is provided for each column and is connected to a pixel located in the corresponding column of the multiple pixels 10. More specifically, each vertical signal line 212 transmits the pixel signals VSIG0 to VSIGp output from the pixel 10 located in the corresponding column of the multiple pixels 10 (columns 0 to p) to the column processing unit 206.

[0035] The column processing unit 206 includes a plurality of column circuits 207. Each column circuit 207 is provided for each row of a plurality of pixels 10. The column processing unit 206 generates image data based on digital signals corresponding to pixel signals output from each pixel 10. Each column circuit 207 includes a load current circuit 215 and a conversion circuit 220. Each column circuit 207 is connected to the vertical signal line 212 of the corresponding row. The load current circuit 215 supplies load current to the vertical signal line 212 of the corresponding row when a pixel signal is transmitted to the vertical signal line 212. The load current circuit 215 forms a source follower circuit together with the vertical signal line 212 and the pixel amplification transistors described later. Each column circuit 207 in the embodiments of this disclosure further includes a counter 209 and a memory 211, described later.

[0036] The reference signal generation circuit 204 generates a reference signal Vramp and supplies the generated reference signal Vramp to each of the multiple conversion circuits 220. In the embodiments of this disclosure, the reference signal Vramp is at least a monotonically increasing or monotonically decreasing ramp signal. The ramp signal indicates the time change of a voltage value that changes at a predetermined rate of change (slope). The conversion circuit 220 compares the reference signal Vramp with the pixel signal transmitted from the pixel 10 to the vertical signal line 212. The configuration and operation of the conversion circuit 220 will be described in detail later.

[0037] The horizontal transfer scanning circuit 203 is configured to control column addressing and column scanning. The horizontal signal line 213 sequentially transmits multiple digital signals generated in the column processing unit 206 for each column. The amplifier circuit 214 is connected to the column processing unit 206 via the horizontal signal line 213. The digital signals for each column are amplified by the amplifier circuit 214 via the horizontal signal line 213, starting with the digital signals corresponding to the pixel signals output from the pixels of the column selected by the horizontal transfer scanning circuit 203, and then output to the outside of the imaging device.

[0038] The imaging apparatus 200 according to the embodiment of this disclosure further comprises a signal processing circuit 208 that receives the digital signal output from the conversion circuit 220. However, the signal processing circuit 208 is not essential. The signal processing circuit 208 may be implemented by a microcontroller including one or more processors and memory. The signal processing circuit 208 may include a dedicated logic circuit that performs the processing described later. The signal processing circuit 208 may be configured to apply correction processing to the digital signal according to the comparison result of the determination circuit described later. For example, as described later, the signal processing circuit 208 may correct the AD conversion value by applying shift correction to the AD conversion value according to the attenuation rate of each pixel.

[0039] The drive control circuit 205 generates signals to drive each circuit inside the imaging device 200. Based on the master clock signal input from the MCLK terminal and data signals for various settings input from the DATA terminal, the drive control circuit 205 generates various internal clocks in a single batch and supplies the generated internal clocks to each circuit inside the imaging device 200. For example, the drive control circuit 205 supplies a control signal CN to the vertical scanning circuit 202. The vertical scanning circuit 202 operates according to this control signal CN.

[0040] <Pixel and conversion circuit configuration> An example of the configuration of pixel 10 will be explained with reference to Figures 2 to 4.

[0041] Figure 2 is a schematic diagram showing an example of the configuration of a pixel 10. Figure 3 is a circuit diagram showing an example of the circuit configuration of the pixel 10. The pixel 10 illustrated in Figure 2 comprises a photoelectric conversion unit 18 including a pixel electrode 12, a counter electrode 13 facing the pixel electrode 12, and a photoelectric conversion layer 11 located between the pixel electrode 12 and the counter electrode 13. The photoelectric conversion unit 18 converts incident light into photoelectric energy. The pixel electrode 12 and the counter electrode 13 are a pair of electrodes stacked on the photoelectric conversion layer 11 so as to sandwich the photoelectric conversion layer 11. Thus, the pixel 10 shown in Figure 2 is a stacked photoelectric conversion element. However, the pixel in the embodiments of this disclosure is not limited to a stacked photoelectric conversion element. The photoelectric conversion layer 11 receives incident light and generates excitons, for example, pairs of holes and electrons. The pixel electrode 12 collects one of the generated hole-electron pairs as a signal charge. For example, a voltage is supplied to the counter electrode 13 such that a potential difference is created between the pixel electrode 12 and the counter electrode 13, and based on this potential difference, one of the hole-electron pairs is collected by the pixel electrode 12.

[0042] Pixel 10 includes a charge storage unit (hereinafter referred to as "floating diffusion: FD") that stores the signal charge converted by the photoelectric conversion unit 18. The FD is provided within the semiconductor substrate 15. The pixel electrode 12 and the FD are electrically connected via a contact plug 14. The signal charge collected by the pixel electrode 12 is stored in the FD.

[0043] Pixel 10 includes a readout circuit provided on the semiconductor substrate 15. The readout circuit of pixel 10 shown in Figure 3 includes an amplification transistor M1, a selection transistor M2, and a reset transistor M3. The amplification transistor M1 amplifies the pixel signal according to the magnitude of the charge stored in FD. The selection transistor M2 selects whether or not to output the pixel signal amplified by the amplification transistor M1 to the vertical signal line 212. In this way, a pixel signal corresponding to the potential of FD is output to the vertical signal line 212. The reset transistor M3 resets FD to a desired reset voltage V1.

[0044] Figure 4 is a circuit diagram showing another example of the circuit configuration of pixel 10. The pixel 10 shown in Figure 4 includes a photodiode PD as a photoelectric conversion unit, and further includes a transfer transistor M4 for transferring the signal charge generated in the photodiode PD to the FD. Thus, the photoelectric conversion unit may be configured using a photoelectric conversion film or using a photodiode. When pixel 10 includes a photodiode PD, it may further include a transistor for discharging the signal charge generated in the photodiode PD. By using this transistor, multiple exposure becomes possible.

[0045] The exposure of multiple pixels 10 in the pixel section 201 may be global shutter driven or rolling shutter driven. In the embodiment of this disclosure, the pixel 10 outputs a reset signal after outputting a pixel signal VSIG during one frame period. The pixel signal VSIG read out by the readout circuit of the pixel 10 is transmitted to the conversion circuit 220 via the vertical signal line 212.

[0046] <First Embodiment> The conversion circuit according to the first embodiment of this disclosure will be described with reference to Figures 5 to 15.

[0047] [1. Configuration of the conversion circuit] Figure 5 is a schematic block diagram showing the configuration of a conversion circuit 220a according to the first embodiment of the present disclosure. The conversion circuit 220a illustrated in Figure 5 includes a comparator 240, an attenuator 250, a comparator 260, a holding circuit 270, a capacitor C1, and a cramp.

[0048] Comparator 240 and attenuator 250 are electrically connected to pixel 10 via vertical signal line 212, and the pixel signal VSIG from pixel 10 is input. The input terminal of the holding circuit 270 is connected to the output terminal of comparator 240. The output terminal of the holding circuit 270 is connected to signal line 222. The output signal DOUT2 from the holding circuit 270 is output to the outside of the conversion circuit 220 via signal line 222. Furthermore, the output terminal of the holding circuit 270 is also connected to attenuator 250. One end of capacitor C1 is connected to the output terminal of attenuator 250, and the other end of capacitor C1 is connected to the input terminal of comparator 260. One end of capacitor Cramp is connected to reference signal generation circuit 204, and the other end of capacitor Cramp is connected to another input terminal of comparator 260.

[0049] The output terminal of the holding circuit 270 is connected to the counter 209 (see Figure 1) via the signal line 222, and the output terminal of the comparator 260 is connected to the counter 209 via the signal line 221. The output terminal of the comparator 260 may be connected to the memory 211 via the signal line 221 instead of the counter 209, or to both the counter 209 and the memory 211. Furthermore, in the example shown in Figure 5, the holding circuit 270 is located inside the conversion circuit 220a, but it may be located inside the counter 209 or the memory 211.

[0050] Figure 6 is a schematic block diagram showing another configuration of the conversion circuit according to the first embodiment of the present disclosure. As shown in Figure 6, the output terminal of the holding circuit 270 may be connected to the input terminal of the comparator 240. In other words, the holding circuit 320 may be connected before the comparator 310.

[0051] [2. Comparator (judgment circuit)] The comparator 240 is electrically connected to the pixel 10 and is configured to compare the level of the pixel signal VSIG with at least one threshold. The comparator 240 may include an inverter circuit, as described later. Based on the comparison result between the level of the pixel signal VSIG and at least one threshold, the comparator 240 sets the amplification factor of the attenuator 250 to one of a plurality of amplification factors.

[0052] In this embodiment, the comparator 240 is configured to compare the pixel signal VSIG of the corresponding column with a predetermined threshold and output the comparison result. As the comparator 240, the comparators according to the first to third configuration examples described below can be used. Note that the configurations described below are just examples, and there are no particular limitations as long as the configuration can compare the pixel signal VSIG with a predetermined threshold.

[0053] (2.1. First example of comparator configuration) Figure 7A is a circuit diagram showing the comparator 240a according to the first configuration example at the functional block level. Figure 7B is a circuit diagram showing the comparator 240a according to the first configuration example at the symbol level. Figure 7C is a circuit diagram showing the comparator 240a according to the first configuration example at the transistor level. As shown in Figures 7A to 7C, the comparator 240a is an inverter-type comparator. The comparator 240a is composed of two inverter circuits 242 and 243. Hereafter, the inverter circuit will simply be referred to as "inverter".

[0054] Comparator 240a comprises inverters 242 and 243 connected in series. The pixel signal VSIG is input to inverter 242, and the output signal from inverter 242 is input to inverter 243. Inverter 243 outputs the output signal DOUT1. The number of inverters connected in series is not limited to the two exemplified, but may be one or three or more. The drive capability can be improved by increasing the number of inverters.

[0055] As shown in Figure 7C, inverter 242 includes a P-type MOS transistor 242a and an N-type MOS transistor 242b. Inverter 243, like inverter 242, includes a P-type MOS transistor 243a and an N-type MOS transistor 243b.

[0056] Figure 7D shows the relationship between the pixel signal VSIG, which is the input signal to comparator 240a, and the output signal DOUT1. The upper part (a) of Figure 7D shows the relationship between the pixel signal VSIG and the number of accumulated charges in FD, and the lower part (b) of Figure 7D shows the relationship between the pixel signal VSIG and the output signal DOUT1.

[0057] In this specification, a logical change in the level of a digital signal from Low to High may be simply described as "the signal level changes to High." Similarly, a logical change in the level of a digital signal from High to Low may be simply described as "the signal level changes to Low."

[0058] As shown in the upper part (a) of Figure 7D, when light incident on the FD, signal charges are generated and accumulated in the FD. As the number of accumulated charges in the FD increases, the pixel signal VSIG also increases. Furthermore, as shown in the lower part (b) of Figure 7D, when the pixel signal VSIG increases and exceeds the threshold voltage VTH0, the level of the output signal DOUT1 logically changes from Low to High. For example, the output signal DOUT1 changes from a digital value of zero to a digital value of 1. Therefore, as the number of accumulated charges in the FD gradually increases and the pixel signal VSIG exceeds the threshold voltage VTH0, the level of the output signal DOUT1 from comparator 240a logically changes from Low to High. Thus, when the voltage level of the pixel signal VSIG input to comparator 240a is greater than or equal to the threshold voltage VTH0, the output signal DOUT1 becomes High, and conversely, when the voltage level of the pixel signal VSIG is less than the threshold voltage VTH0, the output signal DOUT1 becomes Low. The threshold voltage VTH0 is the threshold voltage of the inverter 242 and is determined by the characteristics of the P-type MOS transistor 242a and the N-type MOS transistor 242b. Specifically, the threshold voltage VTH0 is determined by the following equation (1). VTH0 = (Vhigh - |Vtp| + Vtn·(β_n / β_p) 1 / 2 ) / (1 + (β_n / β_p) 1 / 2 ) (1) Here, Vhigh is the voltage applied to the source of the P-type MOS transistor 242a, Vtp is the threshold voltage of the P-type MOS transistor 242a, and Vtn is the threshold voltage of the N-type MOS transistor 242b. Also, β_p and β_n are constants defined by equations (2) and (3) below. β_p = (W_p / L_p)·μ_p·C_ox (2) β_n = (W_n / L_n)·μ_n·C_ox (3) Here, W_p is the gate width of the P-type MOS transistor 242a, L_p is the gate length of the P-type MOS transistor 242a, and μ_p is the carrier mobility of the P-type MOS transistor 242a. W_n is the gate width of the N-type MOS transistor 242b, L_n is the gate length of the N-type MOS transistor 242b, and μ_n is the carrier mobility of the N-type MOS transistor 242b. C_ox is the capacitance per unit volume of the gate oxide film of the P-type MOS transistor 242a and the N-type MOS transistor 242b, respectively.

[0059] The inverter 243 is designed, for example, based on equations (1) to (3), so that the threshold voltage of the inverter 243 becomes a desired threshold voltage VTH0. For example, the desired threshold voltage VTH0 can be obtained by optimally designing the gate width and gate length of the P-type MOS transistor 243a and the N-type MOS transistor 243b, respectively. Also, taking inverter 242 as an example, the effective gate width or gate length can be adjusted by providing multiple P-type MOS transistors 242a and N-type MOS transistors 242b in parallel or in series. The gate width or gate length of inverter 243 can also be adjusted in a similar manner to inverter 242.

[0060] The inverter-type comparator 240a according to the first configuration example has the advantage of being compact and power-efficient because it can be constructed with a small number of transistors.

[0061] (2.2. Second example of comparator configuration) Figure 8A is a circuit diagram showing the comparator 240b according to the second configuration example at the functional block level. Figure 8B is a circuit diagram showing the comparator 240b according to the second configuration example at the symbol level. Figure 8C is a circuit diagram showing the comparator 240b according to the second configuration example at the transistor level. As shown in Figures 8A to 8C, the comparator 240b is an inverter threshold-changing type comparator. The comparator 240b is composed of two inverters 243 and 244. The comparator 240b has a configuration in which inverter 242 is replaced with inverter 244, whose threshold voltage can be changed, in the comparator 240a according to the first configuration example.

[0062] Comparator 240b comprises inverters 244 and 243 connected in series. The pixel signal VSIG is input to inverter 244, and the output signal from inverter 244 is input to inverter 243. A control signal V0 is also applied to inverter 244. In inverter 244, the threshold voltage is changed by the control signal V0. Note that inverter 243 is not essential in the configuration shown in Figure 8. Also, the number of inverters 243 is not limited to one, but may be two or more.

[0063] As shown in Figure 8C, the inverter 244 includes one P-type MOS transistor 242a, two N-type MOS transistors 242b, and one transistor 244a. The inverter 244 has a configuration that adds one N-type MOS transistor 242b and one transistor 244a to the inverter 242 in the first implementation example.

[0064] In inverter 244, two N-type MOS transistors 242b are connected in parallel to the drain of a P-type MOS transistor 242a. Of the two N-type MOS transistors 242b, the pixel signal VSIG is directly applied to the gate of one N-type MOS transistor 242b without going through transistor 244a, while the pixel signal VSIG is applied to the gate of the other N-type MOS transistor 242b via transistor 244a. The conduction and non-conduction of transistor 244a are switched by the control signal V0. The control signal V0 is output, for example, from the drive control circuit 205.

[0065] Figure 8D shows the relationship between the pixel signal VSIG, which is the input signal of comparator 240b, and the output signal DOUT1. The upper part (a) of Figure 8D shows the relationship between the pixel signal VSIG and the number of accumulated charges in FD, and the lower part (b) of Figure 8D shows the relationship between the pixel signal VSIG and the output signal DOUT1.

[0066] In comparator 240b, the basic relationship between the pixel signal VSIG and the output signal DOUT1 is as explained with reference to Figure 7D. It differs from comparator 240a in the first configuration example in that the threshold voltage can be changed to threshold voltage VTH0 or threshold voltage VTH1 by switching the level of the control signal V0 between High and Low.

[0067] In the second configuration example, the decision level of comparator 240b can be changed by the control signal V0. As shown in Figure 8D, when the level of control signal V0 is Low, the number of accumulated charges in FD gradually increases, and when the pixel signal VSIG exceeds the threshold voltage VTH0, the level of the output signal DOUT1 of comparator 240b logically changes from Low to High. For example, the output signal DOUT1 changes from a digital value of zero to a digital value of 1. When the level of control signal V0 is Low, transistor 244a is in a non-conducting state, so the pixel signal VSIG is applied to only one of the two N-type MOS transistors 242b. As a result, the threshold voltage VTH0 of inverter 244 is the same as the threshold voltage of inverter 242 in the first configuration example.

[0068] When the level of the control signal V0 is High, the number of accumulated charges in FD gradually increases, and when the pixel signal VSIG exceeds the threshold voltage VTH1, the level of the output signal DOUT1 of comparator 240b logically changes from Low to High. When the level of the control signal V0 is High, the transistor 244a is in a conducting state, so the pixel signal VSIG is applied to both of the two N-type MOS transistors 242b. As a result, the gate width W_n of the N-type MOS transistor 242b effectively increases. Therefore, the threshold voltage of inverter 244 changes from threshold voltage VTH0 to threshold voltage VTH1, as can be seen from equations (1) to (3) above. In this way, it is possible to change the threshold voltage of comparator 240b according to the control signal V0.

[0069] In the example shown in Figures 8A to 8C, two N-type MOS transistors 242b were provided in parallel, but the number of transistors is not limited to two. For example, three or more N-type MOS transistors 242b may be provided in parallel, and two or more control transistors 244a may also be provided. This makes it possible to realize a configuration in which the threshold voltage can be changed to three or more different values. Alternatively, two or more P-type MOS transistors 242a may be provided in parallel instead of N-type MOS transistors 242b. Furthermore, two or more N-type MOS transistors 242b or P-type MOS transistors 242a may be connected in series. In this case, the threshold voltage of the inverter 244 can be changed by changing the effective gate length with the control signal V0.

[0070] (2.3. Third example of comparator configuration) Figure 9A is a circuit diagram showing the comparator 240c according to the third configuration example at the functional block level. Figure 9B is a circuit diagram showing the comparator 240c according to the third configuration example at the symbol level. Figure 9C is a circuit diagram showing the comparator 240c according to the third configuration example at the transistor level. As shown in Figures 9A to 9C, the comparator 240c is a differential amplifier type comparator and is composed of a differential amplifier 245 to which a reference signal VTH2, whose voltage value can be changed, is input. The pixel signal VSIG and the reference signal VTH2 are input to the two input terminals of the differential amplifier 245, respectively. The reference signal VTH2 is output from, for example, the drive control circuit 205.

[0071] Figure 9D shows the relationship between the pixel signal VSIG, which is the input signal to comparator 240c, and the output signal DOUT1. The upper part (a) of Figure 9D shows the relationship between the pixel signal VSIG and the number of accumulated charges in FD, and the lower part (b) of Figure 9D shows the relationship between the pixel signal VSIG and the output signal DOUT1.

[0072] As shown in Figure 9D, as the number of accumulated charges in the FD gradually increases and the level of the pixel signal VSIG exceeds the level of the reference signal VTH2, the level of the output signal DOUT1 from comparator 240c logically changes from Low to High. For example, the output signal DOUT1 changes from a digital value of zero to a digital value of one.

[0073] In the third configuration example, the judgment level of the comparator 240c can be changed by changing the reference signal VTH2. When the level of the pixel signal VSIG is less than the threshold level of the reference signal VTH2, the level of the output signal DOU1 becomes Low, and when the level of the pixel signal VSIG is equal to or greater than the level of the reference signal VTH2, the level of the output signal DOUT1 becomes High. In this way, by using the differential amplifier 245, the threshold for determining the pixel signal VSIG can be flexibly set.

[0074] [3. Attenuator (Amplifier Circuit)] In this embodiment, the attenuator 250 is electrically connected to the pixel 10. The attenuator 250 is configured to amplify the pixel signal and reset signal, each of which are analog signals, read from the pixel 10, by one of several amplification factors and output the result. The attenuator 250 configured in this way exemplifies an amplification circuit. The attenuator 250 amplifies each of the pixel signal and the reset signal by a single amplification factor set by the comparator 240. The comparator 240 exemplifies a decision circuit. The operation of the attenuator 250 will be described later. As the attenuator 250, the attenuators according to the first and second configuration examples described below can be used. Note that the configuration of the attenuator described below is just an example, and is not particularly limited as long as it can attenuate the pixel signal VSIG.

[0075] (3.1. First example of attenuator configuration) Figure 10A is a circuit diagram showing an attenuator 250a according to the first configuration example. The attenuator 250a comprises capacitors Ca and Cb, switches S1 and S2, and an inverter 224. Switch S1 is connected to the output terminal of the inverter 224 via signal line 223. Switch S2 is connected to signal line 222. The on / off state of switch S1 is controlled by the output signal from the inverter 224, and the on / off state of switch S2 is controlled by the output signal DOUT2 from the holding circuit 270. With this connection, the on / off state of the two switches S1 and S2 is controlled selectively. When switch S1 is on and switch S2 is off, the voltage value of the pixel signal VSIG is output directly to signal line 251 as the output signal AOUT. When switch S1 is off and switch S2 is on, the voltage value obtained from the voltage division ratio of (capacitance of Cb) / (capacitance of Ca + capacitance of Cb) based on the voltage value of the pixel signal VSIG is output as output signal DOUT2 from signal line 222.

[0076] (3.2. Second example of attenuator configuration) Figure 10B is a circuit diagram showing attenuator 250b according to the second configuration example. The configuration example shown in Figure 10B is a configuration in which capacitance Ca is replaced with resistor Ra and capacitance Cb is replaced with resistor Rb in the configuration example shown in Figure 10A. When switch S1 is off and switch S2 is on, the voltage value obtained from the voltage division ratio of (resistance of Rb) / (resistance of Ra + resistance of Rb) based on the voltage value of the pixel signal VSIG is output as output signal VOUT2 from signal line 222. Note that in the examples of Figures 10A and 10B, control signals of different polarities are applied to switch S1 and switch S2 using inverter 224, but inverter 224 is not essential. For example, comparator 240 may generate an inverted signal of output signal DOUT1 and input it to attenuator 250.

[0077] [4. Comparator] In this embodiment, the comparator 260 is electrically connected to the attenuator 250. The analog signal output from the attenuator 250 is converted into a digital signal by the comparator 260 and the subsequent counter 209. The comparator 260 compares the pixel signal VSIG of the corresponding column, which is input via either switch S1 or S2 of the attenuator 250 and capacitor C1, with the reference signal Vramp, which is input via capacitor Cramp, and outputs the comparison result. The output terminal of the comparator 260 is connected to the subsequent counter 209 via signal line 221.

[0078] [5.Holding circuit] In the example shown in Figure 5, the holding circuit 270 is connected downstream of the comparator 240, while in the example shown in Figure 6, the holding circuit 270 is connected upstream of the comparator 240. The holding circuit 270 holds the comparison result or pixel signal VSIG output from the comparator 240.

[0079] As the holding circuit 270, the holding circuits according to the first and second configuration examples described below can be used. Note that the configuration of the holding circuit described below is just one example, and is not particularly limited as long as it can hold the comparison result of the comparator 240 or the pixel signal VSIG.

[0080] (5.1. First example of a holding circuit configuration) Figure 11A is a schematic diagram showing a first configuration example of the holding circuit. The holding circuit 270 in the first configuration example is a D-type latch circuit. In the D-type latch circuit 271, as shown in the truth table in Figure 11B, for example, when the control signal CNT supplied from the drive control circuit 205 is High, the output Q is determined based on the input to terminal D, and when the control signal CNT is Low, the output Q is unaffected by the input to terminal D, and the output Q before the control signal CNT went Low is retained. In the first configuration example, it is desirable that the input to terminal D is a High or Low level voltage, so as shown in Figure 5, the holding circuit 270 is connected downstream of the comparator 240. In the example in Figure 5, the holding circuit 270 includes a latch circuit 271 electrically connected downstream of the comparator 240, which includes an inverter circuit.

[0081] In the example shown in Figure 10A or Figure 10B, instead of signal line 223, signal line 225, which is connected to the output terminal Q# of the holding circuit 270, may be connected to switch S1. In this case, the output signal from output terminal Q# is used as the control signal for switch S1.

[0082] (5.2. Second example of the holding circuit configuration) Figure 12 is a schematic diagram showing a second configuration example of the holding circuit. The holding circuit 270 in the second configuration example includes a switch S4 and a capacitor Cd. When the level of the control signal CNT is High, switch S4 is turned on and the voltage of the pixel signal VSIG is charged to capacitor Cd, and when the level of the control signal CNT is Low, switch S4 is turned off and the voltage of the pixel signal VSIG is held in capacitor Cd (the input node of comparator 240). When the second configuration example is adopted, it is preferable that the impedance of the stage after the holding circuit 270 is large, so as shown in Figure 6, the holding circuit 270 is connected before the comparator 240. In this example, the holding circuit 270 includes a switch S4 that is electrically connected between the pixel 10 and the comparator 240.

[0083] [6. AD Conversion Operation] Referring again to Figure 1, the operation of the AD conversion by the conversion circuit 220 in the imaging device 200 according to the embodiment of this disclosure will be explained. The imaging device 200 according to the embodiment of this disclosure is a column-parallel AD conversion type image sensor. When imaging is performed with the imaging device 200, the light incident on the imaging device 200 is converted into a pixel signal, which is an electrical signal, in the pixel unit 201.

[0084] The exposure, readout, and other operations of each of the multiple pixels 10 in the pixel unit 201 are controlled row by row by row by row by row by row by row by row. The pixel signals VSIG0 to VSIGp generated in the multiple pixels 10 belonging to the row selected by row by row by row by row by row are simultaneously output to row by row by row. At this time, each of the multiple load current circuits 215 (or source follower circuits) supplies load current to the corresponding row of row by row.

[0085] Referring to Figure 5, the operation of the conversion circuit 220 in performing AD conversion on the pixel signal VSIG will be explained in detail.

[0086] The comparator 260 compares the reference signal Vramp output by the reference signal generation circuit 204 with the pixel signal VSIG of the column corresponding to the comparator 260. The counter 209 starts counting at a timing corresponding to the start timing of the ramp signal and counts the time until the relative magnitude relationship between the level of the pixel signal VSIG and the level of the reference signal Vramp reverses. As a result, the analog signal pixel signal VSIG is converted into a digital signal corresponding to the count value of the counter 209. The comparator 260 and the counter 209 function as an AD conversion circuit. The comparator 260 and the counter 209 in this embodiment of the disclosure exemplify an AD conversion circuit. The pixel signal VSIG of each column is converted from an analog signal to a digital signal by the AD conversion circuit of each column.

[0087] The digital signals output from the AD conversion circuit are stored in the memory 211 contained in the column circuit 207 of each column. The digital signals stored in the memory 211 of each column are output sequentially from the column selected by the horizontal transfer scanning circuit 203 via the amplifier circuit 214.

[0088] The comparator 240 compares a predetermined threshold voltage with the level of the pixel signal VSIG of the corresponding column. The comparator 240 outputs a High or Low voltage signal to the signal line 222 indicating whether the level of the pixel signal VSIG is above the predetermined threshold. For example, the comparator 240 outputs a logically High level signal if the level of the pixel signal VSIG is above the predetermined threshold, and outputs a logically Low level signal if the magnitude of the pixel signal VSIG is below the predetermined threshold. Of course, it goes without saying that the logic can also be reversed.

[0089] If the level of the pixel signal VSIG is above a predetermined threshold, the attenuator 250 attenuates the input pixel signal VSIG to 1 / N (where N is 1 or greater) and outputs it to the next stage. The operation of the attenuator 250 will be explained in detail later.

[0090] [7. Operation of the entire imaging device] As mentioned earlier, generally, if the AD conversion range is smaller than the maximum range (or full range) of the pixel signal output from a pixel, it is necessary to attenuate the pixel signal so that it fits within the AD conversion range. On the other hand, attenuating the pixel signal increases the noise in the post-AD conversion processing relative to the pixel signal. Therefore, using an attenuator can degrade the signal-to-noise ratio (S / N) when dealing with dark or low-light subjects.

[0091] In this embodiment, if the level of the pixel signal exceeds a threshold, attenuation processing is applied to the pixel signal before AD conversion. If the level of the pixel signal falls below the threshold, the pixel signal is not attenuated and is maintained at its original level before AD conversion. The imaging device according to this embodiment makes it possible to perform AD conversion on the pixel signal at the maximum range of the pixel signal while avoiding S / N degradation in low light conditions. This can improve the dynamic range. Furthermore, since the time required for AD conversion is also shortened, the imaging device according to this embodiment also contributes to higher speed.

[0092] The operation of the imaging device 200 according to this embodiment will be explained with reference to the timing chart in Figure 13.

[0093] Figures 13 and 14 are timing charts illustrating examples of the operation procedure of an imaging device 200 equipped with the conversion circuit 220a shown in Figure 5. Figure 13 shows examples of each signal waveform when the level of the pixel signal VSI Gp exceeds the threshold of the comparator 240. In describing the operation procedure of the imaging device 200, each of the multiple pixels 10 is a stacked photoelectric conversion element. The comparator 240 of the conversion circuit 220a has the configuration shown in Figure 7A, the attenuator 250 has the configuration shown in Figure 10A, and the holding circuit 270 has the configuration shown in Figure 11A.

[0094] A horizontal synchronization signal HD, which is a pulse signal, is input to the pixel unit 201 from the vertical scanning circuit 202. Imaging of the nth row of the pixel unit 201 begins at the timing of the rising edge of the horizontal synchronization signal HD. A selection signal VSELn is input to the gate of the selection transistor M2 (see Figure 3) contained in each of the multiple pixels 10 in the nth row. The selection transistor M2 is turned on during the period when the selection signal VSELn is HIGH, and a pixel signal corresponding to the potential of FD is output to the vertical signal line 212.

[0095] When the selection transistor M2 is turned on, the pixel signal VSIG is read out to the vertical signal line 212, causing the potential of the vertical signal line 212 to begin changing. The timing chart in Figure 13 shows the threshold VTH of the comparator 240 along with the pixel signal VSIG. In this embodiment, the threshold VTH is set to, for example, half of the saturation signal voltage of the pixel 10.

[0096] The reset control signal VRSTn is input to the gate of the reset transistor M3 (see Figure 3) contained in each of the multiple pixels 10 in the nth row. During the period when the reset control signal VRSTn is high, the reset transistor M3 is turned on, and the potential of FD is reset to the reset voltage V1.

[0097] As shown in Figure 11A, a control signal CNT that controls the latch operation is input to the latch circuit 271. When the level of the control signal CNT is High, the output Q is determined based on the input to terminal D. When the level of the control signal CNT is Low, the output Q is not dependent on the input to terminal D, and the output Q from before the level of the control signal CNT became Low is retained.

[0098] The timing chart in Figure 13 shows the time variation of the output signal AOUT from the attenuator 250 (potential change across signal line 251), the time variation of the output signal DOUT1 from the comparator 240, and the time variation of the output signal DOUT2 from the holding circuit 270 (potential change across signal line 222). The output signal DOUT2 is input to the attenuator 250 and controls the on / off state of switch S2 shown in Figure 10A. The time variation of the inverted signal of output signal DOUT2 (potential change across signal line 223), output from the inverter 224 of the attenuator 250, is also shown. The inverted signal of output signal DOUT2 controls the on / off state of switch S1.

[0099] First, at time t0, the level of the horizontal sync signal HD changes from Low to High, and imaging of the pixel group in the nth row of the pixel unit 201 begins. At time t1, the level of the horizontal sync signal HD changes from High to Low.

[0100] Next, at time t2, the selection signal VSELn becomes high, the selection transistor M2 turns on, and the pixel signal VSIG for the nth row is output to the vertical signal line 212. Also, the control signal CNT becomes high, and the holding circuit 270 operates in an operating mode that outputs an output value based on the pixel signal VSIG.

[0101] Next, at time t3, when the level of the pixel signal VSIG exceeds the threshold VTH of the comparator 240, the output signal DOUT1 from the comparator 240 becomes High. As a result, the inverted signal of the output signal DOUT2, which was High when the level of the pixel signal VSIG was below the threshold VTH, becomes Low, and the state of switch S1 of the attenuator 250 changes from On to Off. Then, the output signal DOUT2, which was Low when the level of the pixel signal VSIG was below the threshold VTH, becomes High, and the state of switch S2 of the attenuator 250 changes from Off to On. In this state, the pixel signal VSIG input to the attenuator 250 undergoes attenuation processing, and as a result, the voltage level of the output signal AOUT from the attenuator 250 becomes capacitance Cb / (capacitance Ca + capacitance Cb) times the voltage level of the pixel signal VSIG.

[0102] In this embodiment, capacitances Ca and Cb are the same. In this case, the attenuation rate of the attenuator 250 becomes 1 / 2. By applying attenuation processing to the pixel signal VSIG according to the level of the pixel signal VSIG, the pixel signal VSIG can be kept within the voltage range of the AD conversion circuit.

[0103] Next, at time t4, the reference signal generation circuit 204 starts generating the reference signal Vramp. During the period from time t4 to time t5, the comparator 260 compares the voltage corresponding to the reference signal Vramp with the output signal AOUT from the attenuator 250, and the counter 209 continues counting until the output levels of both match. Also at time t4, the control signal CNT goes low, and the holding circuit 270 holds the current output value. The holding circuit 270 holds the output value until the control signal CNT goes high again. As a result, the output signal DOUT2 remains high and does not change.

[0104] Next, at time t5, the reset control signal VRSTn applied to the nth row pixel 10 becomes high, and the reset operation of the nth row pixel 10 is initiated by the reset transistor M3. Subsequently, at time t6, when the potential level of the vertical signal line 212 corresponding to the reset signal level falls below the threshold VTH of the comparator 240, the level of the output signal DOUT1 changes from high to low. At this time, since the level of the control signal CNT remains low, the output signal DOUT2 from the holding circuit 270 does not change.

[0105] Next, at time t7, the reset control signal RSTn changes from High to Low, and the reset operation is completed. Also at time t7, the reference signal generation circuit 204 starts generating the reference signal Vramp. During the period from time t7 to time t9, the comparator 260 compares the voltage corresponding to the reference signal Vramp with the reset signal, and the counter 209 continues counting until the output levels of both match.

[0106] Next, at time t10, the horizontal synchronization signal HD becomes high, and the imaging device 200 proceeds to read out the pixel 10 of the (n+1)th row.

[0107] Thus, during the period when the selection signal VSELn is High, the comparator 260 performs the first comparison between the level of the pixel signal VSIG and the level of the reference signal Vramp. Then, after the reset operation is completed, the comparator 260 performs a second comparison between the reset signal and the reference signal Vramp.

[0108] Figure 14 shows examples of signal waveforms when the level of the pixel signal VSIG is below the threshold of comparator 240. Below, we will mainly explain the differences from the case where the pixel signal VSIG is above the threshold of comparator 240, as described above.

[0109] In the timing chart shown in Figure 14, the level of the pixel signal VSIG read from pixel 10 is lower than the threshold VTH of comparator 240. As a result, the output signal DOUT1 from comparator 240 remains low, and consequently, the output signal DOUT2 from the holding circuit 270 and the output signal from inverter 224 of attenuator 250 (the inverted signal of output signal DOUT2) remain low and high, respectively. Therefore, switch S1 of attenuator 250 turns on and switch S2 turns off. Consequently, the pixel signal VSIG is not attenuated by attenuator 250, and an output signal AOUT corresponding to the voltage level of the pixel signal VSIG is output from attenuator 250.

[0110] As explained above, if the level of the pixel signal VSIG exceeds the threshold VTH of the comparator 240, the attenuator 250 attenuates the pixel signal VSIG, and if the level of the pixel signal Vsig falls below the threshold VTH of the comparator 240, the attenuator 250 does not attenuate the pixel signal VSIG. By operating the conversion circuit 220 according to the aforementioned operation sequence, it becomes possible to perform AD conversion of the pixel signal VSIG at the maximum range of the pixel signal while avoiding S / N degradation in low light conditions, thereby improving the dynamic range.

[0111] The comparison result between the level of the pixel signal VSIG and the threshold of the comparator 240 can be provided to either or both of the subsequent counter 209 and memory 211. For example, the signal processing circuit 208 inside the imaging device 200 or a camera signal processing unit externally connected to the imaging device (described later) may correct the AD conversion value by shifting the AD conversion value according to the attenuation rate of each pixel so that the level of the pixel signal VSIG of each pixel 10 matches the magnitude of the AD conversion value.

[0112] In this embodiment, the pixel configuration and operation sequence read out a pixel signal corresponding to the intensity of incident light, followed by a pixel reset and the readout of a reset signal. By first reading out the pixel signal and determining the attenuation rate of the attenuator based on the relationship between the pixel signal level and the comparator threshold, it becomes possible to read out the subsequent reset signal with the same attenuation rate. By using the same attenuation rate for both the pixel signal reading and the reset signal reading, it is possible to improve the signal-to-noise ratio (S / N) without generating unnecessary offsets in post-AD conversion processing. In contrast, when using a pixel configuration and operation sequence that reads out the reset signal first, it is difficult to use the same attenuation rate for both the pixel signal reading and the reset signal reading because the pixel signal level is unknown at the time the reset signal is read out.

[0113] Table 1 shows the theoretical noise values ​​when the attenuation rate of the attenuator is switched according to the level of the pixel signal, according to the pixel configuration and operation sequence in this embodiment. In Table 1, high-level signals refer to pixel signals at a level greater than the threshold VTH of comparator 240, and low-level signals refer to pixel signals at a level less than the threshold VTH of comparator 240. For simplicity of explanation, we assume that there are two noise sources: (1) noise from the pixels and source follower (SF) circuit, and (2) noise from the AD conversion circuit. Here, the combined noise from the pixels and source follower circuit is α [uVrms], and the noise in the AD conversion after comparator 260 is β [uVrms]. The observation point of noise α is on the vertical signal line 212, and the observation point of noise β is inside comparator 260. Furthermore, we assume that there is no attenuation processing other than that of attenuator 250.

[0114] [Table 1]

[0115] The total noise in Table 1 is the sum of the FD (Frequency Diode) values ​​obtained by converting noise α and β to FD. To convert noise β in AD conversion to FD, you simply divide noise β by the attenuation rate of the attenuator. When the attenuation rate is less than 1, the value of noise β becomes large. In other words, when the signal is attenuated by the attenuator, the noise from AD conversion appears relatively large.

[0116] As shown in Table 1, high-level signals are attenuated by attenuator 250, resulting in a signal level reduction to half. Therefore, the FD-reduced noise is (α 2 +(2β) 2 ) 1 / 2 This results in (α). On the other hand, low-level signals are not attenuated by attenuator 250, so their signal level is not attenuated. Therefore, the FD equivalent noise is (α 2 +β 2 ) 1 / 2 It will become.

[0117] Table 2 shows the theoretical values of noise when the attenuation rate of the attenuator is switched uniformly for all pixels according to the conventional method. In the case of the conventional method, the attenuation rate is set uniformly for all pixels for each of the low ISO sensitivity applied to the processing of high-level signals and the high ISO sensitivity applied to the processing of low-level signals. As a result, in the low ISO sensitivity mode, both high-level signals and low-level signals are uniformly attenuated by 1 / 2 by the attenuator, so the FD conversion noise is both (α 2 +(2β) 2 ) 1 / 2 .

[0118]

Table 2

[0119] The S / N of an image is determined by the signal level of the high-brightness part (bright part) and the noise level of the low-brightness part (dark part) in the image. When the total noise (FD conversion noise) for the low-level signal in Table 1 is divided by the total noise for the low-level signal in Table 2, the division value of Equation (4) is obtained. (α 2 + β 2 ) 1 / 2 / (α 2 + (2β) 2 ) 1 / 2 (4)

[0120] When the noise levels of noises α and β are, for example, 2:1, the value of Equation (4) is (5 / 8) 1 / 2 . Thus, according to this embodiment, the total noise is reduced by about 0.79 times. As another example, when the noise levels of noises α and β are 1:1, the value of Equation (4) is (2 / 5) 1 / 2 . Thus, the total noise is reduced by about 0.63 times. As yet another example, when the noise levels of noises α and β are 1:2, the value of Equation (4) is (5 / 17) 1 / 2 . Thus, the total noise is reduced by about 0.54 times. As can be seen from these examples, the noise reduction effect becomes greater when the noises of the pixels and the source follower circuit are smaller than the AD conversion noise.

[0121] Figure 15 is a schematic diagram showing the relationship between the range of the pixel signal VSIG, the threshold VTH, and the attenuation rate of the imaging device 200 according to this embodiment. In this embodiment, as shown in Figure 15, the threshold VTH is set to 1 / 2 of the pixel's saturation signal level. The attenuation rate of the attenuator 250 is 1 / 2. However, a greater noise reduction effect can be obtained by making the attenuation rate smaller than 1 / 2. Furthermore, the level of the threshold VTH is not limited to 1 / 2 of the saturation signal level, but can be varied by circuit design, control signal, or control voltage, as described above.

[0122] Figure 16 is a schematic diagram showing the relationship between the range of the pixel signal VSIG, the threshold voltage VTH, the attenuation rate, and the non-operating range of the source follower circuit of the imaging device 200 according to this embodiment. When the comparator 240 is configured as an inverter-type comparator as shown in Figure 7C, it is desirable to set the threshold voltage of the comparator 240 to be less than or equal to half of the transistor drain voltage VDD, considering the non-operating range of the source follower circuit and the variation in the threshold voltage during circuit design. For example, in the inverter-type comparator shown in Figure 7C, if the power supply voltage is 3.3V, and the W / L ratio of the N-type MOS transistor 242b of the inverter 242 is designed to be 1:2, the threshold voltage of the inverter will be about 1.5V. In contrast, if the W / L ratio of the N-type MOS transistor 242b and the W / L ratio of the P-type MOS transistor 242a of the inverter 242 are designed to be 1:1, the threshold voltage of the inverter will be about 1.3V. Thus, although it varies somewhat depending on the transistor parameters, by designing the N-type MOS transistor so that its W / L ratio is 1 / 2 or more of the P-type MOS transistor's W / L ratio, the threshold voltage can be set to approximately 1 / 2 or less of the voltage VDD.

[0123] <Modified form of the first embodiment> Figure 17 is a schematic block diagram showing a modified example of the conversion circuit according to this embodiment. The conversion circuit 220b shown in Figure 17 differs from the conversion circuit 220 shown in Figure 5 in that it includes first and second comparators. The first comparator 240a is electrically connected to the pixel 10 and is configured to compare the level of the pixel signal VSIG with at least one threshold. The second comparator 240b is electrically connected to the pixel 10 and is configured to compare the level of the pixel signal VSIG with at least one threshold that is different from at least one threshold of the first comparator 240a. The conversion circuit 220b further includes a first holding circuit 270a electrically connected to the first comparator 240a and the attenuator 250 and holding the comparison result of the first comparator 240a, and a second holding circuit 270b electrically connected to the second comparator 240b and the attenuator 250 and holding the comparison result of the second comparator 240b. Two paths exist in parallel: one connecting the first comparator 240a and the first holding circuit 270a in series, and the other connecting the second comparator 240b and the second holding circuit 270b in series.

[0124] In this modified example, the threshold of the first comparator 240a differs from the threshold of the second comparator 240b. Therefore, the level of the output signal DOUT1a from the first comparator 240a differs from the level of the output signal DOUT1b from the second comparator 240b. In other words, the output signals DOUT1a and DOUT1b from the first and second comparators 240a and 240b change at different signal levels.

[0125] Figure 18A is a circuit diagram showing an example configuration of the attenuator in this modified example. Figure 18B is a circuit diagram showing another example configuration of the attenuator in this modified example. The attenuator 250c shown in Figure 18A has a configuration that adds a capacitor Cc, a switch S3, an inverter 224b, and an AND circuit 252 to the attenuator 250a shown in Figure 10A. The attenuator 250d shown in Figure 18B has a configuration that adds a resistor Rc, a switch S3, an inverter 224b, and an AND circuit 252 to the attenuator 250b shown in Figure 10B. However, the configuration of the attenuator is not limited to these. Any configuration that can set the voltage level of the input pixel signal VSIG to 1x, Xx, or Yx (X≠Y, X<1, Y<1) can be adopted.

[0126] Figure 19 is a schematic diagram showing the relationship between the range, threshold VTH, and attenuation rate of the pixel signal VSIG in this modified example. In this modified example, the first comparator 240a has a threshold VTH1, and the second comparator 240b has a threshold VTH2. As shown in Figure 19, threshold VTH1 is set to 1 / 4 of the pixel's saturation signal level, and threshold VTH2 is set to 1 / 2 of the pixel's saturation signal level.

[0127] The attenuator 250c illustrated in Figure 18A has three types of attenuation rates: 1, 1 / 2, and 1 / 4, depending on the level of the pixel signal VSIG. The attenuator 250c does not apply attenuation to pixel signals VSIG whose signal level is less than the threshold VTH1. In this case, the attenuator 250c maintains the level of the pixel signal VSIG, i.e., attenuates it to 1. The attenuator 250c applies attenuation to pixel signals VSIG whose signal level is greater than or equal to the threshold VTH1 and less than the threshold VTH2. In this case, the attenuator 250c attenuates the pixel signal VSIG to 1 / 2. The attenuator 250c applies attenuation to pixel signals VSIG whose signal level is greater than or equal to the threshold VTH2. In this case, the attenuator 250c attenuates the pixel signal VSIG to 1 / 4. In this way, even if the AD conversion range is, for example, 1 / 4 of the pixel saturation level, it is possible to appropriately keep the level of the pixel signal VSIG within the AD conversion range according to the level of the pixel signal. The number of thresholds or attenuation rates is not limited to two or three, but can be four or more.

[0128] In this embodiment, a single-slope type AD conversion circuit is used as an example of the AD conversion circuit, but the invention is not limited to this. For example, successive approximation type AD conversion circuits, delta-sigma AD conversion circuits, or cyclic type AD conversion circuits can also be used.

[0129] <Second Embodiment> The conversion circuit according to the second embodiment of this disclosure will be described with reference to Figures 20 to 25. The conversion circuit according to the second embodiment differs from the conversion circuit according to the first embodiment in that it includes an attenuator electrically connected to the comparator and the reference signal generation circuit. The differences will be mainly described below.

[0130] Figure 20 is a schematic block diagram showing the configuration of a conversion circuit according to the second embodiment of this disclosure.

[0131] The conversion circuit 220c shown in Figure 20 is a comparator 260 electrically connected to the pixel 10, and includes a comparator 260 that converts the pixel signal VSIG and the reset signal, which are analog signals respectively, read from the pixel 10 into digital signals; a reference signal generation circuit 204 that generates and outputs a ramp signal which is a reference signal Vramp; an attenuator 255 electrically connected to the comparator 260 and the reference signal generation circuit 204, which amplifies the ramp signal by one of a plurality of amplification factors and outputs it to the comparator 260; and a comparator 240 electrically connected to the pixel 10, which compares the level of the pixel signal VSIG with at least one threshold.

[0132] In this embodiment, the attenuator 255 is configured to amplify the ramp signal at an amplification factor set by the comparator 240 during the period when the pixel signal VSIG and the reset signal are converted into digital signals.

[0133] Figures 21A and 21B are circuit diagrams showing example configurations of attenuators according to the second embodiment of the present disclosure. The configuration of attenuator 255a shown in Figure 21A differs from the configuration of 250a shown in Figure 10A in that the polarity of the control signals of switches S1 and S2 is reversed. The reason for reversing the polarity of the control signals is that in the first embodiment, the attenuator 250 attenuates the signal when the level of the pixel signal VSIG is relatively large, while in the second embodiment, conversely, the attenuator 255 attenuates the reference signal Vramp when the level of the pixel signal VSIG is relatively small.

[0134] The comparator 240 sets the amplification factor of the attenuator 255 to one of a plurality of amplification factors based on the comparison result of the level of the pixel signal VSIG with at least one threshold. In this embodiment, by connecting the reference signal generation circuit 204 to the attenuator 255, the slope of the reference signal Vramp, i.e., the amount of voltage change per unit time, changes depending on the attenuation factor set in the attenuator 255. The comparator 260 compares the levels of the pixel signal VSIG and the reset signal with the amplified ramp signal output from the attenuator 255, i.e., the reference signal Vramp with a changed slope. In this embodiment, the comparator 260 illustrates a comparison circuit.

[0135] As mentioned earlier, while a low AD conversion gain allows for the conversion of large signals, it reduces resolution. As a result, quantization noise increases. Conversely, a high AD conversion gain suppresses quantization noise. However, it reduces the signal range that can be handled.

[0136] According to this embodiment, when the level of the pixel signal is greater than the threshold, AD conversion is performed with a relatively low AD conversion gain, and when the level of the pixel signal is less than the threshold, AD conversion is performed with a relatively high AD conversion gain. As a result, it becomes possible to perform AD conversion on the pixel signal at the maximum range of the pixel signal while suppressing quantization noise and avoiding S / N degradation in low light conditions, thereby improving the dynamic range.

[0137] The operation of the imaging device 200 according to this embodiment will be described with reference to Figures 22 and 23.

[0138] Figures 22 and 23 are timing charts illustrating examples of the operation procedure of the imaging device 200. Figure 22 shows examples of each signal waveform when the level of the pixel signal VSIG falls below the threshold of the comparator 240. In describing the operation procedure of the imaging device 200, each of the multiple pixels 10 is a stacked photoelectric conversion element. The comparator 240 of the conversion circuit 220c has the configuration shown in Figure 7A, the attenuator 255 has the configuration shown in Figure 21B, and the holding circuit 270 has the configuration shown in Figure 12.

[0139] First, at time t0, the level of the horizontal sync signal HD changes from Low to High, and imaging of the pixel group in the nth row of the pixel unit 201 begins. At time t1, the level of the horizontal sync signal HD changes from High to Low.

[0140] Next, at time t2, the selection signal VSELn goes high, the selection transistor M2 turns on, and the pixel signal VSIG for the nth row is output to the vertical signal line 212. Also, the control signal CNT goes high, and the switch S4 of the holding circuit 270 (see Figure 12) turns on.

[0141] Next, at time t4, switch S4 of the holding circuit 270 is turned off, and a voltage based on the level of the pixel signal VSIG is held in the capacitor Cd.

[0142] In this embodiment, since the output signal SHOUT does not exceed the threshold VTH during the period from time t2 to time t4 when the control signal CNT is High, the output signal DOUT1 is fixed to Low from time t4 onward, and the inverted signal of output signal DOUT1 (the output signal of inverter 224) is fixed to High. As a result, the reference signal Vramp is attenuated by the attenuator 250 to Vramp × Rb / (Ra+Rb) and output from the attenuator 250 as the output signal AOUT. In other words, the reference signal Vramp with a slope multiplied by Rb / (Ra+Rb) is output.

[0143] In this embodiment, resistors Ra and Rb are the same. In this case, the attenuation rate of the attenuator 255 is 1 / 2. By applying the attenuation processing of the attenuator 255 to the reference signal Vramp according to the level of the pixel signal VSIG, the slope of the reference signal Vramp becomes 1 / 2, and therefore, quantization noise during AD conversion can be reduced.

[0144] Next, at time t4, the reference signal generation circuit 204 starts generating the reference signal Vramp. During the period from time t4 to time t5, the comparator 260 compares the voltage corresponding to the attenuated reference signal Vramp with the level of the pixel signal VSIG, and the counter 209 continues counting until the output levels of both match.

[0145] Next, at time t5, the reset control signal VRSTn applied to the nth row pixel 10 becomes high, and the reset operation of the nth row pixel is initiated by the reset transistor M3. Subsequently, since the potential level of the vertical signal line 212 corresponding to the level of the reset signal does not exceed the threshold VTH of the comparator 240, the level of the output signal DOUT1 is maintained at low.

[0146] Next, at time t7, the reset control signal RSTn changes from High to Low, and the reset operation is completed. Also at time t7, the reference signal generation circuit 204 starts generating the reference signal Vramp. During the period from time t7 to time t9, the comparator 260 compares the voltage corresponding to the reference signal Vramp with the reset signal, and the counter 209 continues counting until the output levels of both match.

[0147] Next, at time t10, the level of the horizontal synchronization signal HD becomes high, and the imaging device 200 proceeds to read out the pixels of the (n+1)th row.

[0148] Thus, during the period when the selection signal VSELn is High, the comparator 260 performs the first comparison between the pixel signal VSIG and the reference signal Vramp, and then, after the reset operation is completed, the comparator 260 performs a second comparison between the reset signal and the reference signal Vramp.

[0149] Figure 23 shows examples of signal waveforms when the level of the pixel signal VSIG exceeds the threshold of comparator 240. The differences from the case where the pixel signal VSIG falls below the threshold of comparator 240 are explained below.

[0150] In the timing chart shown in Figure 23, the level of the pixel signal VSIG read from pixel 10 is held by the holding circuit 270, and because its output signal SHOUT is higher than the threshold VTH of comparator 240, the output signal DOUT1 of comparator 240 changes from Low to High. This turns on switch S1 of attenuator 255 and off switch S2. Consequently, the reference signal Vramp is not attenuated by attenuator 250b, and the slope of the reference signal Vramp is output as the output signal AOUT.

[0151] As explained above, when the level of the pixel signal VSIG falls below the threshold VTH of the comparator 240, the reference signal Vramp is attenuated by the attenuator 255. When the level of the pixel signal VSIG exceeds the threshold VTH of the comparator 240, the reference signal Vramp is not attenuated by the attenuator 255. By operating the conversion circuit 220c according to the aforementioned operation sequence, it becomes possible to perform AD conversion of the pixel signal at the maximum range of the pixel signal while suppressing quantization noise and avoiding S / N degradation in low light conditions, thereby improving the dynamic range.

[0152] Similar to the first embodiment, the comparison result between the level of the pixel signal VSIG and the threshold of the comparator 240 can be provided to either or both of the subsequent counter 209 and memory 211. For example, the signal processing circuit 208 inside the imaging device 200 or a camera signal processing unit externally connected to the imaging device (described later) may correct the AD conversion value by shifting the AD conversion value according to the attenuation rate of each pixel so that the level of the pixel signal VSIG of each pixel 10 matches the magnitude of the AD conversion value.

[0153] In this embodiment, the pixel configuration and operation sequence read out a pixel signal corresponding to the intensity of incident light, followed by a pixel reset and the readout of the reset signal. By first reading out the pixel signal and determining the attenuation rate of the attenuator based on the relationship between the pixel signal level and the comparator threshold, it becomes possible to perform AD conversion on the subsequent reset signal using the slope of the reference signal Vramp. By using the same reference signal Vramp waveform for both the pixel signal reading and the reset signal reading, it is possible to improve the signal-to-noise ratio without generating unnecessary offsets. On the other hand, when using a pixel configuration and operation sequence that reads out the reset signal level first, it is difficult to use the same reference signal Vramp waveform for both the pixel signal reading and the reset signal reading because the pixel signal level is unknown at the time the reset signal is read out.

[0154] Table 3 shows the theoretical noise values ​​when the slope of the reference signal Vramp is changed according to the level of the pixel signal, according to the pixel configuration and operation sequence in this embodiment. Similar to the first embodiment, the high-level signals in Table 3 refer to pixel signals at a level greater than the threshold VTH of the comparator 240, and the low-level signals in Table 3 refer to pixel signals at a level less than the threshold VTH of the comparator 240. For simplicity of explanation, we assume that there are two noise sources: (1) noise from the pixels and source follower circuit, and (2) quantization noise during AD conversion. Here, the combined noise from the pixels and source follower circuit is α [uVrms], and the quantization noise at an AD conversion gain of 0 dB is β [uVrms]. The observation point of noise α is on the vertical signal line 212, and the observation point of noise β is on the digital value after AD conversion.

[0155] [Table 3]

[0156] The total noise in Table 3 is the sum of the noise values ​​α and β converted to FD (FD-converted noise). It is assumed that there are no circuit elements that amplify or attenuate the signal in the path from FD to after AD conversion, and the quantization noise β is assumed to be the same magnitude when converted to FD.

[0157] As shown in Table 3, for high-level signals, the AD conversion gain is 0 dB, so the quantization noise is β [uVrms], and as a result, the FD-reduced noise is (α 2 +β 2 ) 1 / 2 On the other hand, for low-level signals, the AD conversion gain is 6dB, so the quantization noise is β / 2[uVrms], and as a result, the FD-reduced noise is (α 2 +(β / 2) 2 ) 1 / 2 It will become.

[0158] Table 4 shows the theoretical noise values ​​when the attenuation rate of the attenuator is switched uniformly for all pixels according to the conventional method. In the conventional method, the AD conversion gain is set uniformly for all pixels for each mode: low ISO sensitivity applied to high-level signal processing and high ISO sensitivity applied to low-level signal processing. As a result, in the low ISO sensitivity mode, both high-level and low-level signals are uniformly AD converted with an AD conversion gain of 0dB, so the FD equivalent noise is (α 2 +β 2 ) 1 / 2 It will become.

[0159] [Table 4]

[0160] The signal-to-noise ratio (S / N) of an image is determined by the signal level in the high-luminance areas (bright parts) and the noise level in the low-luminance areas (dark parts) of the image. Dividing the total noise for low-level signals (FD conversion noise) in Table 3 by the total noise for low-level signals in Table 4 yields the division value in equation (5). (α 2 + (β / 2) 2 ) 1 / 2 / (α 2 + β 2 ) 1 / 2 (5)

[0161] If the noise levels of noise α and β are, for example, 2:1, then the value of equation (5) is (5 / 8). 1 / 2 This results in a reduction of approximately 0.79 times the total noise. As another example, when the noise levels of noise α and β are 1:1, the value of equation (5) is (2 / 5). 1 / 2 This results in a reduction of approximately 0.63 times the total noise. As yet another example, when the noise levels of noise α and β are 1:2, the value of equation (5) is (5 / 17). 1 / 2 This results in a reduction of approximately 0.54 times the total noise. As these examples show, the noise reduction effect is greater when the noise of the pixels and source follower circuits is smaller than the quantization noise.

[0162] Figure 24 is a schematic diagram showing the relationship between the range of the pixel signal VSIG, the threshold VTH, and the AD conversion gain of the imaging device 200 according to this embodiment. In this embodiment, as shown in Figure 24, the threshold VTH is set to 1 / 2 of the pixel's saturation signal level, and the AD conversion gain is 6 dB. However, a greater noise reduction effect can be obtained by making the AD conversion gain smaller than 6 dB.

[0163] <Modified form of the second embodiment> Figure 25 is a schematic block diagram showing a modified example of the conversion circuit according to this embodiment. The conversion circuit 220d shown in Figure 25 is similar in configuration to the modified example of the conversion circuit 220 according to the first embodiment shown in Figure 17, in which two paths are connected in parallel: a first comparator 240a and a first holding circuit 270a connected in series, and a second comparator 240b and a second holding circuit 270b connected in series. The attenuator 255 of the conversion circuit 220d may have the same configuration as shown in, for example, Figure 18A or Figure 18B. However, a reference signal Vramp is input from the reference signal generation circuit 204.

[0164] Figure 26 is a schematic diagram showing the relationship between the range of the pixel signal VSIG, the threshold VTH, and the AD conversion gain in this modified example. As shown in Figure 26, threshold VTH1 is set to 1 / 4 of the pixel's saturation signal level, and threshold VTH2 is set to 1 / 2 of the pixel's saturation signal level. Comparator 260 performs AD conversion on pixel signals and reset signals whose signal level is less than threshold VTH1 with an AD conversion gain of 12 dB. Comparator 260 performs AD conversion on pixel signals and reset signals whose signal level is between threshold VTH1 and threshold VTH2 with an AD conversion gain of 6 dB. Comparator 260 performs AD conversion on pixel signals and reset signals whose signal level is greater than or equal to threshold VTH2 with an AD conversion gain of 0 dB. This allows for a further reduction in quantization noise for low-level signals, which is expected to improve the signal-to-noise ratio and dynamic range.

[0165] <Third Embodiment> A camera system according to the third embodiment of this disclosure will be described with reference to Figure 27.

[0166] Figure 27 schematically shows an example configuration of a camera system 400 according to a third embodiment of this disclosure. The camera system 400 comprises a lens optical system 601, an imaging device 602, a system controller 603, and a camera signal processing unit 604. The camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0167] The lens optical system 601 includes, for example, a group of lenses including an autofocus lens and a zoom lens. The lens optical system 601 may include an aperture. The lens optical system 601 focuses light onto the imaging plane of the imaging device 200. The imaging devices according to the first and second embodiments described above can be widely used as the imaging device 602.

[0168] The system controller 603 controls the entire camera system 400. The system controller 603 is typically a semiconductor integrated circuit, such as a CPU (Central Processing Unit).

[0169] The camera signal processing unit 604 has the function of processing the output signal from the imaging device 602. The camera signal processing unit 604 is, for example, a DSP (Digital Signal Processor). The camera signal processing unit 604 receives output data from the imaging device 602 and performs processing such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The imaging device 602 and the camera signal processing unit 604 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). With such a configuration, the electronic device that includes the imaging device 602 as part can be made smaller.

[0170] The imaging device according to the embodiments of this disclosure does not necessarily have to include all of the components described in the first and second embodiments, and may consist only of components for performing the desired operation. Furthermore, in the above example of operation, there may be operations that are not performed by the imaging device. In one embodiment of the embodiments of this disclosure, the imaging device includes a pixel, an AD conversion circuit that converts an analog signal output from the pixel into a digital signal, a determination circuit electrically connected to the pixel that compares the level of the analog signal with at least one threshold, and a holding circuit that holds the comparison result between the level of the analog signal and at least one threshold.

[0171] In the above embodiment, an attenuator with an attenuation ratio less than 1 was used as an example of the amplification circuit, but it is possible to use an amplifier with an amplification ratio greater than 1 as the amplification circuit.

[0172] In the above embodiment, a processing unit that would normally be executed by a specific processing unit, such as a signal processing circuit, may be executed by another processing unit. Furthermore, the order of multiple processing units may be changed, or multiple processing units may be executed in parallel.

[0173] The general or specific embodiments of this disclosure may be implemented as a system, apparatus, method, integrated circuit, computer program, or recording medium such as a computer-readable CD-ROM. They may also be implemented in any combination of systems, apparatus, method, integrated circuit, computer program, and recording medium.

[0174] For example, this disclosure may be implemented as an imaging device according to the above embodiment, as a processing circuit for an imaging device having the functions of the signal processing circuit according to the above embodiment, as a signal processing method for an imaging device performed by the signal processing circuit according to the above embodiment, as a program for causing a computer to execute such a signal processing method, or as a computer-readable non-temporary recording medium on which such a program is recorded.

[0175] In addition, the scope of this disclosure includes, without departing from the spirit of this disclosure, various modifications to the embodiments and examples that a person skilled in the art could conceive of, as well as other forms constructed by combining some of the components of the embodiments and examples. [Industrial applicability]

[0176] The imaging device described herein is useful as a variety of imaging devices. It can also be applied to applications such as digital cameras, digital video cameras, camera phones, medical cameras such as electronic endoscopes, in-vehicle cameras, and robot cameras. [Explanation of Symbols]

[0177] 10...Pixel, 11...Photoelectric conversion layer, 12...Pixel electrode, 13...Counter electrode, 14...Contact plug, 15...Semiconductor substrate, 18...Photoelectric conversion unit, 200, 602...Imaging device, 201...Pixel unit, 202...Vertical scanning circuit, 203...Horizontal transfer scanning circuit, 204...Reference signal generation circuit, 205...Drive control circuit, 206...Column Processing unit, 207... Column circuit, 212... Vertical signal line, 213... Horizontal signal line, 214... Amplifier circuit, 215... Load current circuit, 220... Conversion circuit, 240, 260... Comparator, 250... Attenuator, 270... Holding circuit, 400... Camera system, 601... Optical system, 603... System controller, 604... Camera signal processing unit

Claims

1. Pixels and An amplification circuit electrically connected to the aforementioned pixel, which amplifies the pixel signal and reset signal, each of which are analog signals, read from the pixel, by one of a plurality of amplification rates and outputs the result. An AD conversion circuit is electrically connected to the aforementioned amplification circuit and converts the output from the amplification circuit into a digital signal. A determination circuit electrically connected to the pixel and comparing the level of the pixel signal with at least one threshold, Equipped with, The determination circuit sets the amplification factor of the amplification circuit to one of the plurality of amplification factors based on the comparison result between the level of the pixel signal and the at least one threshold. The amplification circuit amplifies the pixel signal and the reset signal with the set amplification factor. Imaging device.

2. Pixels and An A / D conversion circuit electrically connected to the aforementioned pixel, which converts the pixel signal and reset signal, each of which are analog signals, read from the aforementioned pixel into digital signals. A reference signal generation circuit that generates and outputs a lamp signal, which is a reference signal, An amplification circuit electrically connected to the aforementioned reference signal generation circuit, which amplifies the lamp signal at one of a plurality of amplification rates and outputs it, A determination circuit electrically connected to the pixel and comparing the level of the pixel signal with at least one threshold, Equipped with, The AD conversion circuit includes a comparison circuit that compares the levels of the pixel signal and the reset signal with the amplified ramp signal output from the amplification circuit. The determination circuit sets the amplification factor of the amplification circuit to one of the plurality of amplification factors based on the comparison result between the level of the pixel signal and the at least one threshold. The amplification circuit amplifies the lamp signal by the single amplification factor set by the determination circuit during the period in which the pixel signal and the reset signal are converted into digital signals. Imaging device.

3. The imaging apparatus according to claim 1 or 2, wherein the determination circuit includes an inverter circuit.

4. The inverter circuit includes an N-type MOS transistor and a P-type MOS transistor. The imaging apparatus according to claim 3, wherein the W / L ratio of the N-type MOS transistor is 1 / 2 or more of the W / L ratio of the P-type MOS transistor.

5. The imaging apparatus according to claim 1 or 2, further comprising a holding circuit for holding the comparison result of the determination circuit.

6. The imaging apparatus according to claim 5, wherein the holding circuit includes a switch electrically connected between the pixel and the inverter circuit.

7. The imaging apparatus according to claim 5, wherein the holding circuit includes a latch electrically connected downstream of the inverter circuit.

8. The imaging apparatus according to claim 1 or 2, wherein the determination circuit includes a differential amplifier.

9. The system further comprises a signal processing circuit that receives the digital signal output from the AD conversion circuit, The imaging apparatus according to claim 1 or 2, wherein the signal processing circuit applies a correction process to the digital signal according to the comparison result of the determination circuit.

10. The aforementioned determination circuit is a first determination circuit, A second determination circuit electrically connected to the pixel compares the level of the pixel signal with at least one other threshold different from the at least one threshold, A first holding circuit is electrically connected to the first determination circuit and the amplification circuit, and holds the comparison result of the first determination circuit, A second holding circuit is electrically connected to the second determination circuit and the amplification circuit, and holds the comparison result of the second determination circuit, The imaging apparatus according to claim 1 or 2, further comprising the following:

11. The imaging apparatus according to claim 1 or 2, wherein the pixel includes a pixel electrode, a counter electrode facing the pixel electrode, and a photoelectric conversion layer located between the pixel electrode and the counter electrode.

12. The imaging apparatus according to claim 1 or 2, wherein the pixel outputs the reset signal after outputting the pixel signal during a one-frame period.

13. Pixels and A determination circuit electrically connected to the pixel and comparing the level of the analog signal output from the pixel with at least one threshold, A holding circuit that holds the result of comparing the level of the analog signal with the at least one threshold, An imaging device equipped with the following features.

Images