Optical communication system and optical data transfer method

Abstract

Reduce the overhead that occurs when switching fiber optic connections. [Solution] An optical communication system is provided in which multiple nodes are connected via an optical network that allows switching of optical line connections. Each node includes a link unit and a memory unit. The first node has information for converting logical addresses referenced by an application to physical addresses in the memory unit of each node, and information for the destination of commands. For example, when transferring data to a second node, the first node converts the source and / or destination logical addresses to physical addresses based on this information, sends a read command including the source address to its own memory unit, and sends a write command including the destination address to its own link unit. The link unit then sends a write command to the second node, specifying the memory unit of the second node as the destination based on the destination information.

Description

Technical Field

[0001] The present invention relates to an optical communication system and an optical data transfer method.

Background Art

[0002] With the evolution of AI (Artificial Intelligence) technology, AI has been increasingly used in various applications and scenarios. On the other hand, in order to realize a high-performance AI model, it is necessary to train a large-scale AI model with a huge amount of learning data. Therefore, recently, a distributed computing system including a large number of nodes has been used for learning processing (see Patent Document 1). In order to efficiently proceed with learning processing in a distributed computing system, broadband data communication between nodes is essential, and therefore, an optical fiber network is used for the connection between nodes. The connection between nodes may be a direct connection or a connection via an optical switch.

[0003] When an optical switch is used, it becomes possible to dynamically change the connection between nodes and / or the connection between computer devices such as memories and accelerators (hereinafter, simply referred to as "connection between nodes" for the sake of simplicity). Therefore, it is also possible to construct an optical communication network system capable of dynamically changing the network topology (see Patent Document 2). When the connection between nodes is changed by controlling the optical switch, the node whose connection destination has been changed needs to obtain information of the connection destination node in order to exchange data with the node that becomes the new connection destination. For example, in a system adopting a distributed shared memory (see Patent Document 3) that shares a memory space among a plurality of nodes, it is necessary to obtain information of the connection destination node at the time of data transfer.

Prior Art Documents

Patent Documents

[0004] [[ID=2!6]]

Patent Document 1

Patent Document 2

[0005] Normally, the operating system (OS) running within a node cannot obtain information about nodes that are not currently connected. Therefore, when the connected node changes, the OS initiates a procedure to obtain information about the new connected node. However, this process of obtaining information about the new node each time a switch occurs adds extra time (overhead) before data transfer can begin. Therefore, minimizing this overhead that occurs when switching optical fiber connections is required.

[0006] In view of the above circumstances, the object of the present invention is to provide an optical communication system and an optical data transmission method that can reduce the overhead that occurs when switching optical line connections. [Means for solving the problem]

[0007] According to a first aspect of the present invention, an optical communication system is provided in which a plurality of nodes are connected via an optical network capable of switching optical line connections. Each node includes a link unit that performs processing related to the transmission and reception of optical signals between nodes, and a memory unit for storing data. At least one of the plurality of nodes has a switching control unit that holds address translation information for converting logical addresses referenced by an application when accessing memory to physical addresses in the memory unit of the corresponding node, and map information for identifying the destination of commands at each node, and when it receives a data transfer instruction, it has a switching control unit that converts the source and / or destination logical addresses to physical addresses, and a memory management unit that generates a write command including the data writing destination address and a read command including the data reading destination address.

[0008] For example, if a transfer instruction indicates a data transfer from the first node to the second node, the memory management unit sends a read command to the memory unit of the first node and a write command to the link unit of the first node. The link unit of the first node then specifies the destination of the write command based on the map information held by the switching control unit and sends the write command to the second node. After the memory unit of the first node receives the read command and the memory unit of the second node receives the write command, the data is transmitted from the memory unit of the first node to the memory unit of the second node.

[0009] As another example, if a transfer instruction indicates a data transfer from the second node to the first node, the memory management unit sends a write command to the memory unit of the first node and a read command to the link unit of the first node. The link unit of the first node specifies the destination of the read command based on the map information held by the switching control unit and sends the read command to the second node. After the memory unit of the first node receives the write command and the memory unit of the second node receives the read command, the data is transmitted from the memory unit of the second node to the memory unit of the first node.

[0010] A second aspect of the present invention provides a data transfer method in an optical communication system in which multiple nodes are connected via an optical network capable of switching optical line connections. Each node includes a link unit that performs processing related to the transmission and reception of optical signals between nodes, and a memory unit for storing data. At least one of the multiple nodes holds address translation information for converting logical addresses referenced by an application when accessing memory to physical addresses in the memory unit of the corresponding node, and map information for identifying the destination of commands at each node.

[0011] The above method includes the steps of: the first node converting the source and / or destination logical addresses to physical addresses in response to a data transfer instruction; and the first node generating a write command including the data writing destination address and a read command including the data reading destination address.

[0012] For example, if the transfer instruction indicates a data transfer from a first node to a second node, the above method further includes the steps of the first node sending a read command to its memory unit and a write command to its link unit, and the link unit of the first node specifying the destination of the write command based on map information and sending the write command to the second node. Furthermore, after the first node's memory unit receives the read command and the second node's memory unit receives the write command, data is transmitted from the first node's memory unit to the second node's memory unit.

[0013] As another example, if the transfer instruction indicates a data transfer from a second node to a first node, the method further includes the steps of the first node sending a write command to its memory unit and a read command to its link unit, and the link unit of the first node specifying the destination of the read command based on map information and sending the read command to the second node. Furthermore, after the memory unit of the first node receives the write command and the memory unit of the second node receives the read command, data is transmitted from the memory unit of the second node to the memory unit of the first node.

[0014] According to the first and second embodiments described above, since the first node holds address translation information for the memory portion of each of the multiple nodes, and map information for each of the multiple nodes, the first node can send commands without obtaining information from other nodes. Therefore, the procedure for obtaining information from other nodes when the optical line connection is switched can be omitted, and the overhead that occurs when the optical line connection is switched can be reduced. [Effects of the Invention]

[0015] According to the present invention, the overhead that occurs when switching optical fiber connections can be reduced. [Brief explanation of the drawing]

[0016] [Figure 1] This is a block diagram showing an example configuration of an optical communication system according to one embodiment of the present invention. [Figure 2] This is a block diagram showing an example of the configuration of nodes in an optical communication system according to one embodiment of the present invention. [Figure 3] This figure shows an example of the information held by a node according to one embodiment of the present invention. [Figure 4A] This is a flowchart illustrating a data transmission method (data transmission from node #1 to node #2) according to one embodiment of the present invention. [Figure 4B] This is a flowchart illustrating a data transmission method (data transmission from node #1 to node #2) according to one embodiment of the present invention. [Figure 5A] This is a flowchart illustrating a data transmission method (data transmission from node #2 to node #1) according to one embodiment of the present invention. [Figure 5B] This is a flowchart illustrating a data transmission method (data transmission from node #2 to node #1) according to one embodiment of the present invention. [Figure 6] This is a block diagram showing an example configuration of an optical communication system and each node according to the first modified example. [Figure 7A]It is a flowchart showing a data transmission method according to the first modification example (data transmission from node #1 to node #2). [Figure 7B] It is a flowchart showing a data transmission method according to the first modification example (data transmission from node #1 to node #2). [Figure 8A] It is a flowchart showing a data transmission method according to the first modification example (data transmission from node #2 to node #1). [Figure 8B] It is a flowchart showing a data transmission method according to the first modification example (data transmission from node #2 to node #1). [Figure 9] It is a block diagram showing an optical communication system according to the second modification example and a configuration example of each node. [Figure 10] It is a diagram showing an example of information held by a node according to the second modification example.

Mode for Carrying Out the Invention

[0017] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the present specification and drawings, elements having substantially the same function may be denoted by the same reference numerals, and redundant description may be omitted.

[0018] (Configuration of Optical Communication System) With reference to FIG. 1, the configuration of an optical communication system according to an embodiment of the present invention will be described. FIG. 1 is a block diagram showing a configuration example of an optical communication system according to an embodiment of the present invention.

[0019] As shown in FIG. 1, the optical communication system includes a master server 10, an optical line network 20, and a plurality of nodes (node #1, node #2, node #3,...). In the example of FIG. 1, for ease of explanation, three nodes are shown, but the number of nodes included in the optical communication system may be any number of 3 or more.

[0020] The optical network 20 includes an optical switch control unit 21 and an optical switch circuit 22. The optical switch control unit 21 may be a control circuit that controls the operation of the optical switch circuit 22 in response to instructions from the master server 10 and / or a specific node (master node). The dashed lines in Figure 1 indicate control signal lines, which may be electrical lines or optical lines. On the other hand, the optical switch circuit 22 and each node are connected by optical lines. This optical line communication may be single-core bidirectional communication or double-core bidirectional communication. The optical switch circuit 22 may include one or more optical switches and optical wiring, and its structure and form are arbitrary as long as it can realize the function of switching the connection relationships between nodes.

[0021] (Node configuration) Next, the node configuration will be described with reference to Figure 2. Figure 2 is a block diagram showing an example of a node configuration. For the sake of simplicity, only the configuration examples of nodes #1 and #2 are explicitly shown in Figure 2, but in the following description, other nodes such as node #3 will be assumed to have the same configuration as node #2. Each node may further include other components not shown, or multiple components may be integrated into a single unit or module. Such configurations may also fall within the technical scope of this embodiment.

[0022] In the example shown in Figure 2, node #1 (the first node) is the master node. Node #1 includes a switching control unit 31a, a link unit 31b, a memory management unit 31c, a memory 31d, and an application execution unit 31e, and these components are connected via a bus 31f. For example, these components can form a bus network within the node via the bus 31f, and each has a unique port address, allowing them to communicate with each other by referring to their port addresses.

[0023] The switching control unit 31a may be a processing unit or module having a processor and a memory device, or a computer. The processor may be one or more CPUs (Central Processing Units), DSPs (Digital Signal Processors), ASICs (Application Specific Integrated Circuits), FPGAs (Field Programmable Gate Arrays), or a combination thereof. The memory device may be ROMs (Read Only Memory), RAMs (Random Access Memory), HDDs (Hard Disk Drives), SSDs (Solid State Drives), flash memory, or a combination thereof.

[0024] The switching control unit 31a has a storage unit that holds information about each node connected to the optical switch circuit 22. The functions of this storage unit can be realized by the storage device described above. The storage unit of the switching control unit 31a holds information such as that shown in Figure 3. Figure 3 is a diagram showing an example of the information held by a node. In the example in Figure 3, the storage unit 300 stores information such as node #1 information 310, node #2 information 320, and node #3 information 330.

[0025] Node #1 information 310 contains information about node #1. Node #1 information 310 includes the memory map information 311 and address translation information 312 for node #1. Node #2 information 320 contains information about node #2. Node #2 information 320 includes the memory map information 321 and address translation information 322 for node #2. Node #3 information 330 contains information about node #3. Node #3 information 330 includes the memory map information 331 and address translation information 332 for node #3. Similarly, information about other nodes connected to the optical switch circuit 22 is stored in the storage unit 300.

[0026] Each address translation information is information that associates a logical memory address (hereinafter simply referred to as "logical address") that an application executed in the application execution unit 31e refers to when accessing data in the memory unit with the physical memory address (hereinafter simply referred to as "physical address") of the memory unit corresponding to that logical address. The memory map information is information that associates a pre-configured logical address range with identification information (e.g., port address) of the component corresponding to that logical address range. For example, one logical address range is associated with the memory unit 31d of node #1, and another logical address range is associated with the memory unit 32d of node #2.

[0027] For example, the memory map information 311 of node #1 information 310 includes information that associates the port address of memory section 31d within node #1 with the range of logical addresses corresponding to the physical address of memory section 31d. Similarly, the memory map information 321 of node #2 information 320 includes information that associates the port address of memory section 32d within node #2 with the range of logical addresses corresponding to the physical address of memory section 32d. Therefore, when accessing data at a particular logical address, it becomes possible to identify the target node and its components by referring to the respective memory map information.

[0028] For example, consider the case of moving data located at logical address X1 to logical address X2. If logical address X1 corresponds to the physical address Y1 of memory section 31d in node #1, then based on the memory map information 311, it is possible to identify that the data read destination is within node #1 and the port address indicating memory section 31d in node #1. If logical address X2 corresponds to the physical address Y2 of memory section 32d in node #2, then based on the memory map information 321, it is possible to identify that the data write destination is within node #2 and the port address indicating memory section 32d in node #2. In other words, by referring to each memory map information, the destination of read and write commands can be identified.

[0029] Furthermore, by referring to the address translation information, the physical addresses of the read and write destinations can be identified, allowing the generation of a read command that includes the physical address of the read destination and a write command that includes the physical address of the write destination. Therefore, node #1 can create the commands necessary for reading and writing data, specify the destination of those commands, and send the commands using the above memory map information and address translation information without obtaining information from other nodes. Once it is confirmed that the commands have reached the data read and write destinations, the data is actually transferred from the memory section of the read destination to the memory section of the write destination.

[0030] If the source node and destination node of the data transfer are not connected by an optical line, the switching control unit 31a requests the optical switch control unit 21 to control the optical switch circuit 22 to connect the source node and the destination node before sending a command. For example, in the case of moving data located at logical address X1 to logical address X2 as described above, the switching control unit 31a requests the optical switch control unit 21 to connect node #1 and node #2. Even in this case, node #1 can identify the node that needs to be connected based on the memory map information described above without obtaining information from other nodes, and can send a request to the optical switch control unit 21 without overhead.

[0031] The link unit 31b is a component that performs processing related to the transmission and reception of optical signals between nodes. The link unit 31b is connected to the optical switch circuit 22 by an optical line. The link unit 31b also includes a signal processing circuit that performs conversion between electrical signals transmitted via the bus 31f and data signals transmitted via the optical line. The link unit 31b may further include a processor, and the implementation form of the link unit 31b may be a processing unit or module, or a computer, etc. The processor may be one or more CPUs, DSPs, ASICs, FPGAs, or a combination thereof.

[0032] The memory management unit 31c is a component that generates a write command including the address to which data is written, and a read command including the address to which data is read. The memory management unit 31c may be a processing unit or module having a processor, or a computer, etc. The processor may be one or more CPUs, DSPs, ASICs, FPGAs, or a combination thereof. The memory management unit 31c refers to the memory map information held by the switching control unit 31a to identify the destination of the commands and sends out the generated write and read commands. Alternatively, the memory management unit 31c may perform address translation from logical addresses to physical addresses by referring to address translation information obtained from the switching control unit 31a, instead of the switching control unit 31a.

[0033] The memory unit 31d includes a storage device composed of ROM, RAM, HDD, SSD, flash memory, or a combination thereof, and a processor that performs reading and writing of data to the storage device. The processor may be one or more CPUs, DSPs, ASICs, FPGAs, or a combination thereof. After receiving a read command or a write command, the memory unit 31d performs data reading or writing according to the command execution instruction based on the physical address included in the command.

[0034] The application execution unit 31e may be a processing unit or module having a processor and a memory device, or a computer. The memory device stores the application program and data used when the application is executed. The processor may be one or more CPUs, DSPs, ASICs, FPGAs, or a combination thereof. The memory device may be ROM, RAM, HDDs, SSDs, flash memory, or a combination thereof. The application execution unit 31e is the entity that executes the application. When accessing data, the application refers to the logical address described above. Because it refers to a logical address, the application can read and write data without being aware of which node the data is actually located on.

[0035] When an application performs a data transfer, the application execution unit 31e sends a data transfer instruction to the switching control unit 31a. This transfer instruction includes the logical address of the source and the logical address of the destination. Based on memory map information for each node, the switching control unit 31a can identify the node and its components corresponding to the source and destination logical addresses indicated in the transfer instruction. Therefore, it can identify the node to be connected via the optical line and the destination of the command without obtaining information from other nodes. Furthermore, based on address translation information, the switching control unit 31a can translate the source and destination logical addresses into physical addresses. Therefore, it can generate a command that includes a physical address without obtaining information from other nodes.

[0036] In the example in Figure 2, node #2 is a slave node. Node #2 includes at least a link section 32b and a memory section 32d. These components are connected via a bus 32f. For example, these components can form a bus network within the node via the bus 32f, each with its own unique port address, and can communicate with each other by referring to their port addresses.

[0037] The link unit 32b is a component that performs processing related to the transmission and reception of optical signals between nodes. The link unit 32b is connected to the optical switch circuit 22 by an optical line. The link unit 32b also includes a signal processing circuit that performs conversion between electrical signals transmitted via the bus 32f and data signals transmitted via the optical line. The link unit 32b may further include a processor, and the implementation form of the link unit 32b may be a processing unit or module, or a computer, etc. The processor may be one or more CPUs, DSPs, ASICs, FPGAs, or a combination thereof.

[0038] The memory unit 32d includes a storage device composed of ROM, RAM, HDD, SSD, flash memory, or a combination thereof, and a processor that performs reading and writing of data to the storage device. The processor may be one or more CPUs, DSPs, ASICs, FPGAs, or a combination thereof. After receiving a read command or a write command, the memory unit 32d reads or writes data according to the command's execution instruction based on the physical address included in the command.

[0039] (Data transmission method: Transmission from node #1 to node #2) Next, referring to Figures 4A and 4B, the operation of each node during data transfer will be explained based on the above-described example of optical communication system configuration. Here, as an example, the processing flow for data transmission from node #1 to node #2 will be explained. Figures 4A and 4B are flowcharts showing the processing flow for data transmission from node #1 to node #2. Note that the execution order of the processing steps does not necessarily have to be the order shown in Figures 4A and 4B, and some processing steps may be omitted, or multiple processing steps may be executed simultaneously or in parallel.

[0040] (S101) The application being executed by the application execution unit 31e instructs the transfer of data from logical address X1 to logical address X2. Upon receiving this instruction, the application execution unit 31e sends a transfer instruction to the switching control unit 31a indicating the transfer of data from the source logical address X1 to the destination logical address X2. Here, logical address X1 corresponds to the physical address Y1 of the memory unit 31d in node #1, and logical address X2 corresponds to the physical address Y2 of the memory unit 32d in node #2. The switching control unit 31a then sends the transfer instruction to the memory management unit 31c.

[0041] (S102) The switching control unit 31a identifies the source node as node #1 based on the logical address X1 and memory map information 311, and identifies the destination node as node #2 based on the logical address X2 and memory map information 321. The switching control unit 31a then requests the optical switch control unit 21 to connect node #1 and node #2. In response to this request, the optical switch control unit 21 controls the optical switch circuit 22 so that node #1 and node #2 are connected by an optical line.

[0042] (S103) The switching control unit 31a converts logical addresses X1 and X2 to physical addresses Y1 and Y2, respectively, based on the address translation information, and sends the information of physical addresses Y1 and Y2 to the memory management unit 31c. Note that the information of physical addresses Y1 and Y2 may also be sent to the memory management unit 31c together with the transfer instruction in S101. Alternatively, the memory management unit 31c may perform the address translation instead of the switching control unit 31a. In this case, the memory management unit 31c obtains the address translation information from the switching control unit 31a and converts the logical addresses X1 and X2 indicated by the transfer instruction to physical addresses Y1 and Y2.

[0043] (S104) The memory management unit 31c creates a read command with the physical address Y1 corresponding to the source logical address X1 as the read destination. The memory management unit 31c also queries the switching control unit 31a for the port address indicating the destination of the read command. In response, the switching control unit 31a sends the port address indicating the memory unit 31d in node #1 corresponding to the logical address X1 to the memory management unit 31c. The memory management unit 31c sends the read command, specifying the port address received from the switching control unit 31a as the destination (address specification). When the memory unit 31d successfully receives the read command, the memory management unit 31c receives an acknowledgment sent from the memory unit 31d.

[0044] (S105) The memory management unit 31c creates a write command with the physical address Y2 corresponding to the logical address X2 of the transfer destination as the write destination. The memory management unit 31c also queries the switching control unit 31a for the port address indicating the destination of the write command. Since the transfer destination is node #2, the switching control unit 31a sends the port address of the link unit 31b to the memory management unit 31c. The memory management unit 31c specifies the port address received from the switching control unit 31a as the destination (address specification) and sends out the write command. When the link unit 31b successfully receives the write command, the memory management unit 31c receives an acknowledgment sent from the link unit 31b.

[0045] The execution order of S104 and S105 may be reversed, and the processes of S104 and S105 may be executed simultaneously or in parallel. Furthermore, in the above description, the memory management unit 31c queries the switching control unit 31a for the port address, but this can be modified so that the memory management unit 31c obtains memory map information from the switching control unit 31a and identifies the port address itself. Such modifications are also included within the technical scope of this embodiment.

[0046] (S106) The link unit 31b queries the switching control unit 31a for the port address indicating the destination of the write command. The switching control unit 31a sends the port address indicating the memory unit 32d in node #2 corresponding to logical address X2 to the link unit 31b. Upon receiving this, the link unit 31b specifies the port address received from the switching control unit 31a as the destination (address specification) and sends the write command over the optical line. When the link unit 32b of node #2 successfully receives the write command, the link unit 31b receives an acknowledgment sent from the link unit 32b of node #2.

[0047] In the above description, the link unit 31b queries the switching control unit 31a for the port address, but the configuration may be modified so that the link unit 31b obtains memory map information from the switching control unit 31a and identifies the port address itself. Such modifications are also included within the technical scope of this embodiment.

[0048] (S107) The link unit 32b of node #2 sends the write command received from the link unit 31b of node #1 to the memory unit 32d of node #2, based on the port address specified by the link unit 31b of node #1. When the memory unit 32d of node #2 successfully receives the write command, the link unit 32b of node #2 receives an acknowledgment sent from the memory unit 32d of node #2.

[0049] (S108) When the link unit 32b of node #2 receives an acknowledgment from the memory unit 32d of node #2, it sends a notification to the link unit 31b of node #1 indicating that the data can be transferred. The link unit 31b also sends a notification to the memory management unit 31c indicating that the data can be transferred.

[0050] (S109, S110) The memory management unit 31c instructs the memory unit 31d to start reading data and retrieves data from the memory unit 31d. At this time, the memory unit 31d reads the data based on the physical address indicated by the read command and sends the read data to the memory management unit 31c. The memory management unit 31c transfers the data received from the memory unit 31d to the link unit 31b. The link unit 31b transfers the data received from the memory management unit 31c to the link unit 32b of node #2 via the optical line. The link unit 32b of node #2 transfers the data received via the optical line to the memory unit 32d of node #2.

[0051] (S111) The memory section 32d of node #2 writes data based on the physical address indicated by the write command. Once the process in S111 is complete, the series of processes shown in Figures 4A and 4B are terminated.

[0052] As described above, since the switching control unit 31a of node #1 holds the memory map information and address translation information of node #2, even if the optical line connection is switched when transferring data from node #1 to node #2, the data transfer procedure can be started immediately without acquiring information about node #2 after the switch. This reduces the overhead that occurs when switching optical line connections.

[0053] (Data transmission method: Transmission from node #2 to node #1) Next, referring to Figures 5A and 5B, the operation of each node during data transfer will be explained based on the above-described example of optical communication system configuration. Here, as an example, the processing flow for data transmission from node #2 to node #1 will be explained. Figures 5A and 5B are flowcharts showing the processing flow for data transmission from node #2 to node #1. Note that the execution order of the processing steps does not necessarily have to be the order shown in Figures 5A and 5B, and some processing steps may be omitted, or multiple processing steps may be executed simultaneously or in parallel.

[0054] (S201) The application being executed by the application execution unit 31e instructs the transfer of data from logical address X2 to logical address X1. Upon receiving this instruction, the application execution unit 31e sends a transfer instruction to the switching control unit 31a indicating the transfer of data from the source logical address X2 to the destination logical address X1. Here, logical address X1 corresponds to the physical address Y1 of the memory unit 31d in node #1, and logical address X2 corresponds to the physical address Y2 of the memory unit 32d in node #2. The switching control unit 31a then sends the transfer instruction to the memory management unit 31c.

[0055] (S202) The switching control unit 31a identifies the destination node as node #1 based on the logical address X1 and memory map information 311, and identifies the source node as node #2 based on the logical address X2 and memory map information 321. The switching control unit 31a then requests the optical switch control unit 21 to connect node #1 and node #2. In response to this request, the optical switch control unit 21 controls the optical switch circuit 22 so that node #1 and node #2 are connected by an optical line.

[0056] (S203) The switching control unit 31a converts logical addresses X1 and X2 to physical addresses Y1 and Y2, respectively, based on the address translation information, and sends the information of physical addresses Y1 and Y2 to the memory management unit 31c. Note that the information of physical addresses Y1 and Y2 may also be sent to the memory management unit 31c together with the transfer instruction in S201. Alternatively, the memory management unit 31c may perform the address translation instead of the switching control unit 31a. In this case, the memory management unit 31c obtains the address translation information from the switching control unit 31a and converts the logical addresses X1 and X2 indicated by the transfer instruction to physical addresses Y1 and Y2.

[0057] (S204) The memory management unit 31c creates a write command with the physical address Y1 corresponding to the logical address X1 of the transfer destination as the write destination. The memory management unit 31c also queries the switching control unit 31a for the port address indicating the destination of the write command. In response, the switching control unit 31a sends the port address indicating the memory unit 31d in node #1 corresponding to the logical address X1 to the memory management unit 31c. The memory management unit 31c sends the write command, specifying the port address received from the switching control unit 31a as the destination (address specification). When the memory unit 31d successfully receives the write command, the memory management unit 31c receives an acknowledgment sent from the memory unit 31d.

[0058] (S205) The memory management unit 31c creates a read command with the physical address Y2 corresponding to the source logical address X2 as the read destination. The memory management unit 31c also queries the switching control unit 31a for the port address indicating the destination of the read command. Since the destination is node #2, the switching control unit 31a sends the port address of the link unit 31b to the memory management unit 31c. The memory management unit 31c specifies the port address received from the switching control unit 31a as the destination (address specification) and sends out the read command. When the link unit 31b successfully receives the read command, the memory management unit 31c receives an acknowledgment sent from the link unit 31b.

[0059] The execution order of S204 and S205 may be reversed, and the processing of S204 and S205 may be executed simultaneously or in parallel. Furthermore, in the above description, the memory management unit 31c queries the switching control unit 31a for the port address, but this can be modified so that the memory management unit 31c obtains memory map information from the switching control unit 31a and identifies the port address itself. Such modifications are also included within the technical scope of this embodiment.

[0060] (S206) The link unit 31b queries the switching control unit 31a for the port address indicating the destination of the read command. The switching control unit 31a sends the port address indicating the memory unit 32d in node #2 corresponding to logical address X2 to the link unit 31b. Upon receiving this, the link unit 31b specifies the port address received from the switching control unit 31a as the destination (address specification) and sends the read command over the optical line. When the link unit 32b of node #2 successfully receives the read command, the link unit 31b receives an acknowledgment sent from the link unit 32b of node #2.

[0061] In the above description, the link unit 31b queries the switching control unit 31a for the port address, but the configuration may be modified so that the link unit 31b obtains memory map information from the switching control unit 31a and identifies the port address itself. Such modifications are also included within the technical scope of this embodiment.

[0062] (S207) The link unit 32b of node #2 sends the read command received from the link unit 31b of node #1 to the memory unit 32d of node #2, based on the port address specified by the link unit 31b of node #1. When the memory unit 32d of node #2 successfully receives the read command, the link unit 32b of node #2 receives an acknowledgment sent from the memory unit 32d of node #2.

[0063] (S208) When the link unit 32b of node #2 receives an acknowledgment from the memory unit 32d of node #2, it sends a notification to the link unit 31b of node #1 indicating that the data can be transferred. The link unit 31b also sends a notification to the memory management unit 31c indicating that the data can be transferred.

[0064] (S209, S210) The memory management unit 31c instructs the memory unit 32d of node #2 to start reading data via the link units 31b and 32b, and retrieves data from the memory unit 32d of node #2 via the link units 31b and 32b. At this time, the memory unit 32d reads the data based on the physical address indicated by the read command and sends it to the link unit 32b of node #2. The link unit 32b of node #2 transfers the data to the link unit 31b of node #1 via the optical line. The memory management unit 31c receives the data transferred from the memory unit 32d of node #2 via the optical line from the link unit 31b and transfers it to the memory unit 31d.

[0065] (S211) The memory unit 31d writes data based on the physical address indicated by the write command. Once the process in S211 is complete, the series of processes shown in Figures 5A and 5B are terminated.

[0066] As described above, since the switching control unit 31a of node #1 holds the memory map information and address translation information of node #2, even if the optical line connection is switched when transferring data from node #2 to node #1, the data transfer procedure can be started without acquiring information from node #2 after the switch. This reduces the overhead that occurs when switching optical line connections.

[0067] (First variation) Next, a first modified example according to this embodiment will be described.

[0068] (Optical communication system and node configuration) Referring to Figure 6, the configuration of the optical communication system and each node according to the first modified example will be described. Figure 6 is a block diagram showing an example configuration of the optical communication system and each node according to the first modified example.

[0069] The system configuration of the optical communication system according to the first modification is substantially the same as the system configuration shown in Figure 1. The main difference lies in the configuration of the slave nodes (nodes #2, #3, ...). As shown in Figure 6, the configuration of node #1 is the same as the configuration of node #1 shown in Figure 2. On the other hand, the configuration of node #2 is different from the configuration of node #2 shown in Figure 2. Other nodes other than node #1, such as node #3, also have substantially the same configuration as node #2. Each node may further include other components not shown, or multiple components may be integrated into a single unit or module. Such configurations may also fall within the technical scope of the first modification.

[0070] In the example in Figure 6, node #1 (the first node) is the master node, and node #2 (the second node) is the slave node. Node #1 includes the components described with reference to Figure 2. Node #2 includes a switching control unit 32a, a link unit 32b, a memory management unit 32c, a memory 32d, and an application execution unit 32e, and these components are connected via a bus 32f. For example, these components can form a bus network within the node via the bus 32f, and each has a unique port address, allowing them to communicate with each other by referring to their port addresses.

[0071] The switching control unit 32a may be a processing unit or module having a processor and a memory device, or a computer, etc. The processor may be one or more CPUs, DSPs, ASICs, FPGAs, or a combination thereof. The memory device may be ROM, RAM, HDDs, SSDs, flash memory, or a combination thereof.

[0072] The switching control unit 32a has a memory unit that holds information about each node connected to the optical switch circuit 22. The functions of this memory unit can be realized by the memory device described above. The memory unit of the switching control unit 32a holds the same information as the information in the memory unit 300 already described with reference to Figure 3 (information such as node #1 information 310, node #2 information 320, and node #3 information 330). However, as a further modification, the switching control unit 32a may hold only information about its own node, i.e., the same information as node #2 information 320. Such a form may also be included in the technical scope of the first modification.

[0073] The link unit 32b is a component that performs processing related to the transmission and reception of optical signals between nodes. The link unit 32b is connected to the optical switch circuit 22 by an optical line. The link unit 32b also includes a signal processing circuit that performs conversion between electrical signals transmitted via the bus 32f and data signals transmitted via the optical line. The link unit 32b may further include a processor, and the implementation form of the link unit 32b may be a processing unit or module, or a computer, etc. The processor may be one or more CPUs, DSPs, ASICs, FPGAs, or a combination thereof.

[0074] The memory management unit 32c is a component that generates a write command including the address to which data is written, and a read command including the address to which data is read. The memory management unit 32c may be a processing unit or module having a processor, or a computer, etc. The processor may be one or more CPUs, DSPs, ASICs, FPGAs, or a combination thereof. The memory management unit 32c refers to the memory map information held by the switching control unit 32a to identify the destination of the commands and sends out the generated write and read commands. Alternatively, the memory management unit 32c may perform address translation from logical addresses to physical addresses by referring to address translation information obtained from the switching control unit 32a, instead of the switching control unit 32a.

[0075] The memory unit 32d includes a storage device composed of ROM, RAM, HDD, SSD, flash memory, or a combination thereof, and a processor that performs reading and writing of data to the storage device. The processor may be one or more CPUs, DSPs, ASICs, FPGAs, or a combination thereof. After receiving a read command or a write command, the memory unit 32d reads or writes data according to the command's execution instruction based on the physical address included in the command.

[0076] The application execution unit 32e may be a processing unit or module having a processor and a storage device, or a computer. The storage device stores the application program and data used when the application is executed. The processor may be one or more CPUs, DSPs, ASICs, FPGAs, or a combination thereof. The storage device may be ROM, RAM, HDDs, SSDs, flash memory, or a combination thereof. The application execution unit 32e is the entity that executes the application. When accessing data, the application refers to the logical addresses described above. Because it refers to logical addresses, the application can read and write data without being aware of which node the data is actually located on.

[0077] As described above, in the first modified example, each slave node has substantially the same configuration as the master node, node #1, and in particular, it holds not only its own node's memory map information and address translation information, but also the memory map information and address translation information of other nodes. Therefore, even if the optical line connection is switched, each slave node can identify the destination of a command by referring to its logical address without obtaining information from other nodes, and furthermore, it can translate the logical address to a physical address. In addition, each node can operate as a master node, and it becomes possible to change the master node.

[0078] As described above, since the switching control unit 32a of node #2 holds the memory map information and address translation information of node #2, node #2 can convert logical addresses to physical addresses. Therefore, the method can be changed so that the memory address included in the command sent to node #2 is a logical address, and the switching control unit 32a or memory management unit 32c of node #2 converts the logical address in the command to a physical address.

[0079] In the above method, the switching control unit 31a of node #1 omits the process of converting the logical address corresponding to the memory unit 32d of node #2 to a physical address. The memory management unit 31c of node #1 includes the logical address in the command sent to the memory unit 32d of node #2. The link unit 31b of node #1 directs the command sent to node #2 to either the switching control unit 32a or the memory management unit 32c of node #2. The switching control unit 32a or the memory management unit 32c of node #2 converts the logical address in the command to a physical address before sending the command to the memory unit 32d. When the memory management unit 32c performs address translation, it refers to the address translation information obtained from the switching control unit 32a to perform the address translation.

[0080] (Data transmission method: Transmission from node #1 to node #2) Next, referring to Figures 7A and 7B, the operation of each node during data transfer will be described based on the configuration example of the optical communication system according to the first modified example described above. Here, as an example, the processing flow for data transmission from node #1 to node #2 will be described. Figures 7A and 7B are flowcharts showing the processing flow for data transmission from node #1 to node #2. Note that the execution order of the processing steps does not necessarily have to be the order shown in Figures 7A and 7B, and some processing steps may be omitted, or multiple processing steps may be executed simultaneously or in parallel.

[0081] (S301) The application being executed by the application execution unit 31e instructs the transfer of data from logical address X1 to logical address X2. Upon receiving this instruction, the application execution unit 31e sends a transfer instruction to the switching control unit 31a indicating the transfer of data from the source logical address X1 to the destination logical address X2. Here, logical address X1 corresponds to the physical address Y1 of the memory unit 31d in node #1, and logical address X2 corresponds to the physical address Y2 of the memory unit 32d in node #2. The switching control unit 31a then sends the transfer instruction to the memory management unit 31c.

[0082] (S302) The switching control unit 31a identifies the source node as node #1 based on the logical address X1 and memory map information 311, and identifies the destination node as node #2 based on the logical address X2 and memory map information 321. The switching control unit 31a then requests the optical switch control unit 21 to connect node #1 and node #2. In response to this request, the optical switch control unit 21 controls the optical switch circuit 22 so that node #1 and node #2 are connected by an optical line.

[0083] (S303) The switching control unit 31a converts the logical address X1 to the physical address Y1 based on the address translation information and sends the information of the physical address Y1 to the memory management unit 31c. The information of the physical address Y1 may also be sent to the memory management unit 31c together with the transfer instruction in S301. Alternatively, the memory management unit 31c may perform the address translation instead of the switching control unit 31a. In this case, the memory management unit 31c obtains the address translation information from the switching control unit 31a and converts the logical address X1 indicated by the transfer instruction to the physical address Y1.

[0084] (S304) The memory management unit 31c creates a read command with the physical address Y1 corresponding to the source logical address X1 as the read destination. The memory management unit 31c also queries the switching control unit 31a for the port address indicating the destination of the read command. In response, the switching control unit 31a sends the port address indicating the memory unit 31d in node #1 corresponding to the logical address X1 to the memory management unit 31c. The memory management unit 31c sends the read command, specifying the port address received from the switching control unit 31a as the destination (address specification). When the memory unit 31d successfully receives the read command, the memory management unit 31c receives an acknowledgment sent from the memory unit 31d.

[0085] (S305) The memory management unit 31c creates a write command that includes the logical address X2 of the transfer destination as information about the write destination. The memory management unit 31c also queries the switching control unit 31a for the port address that indicates the destination of the write command. Since the transfer destination is node #2, the switching control unit 31a sends the port address of the link unit 31b to the memory management unit 31c. The memory management unit 31c specifies the port address received from the switching control unit 31a as the destination (address specification) and sends out the write command. When the link unit 31b successfully receives the write command, the memory management unit 31c receives an acknowledgment sent from the link unit 31b.

[0086] The execution order of S304 and S305 may be reversed, and the processes of S304 and S305 may be executed simultaneously or in parallel. Furthermore, in the above description, the memory management unit 31c queries the switching control unit 31a for the port address, but this can be modified so that the memory management unit 31c obtains memory map information from the switching control unit 31a and identifies the port address itself. Such modifications are also included within the technical scope of the first modification.

[0087] (S306) The link unit 31b queries the switching control unit 31a for the port address indicating the destination of the write command. The switching control unit 31a sends the port address indicating the memory management unit 32c (or switching control unit 32a) in node #2 corresponding to logical address X2 to the link unit 31b. Upon receiving this, the link unit 31b specifies the port address received from the switching control unit 31a as the destination (address specification) and sends the write command over the optical line. When the link unit 32b of node #2 successfully receives the write command, the link unit 31b receives an acknowledgment sent from the link unit 32b of node #2.

[0088] In the above description, the link unit 31b queries the switching control unit 31a for the port address, but the link unit 31b may be modified to obtain memory map information from the switching control unit 31a and determine the port address itself. Such modifications are also included within the technical scope of the first modification.

[0089] (S307) The link unit 32b of node #2 sends the write command received from the link unit 31b of node #1 to the memory management unit 32c (or switching control unit 32a) of node #2, based on the port address specified by the link unit 31b of node #1. When the memory management unit 32c (or switching control unit 32a) of node #2 successfully receives the write command, the link unit 32b of node #2 receives an acknowledgment sent from the memory management unit 32c (or switching control unit 32a) of node #2.

[0090] (S308) The memory management unit 32c (or the switching control unit 32a) converts the logical address X2 in the write command to the physical address Y2. The memory management unit 32c obtains address translation information from the switching control unit 32a and converts the logical address X2 in the write command to the physical address Y2. As shown in parentheses above, in a modified case, the link unit 31b of node #1 may send the write command to the switching control unit 32a, in which case the switching control unit 32a rewrites the logical address X2 in the write command to the physical address Y2 and sends the write command to the memory management unit 31c.

[0091] (S309) The memory management unit 32c queries the switching control unit 32a for the port address corresponding to logical address X2. In response, the switching control unit 32a sends the port address of the memory unit 32d to the memory management unit 32c. The memory management unit 32c specifies the port address received from the switching control unit 32a as the destination (address specification) and sends out a write command. When the memory unit 32d successfully receives the write command, the memory management unit 32c receives an acknowledgment sent from the memory unit 32d.

[0092] (S310) When the memory management unit 32c of node #2 receives an acknowledgment from the memory unit 32d of node #2, it sends a notification to the memory management unit 31c of node #1 via the link unit 32b of node #2 and the link unit 31b of node #1 indicating that the transfer is possible.

[0093] (S311, S312) The memory management unit 31c of node #1 instructs the memory unit 31d of node #1 to start reading data and retrieves data from the memory unit 31d. At this time, the memory unit 31d reads the data based on the physical address indicated by the read command and sends the read data to the memory management unit 31c. The memory management unit 31c transfers the data received from the memory unit 31d to the link unit 31b. The link unit 31b transfers the data received from the memory management unit 31c to the link unit 32b of node #2 via the optical line. The link unit 32b of node #2 transfers the data received via the optical line to the memory management unit 32c of node #2. The memory management unit 32c transfers the data to the memory unit 32d.

[0094] (S313) The memory unit 32d of node #2 writes data based on the physical address indicated by the write command. Once the process in S313 is complete, the series of processes shown in Figures 7A and 7B are terminated.

[0095] As described above, in the first modified example, since the switching control unit 31a of node #1 and the switching control unit 32a of node #2 hold the memory map information and address translation information of node #2, even if the optical line connection is switched when transferring data from node #1 to node #2, node #1 can immediately start the data transfer procedure without acquiring information from node #2 after the switch. This reduces the overhead that occurs when switching optical line connections.

[0096] (Data transmission method: Transmission from node #2 to node #1) Next, referring to Figures 8A and 8B, the operation of each node during data transfer will be explained based on the above-described example of optical communication system configuration. Here, as an example, the processing flow for data transmission from node #2 to node #1 will be explained. Figures 8A and 8B are flowcharts showing the processing flow for data transmission from node #2 to node #1. Note that the execution order of the processing steps does not necessarily have to be the order shown in Figures 8A and 8B, and some processing steps may be omitted, or multiple processing steps may be executed simultaneously or in parallel.

[0097] (S401) The application being executed by the application execution unit 31e instructs the transfer of data from logical address X2 to logical address X1. Upon receiving this instruction, the application execution unit 31e sends a transfer instruction to the switching control unit 31a indicating the transfer of data from the source logical address X2 to the destination logical address X1. Here, logical address X1 corresponds to the physical address Y1 of the memory unit 31d in node #1, and logical address X2 corresponds to the physical address Y2 of the memory unit 32d in node #2. The switching control unit 31a then sends the transfer instruction to the memory management unit 31c.

[0098] (S402) The switching control unit 31a identifies the destination node as node #1 based on the logical address X1 and memory map information 311, and identifies the source node as node #2 based on the logical address X2 and memory map information 321. The switching control unit 31a then requests the optical switch control unit 21 to connect node #1 and node #2. In response to this request, the optical switch control unit 21 controls the optical switch circuit 22 so that node #1 and node #2 are connected by an optical line.

[0099] (S403) The switching control unit 31a converts the logical address X1 to the physical address Y1 based on the address translation information and sends the information of the physical address Y1 to the memory management unit 31c. The information of the physical address Y1 may also be sent to the memory management unit 31c together with the transfer instruction in S401. Alternatively, the memory management unit 31c may perform the address translation instead of the switching control unit 31a. In this case, the memory management unit 31c obtains the address translation information from the switching control unit 31a and converts the logical address X1 indicated by the transfer instruction to the physical address Y1.

[0100] (S404) The memory management unit 31c creates a write command with the physical address Y1 corresponding to the logical address X1 of the transfer destination as the write destination. The memory management unit 31c also queries the switching control unit 31a for the port address indicating the destination of the write command. In response, the switching control unit 31a sends the port address indicating the memory unit 31d in node #1 corresponding to the logical address X1 to the memory management unit 31c. The memory management unit 31c specifies the port address received from the switching control unit 31a as the destination (address specification) and sends out the write command. When the memory unit 31d successfully receives the write command, the memory management unit 31c receives an acknowledgment sent from the memory unit 31d.

[0101] (S405) The memory management unit 31c creates a read command that includes the source logical address X2 as the destination information. The memory management unit 31c also queries the switching control unit 31a for the port address that indicates the destination of the read command. Since the destination is node #2, the switching control unit 31a sends the port address of the link unit 31b to the memory management unit 31c. The memory management unit 31c specifies the port address received from the switching control unit 31a as the destination (address specification) and sends out the read command. When the link unit 31b successfully receives the read command, the memory management unit 31c receives an acknowledgment sent from the link unit 31b.

[0102] The execution order of S404 and S405 may be reversed, and the processing of S404 and S405 may be executed simultaneously or in parallel. Furthermore, in the above description, the memory management unit 31c queries the switching control unit 31a for the port address, but this can be modified so that the memory management unit 31c obtains memory map information from the switching control unit 31a and identifies the port address itself. Such modifications are also included within the technical scope of the first modification.

[0103] (S406) The link unit 31b queries the switching control unit 31a for the port address indicating the destination of the read command. The switching control unit 31a sends the port address indicating the memory management unit 32c (or switching control unit 32a) in node #2 corresponding to logical address X2 to the link unit 31b. Upon receiving this, the link unit 31b specifies the port address received from the switching control unit 31a as the destination (address specification) and sends the read command over the optical line. When the link unit 32b of node #2 successfully receives the read command, the link unit 31b receives an acknowledgment sent from the link unit 32b of node #2.

[0104] In the above description, the link unit 31b queries the switching control unit 31a for the port address, but the link unit 31b may be modified to obtain memory map information from the switching control unit 31a and determine the port address itself. Such modifications are also included within the technical scope of the first modification.

[0105] (S407) The link unit 32b of node #2 sends the read command received from the link unit 31b of node #1 to the memory management unit 32c (or switching control unit 32a) of node #2, based on the port address specified by the link unit 31b of node #1. When the memory management unit 32c (or switching control unit 32a) of node #2 successfully receives the read command, the link unit 32b of node #2 receives an acknowledgment sent from the memory management unit 32c (or switching control unit 32a) of node #2.

[0106] (S408) The memory management unit 32c (or the switching control unit 32a) converts the logical address X2 in the read command to the physical address Y2. The memory management unit 32c obtains address translation information from the switching control unit 32a and converts the logical address X2 in the read command to the physical address Y2. As shown in parentheses above, as a modification, the link unit 31b of node #1 may also send the read command to the switching control unit 32a. In that case, the switching control unit 32a rewrites the logical address X2 in the read command to the physical address Y2 and sends the read command to the memory management unit 31c.

[0107] (S409) The memory management unit 32c queries the switching control unit 32a for the port address corresponding to logical address X2. In response, the switching control unit 32a sends the port address of the memory unit 32d to the memory management unit 32c. The memory management unit 32c specifies the port address received from the switching control unit 32a as the destination (address specification) and sends out a read command. When the memory unit 32d successfully receives the read command, the memory management unit 32c receives an acknowledgment sent from the memory unit 32d.

[0108] (S410) When the memory management unit 32c of node #2 receives an acknowledgment from the memory unit 32d of node #2, it sends a notification to the memory management unit 31c of node #1 via the link unit 32b of node #2 and the link unit 31b of node #1 indicating that the transfer is possible.

[0109] (S411, S412) The memory management unit 31c instructs the memory unit 32d of node #2 to start reading data via the link units 31b, 32b and the memory management unit 32c, and retrieves data from the memory unit 32d of node #2. At this time, the memory unit 32d reads the data based on the physical address indicated by the read command and sends it to the link unit 32b of node #2. The memory management unit 32c of node #2 sends the data to the link unit 32b, and the link unit 32b transfers the data to the link unit 31b of node #1 via the optical line. The link unit 31b also transfers the data to the memory management unit 31c of node #1. The memory management unit 31c sends the transferred data back to the memory unit 31d.

[0110] (S413) The memory unit 31d of node #1 writes data based on the physical address indicated by the write command. Once the process in S413 is complete, the series of processes shown in Figures 8A and 8B are finished.

[0111] As described above, in the first modified example, since the switching control unit 31a of node #1 and the switching control unit 32a of node #2 hold the memory map information and address translation information of node #2, even if the optical line connection is switched when transferring data from node #2 to node #1, node #1 can immediately start the data transfer procedure without acquiring node #2's information after the switch. This reduces the overhead that occurs when switching optical line connections.

[0112] (Second variation) Next, a second modified example according to this embodiment will be described.

[0113] (Optical communication system and node configuration) Referring to Figure 9, the configuration of the optical communication system and each node in the second modified example will be described. Figure 9 is a block diagram showing an example configuration of the optical communication system and each node in the second modified example.

[0114] The system configuration of the optical communication system according to the second modified example is substantially the same as the system configuration shown in Figures 1 and 6, but as shown in Figure 9, a network (NW) topology switching unit 23 is added, and each node is connected to the optical switch circuit 22 by multiple optical lines. Because the optical line network 20 according to this embodiment and each modified example includes an optical switch circuit 22, it is possible to dynamically change the connections between nodes, and furthermore, it is possible to dynamically change the network topology. The NW topology switching unit 23 is a means for changing the network topology by controlling the optical switch circuit 22 via the optical switch control unit 21.

[0115] The network topology may be changed in response to instructions from the master server 10, or in response to instructions from a master node connected to the NW topology switching unit 23. The NW topology may be a broadband connection topology (Topology A) in which master nodes and slave nodes are connected one-to-one, or a full connection topology (Topology B) in which all nodes are connected to each other. Of course, the network topologies that can be realized by the optical network 20 are not limited to these examples.

[0116] Furthermore, the number of optical lines connecting each node to the optical switch circuit 22 may be increased to realize a specific network topology. In the example in Figure 9, each node is connected to the optical switch circuit 22 by multiple optical lines, and accordingly, node #1 is provided with multiple link units 31b1 and 31b2, and node #2 is provided with multiple link units 32b1 and 32b2. The functions of link units 31b1 and 31b2 are substantially the same as those of link unit 31b described above, and the functions of link units 32b1 and 32b2 are substantially the same as those of link unit 32b described above.

[0117] When the network topology switches, the nodes to which a node is connected change, so the master node needs to keep track of the connection relationships corresponding to the network topology. For this reason, the switching control unit 31a in the second modified example maintains network topology information 340 as shown in Figure 10. For example, the network topology information 340 includes the topology A information 341 and the topology B information 342 described above. The topology A information 341 includes information indicating which nodes are connected to node #1 by which optical line when the network topology is topology A. The topology B information 342 includes information indicating which nodes are connected to node #1 by which optical line when the network topology is topology B. As a result, even when the network topology changes, data transfer with reduced overhead is possible using the methods of this embodiment and each modified example described above.

[0118] Preferred embodiments of the present invention have been described above with reference to the attached drawings, but the present invention is not limited to these examples. It is clear to those skilled in the art that various modifications or alterations can be conceived within the scope of the claims, and these also naturally fall within the technical scope of the present invention.

[0119] For example, in the above description, all nodes were connected via optical switch circuit 22, but it is possible to modify the configuration so that at least some nodes are directly connected to the master node. It is also possible to modify the configuration of the NW topology switching unit 23 shown in Figure 9 and the NW topology information 340 shown in Figure 10 to node #1 shown in Figure 2. Furthermore, in the above description, the optical switch control unit 21 is included in the optical network 20, but it is also possible to modify the configuration so that the functions of the optical switch control unit 21 are part of the functions of the master node 10. Such modifications also fall within the technical scope of this embodiment. [Explanation of Symbols]

[0120] 10 Master Servers 20 Fiber Optic Network 21 Optical switch control unit 22 Optical switch circuit 31a, 32a Switching control unit 31b, 31b1, 31b2, 32b, 32b1, 32b2 Link section 31c, 32c Memory Management Section 31d, 32d Memory section 31e, 32e Application Execution Unit 31f, 32f bus 300 Storage section 310 Node #1 Information 311, 321, 331 Memory Map Information 312, 322, 332 Address Translation Information 320 Node #2 Information 330 Node #3 Information 340 Network Topology Information 341 Information on Topology A 342 Information on Topology B

Claims

1. An optical communication system in which multiple nodes are connected via an optical network capable of switching optical line connections, wherein each node includes a link unit that processes the transmission and reception of optical signals between nodes, and a memory unit for storing data. At least one of the plurality of nodes is the first node, A switching control unit that holds address translation information for converting logical addresses referenced by an application during memory access to physical addresses in the memory section of the corresponding node, and map information for identifying the destination of commands in each node, and when it receives a data transfer instruction, converts the source and / or destination logical addresses to the aforementioned physical addresses, A memory management unit that generates a write command including the address to which the data will be written, and a read command including the address to which the data will be read. Equipped with, If the transfer instruction indicates a data transfer from the first node to the second node, the memory management unit sends the read command to the memory unit of the first node, sends the write command to the link unit of the first node, and the link unit of the first node specifies the destination of the write command based on the map information held by the switching control unit and sends the write command to the second node. Optical communication system.

2. The link portion of the first node specifies the memory portion of the second node as the destination for sending the write command. The optical communication system according to claim 1.

3. After the memory unit of the first node receives the read command and the memory unit of the second node receives the write command, data is transmitted from the memory unit of the first node to the memory unit of the second node. The optical communication system according to claim 2.

4. If the transfer instruction indicates a data transfer from the second node to the first node, the memory management unit sends the write command to the memory unit of the first node, sends the read command to the link unit of the first node, and the link unit of the first node specifies the destination of the read command based on the map information held by the switching control unit and sends the read command to the second node. The optical communication system according to claim 1.

5. The link portion of the first node designates the memory portion of the second node as the destination for the read command. The optical communication system according to claim 4.

6. After the memory unit of the first node receives the write command and the memory unit of the second node receives the read command, data is transmitted from the memory unit of the second node to the memory unit of the first node. The optical communication system according to claim 5.

7. The read command includes the physical address as the read destination address, The write command includes the physical address as the destination address, The optical communication system according to claim 1.

8. If the second node holds the same information as the address translation information, the command sent to the second node will include a logical address, and the logical address in the command will be translated to a physical address at the second node. The optical communication system according to claim 1.

9. A data transfer method in an optical communication system in which multiple nodes are connected via an optical network capable of switching optical line connections, wherein each node includes a link unit that performs processing related to the transmission and reception of optical signals between nodes and a memory unit for storing data, and at least a first node among the multiple nodes holds address translation information for converting logical addresses referenced by an application when accessing memory to physical addresses in the memory unit of the corresponding node, and map information for identifying the destination of commands at each node, and the method is as follows: The first node performs the steps of converting the source and / or destination logical addresses to the physical addresses in response to a data transfer instruction, The first node generates a write command including the address to which the data will be written, and a read command including the address to which the data will be read, When the transfer instruction indicates a data transfer from the first node to the second node, the first node sends the read command to the memory unit of the first node, sends the write command to the link unit of the first node, and the link unit of the first node specifies the destination of the write command based on the map information and sends the write command to the second node, wherein after the memory unit of the first node receives the read command and the memory unit of the second node receives the write command, data is transmitted from the memory unit of the first node to the memory unit of the second node. A method of optical data transfer, including the transfer of optical data.

10. The aforementioned method, When the transfer instruction indicates a data transfer from the second node to the first node, the first node sends the write command to its memory unit, sends the read command to its link unit, and the link unit of the first node sends the read command to the second node, specifying the destination of the read command based on the map information, further comprising the steps of: the memory unit of the first node receives the write command, the memory unit of the second node receives the read command, and then data is transmitted from the memory unit of the second node to the memory unit of the first node. The optical data transfer method according to claim 9.

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