Semiconductor equipment and camera systems

Abstract

To provide semiconductor devices and camera systems that can be miniaturized. [Solution] The semiconductor device includes a Hall amplifier circuit HAMP and an input terminal for inputting a sensor control signal generated during periods when the image sensor is not performing image acquisition. In the Hall amplifier circuit HAMP, the differential amplifier DAMP has differential input nodes NiP and NiN for inputting the Hall voltage VH from the Hall sensor HSEN. Multiple capacitors C1p, C2p, C1n, and C2n have one end connected to the differential input nodes NiP and NiN, and determine the gain of the Hall amplifier circuit HAMP. The refresh circuit REFC causes the differential input nodes NiP and NiN to hold correction voltages Vp and Vn to cancel out the offset voltage in accordance with the refresh signal REF which is synchronized with the sensor control signal.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a camera system including the semiconductor device.

Background Art

[0002] Patent Document 1 discloses a variable gain amplifier that can perform calibration according to an offset voltage and suppress the influence of noise of an ADC. The variable gain amplifier includes a fully differential amplifier for amplifying a differential input voltage having an offset voltage. A correction voltage is applied to each of the non-inverting input node and the inverting input node of the fully differential amplifier via a resistance element from a digital-to-analog converter.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] For example, a camera system equipped with a shake correction function called OIS (Optical Image Stabilization) is known. The camera system performs shake correction, for example, by moving the OIS lens so as to cancel out shake. When moving the OIS lens, for example, a Hall element for detecting the position of the OIS lens is required. The differential detection signal from the Hall element is amplified by a differential amplifier and then used for position control of the OIS lens. However, the differential detection signal from the Hall element usually includes an offset voltage.

[0005] Therefore, in order to cancel out such offset voltages, a method can be considered in which a correction voltage is applied to the differential amplifier using a digital-to-analog converter, as shown in Patent Document 1. However, digital-to-analog converters usually require a large circuit area. As a result, semiconductor devices equipped with digital-to-analog converters and differential amplifiers can also become large. In particular, in small camera systems such as those found in smartphones, an increase in the size of the semiconductor device is undesirable.

[0006] The embodiments described later were made in view of these considerations, and other issues and novel features will become clear from the description and accompanying drawings of this specification. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment includes an amplifier circuit that amplifies a differential detection signal from a predetermined sensor with a predetermined gain, and a first input terminal that receives a sensor control signal generated during periods when the image sensor is not performing image acquisition operations. The amplifier circuit comprises a differential amplifier, a plurality of capacitors, and a refresh circuit. The differential amplifier has a differential input node for receiving the differential detection signal. One end of the plurality of capacitors is connected to the differential input node, and they determine a predetermined gain in the amplifier circuit. The refresh circuit, synchronized with the sensor control signal, causes the differential input node to hold a correction voltage to cancel out the offset voltage included in the differential detection signal. [Effects of the Invention]

[0008] According to the above embodiment, the semiconductor device can be miniaturized. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a schematic diagram showing an example of the configuration of a camera system according to the first embodiment. [Figure 2A] Figure 2A is a schematic diagram showing an example of the main components of the image sensor in Figure 1. [Figure 2B]Figure 2B is a circuit diagram showing an example of the pixel circuit configuration in Figure 2A. [Figure 3] Figure 3 is a circuit diagram showing an example configuration of the Hall amplifier circuit shown in Figure 1 in a semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a timing chart showing an example of the operation sequence in the camera system shown in Figures 1 and 3. [Figure 5] Figure 5 is a circuit diagram showing an example of a Hall amplifier circuit configuration, including details of the refresh circuit, as shown in Figure 3. [Figure 6] Figure 6 is a schematic diagram showing an example of the operation of the Hall amplifier circuit in Figure 5. [Figure 7] Figure 7 is a circuit diagram showing an example configuration of a Hall amplifier circuit in a semiconductor device according to the second embodiment, including the details of the refresh circuit shown in Figure 3. [Figure 8] Figure 8 is a timing chart showing an example of the operation sequence in the camera system shown in Figures 1 and 7. [Figure 9] Figure 9 is a circuit diagram showing an example of a Hall amplifier circuit configuration in a semiconductor device according to the third embodiment, which is a modified version of the one in Figure 5. [Figure 10] Figure 10 is a circuit diagram showing an example of a Hall amplifier circuit configuration in a semiconductor device according to the third embodiment, which is a modified version of the one in Figure 7. [Figure 11] Figure 11 is a circuit diagram showing an example configuration of the Hall amplifier circuit shown in Figure 1 in a semiconductor device according to the fourth embodiment. [Figure 12] Figure 12 is a schematic diagram showing an example of the operation of the offset cancellation circuit in Figure 11. [Figure 13] Figure 13 is a circuit diagram showing an example configuration of a Hall amplifier circuit as a comparative example. [Figure 14] Figure 14 shows an example of the characteristics of the Hall sensor in Figure 13. [Figure 15] Figure 15 is a timing chart showing an example of the operation sequence in a comparative camera system.

Best Mode for Carrying Out the Invention

[0010] In the following embodiments, when necessary for convenience, they will be described by being divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is related to a modification, detail, supplementary explanation, etc. of a part or all of the other. Also, when referring to the number of elements, etc. (number, numerical value, quantity, range, etc.), unless otherwise specified and unless it is clearly limited to a specific number in principle, it is not limited to that specific number. That is, the number of elements, etc. may be more than or less than the specific number.

[0011] Furthermore, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified and unless they are clearly considered essential in principle. Similarly, when referring to the shape, positional relationship, etc. of the constituent elements, etc., unless otherwise specified and unless it is clearly considered otherwise in principle, those substantially approximating or similar to the shape, etc. are included. This also applies to the above numerical values and ranges.

[0012] In all the drawings for explaining the embodiments, the same members are generally denoted by the same reference numerals, and the repeated explanation thereof is omitted.

[0013] (First Embodiment) <Outline of Camera System> FIG. 1 is a schematic diagram showing a configuration example of a camera system according to the first embodiment. The camera system shown in FIG. 1 includes an image sensor CIS, an OIS lens OISL, a voice coil motor VCM, and an image sensor control device ISC. Furthermore, the camera system includes a hall sensor unit HSENU, a motion sensor MSEN, and a semiconductor device DEV. The camera system is mounted as a camera module in one housing, for example, as represented by a smartphone.

[0014] The image sensor CIS is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. However, the image sensor CIS may also be a CCD (Charge Coupled Device) image sensor. The lens for OIS, OISL, collects light from a light source onto the image sensor CIS. The lens for OIS, OISL, is installed so as to be movable relative to the image sensor CIS. The voice coil motor VCM is an example of an actuator that moves the lens for OIS, OISL. The voice coil motor VCM moves the position of the lens for OIS, OISL in the X-axis direction, Y-axis direction, or Z-axis direction based on an input drive signal.

[0015] The image sensor control device ISC includes, for example, an image signal processor ISP, a clock generation circuit CKG, a microcontroller unit MCU, etc. The clock generation circuit CKG supplies a reference clock signal RCK for operation to the image sensor CIS. The microcontroller unit MCU includes a processor, a memory, etc., and controls the image sensor CIS using a sensor control signal CS. The image signal processor ISP executes various image processes on the digital pixel data PXDT output from the image sensor CIS. Examples of the content of the image process include a demosaic process, a contrast adjustment process, etc.

[0016] The hall sensor unit HSENU has, for example, three hall sensors HSENx, HSENy, HSENz. In the specification, the three hall sensors HSENx, HSENy, HSENz are collectively referred to as the hall sensor HSEN. The hall sensor HSEN is an example of a position sensor that detects the position of the lens for OIS, OISL. The three hall sensors HSENx, HSENy, HSENz respectively detect the X-axis position, Y-axis position, and Z-axis position of the lens for OIS, OISL. The motion sensor MSEN is, for example, a gyro sensor. The motion sensor MSEN detects the movement of a housing typified by a smartphone. That is, the motion sensor MSEN detects the amount of camera shake.

[0017] A semiconductor device (DEV) is, for example, a System on Chip (SoC) or microcontroller unit composed of a single semiconductor chip. In this example, the semiconductor device DEV is also the OIS control device (OISC) that controls the voice coil motor (VCM) and, consequently, the OIS lens (OISL). The semiconductor device DEV has five input terminals PN1, PN2, PN3x, PN3y, and PN3z. The semiconductor device DEV also includes internal units connected to each other by a bus BS. Furthermore, the semiconductor device DEV also includes a power supply circuit (PWG) and a clock generation circuit (CKG).

[0018] Input terminal (first input terminal) PN1 receives the sensor control signal CS from the image sensor control device ISC, specifically the microcontroller unit MCU. Input terminal (second input terminal) PN2 receives the detection signal from the motion sensor MSEN. The three input terminals PN3x, PN3y, and PN3z receive the differential detection signals, i.e., Hall voltages, from the three Hall sensors HSENx, HSENy, and HSENz, respectively.

[0019] The power supply circuit PWG receives an external power supply voltage Vcc and generates the internal power supply voltage Vdd used within the semiconductor device DEV. The clock generation circuit CKG generates the internal clock signal CK used within the semiconductor device DEV using a PLL (Phase Locked Loop) circuit or the like. The internal units connected by the bus BS include a processor PRC, volatile memory RAM, and non-volatile memory NVM. The internal units also include an amplifier circuit unit AMPU, an analog-to-digital converter ADC, a digital-to-analog converter DAC, and a driver unit DRVU. Furthermore, the internal units include a serial-to-parallel interface SPI, a control input interface CIF, and other peripheral circuits PERI.

[0020] Volatile memory (RAM) is, for example, SRAM (Static Random Access Memory). Non-volatile memory (NVM) is, for example, flash memory. The processor (PRC) includes the CPU (Central Processing Unit). Furthermore, the processor (PRC) may also include a DSP (digital signal processor) and a GPU (Graphics Processing Unit). The processor (PRC) executes a predetermined program, in this case a control program for OIS, which has been copied from the non-volatile memory (NVM) to the volatile memory (RAM).

[0021] The serial-parallel interface SPI converts the detection signal from the motion sensor MSEN input via input terminal PN2 into a parallel signal. The serial-parallel interface SPI outputs the parallel signal representing the detection result of the motion sensor MSEN to the processor PRC via bus BS. Meanwhile, the amplifier circuit unit AMPU comprises three Hall amplifier circuits HAMP1, HAMP2, and HAMP3. In this specification, the three Hall amplifier circuits HAMP1-HAMP3 are collectively referred to as the Hall amplifier circuit HAMP.

[0022] The three Hall amplifier circuits HAMP1-HAMP3 each amplify the differential detection signal input from the Hall sensor unit HSENU via the three input terminals PN3x-PN3z with a predetermined gain. The analog-to-digital converter (ADC) converts the output voltage of the Hall amplifier circuit HAMP into a digital value. The ADC outputs this digital value, i.e., the detection result of the Hall sensor HSEN, to the processor PRC via the bus BS.

[0023] Here, the processor PRC calculates the amount of manipulation required to move the OIS lens OISL based on the detection results of the motion sensor MSEN and the Hall sensor HSEN. Specifically, the processor PRC calculates the target left amount of the OIS lens OISL to compensate for camera shake based on the detection results of the motion sensor MSEN. The processor PRC also recognizes the amount of shift of the OIS lens OISL based on the detection results of the Hall sensor HSEN. Then, the processor PRC calculates the amount of manipulation required to match the shift amount of the OIS lens OISL to the target shift amount, for example, using PID (Proportional Integral Differential) control.

[0024] The processor PRC outputs the calculated manipulated variable to the digital-to-analog converter DAC via the bus BS. The digital-to-analog converter DAC converts the input manipulated variable, i.e., the digital value, into an analog value. The driver unit DRVU generates a drive signal proportional to this analog value, for example. Alternatively, the processor PRC may output the calculated manipulated variable to the driver unit DRVU via the bus BS. The driver unit DRVU may then generate a PWM (Pulse Width Modulation) signal with a duty cycle corresponding to the input manipulated variable as the drive signal.

[0025] The driver unit DRVU outputs the generated drive signal to the voice coil motor VCM. The voice coil motor VCM moves the position of the OIS lens OISL based on the input drive signal. This enables image stabilization. In other words, the focal position on the image sensor CIS can be maintained regardless of camera shake, even with light from the same light source. Details of the input terminal PN1 and the control input interface CIF will be described later.

[0026] <Overview of Image Sensors> Figure 2A is a schematic diagram showing an example of the main components of the image sensor CIS in Figure 1. Figure 2B is a circuit diagram showing an example of the pixel circuit PXC configuration in Figure 2A. The image sensor CIS shown in Figure 2A comprises multiple row selection lines RSL, multiple column readout lines CRL, and multiple pixel circuits PXC. The multiple pixel circuits PXC are arranged at the intersections of the multiple row selection lines RSL and the multiple column readout lines CRL.

[0027] Furthermore, the image sensor CIS also includes a vertical scanning circuit VSC, a horizontal scanning circuit HSC, an analog-to-digital converter ADCp, and a timing generation circuit (not shown). The vertical scanning circuit VSC scans multiple row selection lines RSL. The horizontal scanning circuit HSC scans multiple column readout lines CRL.

[0028] The image sensor CIS receives a sensor control signal CS from the microcontroller unit (MCU) and a reference clock signal RCK from the clock generation circuit (CKG). The image sensor CIS generates various timing signals synchronized with the reference clock signal RCK using a timing generation circuit and operates based on these timing signals. In general terms, the image sensor CIS sequentially performs a reset operation and an image acquisition operation, or in other words, an exposure operation, in response to a start command based on the sensor control signal CS. Furthermore, the image sensor CIS also performs an image output operation, outputting the digital pixel data PXDT acquired by the image acquisition operation to the image signal processor (ISP).

[0029] Each of the multiple pixel circuits PXC comprises a photodiode PD, a transfer transistor TRtx, and a capacitor Cfd, as shown in Figure 2B. Furthermore, the pixel circuit PXC comprises a reset transistor TRrst, an amplification transistor TRamp, and a selection transistor TRsel. First, in the reset operation, the pixel circuit PXC controls the reset transistor TRrst to be ON for a predetermined time. As a result, the pixel circuit PXC resets the pixel signal stored in the capacitor Cfd with the reset power supply voltage Vrst.

[0030] Next, during the image acquisition operation, the pixel circuit PXC controls the transfer transistor TRtx to the ON state. As a result, the pixel circuit PXC transfers the pixel signal obtained by the photodiode PD, i.e., the exposed pixel signal, to the capacitor Cfd. The pixel circuit PXC amplifies the pixel signal transferred to the capacitor Cfd using the amplification transistor TRamp and reads it out to the column readout line CRL via the selection transistor TRsel.

[0031] The image sensor CIS shown in Figure 2A converts the pixel signals read out to the column readout line CRL into digital pixel data PXDT using an analog-to-digital converter ADCp. Then, in image output operation, the image sensor CIS outputs this digital pixel data PXDT to the image signal processor ISP. At this time, the image sensor CIS also outputs, for example, a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, and a pixel clock signal PCK.

[0032] The vertical sync signal VSYNC represents the start and end points when outputting digital pixel data PXDT in units of one frame. The horizontal sync signal HSYNC represents the start and end points when outputting digital pixel data PXDT in units of one row within one frame. The pixel clock signal PCK represents the output point when outputting digital pixel data PXDT in units of one pixel within one row.

[0033] In this type of operation, the period during which the Hall amplifier circuit (HAMP) is required to operate from the perspective of image stabilization is the image acquisition period, or in other words, the exposure period. The image acquisition period, i.e., the period during which the Hall amplifier circuit (HAMP) is required to operate, occurs intermittently rather than continuously, even when shooting video, for example. In this specification, the period excluding the image acquisition period, i.e., the period during which no image acquisition operation is performed by the image sensor (CIS), is called the blanking period.

[0034] The sensor control signal CS from the microcontroller unit (MCU) is a signal generated and output during this blanking period. The specific content of the sensor control signal CS may vary depending on the specifications of the image sensor (CIS). One specific example of a sensor control signal CS is a start trigger signal to instruct the image sensor (CIS) to begin imaging. Another specific example is various setting signals to instruct the image sensor (CIS) to set various values ​​or change setting values. In this case, an I2C (Inter-Integrated Circuit) interface is used for communication of the various setting signals.

[0035] <Hall amplifier circuit (comparative example) and its problems> Figure 13 is a circuit diagram showing an example configuration of a Hall amplifier circuit HAMP-C, which serves as a comparative example. In addition to the example configuration of the Hall amplifier circuit HAMP-C, Figure 13 also shows the equivalent circuit of the Hall sensor HSEN, in other words, the Hall element. Figure 14 is a diagram showing an example of the characteristics of the Hall sensor HSEN in Figure 13. Figure 14 shows the characteristics of the Hall voltage VH that changes in response to the magnetic field B.

[0036] As shown in Figure 13, the equivalent circuit of the Hall sensor HSEN, or Hall element, is represented by a bridge circuit consisting of four resistive elements Rh1-Rh4. When the power supply voltage VCC is applied to this bridge circuit, it outputs the Hall voltage VHp on the positive side and the Hall voltage VHn on the negative side as differential detection signals. The final Hall voltage VH is obtained by the difference voltage "VHp-VHn" between the Hall voltage VHp on the positive side and the Hall voltage VHn on the negative side. Ideally, the resistance values ​​of the four resistive elements Rh1-Rh4 are all the same. In this case, the Hall voltage VH is zero [V] when the magnetic field B is zero. That is, no offset voltage is generated in the Hall voltage VH.

[0037] However, in reality, the resistance values ​​of the four resistive elements Rh1-Rh4 may differ from each other due to variations in manufacturing and temperature characteristics of the Hall elements. In this case, the Hall voltage VH may be non-zero [V] even when the magnetic field B is zero, as shown in Figure 14. That is, an offset voltage Voff is generated in the Hall voltage VH. The value of the offset voltage Voff can be either the positive or negative value for each Hall element. Thus, when a variation ΔVoff occurs in the offset voltage Voff for each Hall element, the accuracy of lens position detection, and consequently the accuracy of image stabilization, decreases in the semiconductor device DEV shown in Figure 1.

[0038] Therefore, it is conceivable to use a Hall amplifier circuit HAMP-C as shown in Figure 13. This Hall amplifier circuit HAMP-C comprises a differential output type differential amplifier DAMP, i.e., a fully differential amplifier, and four resistors R1p, R2p, R1n, and R2n. The four resistors R1p, R2p, R1n, and R2n determine the gain of the differential amplifier DAMP. Here, if the Hall voltage VH includes an offset voltage Voff, the differential amplifier DAMP will perform amplification including the DC component, the offset voltage Voff. In this case, in addition to a decrease in the accuracy of image stabilization, it is possible that the differential output voltage VOUT (=VOUTp-VOUTn) from the differential amplifier DAMP may not fall within the output range.

[0039] Therefore, the Hall amplifier circuit HAMP-C further comprises two variable resistor elements ROFp and ROFn, and two digital-to-analog converters DAC1 and DAC2. Digital-to-analog converter DAC1 applies a predetermined correction voltage to the non-inverting differential input node NiP of the differential amplifier DAMP via the variable resistor element ROFp. Similarly, digital-to-analog converter DAC2 applies a predetermined correction voltage to the inverting differential input node NiN of the differential amplifier DAMP via the variable resistor element ROFn. By applying such correction voltages, the offset voltage Voff included in the Hall voltage VH can be canceled out, and furthermore, the offset voltage generated in the differential amplifier DAMP itself can also be canceled out.

[0040] However, when using the comparative Hall amplifier circuit HAMP-C, two main problems arise. The first problem is that the inclusion of two digital-to-analog converters, DAC1 and DAC2, increases the circuit area of ​​the semiconductor device DEV. In other words, digital-to-analog converters generally require a large circuit area. On the other hand, miniaturization of the semiconductor device DEV is required, especially in camera systems such as those in smartphones. The second problem is that when starting up the Hall amplifier circuit HAMP-C, a startup test is required to determine the optimal correction voltage. The time required for the startup test may affect, for example, the startup time of the camera system.

[0041] Figure 15 is a timing chart showing an example of the operation sequence in a comparative camera system. The comparative camera system includes the same comparative semiconductor device as in Figure 1, i.e., an OIS control device. The three Hall amplifier circuits HAMP1-HAMP3 in the OIS control device are configured as shown in Figure 13. However, the comparative OIS control device does not have an input terminal PN1 or a control input interface CIF for receiving the sensor control signal CS from the image sensor control device ISC.

[0042] In Figure 15, the image sensor CIS and the comparative OIS control device begin their startup sequence at time t0. During this startup sequence, the OIS control device performs a startup test to determine the optimal correction voltage as described above. In the startup test, the OIS control device first sets initial values ​​for the two digital-to-analog converters DAC1 and DAC2 and the two variable resistor elements ROFp and ROFn. In this state, the OIS control device obtains the Hall voltage VH for each case, for example, when the OIS lens OISL is moved to the positive electrode limit position and when it is moved to the negative electrode limit position.

[0043] The OIS control unit then references two digital values ​​corresponding to the two Hall voltages VH output from the analog-to-digital converter (ADC). The OIS control unit calculates the correction voltage necessary to match the center position based on these two digital values ​​to the center position of the output range of the analog-to-digital converter (ADC). The OIS control unit sets the digital value based on this calculation result to, for example, one of the two digital-to-analog converters, DAC1 and DAC2. Once the startup sequence is completed at time t1, the OIS control unit continues to perform the image stabilization control described above.

[0044] Meanwhile, the image sensor CIS completes its startup sequence at time t2. In response, the image sensor control unit ISC, specifically the microcontroller unit MCU, outputs a sensor control signal CS to the image sensor CIS during the period from time t2 to t3. The image sensor CIS performs image acquisition and image output operations during the period from time t3 to t4 in response to the sensor control signal CS. During this time, image stabilization control by the OIS control unit is also performed in parallel.

[0045] Furthermore, using the example of motion capture, the microcontroller unit (MCU) outputs a sensor control signal (CS) to the image sensor (CIS) during the period t4-t5. In response, the image sensor (CIS) performs the second image acquisition and image output operations. Similarly, while the OIS control device continuously performs image stabilization, the image sensor (CIS) sequentially performs image acquisition and image output operations. Thus, in the comparative example camera system, the image sensor (CIS), the image sensor control device (ISC), and the OIS control device operate asynchronously with respect to each other.

[0046] In Figure 15, an example is shown where the startup sequence time for the OIS control unit is shorter than the startup sequence time for the image sensor CIS. However, if this time relationship is reversed, for example, the image sensor CIS needs to wait for the OIS control unit startup sequence to finish before performing its first image acquisition operation. In other words, the image sensor CIS needs to perform its first image acquisition operation with image stabilization control enabled. In this case, the startup time of the camera system may be longer.

[0047] <About the Hall amplifier circuit (embodiment)> Figure 3 is a circuit diagram showing an example configuration of the Hall amplifier circuit HAMP shown in Figure 1 in a semiconductor device according to the first embodiment. The Hall amplifier circuit HAMP shown in Figure 3 comprises a differential amplifier DAMP, four capacitors C1p, C2p, C1n, and C2n, and a refresh circuit REFC. The differential amplifier DAMP is a fully differential amplifier having differential input nodes NiP and NiN, as well as differential output nodes NoN and NoP. The differential input nodes NiP and NiN consist of the non-inverting differential input node NiP and the inverting differential input node NiN. The differential output nodes NoN and NoP consist of the inverting differential output node NoN and the non-inverting differential output node NoP.

[0048] Two capacitors C1p and C2p have one end connected to the non-inverting differential input node NiP. The positive Hall voltage VHp is applied to the other end of capacitor C1p as the positive differential input voltage VINp. The other end of capacitor C2p is connected to the inverting differential output node NoN. Similarly, two capacitors C1n and C2n have one end connected to the inverting differential input node NiN. The negative Hall voltage VHn is applied to the other end of capacitor C1n as the negative differential input voltage VINn. The other end of capacitor C2n is connected to the non-inverting differential output node NoP.

[0049] The four capacitors C1p, C2p, C1n, and C2n determine the gain of the Hall amplifier circuit HAMP. Specifically, two of the four capacitors, C1p and C1n, are set to the same capacitance value "C1". The remaining two capacitors, C2p and C2n, are also set to the same capacitance value "C2". In this case, the Hall amplifier circuit HAMP amplifies the Hall voltage VH, which is the differential detection signal from the Hall sensor HSEN, with a gain of "C1 / C2". The Hall amplifier circuit HAMP then outputs the amplified differential output voltages VOUTn and VOUTp to the differential output nodes NoN and NoP. Note that the two capacitors C2p and C2n are, in detail, variable capacitors to achieve variable gain.

[0050] Thus, by using a capacitor-type Hall amplifier circuit HAMP, the digital-to-analog converters DAC1 and DAC2 shown in Figure 13 can be eliminated. As a result, the circuit area of ​​the Hall amplifier circuit HAMP can be reduced, making the semiconductor device DEV smaller and less expensive. In detail, the differential input nodes NiP and NiN can hold correction voltages Vp and Vn by four capacitors C1p, C2p, C1n, and C2n. The correction voltages Vp and Vn are voltages that cancel out the offset voltage Voff included in the Hall voltage VH. As a result, the Hall amplifier circuit HAMP can amplify the input Hall voltage VH while the offset voltage Voff is canceled out.

[0051] However, the correction voltages Vp and Vn held by the differential input nodes NiP and NiN may change over time due to charge loss from the four capacitors C1p, C2p, C1n, and C2n. Therefore, a refresh circuit REFC is provided. The refresh circuit REFC refreshes the correction voltages Vp and Vn in response to a refresh signal REF that is periodically input, for example. As will be described later, the refresh signal REF is a signal synchronized with the sensor control signal CS from the microcontroller unit MCU. For this reason, the refresh circuit REFC synchronizes with the sensor control signal CS to cause the differential input nodes NiP and NiN to hold the correction voltages Vp and Vn to cancel out the offset voltage Voff.

[0052] Figure 4 is a timing chart showing an example of the operation sequence in the camera system shown in Figures 1 and 3. Figure 4 differs from Figure 15 in the following three ways. The first difference is the addition of a refresh signal REF, which is generated in synchronization with the sensor control signal CS. In detail, in Figure 1, the control input interface CIF receives the sensor control signal CS via the input terminal (first input terminal) PN1. The control input interface CIF is configured with specifications similar to, for example, the input interface of the sensor control signal CS of the image sensor CIS. For example, the control input interface CIF may be an I2C interface.

[0053] The control input interface CIF generates a refresh signal REF, which is asserted at regular intervals, for example, according to the sensor control signal CS. This regular interval can be sufficiently shorter than, for example, about 1 ms. The control input interface CIF outputs the generated refresh signal REF to the Hall amplifier circuit HAMP via the bus BS. The Hall amplifier circuit HAMP refreshes the correction voltages Vp and Vn during the assertion period of this refresh signal REF. Depending on the type of sensor control signal CS, it is also possible to use the sensor control signal CS directly as the refresh signal REF.

[0054] The second difference is that, in line with the first difference, the OIS control device OISC operates intermittently rather than continuously. That is, the OIS control device OISC does not control image stabilization during the period t2-t3 and t4-t5 when the Hall amplifier circuit HAMP is performing a refresh operation. On the other hand, the OIS control device OISC does control image stabilization during the period t3-t4 and t5-t6 when image acquisition is performed.

[0055] In detail, the OIS control unit OISC controls the system to maintain the position of the OIS lens OISL at time t4 during the period from time t4 to t5. Specifically, the processor PRC should retain the detection results of the Hall sensor HSEN and the motion sensor MSEN when the refresh signal REF is asserted. Then, the processor PRC should perform the calculation of the manipulated variable while retaining the detection results at time t4 until time t5.

[0056] A third difference is that the digital-to-analog converters DAC1 and DAC2 are no longer required, and therefore the startup sequence by the OIS control device OISC shown in Figure 15 is also unnecessary. As a result, the startup time of the camera system can be shortened in some cases. In addition, the power consumption required for this startup sequence can also be reduced.

[0057] <Details of the refresh circuit> Figure 5 is a circuit diagram showing an example configuration of the Hall amplifier circuit HAMPa, including the details of the refresh circuit REFC shown in Figure 3. The refresh circuit REFC shown in Figure 5 consists of two switches SWp and SWn that short-circuit the differential output nodes NoN and NoP and the differential input nodes NiP and NiN. Switch SWp short-circuits the inverting differential output node NoN and the non-inverting differential input node NiP. Switch SWn short-circuits the non-inverting differential output node NoP and the inverting differential input node NiN.

[0058] The two switches (first refresh switches) SWp and SWn are both controlled to be on and off in response to the refresh signal REF. Specifically, the two switches SWp and SWn are controlled to be on during the assertion period of the refresh signal REF and off during the negate period. Each of the two switches SWp and SWn may be composed of, for example, a CMOS switch.

[0059] Figure 6 is a schematic diagram showing an example of the operation of the Hall amplifier circuit HAMPa in Figure 5. During the refresh period, the Hall amplifier circuit HAMPa short-circuits the differential input nodes NiP,NiN and the differential output nodes NoN,NoP. As a result, as shown in Figure 6, the Hall amplifier circuit HAMPa functions as a unity-gain amplifier.

[0060] Here, two offset voltages, VoffN and VOFn, are applied to the inverting differential input node NiN. Offset voltage VoffN is a voltage included in the negative side Hall voltage VHn. Offset voltage VOFn is a voltage equivalent to that generated in the differential amplifier DAMP itself. Similarly, two offset voltages, VoffP and VOFp, are applied to the non-inverting differential input node NiP. Offset voltage VoffP is a voltage included in the positive side Hall voltage VHp. Offset voltage VOFp is a voltage equivalent to that generated in the differential amplifier DAMP itself.

[0061] In this case, due to the operation of the unity-gain amplifier, a voltage equal to the voltage applied to the inverting differential input node NiN is applied to the non-inverting differential input node NiP. That is, a voltage equal to the sum of the two offset voltages VoffN and VOFn is applied to the non-inverting differential input node NiP. Similarly, a voltage equal to the voltage applied to the inverting differential input node NiN is applied to the inverting differential input node NiN. That is, a voltage equal to the sum of the two offset voltages VoffP and VOFp is applied to the inverting differential input node NiN. After this refresh period, the Hall amplifier circuit HAMPa transitions to the normal period.

[0062] During normal operation, the two switches SWp and SWn are controlled to the off state. In this state, the non-inverting differential input node NiP holds the voltage "VoffN + VOFn" applied during the refresh period as a correction voltage Vp using capacitors C1p and C2p. Similarly, the inverting differential input node NiN holds the voltage "VoffP + VOFp" applied during the refresh period as a correction voltage Vn using capacitors C1n and C2n. In this state, the Hall amplifier circuit HAMPa amplifies the input Hall voltage VH. As a result, both the offset voltages VoffP and VoffN included in the Hall voltage VH and the offset voltages VOFp and VOFn generated in the differential amplifier DAMP itself can be canceled out.

[0063] In Figure 4, mentioned above, the period Tc of the image acquisition operation is 33 ms when shooting video at a low rate such as 30 fps. In reality, rates higher than 30 fps are often used, and the period Tc may be shorter than 33 ms. On the other hand, in the configuration example shown in Figure 5, charge loss may occur due to capacitors C1p, C2p, C1n, and C2n during the image stabilization control period, as described in Figure 3. In addition, leakage current may also occur through switches SWp and SWn, which are in the off state.

[0064] In this case, the refresh operation period Tref is preferably around 100 ms or less in order to maintain the correction voltages Vp and Vn with a certain degree of accuracy. This condition can be sufficiently met if the image acquisition operation period Tc is 33 ms or less. Therefore, the sensor control signal CS can be used without any problems as the synchronization signal for the refresh signal REF. Furthermore, by utilizing the existing sensor control signal CS, the circuit area overhead associated with generating the refresh signal REF can be suppressed.

[0065] <Main effects of the first embodiment> In the first embodiment described above, a capacitor-type Hall amplifier circuit HAMP is provided. The Hall amplifier circuit HAMP includes a refresh circuit REFC that synchronizes with the sensor control signal CS and holds the correction voltages Vp and Vn at the differential input nodes NiP and NiN. This allows offset correction to be performed without using a digital-to-analog converter. As a result, the semiconductor device DEV can be miniaturized. Furthermore, startup tests, i.e., startup sequences, for determining the optimal correction voltages Vp and Vn can be eliminated.

[0066] (Second Embodiment) <Details of the refresh circuit> In the second embodiment, a refresh circuit REFC different from that in Figure 5 will be described. Figure 7 is a circuit diagram showing an example configuration of a Hall amplifier circuit HAMPb in a semiconductor device according to the second embodiment, including details of the refresh circuit REFC shown in Figure 3. The refresh circuit REFC shown in Figure 7 includes a switch (second refresh switch) SWc that short-circuits two differential input nodes NiP and NiN. Switch SWc is controlled to be ON during the assertion period of the refresh signal REF and OFF during the negate period. Note that switch SWc may be configured as, for example, a CMOS switch.

[0067] Figure 8 is a timing chart showing an example of the operation sequence in the camera system shown in Figures 1 and 7. Figure 8 shows the period from time t2 in Figure 4 onwards. Also, in Figure 8, the image acquisition operation is performed up to the nth time (where n is an integer greater than or equal to 3). In Figure 8, the refresh operation period Tref is longer than in Figure 4. In this example, the refresh operation period Tref is "(n-1)*Tc".

[0068] For example, the control input interface CIF generates a refresh signal REF by downsampling the input sensor control signal CS. Specifically, the control input interface CIF generates the first refresh signal REF according to the sensor control signal CS at time t2-t3 to instruct the first image acquisition operation. Subsequently, the control input interface CIF generates the second refresh signal REF according to the sensor control signal CS at time t7-t8 to instruct the nth image acquisition operation.

[0069] The OIS control unit OISC causes the Hall amplifier circuit HAMPb to perform a refresh operation in response to the refresh signal REF at times t2-t3. From time t3 onward, the OIS control unit OISC continuously performs the image stabilization control operation until time t7. Then, in response to the refresh signal REF at times t7-t8, the OIS control unit OISC causes the Hall amplifier circuit HAMPb to perform a refresh operation again. From time t7 onward, the OIS control unit OISC continues to perform the image stabilization control operation again.

[0070] Here, the refresh circuit REFC, or switch SWc, shown in Figure 7, sets the differential voltage between the two differential input nodes NiP and NiN to zero [V] during the refresh period. As a result, the two differential input nodes NiP and NiN can hold correction voltages Vp and Vn to cancel out the offset voltage Voff included in the Hall voltage VH during the refresh period. In other words, the two differential input nodes NiP and NiN hold correction voltages Vp and Vn such that "Vp - Vn = 0 [V]".

[0071] In this way, by setting both ends of switch SWc to the same potential during the refresh period, no leakage current occurs through the off-state switch SWc during the subsequent normal period. Therefore, as shown in Figure 8, the refresh operation period Tref can be extended. For example, it is possible to set the period Tref to several seconds or more. As a result, for example, power consumption associated with the refresh operation can be reduced.

[0072] Furthermore, even if the sensor control signal CS is designed to be generated only once for multiple image acquisition operations, it can be handled without any problems. Note that in the configuration example shown in Figure 7, unlike the configuration example shown in Figure 5, the offset voltages VOFp and VOFn equivalently generated in the differential amplifier DAMP itself are not canceled out. From this perspective, it is advantageous to use the configuration example shown in Figure 5. However, generally speaking, the offset voltages VOFp and VOFn of the differential amplifier DAMP itself are sufficiently small compared to the offset voltage Voff included in the Hall voltage VH. Therefore, in practical use, there are no particular problems in using the configuration example shown in Figure 7.

[0073] <Main effects of the second embodiment> As described above, the method according to the second embodiment also provides the same effects as those described in the first embodiment. Furthermore, compared to the method of the first embodiment, the power consumption of the semiconductor device DEV can be reduced by lowering the frequency of refresh operations.

[0074] (Third embodiment) <Details of the refresh circuit> In the third embodiment, a configuration in which the differential output type differential amplifier DAMP shown in Figures 5 and 7 is replaced with a single output type differential amplifier will be described. For example, when a digital-to-analog converter DAC1 and DAC2 as shown in Figure 13 are provided, a differential output type differential amplifier DAMP is required. On the other hand, by using the configuration example shown in Figures 5 and 7, the digital-to-analog converter DAC1 and DAC2 can be made unnecessary. For this reason, a single output type differential amplifier may be used.

[0075] Specifically, in order to miniaturize the semiconductor device DEV, it is desirable to share power supply terminals between the digital-to-analog converters DAC1 and DAC2 and the differential amplifier. In this case, noise from the digital-to-analog converters DAC1 and DAC2 enters the differential amplifier via the power supply wiring. This can reduce the accuracy of the correction voltage setting. For this reason, a differential output type differential amplifier DAMP is required. This differential amplifier DAMP can remove the noise that enters via the power supply wiring as common-mode noise. On the other hand, in the configuration examples shown in Figures 5 and 7, such noise itself does not occur.

[0076] Figure 9 is a circuit diagram showing an example configuration of a Hall amplifier circuit HAMPc, which is a modified version of Figure 5, in a semiconductor device according to the third embodiment. In the Hall amplifier circuit HAMPc shown in Figure 9, the differential output type differential amplifier DAMP shown in Figure 5 is replaced with a single output type differential amplifier SAMP. Accordingly, the inverting differential output node NoN, and the capacitor C2p and switch SWp connected to it in Figure 5 are removed.

[0077] In other words, the Hall amplifier circuit HAMPc includes a differential amplifier SAMP having a single-ended output node No. In addition, the Hall amplifier circuit HAMPc includes a capacitor C1p, two capacitors C1n and C2n, and a switch SWn, similar to those in Figure 5. The switch (first refresh switch) SWn shorts the output node No of the differential amplifier SAMP with one of the differential input nodes NiP or NiN, depending on the refresh signal REF. More specifically, the switch SWn shorts the output node No with the inverting differential input node NiN.

[0078] Figure 10 is a circuit diagram showing an example configuration of a Hall amplifier circuit HAMPd, which is a modification of Figure 7, in a semiconductor device according to the third embodiment. In the Hall amplifier circuit HAMPd shown in Figure 10, the differential output type differential amplifier DAMP shown in Figure 7 is replaced with a single output type differential amplifier SAMP. Accordingly, the inverting differential output node NoN and the capacitor C2p connected to it in Figure 7 are removed.

[0079] In other words, the Hall amplifier circuit HAMPd includes a differential amplifier SAMP having a single-ended output node No. In addition, the Hall amplifier circuit HAMPd includes a capacitor C1p, two capacitors C1n and C2n, and a switch SWc, similar to those in Figure 7. The switch (second refresh switch) SWc shorts the differential input nodes NiP and NiN in response to the refresh signal REF.

[0080] By using the configuration example shown in Figure 9 or Figure 10, the circuit area can be further reduced compared to the configuration example shown in Figure 5 or Figure 7. In other words, further miniaturization and cost reduction of the semiconductor device DEV becomes possible. However, the differential amplifier SAMP can, more specifically, share a power supply terminal with the analog-to-digital converter ADC provided in the subsequent stage. For this reason, the differential amplifier SAMP needs to tolerate a certain amount of noise that enters through the power supply terminal. If the precision of the Hall amplifier circuit HAMP is required to such an extent that such noise is unacceptable, a differential output type differential amplifier DAMP can be used.

[0081] <Main effects of the third embodiment> As described above, the method according to the third embodiment can be used to obtain the same effects as those described in the first or second embodiment. Furthermore, by making the differential amplifier single-ended, the semiconductor device DEV can be made smaller compared to the method of the first or second embodiment.

[0082] (Fourth embodiment) <Details of the Hall amplifier circuit> In the fourth embodiment, a configuration is described in which a resistive element type Hall amplifier circuit, as shown in Figure 13, is used, while eliminating the need for a digital-to-analog converter. Figure 11 is a circuit diagram showing an example configuration of the Hall amplifier circuit HAMP shown in Figure 1 in the semiconductor device according to the fourth embodiment. Figure 12 is a schematic diagram showing an example of the operation of the offset cancellation circuit OFC in Figure 11.

[0083] The Hall amplifier circuit HAMPe shown in Figure 11 comprises a differential amplifier DAMP and resistors R1p, R2p, R1n, and R2n, similar to those in Figure 13. Each resistor R1p, R2p, R1n, and R2n has one end connected to the differential input nodes NiP and NiN, determining the gain of the Hall amplifier circuit HAMPe. Specifically, if the resistance of the two resistors R1p and R1n is "R1," and the resistance of the remaining two resistors R2p and R2n is "R2," the gain is determined by "R2 / R1." Note that the two resistors R1p and R1n are, in detail, variable resistors.

[0084] Furthermore, the Hall amplifier circuit HAMPe includes a refresh circuit REFCa. Unlike the case in Figure 3, the refresh circuit REFCa acquires and holds the offset voltage Voff included in the Hall voltage VH in synchronization with the sensor control signal CS. The refresh circuit REFCa then removes the held offset voltage Voff from the Hall voltage VH and outputs it to the differential input nodes NiP and NiN.

[0085] In detail, the refresh circuit REFCa has two offset canceller circuits OFCPp and OFCN. The offset canceller circuit OFCPp is inserted into the input path of the positive Hall voltage VHp to the non-inverting differential input node NiP. The offset canceller circuit OFCNn is inserted into the input path of the negative Hall voltage VHn to the inverting differential input node NiN. The two offset canceller circuits OFCPp and OFCN have the same configuration. In this specification, the two offset canceller circuits OFCPp and OFCN are collectively referred to as the offset canceller circuit OFC.

[0086] The OFC offset cancellation circuit comprises an operational amplifier circuit OPC, four switches SWb1, SWt2, SWt3, and SWb4, and a capacitor Cof. The operational amplifier circuit OPC has an inverting input node NinN, a non-inverting input node NinP, and an output node Nout. The operational amplifier circuit OPC is composed of a typical differential amplifier circuit consisting of a differential amplifier and four resistors. The operational amplifier circuit OPC is set to have a gain of 1x by four resistors with the same resistance value.

[0087] Switch (first switch) SWb1 and capacitor Cof are connected in series between the inverting input node NinN and the power supply node, for example, the ground power supply node. Switch (second switch) SWt2 connects the reference voltage node to which the reference voltage Vcm is applied to the inverting input node NinN. Switch (third switch) SWt3 connects the output node Nout to capacitor Cof. Switch (fourth switch) SWb4 connects the output node Nout to one of the differential input nodes NiP,NiN.

[0088] In detail, switch SWb4 in the offset canceling circuit OFCp connects the output node Nout to the non-inverting differential input node NiP. Switch SWb4 in the offset canceling circuit OFCn connects the output node Nout to the inverting differential input node NiN. In addition, in the offset canceling circuit OFCp, the non-inverting input node NinP of the operational amplifier circuit OPC receives the positive side Hall voltage VHp. In the offset canceling circuit OFCn, the non-inverting input node NinP of the operational amplifier circuit OPC receives the negative side Hall voltage VHn.

[0089] Here, the two switches SWt2 and SWt3 are controlled to be ON during the assertion period of the refresh signal REF. That is, the two switches SWt2 and SWt3 are both controlled to be ON for a certain period of time in synchronization with the sensor control signal CS. On the other hand, the remaining two switches SWb1 and SWb4 are both controlled to be ON and OFF in a complementary manner to the two switches SWt2 and SWt3. That is, the remaining two switches SWb1 and SWb4 are controlled to be ON during the assertion period of the inverted refresh signal BREF, which is the inverted signal of the refresh signal REF.

[0090] Figure 12 shows the operation during the assertion period of the refresh signal REF, i.e., the "H" level period, and the operation during the assertion period of the inverting refresh signal BREF. During the "H" level period of the refresh signal REF, i.e., the refresh period, two of the four switches, SWt2 and SWt3, are controlled to be ON. In this case, the operational amplifier circuit OPC outputs a difference voltage between the Hall voltage VHx at the non-inverting input node NinP and the reference voltage Vcm at the inverting input node NinN. This difference voltage "VHx-Vcm" is applied to the capacitor Cof via switch SWt3 as an offset voltage Voffx.

[0091] As a result, as shown in Figure 11, capacitor Cof in the offset canceling circuit OFCp holds the offset voltage VoffP. The offset voltage VoffP is the difference voltage "VHp-Vcm" between the Hall voltage VHp on the positive side and the reference voltage Vcm. Similarly, capacitor Cof in the offset canceling circuit OFCn holds the offset voltage VoffN. The offset voltage VoffN is the difference voltage "VHn-Vcm" between the Hall voltage VHn on the negative side and the reference voltage Vcm.

[0092] On the other hand, in Figure 12, during the "H" level period of the inverting refresh signal BREF, i.e., the normal period, two of the four switches, SWb1 and SWb4, are controlled to be ON. In this case, the operational amplifier circuit OPC outputs the difference voltage between the Hall voltage VHx at the non-inverting input node NinP and the offset voltage Voffx at the inverting input node NinN.

[0093] Thus, during the refresh period, the OFC offset canceller acquires and holds the offset voltage Voffx. Then, during the normal period, the OFC offset canceller subtracts the held offset voltage Voffx from the Hall voltage VHx and outputs the result. As a result, the OFC offset canceller can output a Hall voltage VHoc with the offset voltage Voffx canceled out, or in other words, removed.

[0094] In other words, as shown in Figure 11, the offset cancel circuit OFCp can output a Hall voltage VHocP, from which the offset voltage VoffP has been removed, toward the non-inverting differential input node NiP. Similarly, the offset cancel circuit OFCn can output a Hall voltage VHocN, from which the offset voltage VoffN has been removed, toward the inverting differential input node NiN.

[0095] <Main effects of the fourth embodiment> As described above, by using the method of the fourth embodiment, offset correction can be performed without using a digital-to-analog converter, similar to the case of the first embodiment. As a result, the semiconductor device DEV can be miniaturized. That is, the refresh circuit REFCa shown in Figure 11 can usually be constructed in a smaller area than the digital-to-analog converters DAC1 and DAC2 shown in Figure 13. Furthermore, since the digital-to-analog converters DAC1 and DAC2 are unnecessary, the startup test, i.e., the startup sequence, as described in Figure 15, can also be eliminated.

[0096] The present invention has been described in detail above based on embodiments, but the present invention is not limited to the embodiments described above and can be modified in various ways without departing from its essence. For example, the embodiments described above are described in detail in order to explain the present invention in an easy-to-understand manner and are not necessarily limited to those having all the described configurations. Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add a configuration from another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with a configuration from another embodiment. [Explanation of symbols]

[0097] ADC (Analog-to-Digital Converter) C1p, C2p, C1n, C2n, Cof capacitors CIS Image Sensor CS sensor control signal DAMP, SAMP Differential Amplifier DEV semiconductor equipment HAMP Hall Amplifier Circuit HSEN Hall Sensor ISC Image Sensor Control Unit MSEN Motion Sensor NiP, NiN differential input node NinN Inverted Input Node NinP Non-Inverting Input Node Nout output node OFC offset cancellation circuit OISC OIS control unit OISL lenses for OIS OPC (Operational Propeller) Circuit PN1, PN2 input terminals PRC Processor R1p, R2p, R1n, R2n Resistor elements REF refresh signal REFC, REFCa refresh circuit SWp,SWn,SWc,SWb1,SWt2,SWt3,SWb4 Switch VH Hall Voltage Voff offset voltage Vp, Vn Correction Voltage

Claims

1. An amplifier circuit that amplifies the differential detection signal from a predetermined sensor with a predetermined gain, A first input terminal for inputting sensor control signals generated during periods when the image sensor is not performing image acquisition operations, A semiconductor device having, The aforementioned amplifier circuit is A differential amplifier having a differential input node for inputting the differential detection signal, One end is connected to the differential input node, and a plurality of capacitors for determining the predetermined gain, A refresh circuit, synchronized with the sensor control signal, causes the differential input node to hold a correction voltage for canceling out the offset voltage included in the differential detection signal, Equipped with, Semiconductor equipment.

2. In the semiconductor device described in claim 1, The aforementioned predetermined sensor is a Hall sensor that detects the position of an OIS (Optical Image Stabilization) lens. Semiconductor equipment.

3. In the semiconductor device described in claim 2, further, An analog-to-digital converter that converts the output voltage of the aforementioned amplifier circuit into a digital value, A second input terminal for receiving detection signals from the motion sensor, A processor that calculates the amount of manipulation required to move the position of the OIS lens based on the detection signal from the motion sensor and the digital value from the analog-to-digital converter, Equipped with, Semiconductor equipment.

4. In the semiconductor device described in claim 1, The sensor control signal is a signal that instructs the image sensor to start the image acquisition operation. Semiconductor equipment.

5. In the semiconductor device described in claim 1, The refresh circuit includes a first refresh switch that, in synchronization with the sensor control signal, short-circuits the output node of the differential amplifier and at least one of the differential input nodes. Semiconductor equipment.

6. In the semiconductor device described in claim 5, The differential amplifier has differential output nodes, The first refresh switch is composed of two switches that short-circuit the differential output node and the differential input node. Semiconductor equipment.

7. In the semiconductor device described in claim 1, The refresh circuit includes a second refresh switch that short-circuits the differential input nodes in synchronization with the sensor control signal. Semiconductor equipment.

8. An amplifier circuit that amplifies the differential detection signal from a predetermined sensor with a predetermined gain, A first input terminal for inputting sensor control signals generated during periods when the image sensor is not performing image acquisition operations, A semiconductor device having, The aforementioned amplifier circuit is A differential amplifier having a differential input node for inputting the differential detection signal, One end is connected to the differential input node, and a plurality of resistors for determining the predetermined gain, A refresh circuit that, in synchronization with the sensor control signal, acquires and holds the offset voltage included in the differential detection signal, removes the held offset voltage from the differential detection signal, and outputs it to the differential input node, Equipped with, The refresh circuit has two offset cancellation circuits, each inserted into the input path of the differential detection signal to the two nodes constituting the differential input node. Each of the two offset cancellation circuits is: An operational amplifier circuit having an inverting input node, a non-inverting input node, and an output node, and set to have a gain of 1x by a resistive element, A first switch and a capacitor are connected in series between the inverting input node and the power supply node, A second switch connects a reference voltage node to which a reference voltage is applied to the inverting input node, A third switch connects the output node to the capacitor, A fourth switch connects the output node to one of the two nodes constituting the differential input node, Equipped with, The second switch and the third switch are both controlled to be ON for a certain period of time in synchronization with the sensor control signal. The first switch and the fourth switch are both controlled to be on and off in a complementary manner with respect to the second switch and the third switch. The non-inverting input node receives one of the two signals that constitute the differential detection signal. Semiconductor equipment.

9. In the semiconductor device according to claim 8, The aforementioned predetermined sensor is a Hall sensor that detects the position of an OIS (Optical Image Stabilization) lens. Semiconductor equipment.

10. In the semiconductor device described in claim 9, further, An analog-to-digital converter that converts the output voltage of the aforementioned amplifier circuit into a digital value, A second input terminal for receiving detection signals from the motion sensor, A processor that calculates the amount of manipulation required to move the position of the OIS lens based on the detection signal from the motion sensor and the digital value from the analog-to-digital converter, Equipped with, Semiconductor equipment.

11. A camera system that is mounted within a single enclosure, An image sensor that acquires images, A lens for Optical Image Stabilization (OIS) is movably mounted relative to the image sensor and focuses light from a light source onto the image sensor. A position sensor for detecting the position of the OIS lens, An image sensor control device that controls the aforementioned image sensor, A motion sensor for detecting the movement of the aforementioned housing, An OIS control device controls the position of the OIS lens based on the detection results of the position sensor and the detection results of the motion sensor, Equipped with, The OIS control device is An amplifier circuit that amplifies the differential detection signal from the position sensor with a predetermined gain, A first input terminal for inputting sensor control signals generated during periods when the image acquisition operation by the image sensor is not performed, It has, The aforementioned amplifier circuit is A differential amplifier having a differential input node for inputting the differential detection signal, One end is connected to the differential input node, and a plurality of capacitors for determining the predetermined gain, A refresh circuit, synchronized with the sensor control signal, causes the differential input node to hold a correction voltage for canceling out the offset voltage included in the differential detection signal, Equipped with, Camera system.

12. In the camera system according to claim 11, The position sensor is a Hall sensor. Camera system.

13. In the camera system according to claim 12, The OIS control device further, An analog-to-digital converter that converts the output voltage of the aforementioned amplifier circuit into a digital value, A second input terminal for receiving the detection signal from the motion sensor, A processor that calculates the amount of manipulation required to move the position of the OIS lens based on the detection signal from the motion sensor and the digital value from the analog-to-digital converter, Equipped with, Camera system.

14. In the camera system according to claim 11, The OIS control device controls the differential input node to maintain the position of the OIS lens at the start of the refresh period during which the correction voltage is held. Camera system.

Images