Level shift circuit

Abstract

This prevents excessive voltage from being applied to the transistor. [Solution] The level shift circuit 11 has a first inverter IV3 having a first input terminal Nin and a first output terminal NA, and a second inverter IV4 having a second input terminal Nin and a second output terminal NB. The first and second transistors PM5 and PM7 are connected between the third node NK and the fifth node ND and have gates connected to the first input terminal and the sixth node NE, respectively. The third and fourth transistors PM6 and PM8 are connected between the third node and the sixth node and have gates connected to the second input terminal and the fifth node, respectively. The fifth transistor NM9 and the first capacitor C1 are connected between the fifth node and the first output terminal. The sixth transistor NM10 and the second capacitor C2 are connected between the sixth node and the second output terminal. The gates of the fifth and sixth transistors and the first and second inverters are connected to the first node NVDDA.

Description

Technical Field

[0001] Embodiments generally relate to level - shift circuits.

Background Art

[0002] A level - shift circuit converts an input voltage into another voltage with a different magnitude and outputs it. Conventionally, a level - shift circuit having a tolerant function may unintentionally apply an excessive voltage to each circuit element, thereby degrading the reliability of the circuit element. There is a need for a level - shift circuit that suppresses the application of an excessive voltage to a circuit element.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a level - shift circuit having a tolerant function that suppresses the application of an excessive voltage to a circuit element.

Means for Solving the Problems

[0005] A level shift circuit according to one embodiment includes a first inverter, a second inverter, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor, a sixth transistor, and a second capacitor. The first inverter is connected between a first node receiving a first potential and a second node receiving a second potential lower than the first potential, has a first input node receiving a first signal, and has a first output node. The second inverter is connected between the first node and the second node, has a second input node receiving a signal complementary to the first signal, and has a second output node. The first transistor is connected between a third node and a fourth node receiving a second potential higher than the first potential, and has a gate connected to the first input node. The second transistor is connected between the fourth node and the fifth node, and has a gate connected to the sixth node. The third transistor is connected between the third node and the seventh node, and has a gate connected to the second input node. The fourth transistor is connected between the seventh node and the sixth node and has a gate connected to the fifth node. The fifth transistor is connected between the fifth node and the first output node and has a gate connected to the first node. The first capacitor is connected between the fifth node and the first output node. The sixth transistor is connected between the sixth node and the second output node and has a gate connected to the first node. The second capacitor is connected between the sixth node and the second output node. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a block diagram of a memory system including a level shift circuit according to the first embodiment. [Figure 2] Figure 2 is a block diagram of a transmission circuit including a level shift circuit according to the first embodiment. [Figure 3] Figure 3 is a circuit diagram of a level shift circuit used in a comparative example. [Figure 4]Figure 4 shows the potentials of several nodes and several signals over time during startup and shutdown of the comparative level shift circuit. [Figure 5] Figure 5 shows the potentials of several nodes and several signals over time during the operation of the level shift circuit of the first embodiment. [Figure 6] Figure 6 is a circuit diagram of the level shift circuit of the first embodiment. [Figure 7] Figure 7 shows the potentials of several nodes and several signals over time during the startup and shutdown of the level shift circuit of the first embodiment. [Figure 8] Figure 8 shows the potentials of several nodes and several signals over time during the operation of the level shift circuit of the first embodiment. [Figure 9] Figure 9 shows the potentials at several nodes over time during the operation of the level shift circuit in the first embodiment and comparative example. [Figure 10] Figure 10 is a circuit diagram of the level shift circuit of the second embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. All descriptions of one embodiment also apply to other embodiments unless explicitly or obviously excluded.

[0008] In this specification and the claims, "connected" to another second element means that the first element is connected to the second element directly, or via an element that is always or selectively conductive. Furthermore, "substantially identical" means that two elements are formed with the aim of being identical, but are not exactly identical due to unavoidable reasons such as limitations in the technology for generating and / or measuring these elements.

[0009] 1. First Embodiment 1.1.Configuration (Structure) A level shift circuit with a tolerant function according to the embodiment (tolerant level shifter) suppresses the application of excessive voltage to each circuit element so as not to cause damage to each circuit element. Circuit elements include, for example, transistors. Figure 1 is a block diagram of a memory system including a level shift circuit according to the first embodiment. An example of a memory system 100 including a level shift circuit according to the first embodiment includes an SSD (Solid State Drive). The memory system 100 includes a storage device 200 and a memory controller 300. The storage device 200 stores data. The memory controller 300 controls the storage device 200. In one example, the storage device 200 and the memory controller 300 are provided on a printed circuit board. The storage device 200 and the memory controller 300 are connected by wiring 400 so that they can communicate with each other. In one example, the wiring 400 is provided on a printed circuit board.

[0010] The storage device 200 includes a memory 10, an interface circuit 20, a regulator circuit 40, and a control circuit 50. The memory 10 includes memory cells and peripheral circuits, and stores data in the memory cells based on the control of the peripheral circuits. In one example, the memory 10 has the form of a chip implemented using semiconductors.

[0011] The interface circuit 20 connects the memory controller 300 and the memory 10 and performs processing for sending and receiving signals between the memory controller 300 and the memory 10. The interface circuit 20 includes input / output circuits 21 and 22 and a core logic circuit 23.

[0012] The input / output circuit 21 receives a signal from the memory controller 300 and outputs a signal based on the received signal. The input / output circuit 21 is connected to the wiring 400. The input / output circuit 21 includes a transmission circuit 1 (1a) and a reception circuit 2 (2a). The reception circuit 2a receives a signal from the memory controller 300 on the wiring 400 and transmits an output signal based on the received signal to the core logic circuit 23. The transmission circuit 1a receives a signal from the core logic circuit 23 and transmits a signal based on the received signal to the memory controller 300 on the wiring 400.

[0013] The input / output circuit 22 receives a signal from the core logic circuit 23 and outputs a signal based on the received signal. The input / output circuit 22 includes a transmission circuit 1 (1b) and a reception circuit 2 (2b). The reception circuit 2b receives a signal from the memory 10 and transmits a signal based on the received signal to the core logic circuit 23. The transmission circuit 1b receives a signal from the core logic circuit 23 and transmits a signal based on the received signal to the memory 10.

[0014] The core logic circuit 23 receives a signal from the reception circuit 2a and transmits a signal based on the received signal to the transmission circuit 1b. The core logic circuit 23 receives a signal from the reception circuit 2b and transmits a signal based on the received signal to the transmission circuit 1a.

[0015] The voltage VDDB has a fixed magnitude. In one example, the voltage VDDB is a power supply voltage supplied from outside the memory system 100. The voltage VDDB is supplied to the regulator circuit 40, as well as to the transmission circuits 1a and 1b.

[0016] The regulator circuit 40 receives a voltage and outputs another voltage of a different magnitude based on the received voltage. The regulator circuit 40 receives the voltage VDDB and operates using the voltage VDDB. The regulator circuit 40 outputs the voltage VDDA. The voltage VDDA is lower than the voltage VDDB. The voltage VDDA has a fixed magnitude. The regulator circuit 40 supplies the voltage VDDA to the transmission circuits 1a and 1b.

[0017] The control circuit 50 controls the interface circuit 20 and the regulator circuit 40. The control circuit 50 generates control signals SW1, SW2, and SW3, and supplies the control signals SW1, SW2, and SW3 to the transmission circuits 1a and 1b.

[0018] The memory controller 300 includes a core circuit 70 and an input / output circuit 80. The core circuit 70 executes various processes for controlling the storage device 200. The memory controller 300 processes and generates data stored in the storage device 200. The storage device 200 generates various signals for controlling the storage device 200.

[0019] The input / output circuit 80 receives a signal from the core circuit 70 and outputs a signal based on the received signal. The input / output circuit 80 receives a signal from the storage device 200 and transmits a signal based on the received signal to the core circuit 70. The input / output circuit 80 is connected to the wiring 400. The input / output circuit 80 includes a receiving circuit 2(1c) and a transmission circuit 1(2c).

[0020] FIG. 2 is a block diagram of a transmission circuit including the level shift circuit according to the first embodiment. As shown in FIG. 2, the transmission circuit 1 includes a level shift circuit 11 and a signal conversion circuit 12.

[0021] The signal conversion circuit 12 receives a single-ended signal Sin, and converts the received signal Sin into differential signals SGN and ~SGN. Then, the signal conversion circuit 12 outputs the signals SGN and ~SGN. The symbol "~" indicates the logic of the inversion of the logic of the signal without the symbol "~". That is, the signal without the symbol "~" and the signal with the symbol "~" are complementary to each other.

[0022] The signal conversion circuit 12 includes a buffer circuit 121 and an inverter circuit 122. The buffer circuit 121 receives a signal Sin and outputs a signal SGN. The signal SGN has the same logic as the signal Sin. At high levels, the signal SGN has a potential VDDA, and at low levels, it has a potential VSS. The potential VDDA is the potential that the wiring has when it receives the voltage VDDA. The potential VDDA has substantially the same magnitude as the voltage VDDA. The potential VSS is the potential that the wiring has when it receives a reference voltage VSS. The potential VSS has substantially the same magnitude as the reference voltage VSS. The reference voltage VSS is lower than the voltage VDDA, and in one example, it is 0V.

[0023] The inverter circuit 122 receives the signal Sin and outputs the signal ￣SGN. The signal ￣SGN has the opposite logic to the signal Sin. At high levels, the signal ￣SGN has a potential VDDA, and at low levels, it has a potential VSS.

[0024] The level shift circuit 11 receives signals SGN and ￣SGN, converts the received signals SGn and ￣SGN into a single-ended signal Sout, and outputs the signal Sout. The signal Sout has a potential VDDB at high levels and a potential VSS at low levels. The potential VDDB is the potential that the wiring has when it receives the voltage VDDB, and has substantially the same magnitude as the voltage VDDB. The level shift circuit 11 receives voltages VDDA and VDDB.

[0025] Here, we will explain the level shift circuit used in the comparative example. Figure 3 is the circuit diagram of the level shift circuit used in the comparative example.

[0026] The comparative example level shift circuit 11R includes a pre-stage circuit 500R and a post-stage circuit 600R. The pre-stage circuit 500R is a circuit that operates at the power supply potential voltage VDDA. The post-stage circuit 600R is a circuit that operates at the power supply potential voltage VDDB. Voltage VDDB is a voltage that is relatively higher than voltage VDDA. The level shift circuit 11R has a configuration in which the pre-stage circuit 500R and the post-stage circuit 600R are connected in series between the ground potential and voltage VDDB.

[0027] The preceding circuit 500R includes inverter circuits IV1, IV2, IV3, and IV4, and n-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) NM9 and NM10.

[0028] Inverter circuits IV1, IV2, IV3, and IV4 are connected in parallel between node NVDDA and node NVSS. Node NVDDA receives the voltage VDDA. Node NVSS receives the reference voltage VSS.

[0029] Inverter circuit IV1 receives the signal SGN at its input and is connected to node ￣Nin at its output. Inverter circuit IV1 outputs a high-level signal of magnitude VDDA and a low-level signal of magnitude VSS. In one example, inverter circuit IV1 includes a p-type MOSFET PM1 and an n-type MOSFET NM2. Transistors PM1 and NM2 are connected in series between node NVDDA and node NVSS in this order. Transistors PM1 and NM2 receive the signal SGN at their gates. The node to which transistors PM1 and NM2 are connected functions as node ￣Nin.

[0030] Inverter circuit IV2 receives the signal ￣SGN at its input and is connected to node Nin at its output. Inverter circuit IV2 outputs a high-level signal of magnitude VDDA and a low-level signal of magnitude VSS. In one example, inverter circuit IV2 includes a p-type MOSFET PM3 and an n-type MOSFET NM4. Transistors PM3 and NM4 are connected in series between node NVDDA and node NVSS in this order. Transistors PM3 and NM4 receive the signal ￣SGN at their gates. The node to which transistors PM3 and NM4 are connected functions as node Nin.

[0031] Inverter circuit IV3 is connected to node Nin at the input and to node NA at the output. Inverter circuit IV3 outputs a high-level signal of magnitude VDDA and a low-level signal of magnitude VSS. In one example, inverter circuit IV3 includes a p-type MOSFET PM5 and an n-type MOSFET NM6. Transistors PM5 and NM6 are connected in series between node NVDDA and node NVSS in this order. Transistors PM5 and NM6 are connected to node Nin at the gate. The node to which transistors PM5 and NM6 are connected functions as node NA.

[0032] Inverter circuit IV4 is connected to node ￣Nin at the input and to node NB at the output. Inverter circuit IV4 outputs a high-level signal of magnitude VDDA and a low-level signal of magnitude VSS. In one example, inverter circuit IV4 includes a p-type MOSFET PM12 and an n-type MOSFET NM14. Transistors PM12 and NM14 are connected in series between node NVDDA and node NVSS in this order. Transistors PM12 and NM14 are connected to node ￣Nin at the gate. The node to which transistors PM12 and NM14 are connected functions as node NB.

[0033] Transistor NM9 is connected between node ND and node NA. Transistor NM9 is connected to node NVDDA at its gate.

[0034] Transistor NM10 is connected between node NE and node NB. Transistor NM10 is connected to node NVDDA at its gate.

[0035] The circuit elements in the preamplifier circuit 500R operate at a relatively low power supply voltage VDDA. Therefore, each transistor PM1, NM2, PM3, NM4, NM9, NM10, PM11, NM13, PM12, and NM14 in the preamplifier circuit 500R can be composed of low-voltage transistors.

[0036] Low-voltage transistors may also be LVMOS (Low Voltage Metal Oxide Semiconductor) transistors. Low-voltage transistors can be realized by making the gate insulating film relatively thin. Low-voltage transistors have a relatively low threshold voltage and can be appropriately turned on or off at the voltage VDDA, which is the power supply potential of the preceding circuit 500R.

[0037] The subsequent circuit 600R includes inverter circuits IV5 and IV6, and p-type MOSFETs PM5, PM6, PM7, and PM8.

[0038] Transistor PM5 is connected between node NVDDB and node NH. Node NVDDB receives the voltage VDDB. Transistor PM5 is connected to node Nin at its gate.

[0039] Transistor PM7 is connected between node NH and node ND. Transistor PM7 is connected to node NE at its gate.

[0040] Transistor PM6 is connected between nodes NVDDB and NJ. Transistor PM6 is connected to node ￣Nin at its gate.

[0041] Transistor PM8 is connected between nodes NJ and NE. Transistor PM8 is connected to node ND at its gate.

[0042] The inverter circuit IV5 is connected to node NE at the input and to node NF at the output. The inverter circuit IV5 outputs a high-level signal of magnitude VDDB and a low-level signal of magnitude VSS. In one example, the inverter circuit IV5 includes a p-type MOSFET PM15 and an n-type MOSFET NM16. Transistors PM15 and NM16 are connected in series between node NVDDB and node NVSS in this order. Transistors PM15 and NM16 are connected to node NE at the gate. The node to which transistors PM15 and NM16 are connected functions as node NF.

[0043] The inverter circuit IV6 is connected to node NF at the input and outputs the signal Sout at the output. The inverter circuit IV6 outputs a high-level signal of magnitude VDDB and a low-level signal of magnitude VSS. In one example, the inverter circuit IV6 includes a p-type MOSFET PM17 and an n-type MOSFET NM18. Transistors PM17 and NM18 are connected in series between node NVDDB and node NVSS in this order. Transistors PM17 and NM18 are connected to node NF at the gate. The node to which transistors PM17 and NM18 are connected outputs the signal Sout.

[0044] The circuit elements in the subsequent circuit 600R operate at a relatively high power supply potential of VDDB (>VDDA). Therefore, each transistor PM5, PM6, PM7, PM8, PM15, PM16, PM17, and PM18 in the subsequent circuit 600R can be composed of high-voltage transistors.

[0045] High-voltage transistors may be HVMOS (High Voltage Metal Oxide Semiconductor) transistors or MVMOS (Middle Voltage Metal Oxide Semiconductor) transistors. High-voltage and medium-voltage transistors can be realized by using a relatively thick gate insulating film. High-voltage and medium-voltage transistors have a relatively higher threshold voltage compared to low-voltage transistors and can be appropriately turned on or off at the voltage VDDB, which is the power supply potential of the downstream circuit 600R. Also, high-voltage and medium-voltage transistors require more mounting area than low-voltage transistors.

[0046] Figure 4 shows the potentials of several nodes and several signals over time during the startup and shutdown of the comparative example level shift circuit. The startup period is from the start of the period shown in Figure 4 to time t2. The shutdown period is from time t4 to the end of the period shown in Figure 4.

[0047] At the start of the period shown in Figure 4, all nodes and signals shown in Figure 4 have a low (L) level or potential VSS. Since both nodes NVDDA and NVDDB have a low level, the level shift circuit 11 is not operating, and nodes NA, ND, NB, and NE have a low level.

[0048] The potential difference VNDA is equal to the potential VND minus the potential VNA. The potential VND is the potential at node ND. The potential VNA is the potential at node NA. The potential difference VNEB is equal to the potential VNE minus the potential VNB. The potential VNE is the potential at node NE. The potential VNB is the potential at node NB.

[0049] At time t1, a voltage VDDB is applied to node NVDDB, and node NVDDB becomes high (H) level, i.e., has a potential VDDB. Based on the fact that node NVDDB has a potential VDDB at time t1, the regulator circuit 40 starts operating. Due to the leakage current of transistors PM5, PM6, PM7, and PM8, current flows from node NVDDB to nodes ND and NE, which may cause the potential of node ND or node NE to rise.

[0050] The regulator circuit 40 takes time from the time voltage VDDB is applied until it starts outputting voltage VDDA. Therefore, even at time t1, the potential of node NVDDA is low, and nodes NA and NB are also low. As a result, both potential differences VNDA and VNEB become high, i.e., they are about the same magnitude as potential VDDB.

[0051] The regulator circuit 40 starts operating at time t1, and at time t2, after a period Δt1 has elapsed from time t1, the potential of node NVDDA becomes high, i.e., it has the potential VDDA.

[0052] Based on the high potential of node NVDDA, inverter circuits IV1, IV2, IV3, and IV4 are enabled. Based on the high potential of node NVDDA, transistor NM9 is turned on and nodes ND and NA are connected. Based on the high potential of node NVDDA, transistor NM10 is turned on and nodes NE and NB are connected. Based on the enabled inverter circuits IV1, IV2, IV3, and IV4, with nodes ND and NA connected, and nodes NE and NB connected, level shift circuit 11R is enabled.

[0053] From time t2, the level shift circuit 11R is in operation. From time t2, signals SGN and ￣SGN transition between high and low levels at timings based on the information they transmit. Figure 4 shows an example where signal ￣SGN is at a high level at time t2. Based on signal ￣SGN being at a high level, node NA becomes high level. As a result, the potential difference VNDA becomes the magnitude of potential VDDB minus the magnitude of potential VDDA. Since the difference between potentials VDDB and VDDA is small, the potential difference VNDA is small. The potentials of some nodes and some signals during the operation state will be described later with reference to Figure 5.

[0054] At time t4, the regulator circuit 40 is disabled. As a result, the potential of node NVDDA becomes low. Consequently, inverter circuits IV1, IV2, IV3, and IV4 are disabled.

[0055] From time t4 onward, both signals SGN and ￣SGN remain at low levels. Figure 4 shows an example where signal ￣SGN changes from a high level to a low level at time t4. Based on the fact that signal ￣SGN is at a low level, node NA also becomes low level.

[0056] Based on the low potential of node NVDDA, transistor NM9 is turned off. This disconnects nodes ND and NA. Based on the low potential of node NVDDA, transistor NM10 is turned off. This disconnects nodes NE and NB.

[0057] From time t4 onward, node NVDDB still has potential VDDB. Therefore, due to the leakage currents of transistors PM5, PM6, PM7, and PM8, current flows from node NVDDB into nodes ND and NE, causing the potential of node ND or node NE to remain high or rise, and thus potentially have potential VDDB. As a result, a potential difference is created between node ND and node NA, and between node NE and node NB, with an magnitude equal to the magnitude of potential VDDB minus the magnitude of potential VSS. This potential difference is applied to transistor NM9 or NM10, which can reduce the reliability of transistors NM9 and NM10.

[0058] At time t6, after a period Δt2 has elapsed from time t4, the application of voltage VDDB to node NVDDB is stopped. As a result, node NVDDB will have a low level.

[0059] Figure 5 shows the potentials of several nodes and several signals over time during the operation of the comparative example level shift circuit. Figure 5 shows the period during operation, i.e., the period between time t3 and time t4 in the period shown in Figure 4. Figure 5 shows, as an example, the case where the signal SGN is the clock.

[0060] At time t11, signal SGN becomes high level, and signal ￣SGN becomes low level. As a result, the potential of node ￣Nin becomes low level, and the potential of node Nin becomes high level. Due to this change in potential, the potential of node NA becomes low level, and the potential of node NB becomes high level.

[0061] The potential of node ND follows the change in the potential of node NA. At time t11, the potential of node NA is low, but due to various factors including parasitic capacitance in the wiring, the change in the potential of node ND lags behind the change in the potential of node NA. Therefore, at time t12, before the potential of node ND becomes low and the potential difference VNDA becomes substantially zero, immediately after time t11, the potential difference VNDA has a peak magnitude Vpr1. Thus, a voltage of substantially the same magnitude as the potential Vpr1 is applied to transistor NM9. The peak of the potential difference VNDA can exceed the voltage Vul1. This leads to the application of a high voltage to transistor NM9, which may destroy transistor NM9 or shorten its lifetime. As a result, the reliability of transistor NM9 is reduced. Voltage Vul1 is the upper limit of voltage that is allowed to be applied to transistor NM9.

[0062] At time t13, signal SGN becomes low level, and signal ￣SGN becomes high level. As a result, the potential of node ￣Nin becomes high level, and the potential of node Nin becomes low level. Due to this change in potential, the potential of node NA becomes high level, and the potential of node NB becomes low level.

[0063] The potential of node NE follows the change in the potential of node NB. At time t13, the potential of node NB is low, but due to various factors including parasitic capacitance in the wiring, the change in the potential of node NE lags behind the change in the potential of node NB. Therefore, at time t14, before the potential of node NE becomes low and the potential difference VNEB becomes substantially zero, immediately after time t13, the potential difference VNEB has a peak magnitude Vpr2. Thus, a voltage of substantially the same magnitude as the potential Vpr2 is applied to transistor NM10. The peak of the potential difference VNEB can exceed the voltage Vul2. This leads to the application of a high voltage to transistor NM10, which may destroy transistor NM10 or shorten its lifetime. As a result, the reliability of transistor NM10 is reduced. Voltage Vul2 is the upper limit of the voltage that is allowed to be applied to transistor NM10.

[0064] A level-shift circuit of the first embodiment, which improves upon the problems of the comparative examples described above, will now be described. Figure 6 is a circuit diagram of the level-shift circuit of the first embodiment. As shown in Figure 6, the level-shift circuit 11 includes a pre-stage circuit 500 and a post-stage circuit 600. The pre-stage circuit 500 includes inverter circuits IV1, IV2, IV3, and IV4, n-type MOSFETs NM9 and NM10, and capacitors C1 and C2. The post-stage circuit 600 includes inverter circuits IV5 and IV6, p-type MOSFETs PM5, PM6, PM7, PM8, PM19, PM20, PM22, PM21, PM23, and PM25, and n-type MOSFET NM24. The following description will mainly focus on the configuration and operation that differ from the comparative examples. For the configuration and operation of the first and second embodiments described later, all descriptions of the comparative examples apply to points not described.

[0065] Capacitor C1 is connected in parallel between node ND and node NA.

[0066] Capacitor C2 is connected in parallel between node NE and node NB.

[0067] Transistor PM19 is connected between node NVDDB and node NK. Node NVDDB receives the voltage VDDB. Transistor PM19 receives the control signal SW1 at its gate.

[0068] Transistor PM5 is connected between node NK and node NH.

[0069] Transistor PM6 is connected between node NK and node NJ.

[0070] Transistor PM8 is connected between nodes NJ and NE. Transistor PM8 is connected to node ND at its gate.

[0071] Transistors PM20 and PM22 are connected in series between node ND and node NVSS in this order. Transistor PM20 receives the control signal SW2 at its gate. Transistor PM22 is connected to node NVDDA at its gate.

[0072] Transistors PM21 and PM23 are connected in series between node NE and node NVSS in this order. Transistor PM21 receives the control signal SW2 at its gate. Transistor PM23 is connected to node NVDDA at its gate.

[0073] Transistors PM15 and NM16 are connected in this order in series between node NVDDB and node NI.

[0074] Transistor NM24 is connected between node NI and node NVSS. Transistor NM24 receives the control signal SW3 at its gate.

[0075] Transistor PM25 is connected between node NVDDB and node NF. Transistor PM25 receives the control signal SW3 at its gate.

[0076] The breakdown voltages of the transistors included in inverter circuits IV1, IV2, IV3, and IV4, as well as transistors NM9 and NM10, are lower than those of transistors PM5, PM6, PM7, PM8, PM19, PM20, PM21, PM22, PM23, NM24, and PM25, as well as the breakdown voltages of the transistors included in inverter circuits IV5 and IV6. That is, the breakdown voltages of the transistors PM1, NM2, PM3, NM4, PM11, NM13, PM12, NM14, NM9, and NM10 included in the pre-stage circuit 500 are lower than those of transistors PM5, PM6, PM7, PM8, PM15, NM16, PM17, NM18, PM19, PM20, PM21, PM22, PM23, NM24, and PM25 included in the post-stage circuit 600. Low-breakdown transistors may be LVMOS transistors, and high-breakdown transistors may be HVMOS transistors or MVMOS transistors.

[0077] 1.2.Operation Figure 7 shows the potentials of several nodes and several signals over time during the startup and shutdown of the level shift circuit of the first embodiment. The startup period spans from the start of the period shown in Figure 7 to time t2. The shutdown period spans from time t4 to the end of the period shown in Figure 7.

[0078] At the start of the period shown in Figure 7, all nodes and signals shown in Figure 7 are at a low (L) level or potential VSS. Since both nodes NVDDA and NVDDB are at a low level, the level shift circuit 11 is not operating, and nodes NA, ND, NB, and NE are at a low level.

[0079] Because the control signal SW1 is at a low level, transistor PM19 is on, and node NK is connected to node NVDDB.

[0080] Because control signal SW2 is at a low level, transistors PM20 and PM21 are on. Because node NVDDA is at a low level, transistors PM22 and PM23 are on. Because transistors PM20, PM21, PM22, and PM23 are on, nodes ND and NE are connected to node NVSS and have the potential of node NVSS.

[0081] Because control signal SW3 is at a low level, transistor NM24 is off and transistor PM25 is on. Because transistor NM24 is off, node NI is disconnected from node NVSS. Because node NI is disconnected from node NVSS, inverter circuit IV5 is disabled. Because transistor PM25 is on, node NF is connected to node NVDDB.

[0082] At time t1, the control signal SW1 is set to a high level. This turns off transistor PM19, and node NK is disconnected from node NVDDB. Due to leakage currents from transistors PM5, PM6, PM7, and PM8, current flows from node NK to nodes ND and NE, potentially raising the potential of node ND or node NE. However, since the potential VDDB is not applied to node NK via node NVDDB, even if leakage currents occur in transistors PM5, PM6, PM7, and PM8, the rise in potential of nodes ND and NE is suppressed. Therefore, at time t1, nodes ND and NE remain at a low level.

[0083] The regulator circuit 40 takes time from the time voltage VDDB is applied until it starts outputting voltage VDDA. Therefore, even at time t1, the potential of node NVDDA is low, and nodes NA and ND are also low. Consequently, the potential difference VNDA is low (effectively zero), and the potential difference VNEB is also low.

[0084] The regulator circuit 40 starts operating at time t1, and at time t2, after a period Δt1 has elapsed from time t1, transistors PM22 and PM23 are turned off based on the fact that the potential of node NVDDA is at a high level.

[0085] At time t2, the control signal SW1 is set to a low level. As a result, node NK is connected to node NVDDB, and the potential VDDB on node NVDDB is transmitted to node NK. This enables the level shift circuit 11.

[0086] At time t2, the control signal SW2 is set to a high level. As a result, transistors PM20 and PM21 are turned off.

[0087] Based on the fact that transistors PM20, PM21, PM22, and PM23 are turned off, nodes ND and NE are disconnected from node NVSS.

[0088] At time t3, after a period Δt3 has elapsed from time t2, the control signal SW3 is set to a high level. As a result, node NI is connected to node NVSS. Consequently, the inverter circuit IV5, and thus the level shift circuit 11, are enabled.

[0089] Based on the control signal SW3 being set to high level, transistor PM25 is turned off, node NF is disconnected from node NVDDB, and a potential based on the potential of node NF is output as signal Sout.

[0090] From time t3, the level shift circuit 11 is in operation. The potentials of some nodes and some signals during the operation state will be described later with reference to Figure 8.

[0091] At time t2, nodes ND and NE are disconnected from node NVSS, and the potentials of nodes ND and NE can be affected by the inflow of current due to the leakage current of transistors PM5, PM6, PM7, and PM8. As a result, either node ND or node NE may become high level. Figure 7 shows an example where node ND becomes high level. When node ND becomes high level, the potential difference VNDA becomes the magnitude of potential VDDB minus the magnitude of potential VDDA. Since the difference between potentials VDDB and VDDA is small, the potential difference VNDA is small.

[0092] From time t4 onward, signals SGN and ￣SGN remain at low levels. Figure 7 shows an example where signal ￣SGN changes from a high level to a low level at time t4. Based on the low level of signal ￣SGN, nodes NA and ND also become low levels.

[0093] Based on the low potential of node NVDDA, transistor NM9 is turned off. This disconnects nodes ND and NA. Based on the low potential of node NVDDA, transistor NM10 is turned off. This disconnects nodes NE and NB.

[0094] Based on the low potential of node NVDDA, transistors PM22 and PM23 are turned on.

[0095] At time t4, the control signal SW3 is set to a low level. This turns off transistor NM24 and disables inverter circuit IV5. Based on the low level of control signal SW3, transistor PM25 is turned on. This fixes the potential of node NF to the potential of node NVDDB.

[0096] At time t5, after a period Δt4 has elapsed from time t4, the control signal SW2 is set to a low level. As a result, transistors PM20 and PM21 are turned on.

[0097] Based on the activation of transistors PM20, PM21, PM22, and PM23, nodes ND and NE are connected to node NVSS and fixed to the potential of node NVSS.

[0098] At time t5, the control signal SW1 is set to high level. This turns off transistor PM19. With transistor PM19 turned off, node NK is disconnected from node NVDDB, and the potential of node NVDDB is not transmitted to node NK. Therefore, even if leakage current occurs in transistors PM20, PM21, PM22, and PM23, the rise in potential of nodes ND and NE is suppressed. For this reason, nodes ND and NE remain at low levels even at time t5. Therefore, the potential difference VNDA remains at a low level.

[0099] Figure 8 shows the potentials of several nodes and several signals over time during the operation of the level shift circuit of the first embodiment. Figure 8 shows the period during operation, i.e., the period between time t3 and time t4 in the period shown in Figure 7. Figure 8 shows, as an example, the case where the signal SGN is the clock.

[0100] As shown above with reference to Figure 5, the change in potential at node ND lags behind the change in potential at node NA. Therefore, at time t12, before the potential at node ND becomes low and the potential difference VNDA becomes substantially zero, immediately after time t11, the potential difference VNDA has a peak magnitude Vp1. Thus, a voltage of substantially the same magnitude as potential Vp1 is applied to transistor NM9. However, nodes NA and ND are coupled by capacitor C1, and therefore, the decrease in potential at node ND approaches the decrease in potential at node NA. Thus, the peak magnitude Vp1 of the potential difference VNDA is lower than the voltage Vul1. In other words, the potential difference VNDA is always lower than the voltage Vul1.

[0101] As shown above with reference to Figure 5, the change in potential at node NE lags behind the change in potential at node NB. The potential at node NE becomes high at a time after time t11. Here, node NB oscillates with voltage VSS-VDDA, and node NE oscillates with voltage VSS-VDDB. Based on the high level of potential at node NE, the potential difference VNEB is the magnitude of potential VDDB minus the magnitude of potential VDDA.

[0102] At a time after t11, the potential of node NF becomes the opposite logic level to that of signal SGN, i.e., a low level. Based on the low level of node NF's potential, signal Sout becomes a high level.

[0103] As described above, the change in potential at node NE lags behind the change in potential at node NB. Therefore, at time t14, before the potential at node NE becomes low and the potential difference VNEB becomes virtually zero, immediately after time t13, the potential difference VNEB has a peak magnitude Vp2. Thus, a voltage of substantially the same magnitude as potential Vp2 is applied to transistor NM10. However, nodes NB and NE are coupled by capacitor C2, and therefore, the decrease in potential at node NE approaches the decrease in potential at node NB. Thus, the peak magnitude Vp2 of potential difference VNEB is lower than the voltage Vul2. In other words, potential difference VNEB is always lower than voltage Vul2.

[0104] As described above, the change in potential at node ND lags behind the change in potential at node NA. Therefore, the potential at node ND becomes high at a time after time t13. Here, node NA receives voltage VDDA and node ND receives voltage VDDB. Based on the high level of potential at node ND, the potential difference VNDA is the magnitude of potential VDDB minus the magnitude of potential VDDA.

[0105] At a time after t13, the potential of node NF becomes the opposite logic level to that of signal SGN, i.e., a high level. Based on the high level of the potential of node NF, signal Sout becomes a low level.

[0106] The behavior caused by the signal SGN becoming high-level after time t14 is the same as the behavior caused by the signal SGN becoming high-level at time t11.

[0107] The behavior caused by the signal SGN becoming low level after time t14 is the same as the behavior caused by the signal SGN becoming low level at time t13.

[0108] The potential difference VNDA of the comparative example and the first embodiment will be described in detail. Figure 9 is a diagram showing the potentials of several nodes over time during the operation of the level shift circuit in the first embodiment and the comparative example. Figure 9 shows an enlarged view of the potentials of nodes NA and ND in Figures 5 and 8 from time t11 onwards. As shown in Figure 9, in the comparative example, the falling edge of the potential of node NA falls vertically. Also, as described above with reference to Figure 5, the change in the potential of node ND lags behind the change in the potential of node NA. For example, suppose that it takes time Tx for the potential of node ND in the comparative example to finish falling. Because the falling edge of the potential of node ND is slower than that of node NA, the potential difference VNDA in the comparative example is greater than or equal to the voltage Vul1.

[0109] In the first embodiment, as shown in Figure 9, the potential fall of node NA is not vertical, but gradualer than that of the comparative example. On the other hand, the potential fall of node ND is faster than that of the comparative example. For example, in the first embodiment, it takes time Ty for the potential of node ND to finish falling. At this time, time Ty is shorter than time Tx, and the fall times of the potential of node NA and the fall times of the potential of node ND are approaching each other. This is because the capacitive coupling of node NA and node ND by capacitor C1 averages out the changes in the potential of node NA and the changes in the potential of node ND. Therefore, the potential difference VNDA in the first embodiment is less than or equal to the voltage Vul1. Although nodes NA and ND and the voltage difference VNDA have been described here, the same phenomenon occurs with nodes NB and NE and the voltage difference VNEB.

[0110] 1.3. Advantages (Effects) According to the first embodiment, the peak magnitude Vp1 of the potential difference VNDA is suppressed. Similarly, the peak magnitude Vp2 of the potential difference VNEB is suppressed. As a result, the degradation of the reliability of transistors NM9 and NM10 is suppressed.

[0111] Furthermore, according to the first embodiment, transistor PM19 is provided between node NVDDB and node NK, transistors PM20 and PM22 are provided between node ND and node NVSS, and transistors PM21 and PM23 are provided between node NE and node NVSS. Transistor PM19 is turned off while node NVDDB has a potential VDDB and node NVDDA has a potential VSS. Therefore, the potential VDDB on node NVDDB prevents node ND or node NE from rising to the potential VDDB. Thus, a potential difference equal to the difference between the magnitude of potential VDDB and the magnitude of potential VSS is prevented from occurring across transistor NM9 or NM10, and the decrease in reliability of transistors NM9 and NM10 is suppressed.

[0112] Transistors PM20, PM21, PM22, and PM23 are turned on while node NVDDB has potential VDDB and node NVDDA has potential VSS. Therefore, nodes ND and NE are connected to node NVSS by transistors PM20, PM21, PM22, and PM23 while node NVDDB has potential VDDB and node NVDDA has potential VSS. Thus, even if potential VDDB on node NVDDB and leakage current from transistor PM19 flow into node ND or node NE, the rise in potential of nodes ND and NE is suppressed.

[0113] The level shift circuit of the first embodiment includes transistors NM24 and PM25. Transistor NM24 is off and transistor PM25 is on while node NVDDB has potential VDDB and node NVDDA has potential VSS. Therefore, while node NVDDB has potential VDDB and node NVDDA has potential VSS, the signal Sout is fixed at a low level and is suppressed from becoming an intermediate level. Thus, the intermediate level signal Sout turns on both the p-type transistor and the n-type transistor of the inverter circuit that receives the signal Sout, and current flow between the node at power supply potential and the node at common potential through these transistors is suppressed.

[0114] Furthermore, the level shift circuit of the first embodiment includes capacitors C1 and C2, and transistors PM19, PM20, PM21, PM22, PM23, PM24, and PM25. This allows for suppression of a decrease in the reliability of the LVMOS transistors even when the transistors of the preceding circuit 500 are implemented as LVMOS transistors. In other words, a decrease in transistor reliability can be suppressed even without applying HVMOS transistors or MVMOS transistors to the transistors of the preceding circuit 500. As a result, it becomes possible to suppress the current consumption of the level shift circuit without compromising the reliability of the transistors, compared to the case where the transistors of the preceding circuit 500 are implemented as HVMOS transistors. In addition, it becomes possible to reduce the mounting area of ​​the level shift circuit without compromising the reliability of the transistors.

[0115] 2. Second Embodiment Figure 10 is a circuit diagram of the level shift circuit of the second embodiment. As shown in Figure 10, the level shift circuit 11B of the second embodiment differs from the first embodiment in that it further includes an n-type MOSFET NM25 in the subsequent circuit 600B. The structure and operation, which are the same as those of the first embodiment, will not be described. The transistor NM25 of the level shift circuit 11B is connected between node ND and node NF. The transistor NM25 receives the control signal SW3 at its gate.

[0116] While the level shift circuit 11B is operating, the control signal SW3 is at a high level, and therefore transistor NM25 is on. As a result, the potential of node ND is added to the potential of node NF. Since node ND has a logic level opposite to the logic level of signal SGN, when the logic level of signal SGN becomes high, the potential of node ND becomes low. The low potential of node ND assists in the decrease of the potential of node NF, thus accelerating the decrease in the potential of node NF. On the other hand, when the logic level of signal SGN becomes low, the high potential of node ND assists in the increase of the potential of node NF, thus accelerating the increase in the potential of node NF. As a result, the duty cycle of the potential of node NF is high.

[0117] According to the second embodiment, the level shift circuit 11B can output a signal Sout with a high duty cycle. Thus, in addition to the advantages of the first embodiment, the level shift circuit of the second embodiment can improve the accuracy of communication between the storage device and the memory controller.

[0118] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0119] 100...Memory system, 200...Storage device, 300...Memory controller, 400...Wiring, 10...memory, 20… Interface circuit, 21…Input / Output Circuits, 22…Input / Output Circuits, 23…Core logic circuit, 40... Regulator circuit, 50...control circuit, 70... Core circuit, 80…Input / Output Circuit 80 1...Transmitter circuit, 2...receiving circuit, 11... Level shift circuit, 12... Signal conversion circuit

Claims

1. A first inverter is connected between a first node receiving a first potential and a second node receiving a second potential lower than the first potential, and has a first input node that receives a first signal and a first output node. A second inverter having a second input node connected between the first node and the second node, which receives a signal complementary to the first signal, and a second output node, A first transistor having a gate connected to the first input node, which is connected between a third node and a fourth node that receive a second potential higher than the first potential, A second transistor having a gate connected between the fourth node and the fifth node and connected to the sixth node, A third transistor having a gate connected between the third node and the seventh node and connected to the second input node, A fourth transistor having a gate connected between the seventh node and the sixth node and connected to the fifth node, A fifth transistor having a gate connected to the first node and connected to the fifth node, A first capacitor connected between the fifth node and the first output node, A sixth transistor having a gate connected between the sixth node and the second output node and connected to the first node, A second capacitor connected between the sixth node and the second output node, A level shift circuit equipped with this feature.

2. A seventh transistor connected between the third node and the first transistor, and between the third node and the third transistor, The eighth transistor connected between the fifth node and the eighth node, A ninth transistor having a gate connected between the eighth node and the second node and connected to the first node, A 10th transistor is connected between the 6th node and the 9th node and has a gate connected to the gate of the 8th transistor, A 11th transistor having a gate connected between the 9th node and the 2nd node and connected to the 1st node, Furthermore, The level shift circuit according to claim 1.

3. The seventh transistor has a gate that receives a second signal, The gate of the eighth transistor and the gate of the tenth transistor receive the third signal. During the first period in which the third node has the second potential and the first node has a third potential lower than the first potential, the second signal has a potential magnitude that turns off the seventh transistor, and the third signal has a potential magnitude that turns on the eighth and tenth transistors. The level shift circuit according to claim 2.

4. The aforementioned first period includes the second and third periods, The second period is the period from when the third node had the second potential until the first node, which had the third potential, has the first potential. The third period is the period after the first node, which had the first potential while the third node had the second potential, has acquired the third potential. The level shift circuit according to claim 3.

5. A third inverter having a third input node connected between the third node and the tenth node, and a fourth output node, An eleventh transistor connected between the tenth node and the second node, A 12th transistor connected between the third node and the fourth output node, A fourth inverter having an input node connected between the third node and the second node and connected to the fourth output node, Furthermore, The level shift circuit according to claim 1.

6. The 11th transistor has a gate that receives a fourth signal, The 12th transistor has a gate that receives the 4th signal, During the first period in which the third node has the second potential and the first node has a third potential lower than the first potential, the fourth signal has a potential magnitude that turns on both the eleventh transistor and the twelfth transistor. The level shift circuit according to claim 5.

7. The system further comprises a thirteenth transistor connected between the fifth node and the fourth output node. The level shift circuit according to claim 5.

8. The 13th transistor has a gate that receives a fourth signal, While the third node has the second potential and the first node has the first potential, the fourth signal has a potential magnitude that turns on the thirteenth transistor. The level shift circuit according to claim 7.

9. A third inverter having a third input node connected between the third node and the tenth node, and a fourth output node, An eleventh transistor connected between the tenth node and the second node, A 12th transistor connected between the third node and the fourth output node, A fourth inverter having an input node connected between the third node and the second node and connected to the fourth output node, Furthermore, The level shift circuit according to claim 2.

10. The seventh transistor has a gate that receives a second signal, The gate of the eighth transistor and the gate of the tenth transistor receive the third signal. The 11th transistor has a gate that receives a fourth signal, The 12th transistor has a gate that receives the 4th signal, During the first period in which the third node has the second potential and the first node has a third potential lower than the first potential, the second signal has a potential magnitude that turns off the seventh transistor, the third signal has a potential magnitude that turns on the eighth and tenth transistors, and the fourth signal has a potential magnitude that turns on the eleventh transistor and the twelfth transistor. The level shift circuit according to claim 9.

11. The system further comprises a thirteenth transistor connected between the fifth node and the fourth output node. The level shift circuit according to claim 10.

12. The 13th transistor has a gate that receives the 4th signal, While the third node has the second potential and the first node has the first potential, the fourth signal has a potential magnitude that turns on the thirteenth transistor. The level shift circuit according to claim 11.

13. The breakdown voltage of each of the transistors included in the first inverter, the transistors included in the second inverter, the fifth transistor, and the sixth transistor is lower than the breakdown voltage of each of the first transistor, the second transistor, the third transistor, and the fourth transistor. A level shift circuit according to any one of claims 1 to 12.

14. The first inverter is A 14th transistor having a gate connected between the first node and the first output node and connected to the first input node, A 15th transistor having a gate connected between the first output node and the second node and connected to the first input node, Includes, The second inverter is, A 16th transistor having a gate connected between the first node and the second output node and connected to the second input node, A 17th transistor having a gate connected between the second output node and the second node and connected to the second input node, Includes, The breakdown voltage of each of the fifth transistor, the sixth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, and the seventeenth transistor is lower than the breakdown voltage of each of the first transistor, the second transistor, the third transistor, and the fourth transistor. A level shift circuit according to any one of claims 1 to 12.

15. A fifth inverter having an input node connected between the first node and the second node that receives a fifth signal, and an output node connected to the second input node, A sixth inverter having an input node connected between the first node and the second node, which receives a sixth signal complementary to the fifth signal, and an output node connected to the first input node, Furthermore, A level shift circuit according to any one of claims 1 to 12.

16. The breakdown voltage of each of the transistors included in the first inverter, the second inverter, the fifth inverter, the sixth inverter, the fifth transistor, and the sixth transistor is lower than the breakdown voltage of each of the first transistor, the second transistor, the third transistor, and the fourth transistor. The level shift circuit according to claim 15.

17. The first inverter is A 14th transistor having a gate connected between the first node and the first output node and connected to the first input node, A 15th transistor having a gate connected between the first output node and the second node and connected to the first input node, Includes, The second inverter is, A 16th transistor having a gate connected between the first node and the second output node and connected to the second input node, A 17th transistor having a gate connected between the second output node and the second node and connected to the second input node, Includes, The fifth inverter is, A 18th transistor is connected between the first node and the second input node and has a gate that receives the fifth signal, A 19th transistor is connected between the second input node and the second node and has a gate that receives the fifth signal, Includes, The sixth inverter is, A 20th transistor is connected between the first node and the first input node and has a gate that receives the sixth signal, A 21st transistor connected between the first input node and the second node, having a gate that receives the sixth signal, Includes, The breakdown voltage of each of the fifth transistor, sixth transistor, fourteenth transistor, fifteenth transistor, sixteenth transistor, seventeenth transistor, eighteenth transistor, nineteenth transistor, twenty-tenth transistor, and twenty-first transistor is lower than the breakdown voltage of each of the first transistor, second transistor, third transistor, and fourth transistor. The level shift circuit according to claim 16.

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