Magnetic disk drive

Abstract

To provide a magnetic disk drive with high recording quality. [Solution] When writing data to the first track, the processing circuit of the magnetic disk device modulates the radial recording width of the first data sequence according to a first combination and a second combination. The first track is a track adjacent to the second track, which is a track on which data has already been written. The first combination is a combination of the first data sequence, which is the data to be written to the first track, and the second data sequence, which is the data already written to the second track. The second combination is a combination of the polarity of the bit positions of the first track and the bit positions of the second track, which are radially adjacent to each other.

Description

[Technical Field]

[0001] This embodiment relates to a magnetic disk drive. [Background technology]

[0002] In recent years, the SMR (Shingled Magnetic Recording) method has become the mainstream writing method for magnetic disk drives. The SMR method has a narrower track width compared to the CMR (Conventional Magnetic Recording) method. Therefore, in the SMR method, the impact on the recording quality of data in tracks adjacent to the track being written to is greater than in the CMR method. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent No. 9754610 [Patent Document 2] U.S. Patent No. 9715887 [Overview of the project] [Problems that the invention aims to solve]

[0004] One embodiment aims to provide a magnetic disk device with high recording quality. [Means for solving the problem]

[0005] According to one embodiment, the system comprises a magnetic disk, a magnetic head, and a processing circuit. The magnetic disk is provided with multiple tracks. The magnetic head writes or reads data from the magnetic disk. When the processing circuit writes data to the first track among the multiple tracks using the magnetic head, it modulates the radial recording width of the first data sequence according to a first combination and a second combination. The first track is a track adjacent to the second track, which is a track on which data has already been written. The first combination is a combination of the first data sequence, which is the data to be written to the first track, and the second data sequence, which is the data already written to the second track. The second combination is a combination of the polarity of the bit positions of the first track and the bit positions of the second track, which are radially adjacent to each other. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 shows an example of the configuration of a magnetic disk device according to the first embodiment. [Figure 2] Figure 2 is a schematic diagram showing an example of the configuration of a magnetic disk according to the first embodiment. [Figure 3] Figure 3 is a schematic diagram illustrating the SMR method used in the magnetic disk device according to the first embodiment. [Figure 4] Figure 4 shows an example of a detailed configuration of the RWC and preamplifier according to the embodiment. [Figure 5] Figure 5 shows an example of a detailed configuration of a control signal generation circuit according to the embodiment. [Figure 6] Figure 6 shows an example of modulation that increases the amplitude of the recording current in a magnetic disk device according to the embodiment. [Figure 7] Figure 7 shows an example of modulation that reduces the amplitude of the recording current in a magnetic disk device according to an embodiment. [Figure 8]FIG. 8 is a diagram for explaining an example in which both modulation for increasing the amplitude of a recording current and modulation for decreasing the amplitude of the recording current are performed in the magnetic disk device according to the embodiment. [Figure 9] FIG. 9 is a flowchart showing an example of an operation related to modulation for increasing the amplitude of a recording current by the control signal generation circuit according to the embodiment. [Figure 10] FIG. 10 is a flowchart showing an example of an operation related to modulation for decreasing the amplitude of a recording current by the control signal generation circuit according to the embodiment. [Figure 11] FIG. 11 is a diagram showing a detailed configuration of the processing circuit according to Modification 1. [Figure 12] FIG. 12 is a diagram showing an example of a waveform of a boost / shrink control signal according to Modification 1. [Figure 13] FIG. 13 is a diagram for explaining an example in which two bit positions adjacent to each other in the radial direction are shifted in the circumferential direction according to Modification 2. [Figure 14] FIG. 14 is another diagram for explaining an example in which two bit positions adjacent to each other in the radial direction are shifted in the circumferential direction according to Modification 2. [Figure 15] FIG. 15 is yet another diagram for explaining an example in which two bit positions adjacent to each other in the radial direction are shifted in the circumferential direction according to Modification 2. [Figure 16] FIG. 16 is a flowchart showing an example of control according to the amount of positional shift according to Modification 2. [Figure 17] FIG. 17 is a flowchart showing another example of control according to the amount of positional shift according to Modification 2. [Figure 18] FIG. 18 is a flowchart showing yet another example of control according to the amount of positional shift according to Modification 2. MODE FOR CARRYING OUT THE INVENTION

[0007] Referring to the accompanying drawings below, the magnetic disk device according to the embodiment will be described in detail. Note that the present invention is not limited by this embodiment.

[0008] (Embodiment) FIG. 1 is a diagram showing an example of the configuration of a magnetic disk device 1 according to the first embodiment.

[0009] The magnetic disk device 1 is connected to a host 2. The magnetic disk device 1 can receive an access command such as a write command or a read command from the host 2.

[0010] The magnetic disk device 1 includes a magnetic disk 11 having a magnetic layer formed on its surface. The magnetic disk device 1 accesses the magnetic disk 11 in response to an access command. The access includes data writing and data reading. Note that the magnetic disk device 1 may have a plurality of magnetic disks 11, but in the first embodiment, for simplicity of explanation and illustration, the magnetic disk device 1 is assumed to include one magnetic disk 11.

[0011] Data writing and reading are performed by a magnetic head 22. Specifically, in addition to the magnetic disk 11, the magnetic disk device 1 includes a spindle motor (SPM) 12, a lamp 13, an actuator arm 15, a voice coil motor (VCM) 16, a servo controller (SVC) 21, a magnetic head 22, a hard disk controller (HDC) 23, a preamplifier 24, a read / write channel (RWC) 25, a processor 26, a FROM (Flash Read Only Memory) 28, and a DRAM (Dynamic Random Access Memory) 29.

[0012] The magnetic disk 11 is rotated at a predetermined rotational speed by the coaxially mounted SPM 12.

[0013] SVC21 is an integrated circuit that functions as a driver for SPM12 and VCM16. The processor 26 controls the rotation of SPM12 and VCM16 via SVC21.

[0014] The magnetic head 22 includes a write element 22w and a read element 22r. The magnetic head 22 writes data to the magnetic disk 11 using the write element 22w. The magnetic head 22 reads data from the magnetic disk 11 using the read element 22r. The magnetic head 22 is mounted on the tip of the actuator arm 15. The magnetic head 22 is moved radially across the magnetic disk 11 by a VCM 16 driven by an SVC 21. Note that either one or both of the write element 22w and the read element 22r on the magnetic head 22 may be provided in multiple quantities on a single magnetic head 22.

[0015] When the rotation of the magnetic disk 11 is stopped, the magnetic head 22 is moved onto the ramp 13. The ramp 13 holds the magnetic head 22 in a position away from the magnetic disk 11.

[0016] The preamplifier 24 is an integrated circuit that performs data writing and reading via the magnetic head 22. During a read operation, the preamplifier 24 amplifies the signal read by the magnetic head 22 from the magnetic disk 11 and outputs it, supplying it to the RWC 25. During a write operation, the preamplifier 24 amplifies the signal corresponding to the data to be written supplied from the RWC 25 and supplies it to the magnetic head 22.

[0017] DRAM29 is used as a buffer for data transferred to and from host 2. For example, DRAM29 is used to temporarily store data to be written or data read from magnetic disk 11.

[0018] Furthermore, DRAM 29 is used by the processor 26 as operating memory. DRAM 29 is used as an area where the firmware program is loaded and an area where various management data is temporarily stored.

[0019] HDC23 controls the transfer of data between it and host 2 via the I / F bus. HDC23 supplies the data to be written, received from host 2, to RWC25 via DRAM29. HDC23 receives the read data output from RWC25 via DRAM29 and transmits that read data to host 2.

[0020] The RWC25 modulates the data to be written, supplied from the HDC23, and provides it to the preamplifier 24. The RWC25 also performs demodulation, including error correction, on the signal read from the magnetic disk 11 and supplied from the preamplifier 24, and then outputs the signal as digital data to the HDC23.

[0021] The processor 26 is, for example, a CPU (Central Processing Unit). FROM 28 and DRAM 29 are connected to the processor 26.

[0022] FROM28 stores the firmware program and various configuration information. The firmware program may also be stored on the magnetic disk 11.

[0023] The processor 26 controls the magnetic disk device 1 according to a firmware program stored in FROM 28 or the magnetic disk 11. For example, the processor 26 loads the firmware program from FROM 28 or the magnetic disk 11 into DRAM 29 and controls the SVC 21, preamplifier 24, RWC 25, HDC 23, etc., according to the firmware program loaded into DRAM 29.

[0024] Furthermore, some or all of the functions of the processor 26 may be implemented by hardware circuits such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application Specific Integrated Circuits).

[0025] The HDC23, RWC25, and processor 26 are configured as a System-On-a-Chip (SoC) 30. The SoC 30 is an example of a controller. In addition to these, the SoC 30 may also include other elements (e.g., FROM 28 or DRAM 29).

[0026] Figure 2 is a schematic diagram showing an example of the configuration of a magnetic disk 11 according to the first embodiment. This figure shows an example of the rotation direction of the magnetic disk 11. The magnetic head 22 moves relative to the magnetic disk 11 as the magnetic disk 11 rotates. Therefore, the write / read direction, i.e., the direction in which data is written or read by the magnetic head 22 along the circumferential direction, is opposite to the rotation direction of the magnetic disk 11.

[0027] During the manufacturing process, servo information is written to the magnetic disk 11, for example, by a servo writer or by self-servo writing (SSW). As shown in Figure 2, a radial arrangement of servo regions 42 is shown as an example of the arrangement of servo regions to which servo information has been written. Between the servo regions 42, data regions 43 to which data can be written are provided.

[0028] Multiple concentric tracks 41 are set in the radial direction of the magnetic disk 11.

[0029] The servo information includes a servo mark, Gray code, burst pattern, and postcode. When the SoC30 writes data to or reads data from a sector, it generates a Positional Error Signal (PES) based on the servo information read by the magnetic head 22 from the servo area 42. The PES indicates the amount of radial deviation from the track center of the target track. Based on the PES acquired each time the magnetic head 22 passes through the servo area 42, the SoC30 performs positioning of the magnetic head 22, i.e., seek control and tracking control. For example, before the start of a write operation, the SoC30 performs seek control to move the magnetic head 22 to the track 41 to be written to. Then, it performs tracking control to keep the magnetic head 22 on the track 41 to be written to from just before the start of the write operation until the end of the write operation.

[0030] Multiple data areas 43 are arranged along track 41, with multiple sectors on which data is written.

[0031] Furthermore, the servo information may define multiple servo tracks that are different from the multiple tracks 41. In such cases, the correspondence between the multiple tracks 41 and the multiple servo tracks is generated during manufacturing or otherwise and stored in a predetermined non-volatile memory area (e.g., FROM 28 or magnetic disk 11). The SoC 30 then performs positioning control (seek control and tracking control) of the magnetic head 22 based on the servo information read by the magnetic head 22 and the said correspondence.

[0032] Two methods are known for writing data to a magnetic disk: the SMR method and the CMR method. In the first embodiment, the SoC 30 is configured to write data requested by the host 2 to the magnetic disk 11 using the SMR method.

[0033] Figure 3 is a schematic diagram illustrating the SMR method used in the magnetic disk device 1 according to the first embodiment. In the SMR method, when writing data to a track 41 (referred to as the first data) and then writing data to a track 41 radially adjacent to that track 41 (referred to as the second data), each track 41 is arranged such that a portion of the second data overlaps with a portion of the first data. In other words, according to the SMR method, data from one of two radially adjacent tracks 41 of the magnetic disk 11 is written over a portion of the data from the other track 41.

[0034] For example, the data on track #2 is written so as to overlap with a portion of the data on track #1 that has already been written. Similarly, the data on track #3 is written so as to overlap with a portion of the data on track #2 that has already been written. In other words, with the SMR method, the data on one track 41 repeatedly overlaps with a portion of the data on an adjacent track that has already been written. This narrows the width of each track TW to less than the width of the write element 22w (WHw), improving the recording density.

[0035] In the SMR method, because the track width TW is narrower than the width WHw of the 22w light element, updating a portion of the 41 minutes of data across multiple tracks will corrupt the data in tracks adjacent to the updated data. To prevent data corruption, the data for multiple tracks, including the portion of data in question, is updated simultaneously. The area of ​​multiple tracks that is updated simultaneously is called the band area.

[0036] Furthermore, according to the SMR method, for multiple tracks 41 within a single band region, writing can only be performed from one predetermined end (outer side) to the other predetermined end (inner side) of the magnetic disk. In the example shown in Figure 3, writing is performed in units of track 41 from the outer side to the inner side. The SoC 30 may be configured so that writing is performed in units of track 41 from the inner side to the outer side. Alternatively, the writing order may be set individually for each band region.

[0037] In the following explanation, each track 41 included in the band region is assigned a track number corresponding to its arrangement order in the radial direction, and in the SMR method, writing is performed in units of track 41 in the order of the track numbers.

[0038] The CMR method is a method in which data from two tracks 41 adjacent to each other in the radial direction of the magnetic disk 11 is written so that they do not overlap. With the CMR method, the width of each track 41 is greater than or equal to the width (WHw) of the write element 22w, so data at any position can be updated.

[0039] When data is written to one track 50 (referred to as the write target track), the magnetic field of the magnetic head 22 may interfere with data already written to adjacent tracks 50 (referred to as the adjacent track). This magnetic field interference can degrade the recording quality of the data on the adjacent track. This type of interference caused by a write operation to data on an adjacent track is known as ATI (Automatic Interference).

[0040] In the SMR method, the influence of ATI is greater than in the CMR method. Therefore, in the SMR method, it is desirable to control the recording current, that is, the current supplied to the 22W writing element, when writing, taking into account the recording quality of data not only on the track being written but also on adjacent tracks.

[0041] According to the embodiment, in order to balance and improve both the recording quality of the data on the track to be written and the recording quality of the data on adjacent tracks, the magnetic disk drive 1 operates as follows: The magnetic disk drive 1 modulates the recording current based on the combination of the data sequence to be written to the track to be written and the data sequence already written to the adjacent track, and the combination of the polarity of the bit positions of the radially adjacent track to be written and the bit positions of the adjacent track. Modulating the recording current means increasing the amplitude of the recording current beyond its intrinsic value or decreasing the amplitude of the recording current from its intrinsic value. The intrinsic value is the value of the amplitude of the recording current determined solely based on the data on the track to be written.

[0042] To enable modulation based on these combinations, the magnetic disk device 1 has the following configuration.

[0043] Figure 4 shows a detailed example of the configuration of the RWC25 and preamplifier 24 according to the embodiment. Note that the RWC25 and preamplifier 24 are examples of processing circuits.

[0044] The RWC25 includes a media write data generation circuit 251, a control signal generation circuit 252, a first driver 253, a second driver 254, and a third driver 255. The preamplifier 24 includes a modulation circuit 241, a fourth driver 242, a fifth driver 243, and a sixth driver 244.

[0045] The media write data generation circuit 251 generates data to be written to the magnetic disk 11 by performing various modulations, including error correction coding, on the data to be written supplied from the HDC 23. Hereafter, "write data" will refer to the data generated by the media write data generation circuit 251 that is written to the magnetic disk 11.

[0046] The light data generated by the media light data generation circuit 251 is transferred to the preamplifier 24 via the first driver 253 as a binary differential signal. This light data signal transferred to the preamplifier 24 is referred to as the light data signal.

[0047] To enable the current track's write data to be later referenced as the write data of an adjacent track, the current track's write data is stored in a predetermined memory area. In the example shown in Figure 4, the write data of the current track generated by the media write data generation circuit 251 is transferred to the DRAM 29 and stored in the DRAM 29 for 41 minutes per track.

[0048] In the explanations from Figure 4 onward, track #n represents the track to be written to, and track #(n-1) represents the adjacent track.

[0049] The media write data generation circuit 251 transfers the write data for track #n not only to the first driver 253 and DRAM 29 but also to the control signal generation circuit 252.

[0050] The control signal generation circuit 252 receives the write data for track #n from the media write data generation circuit 251 and acquires the write data for track #(n-1) from the DRAM 29. The control signal generation circuit 252 determines whether the combination of data sequences between the write data for track #n and the write data for track #(n-1) corresponds to a specific combination, and whether the combination of polarities of the bit positions on each track 41 corresponds to a specific combination. Based on the results of these determinations, the control signal generation circuit 252 generates a boost control signal and a shrink control signal. The boost control signal is a signal that instructs whether or not to increase the amplitude of the recording current. The shrink control signal is a signal that instructs whether or not to decrease the amplitude of the recording current.

[0051] In the example shown in Figure 4, both the boost control signal and the shrink control signal are transmitted as binary differential signals. The boost control signal is transmitted to the preamplifier 24 via the second driver 254. The shrink control signal is transmitted to the preamplifier 24 via the third driver 255.

[0052] In the preamplifier 24, the fifth driver 243 receives a boost control signal, and the sixth driver 244 receives a shrink control signal.

[0053] The boost control signal received by the fifth driver 243 and the shrink control signal received by the sixth driver 244 are transferred to the modulation circuit 241. The modulation circuit 241 controls the fourth driver 242 based on the boost control signal and the shrink control signal.

[0054] The fourth driver 242 receives the write data signal transferred from the RWC 25. Based on the write data signal, the fourth driver 242 generates the waveform of the recording current supplied to the light element 22w. At this time, the fourth driver 242 modulates the recording current under the control of the modulation circuit 241.

[0055] Figure 5 shows an example of a detailed configuration of the control signal generation circuit 252 according to the embodiment.

[0056] The control signal generation circuit 252 includes a first data processing circuit 101, a first pre-compensation circuit 102, a second data processing circuit 103, a second pre-compensation circuit 104, a polarity comparison circuit 105, and an AND circuit 106.

[0057] Furthermore, the control signal generation circuit 252 is equipped with a polarity comparison circuit 105 and an AND circuit 106 for each of the boost and shrink control signals, respectively, in order to generate the boost control signal and the shrink control signal. To avoid complicating the diagram, this explanation assumes that the control signal generation circuit 252 is equipped with one polarity comparison circuit 105 and one AND circuit 106.

[0058] The first data processing circuit 101 receives the write data for track #n. The second data processing circuit 103 receives the write data for track #(n-1). The write data is input to the first data processing circuit 101 and the second data processing circuit 103 one bit at a time in synchronous order from the beginning of each write data. The input of the write data for track #n to the first data processing circuit 101 and the input of the write data for track #(n-1) to the second data processing circuit 103 are synchronized so that when a bit from a pair of bits adjacent in the radial direction that corresponds to a write position in the write data for track #n is input to the first data processing circuit 101, the bit from the same pair that corresponds to a write data for track #(n-1) is input to the second data processing circuit 103.

[0059] The first data processing circuit 101 transfers the write data for track #n one bit at a time to the polarity comparison circuit 105. The second data processing circuit 103 transfers the write data for track #(n-1) one bit at a time to the polarity comparison circuit 105.

[0060] The polarity comparison circuit 105 compares the polarity of the light position between the light data of track #n and the light data of track #(n-1), and outputs the result of the comparison as a binary signal. For each pair of bits where the light position is radially adjacent, the polarity comparison circuit 105 compares the polarity of the light position of one bit of track #n with the polarity of the light position of one bit of track #(n-1).

[0061] The write data is written to the magnetic disk 11 as a binary signal. On the magnetic disk 11, an area on the recording surface of the magnetic disk 11 corresponding to one bit (an example of a bit position) is magnetized to a polarity corresponding to the level of the binary signal, either positive or negative, and one bit of data is recorded in that area. In other words, the level of the binary signal of the write data corresponds to the polarity of the magnetization of the magnetic disk 11. The polarity comparison circuit 105 performs a logical operation using the value of the write data of track #n and the value of the write data of track #(n-1) to determine whether pairs of polarities of radially adjacent bit positions are pairs of the same polarity or pairs of different polarities.

[0062] The bit included in the light data of track #n of a pair of bits whose light positions are radially adjacent is denoted as the target bit, and the bit included in the light data of track #(n-1) of the same pair of bits is denoted as the adjacent bit. A pair of bits whose light positions are radially adjacent is simply referred to as a bit pair.

[0063] The correspondence between the level and value of a binary signal can be arbitrarily determined by the designer. Hereafter, when discussing binary signals, the "H" level of a binary signal will correspond to the value "1", and the "L" level of a binary signal will correspond to the value "0".

[0064] The method of outputting the determination result by the polarity comparison circuit 105 differs depending on the control signal being generated.

[0065] The polarity comparison circuit 105 for generating the boost control signal outputs an "H" level signal when the polarity pairs of the bit positions to be written are the same polarity, and outputs an "L" level signal when the polarity pairs of the bit positions are different polarity. In other words, the polarity comparison circuit 105 performs a negative exclusive OR (XNOR) logical operation on the bit pairs.

[0066] The polarity comparison circuit 105 for generating the shrink control signal outputs a "L" level signal when the polarity pairs of the bit positions to be written are the same polarity, and outputs a "H" level signal when the polarity pairs of the bit positions are different polarity. In other words, the polarity comparison circuit 105 performs an exclusive OR (XOR) logical operation on the bit pairs.

[0067] The first data processing circuit 101 sequentially performs NRZI (Non Return to Zero Inversion) encoding on the write data for track #n. The write data for track #n, which has been NRZI encoded by the first data processing circuit 101, is sequentially input to the first pre-compensation circuit 102.

[0068] The second data processing circuit 103 sequentially performs NRZI encoding on the write data for track #(n-1). The write data for track #(n-1) that has been NRZI encoded by the second data processing circuit 103 is sequentially input to the second pre-compensation circuit 104.

[0069] In NRZI coding, "0" indicates that the value of the write data (in other words, the polarity of magnetization) is maintained without inversion, while "1" indicates that the value of the write data (in other words, the polarity of magnetization) is inverted. NRZI-coded write data is referred to as an NRZI label.

[0070] The first pre-compensation circuit 102 compares the NRZI label of track #n with a pre-set fixed-length pattern PP(n) each time a character of the NRZI label for track #n is input. The first pre-compensation circuit 102 outputs the comparison result as a binary signal. The section of the NRZI label of track #(n-1) that is compared with pattern PP(n) (hereinafter referred to as the comparison section) is a fixed-length range that includes the position of the bit being written by the polarity comparison circuit 105. If the NRZI label in the comparison section matches pattern PP(n), the first pre-compensation circuit 102 sets the output signal to the "H" level. If the NRZI label in the comparison section does not match pattern PP(n), the first pre-compensation circuit 102 sets the output signal to the "L" level.

[0071] The second pre-compensation circuit 104 compares the NRZI label of track #(n-1) with a preset fixed-length pattern PP(n-1) each time an NRZI label of track #(n-1) is input. The second pre-compensation circuit 104 outputs the comparison result as a binary signal. For the NRZI label of track #(n-1), as with the first pre-compensation circuit 102, the comparison interval is a fixed-length section that includes the position of the adjacent bit being processed by the polarity comparison circuit 105. If the NRZI label in the comparison interval matches the pattern PP(n-1), the second pre-compensation circuit 104 sets the output signal to the "H" level. If the NRZI label in the comparison interval does not match the pattern PP(n-1), the second pre-compensation circuit 104 sets the output signal to the "L" level.

[0072] The first pre-compensation circuit 102 and the second pre-compensation circuit 104 each have registers. The register of the first pre-compensation circuit 102 is set to pattern PP(n), and the register of the second pre-compensation circuit 104 is set to pattern PP(n-1). The first pre-compensation circuit 102 compares the NRZI label in the comparison interval of track #n with the pattern PP(n) set in the register. The second pre-compensation circuit 104 compares the NRZI label in the comparison interval of track #(n-1) with the pattern PP(n-1) set in the register. The timing of setting the pattern PP in each register is arbitrary. Furthermore, the components that set the pattern PP in each register are not limited to specific components. For example, the processor 26 may set each pattern PP in the register for each track 41 to be written to. The choice of which pattern to use as the pattern PP is arbitrary. The designer can determine the pattern PP to set in each register in the manufacturing process so that the recording quality of the data on the track to be written and adjacent tracks is high. The processor 26 sets the pattern PP determined by the designer. The processor 26 may be configured to change the pattern PP set in each register according to the radial position of the magnetic disk 11, the magnetic head 22, the set recording density, etc. An example of each pattern PP is described below.

[0073] The AND gate 106 performs a logical AND operation on the output signals from the first pre-compensation circuit 102, the second pre-compensation circuit 104, and the polarity comparison circuit 105. The AND gate 106 outputs the result of the logical operation as a binary signal. The output signal from the AND gate 106 is either a boost control signal or a shrink control signal.

[0074] Next, we will describe an example of modulation of the recording current by the RWC25 and preamplifier 24 configured as described above.

[0075] Figure 6 shows an example of modulation that increases the amplitude of the recording current in the magnetic disk device 1 according to the embodiment.

[0076] In Figure 6, the α sequence represents the data sequence of the write data for track #n. The β sequence represents the data sequence of the write data for track #(n-1). When x is a non-negative natural number, the x-th bit from the beginning of the write data for track #n is denoted as α(x), and the x-th bit from the beginning of the write data for track #(n-1) is denoted as β(x).

[0077] Each of these write data points represents one sector's worth of data. The sector to which the write data for track #n is written and the sector to which the write data for track #(n-1) is written are adjacent to each other in the radial direction. Therefore, the position where α(x) is written and the position where β(x) is written are adjacent in the radial direction.

[0078] x indicates the position of a bit in the written data. x can also be thought of as corresponding to the order or time in which data is written to the magnetic disk 11.

[0079] In the α and β sequences, bits with dot hatching have a value of "1," and bits with diagonal hatching have a value of "0." As mentioned above, the magnetic disk 11 is magnetized with a polarity corresponding to the data value, from among positive and negative polarity. In one example, the value "1" corresponds to positive polarity, and the value "0" corresponds to negative polarity. However, the correspondence between value and polarity is not limited to this.

[0080] Figure 6 shows the magnetization state when the β series is lit on track #(n-1), and then the α series is lit on track #n. Dot hatching indicates positive polarity magnetization, and diagonal hatching indicates negative polarity magnetization.

[0081] The data sequence from α(i-5) to α(i+5) is "11000101001". Therefore, the NRZI label generated from this data sequence by the first data processing circuit 101 is "0100111101".

[0082] The data sequence from β(i-5) to β(i+5) is "01110100111". Therefore, the NRZI label generated from this data sequence by the second data processing circuit 103 is "1001110100".

[0083] In this specification, data series and NRZI labels are presented in chronological order.

[0084] Furthermore, in the example shown in Figure 6, the pair α(i) and β(i) is the bit pair being processed by the polarity comparison circuit 105, and the interval of the NRZI label generated from the data sequence ranging from 3 bits before this bit pair to 2 bits after this bit pair (intervals SC1 and SC2 in Figure 6) is set as the comparison interval.

[0085] As mentioned above, patterns PP(n) and PP(n-1) can be arbitrarily set according to the design. Here, we assume that patterns indicating that the bit to be written and the adjacent bits are 1T data are set as patterns PP(n) and PP(n-1). Note that "T" indicates the length of the bit that is maintained without polarity reversal. In other words, for the bit to be written to be 1T data, the polarity is reversed immediately before the bit to be written and immediately after the bit to be written in the data sequence. Therefore, "**11*" is set as pattern PP(n). Similarly, for the adjacent bits to be 1T data, the polarity is reversed immediately before the adjacent bits and immediately after the adjacent bits. Therefore, "**11*" is set as pattern PP(n-1). Note that in the notation of pattern PP, "*" indicates a single-character wildcard. In other words, the "*" part can be either "1" or "0".

[0086] The light from α(i) magnetizes the bit position of α(i) to positive polarity. The polarity of the bit position to which β(i) is lit is positive. In other words, the pairs of polarities of the bit positions to which α(i) and β(i) are lit are pairs of the same polarity. Therefore, the polarity comparison circuit 105 outputs "1" as the result of the negated exclusive OR logical operation.

[0087] The NRZI label for comparison interval SC1 applied to the write data of track #n is "01110". This NRZI label for comparison interval SC1 matches the pattern PP(n), which is "**11*". Therefore, the first pre-compensation circuit 102 outputs "1" as the comparison result.

[0088] The NRZI label of comparison interval SC2 for the write data of track #(n-1) is "00111". This NRZI label of comparison interval SC2 matches the pattern PP(n-1), which is "**11*". Therefore, the second pre-compensation circuit 104 outputs "1" as the comparison result.

[0089] With respect to α(i), the AND gate 106 receives a "1" input from all three circuits: the polarity comparison circuit 105, the first pre-compensation circuit 102, and the second pre-compensation circuit 104. Therefore, the AND gate 106 outputs a "1" as its output signal (i.e., boost control signal).

[0090] Figure 6 shows the waveform of the write data signal for track #n, the waveform of the boost control signal transmitted in parallel with the write data signal for track #n, and the waveform of the recording current generated based on these signals.

[0091] The modulation circuit 241 controls the recording current amplitude to be higher than the normal value when the boost control signal is "H" at the edge timing of the write data signal. When the boost control signal is "L" at the edge timing of the write data signal, it does not control the recording current amplitude to be higher than the normal value. To enable this operation, the control signal generation circuit 252 transmits the boost control signal slightly earlier than the transmit timing of the write data signal.

[0092] In the example shown in Figure 6, the light data signal rises at the start of the α(i) light (timing t0). To ensure that the boost control signal is already at the "H" level at timing t0, the control signal generation circuit 252 transitions the boost control signal from the "L" level to the "H" level at timing t1, which is slightly earlier than timing t0.

[0093] Immediately after the data value inverts, the recording current is temporarily increased in amplitude to quickly stabilize the magnetic field of the light element 22w. In this recording current waveform, the portion where the amplitude of the recording current is temporarily increased immediately after the data value inverts is known as OSA (Overshoot Amplitude). From the end of OSA until the next data value inverts, the amplitude of the recording current is maintained at a constant value to maintain the magnetic field. This portion where the amplitude of the recording current is maintained at a constant value is called IW. In one embodiment, for example, the OSA portion is modulated based on a boost control signal.

[0094] According to the write data signal, the data values ​​are inverted at α(i-3), α(i), α(i+1), α(i+2), and α(i+5). Therefore, the amplitude is increased by the OSA when writing begins at α(i-3), α(i), α(i+1), α(i+2), and α(i+5). Of these OSAs, the amplitude of the OSA when writing data at α(i), where the boost control signal instructs an increase in the amplitude of the recording current, is larger than the amplitude of the other OSAs.

[0095] When modulation is applied that increases the amplitude of the recording current, the effect of ATI on adjacent tracks at the location where the modulation is applied to the track being written becomes greater. However, modulation that increases the amplitude of the recording current is performed on the premise that pairs of polarities of radially adjacent bit positions are the same. Therefore, the enhanced effect of ATI during the writing of the target bit reinforces the recording quality of adjacent bits. In other words, the recording quality of bits written to adjacent tracks is improved.

[0096] Furthermore, at the location where the modulation occurs on the track being written, the amplitude of the recording current is increased compared to the normal value, thus improving the recording quality of the bits written to the track being written.

[0097] In other words, it is possible to improve the recording quality of data on the target track and adjacent tracks in a balanced manner.

[0098] Figure 7 shows an example of modulation that reduces the amplitude of the recording current in the magnetic disk device 1 according to the embodiment.

[0099] The example shown in Figure 7 differs from the example shown in Figure 6 in that the value of each bit in the sequence of write data for track #(n-1) is inverted. Therefore, as in the example shown in Figure 6, when α(i) is written, the first pre-compensation circuit 102 outputs "1" as a comparison result, and the second pre-compensation circuit 104 outputs "1" as a comparison result.

[0100] The light from α(i) magnetizes the bit position α(i) to positive polarity. The polarity of the bit position β(i) is negative. In other words, the pairs of bit positions α(i) and β(i) that are lit have opposite polarities. Therefore, the polarity comparison circuit 105 outputs "1" as the result of the exclusive OR operation.

[0101] With respect to α(i), the AND gate 106 receives a "1" input from all three circuits: the polarity comparison circuit 105, the first pre-compensation circuit 102, and the second pre-compensation circuit 104. Therefore, the AND gate 106 outputs a "1" as its output signal (i.e., shrink control signal).

[0102] The modulation circuit 241 controls the recording current amplitude to be lower than the normal value when the shrink control signal is "H" at the edge timing of the write data signal. When the shrink control signal is "L" at the edge timing of the write data signal, it does not control the recording current amplitude to be lower than the normal value. To enable this operation, the control signal generation circuit 252 transmits the shrink control signal slightly earlier than the transmit timing of the write data signal.

[0103] In the example shown in Figure 7, the light data signal rises at the start of the α(i) light (timing t2). To ensure that the shrink control signal is already at the "H" level at timing t2, the control signal generation circuit 252 transitions the shrink control signal from the "L" level to the "H" level at timing t3, which is slightly earlier than timing t2.

[0104] The modulation circuit 241 reduces the amplitude of the recording current to a lower value than normal when the shrink control signal is "H" at timing t2. In this example, the modulation circuit 241 makes the amplitude of the OSA when writing data for α(i) smaller than the amplitude of other OSAs.

[0105] When modulation is applied that reduces the amplitude of the recording current, the influence of ATI on adjacent tracks at the point where the modulation is applied to the track being written to is reduced. Furthermore, modulation that reduces the amplitude of the recording current is performed on the premise that the bit pairs are of opposite polarity. Therefore, it is possible to prevent the values ​​of bits already written to adjacent tracks from being inverted due to the influence of ATI. In other words, it is possible to suppress the deterioration of the recording quality of bits written to adjacent tracks.

[0106] In a write operation to one track 41, both modulation that increases the amplitude of the recording current and modulation that decreases the amplitude of the recording current may be performed.

[0107] Figure 8 illustrates an example in the magnetic disk device 1 according to the embodiment in which both modulation that increases the amplitude of the recording current and modulation that decreases the amplitude of the recording current are performed. In the example shown in this figure, the boost control signal is transitioned to the "H" level at a timing t5 that is slightly earlier than the write timing t4 of α(i). As a result, the amplitude of the OSA portion is increased when α(i) is written. Also, the shrink control signal is transitioned to the "H" level at a timing t5 that is slightly earlier than the write timing t7 of α(i+3). As a result, the amplitude of the OSA portion is decreased when α(i+3) is written.

[0108] Figure 9 is a flowchart illustrating an example of the operation of the control signal generation circuit 252 according to the embodiment, which modulates the amplitude of the recording current. The series of operations shown in this figure are repeatedly performed for each bit of the write data of the track to be written. This figure shows the operation performed when a certain bit to be written is written.

[0109] In RWC25, the first pre-compensation circuit 102 determines whether the NRZI label of the target section SC1, generated from the sequence of write data of the track to be written, in other words track #n, matches the pattern PP(n) (S101).

[0110] The second pre-compensation circuit 104 determines whether the NRZI label for the target section SC2, generated from the sequence of write data of the adjacent track, in other words, track #(n-1), matches the pattern PP(n-1) (S102).

[0111] Furthermore, the polarity comparison circuit 105 determines whether the polarity pairs of the bit positions where the bit to be written and the adjacent bit are written are the same polarity pair (S103).

[0112] For convenience, we assume here that these three judgments are performed in the order of S101, S102, and S103, but in reality, these three judgments are performed simultaneously or almost simultaneously.

[0113] If the results of all the judgments in S101, S102, and S103 are positive, the AND gate 106 instructs the preamplifier 24 to perform modulation to increase the amplitude of the recording current (S104). Specifically, the boost control signal is transitioned from the "L" level to the "H" level. Then the operation ends.

[0114] If the result of any of the judgments in S101, S102, or S103 is negative, the instruction to modulate to increase the amplitude of the recording current is not given. Then the operation ends.

[0115] Figure 10 is a flowchart showing an example of the operation related to modulation that reduces the amplitude of the recording current by the control signal generation circuit 252 according to the embodiment. Note that the series of operations shown in this figure are repeatedly performed for each bit of the write data of the track to be written. This figure shows the operation performed when a certain bit to be written is written.

[0116] In RWC25, the first pre-compensation circuit 102 determines whether the NRZI label of the target section SC1, generated from the sequence of write data of the track to be written, in other words track #n, matches the pattern PP(n) (S201).

[0117] The second pre-compensation circuit 104 determines whether the NRZI label for the target section SC2, generated from the sequence of write data of the adjacent track, in other words track #(n-1), matches pattern PP(n-1) (S202).

[0118] Furthermore, the polarity comparison circuit 105 determines whether the polarity pairs of the bit positions where the bit to be written and the adjacent bit are written are pairs of opposite polarities (S203).

[0119] In Figure 10, for convenience, these three decisions are assumed to be performed in the order of S201, S202, and S203, but in reality, these three decisions are performed simultaneously or almost simultaneously.

[0120] If the results of all the judgments in S201, S202, and S203 are affirmative, the AND gate 106 instructs the preamplifier 24 to perform modulation to reduce the amplitude of the recording current (S204). Specifically, the shrink control signal is transitioned from the "L" level to the "H" level. Then the operation ends.

[0121] If the result of any of the S201, S202, or S203 checks is negative, the instruction to perform modulation to reduce the amplitude of the recording current is not issued. Then, the operation ends.

[0122] In the explanation above, the first pre-compensation circuit 102 and the second pre-compensation circuit 104 each compared the NRZI-encoded write data with the pattern PP to determine whether the combination of the sequence of write data of the track to be written and the sequence of write data of the adjacent track corresponds to a specific combination. The first pre-compensation circuit 102 and the second pre-compensation circuit 104 may also determine whether the combination of the sequence of write data of the track to be written and the sequence of write data of the adjacent track corresponds to a specific combination based not only on NRZI-encoded write data, but also on write data that is not NRZI-encoded or on write data that has been coded arbitrarily.

[0123] Furthermore, as an example of a specific combination, a combination in which both the bit to be written and the adjacent bit are 1T data was given. Generally, when 1T data is written to a magnetic disk, the recording quality of the data tends to be unstable because the circumferential width magnetized with the polarity corresponding to the data is narrow. As in the example above, when both the bit to be written and the adjacent bit are 1T data, the processing circuit modulates the recording current according to the polarity of the write position of the bit pair, thereby improving the recording quality of the 1T data for both the bit to be written and the adjacent bits.

[0124] Note that the specific combinations are not limited to the examples given above. The designer can test various combinations and, based on the test results, designate any combination as a specific combination.

[0125] Furthermore, as an example of recording current modulation, the amplitude of the OSA portion was changed. The method of recording current modulation is not limited to this. In addition to the OSA portion, or instead of the OSA portion, the amplitude of the IW portion may also be changed.

[0126] As described above, according to the embodiment, the processing circuit (i.e., RWC25 and preamplifier24) modulates the recording current supplied to the magnetic head22 in accordance with the sequence of write data of the track to be written, the combination of the bit positions of radially adjacent tracks to be written and the polarity of the bit positions of adjacent tracks.

[0127] Therefore, the recording quality of data not only on the track being written to, but also on adjacent tracks, can be improved. In other words, the recording quality is enhanced.

[0128] Furthermore, according to the embodiment, the processing circuit increases the amplitude of the recording current when writing a bit when the bit to be written is a combination of polarities between the bit position of the bit to be written and the bit position of an adjacent bit.

[0129] Therefore, it is possible to improve the recording quality of data on the target track and adjacent tracks in a balanced manner.

[0130] Furthermore, according to the embodiment, when the polarity combination of the bit position of the bit to be written and the bit position of the adjacent bit are different polarities, the processing circuit reduces the amplitude of the recording current when writing the bit to be written.

[0131] Therefore, it is possible to suppress the deterioration of the recording quality of bits written to adjacent tracks. In other words, the recording quality of adjacent tracks is improved.

[0132] Furthermore, according to this embodiment, pattern PP(n) is set in the first pre-compensation circuit 102 and pattern PP(n-1) is set in the second pre-compensation circuit 104. When the sequence of write data of the track to be written matches pattern PP(n) and the sequence of write data of the adjacent track matches pattern PP(n-1), the processing circuit modulates the recording current according to the polarity combination between the bit position of the bit to be written and the bit position of the adjacent bit.

[0133] Therefore, designers can optimize the combination of each light data sequence during modulation so that the recording quality of both the light data on the target track and the light data on adjacent tracks is as high as possible.

[0134] (Variation 1) In this embodiment, both the boost control signal and the shrink control signal are configured as binary signals. The configuration of each signal is not limited to these. Modification 1 describes an example in which the boost control signal and the shrink control signal are combined into a ternary control signal.

[0135] Figure 11 shows a detailed configuration of the processing circuit according to Modification Example 1.

[0136] The RWC25 includes a media write data generation circuit 251, a control signal generation circuit 252a, and a seventh driver 256. The preamplifier 24 includes a fourth driver 242, a modulation circuit 241, and an eighth driver 245.

[0137] Among the components of the processing circuit according to Modified Example 1, those components that are denoted by the same reference numerals as the components of the embodiment have the same functions as the components of the embodiment. Therefore, the description of components that are denoted by the same reference numerals as the components of the embodiment will be omitted.

[0138] The control signal generation circuit 252a receives the write data for track #n from the media write data generation circuit 251 and acquires the write data for track #(n-1) from the DRAM 29. The control signal generation circuit 252a determines whether the combination of data sequences between the write data for track #n and the write data for track #(n-1) corresponds to a specific combination, and whether the combination of polarities of the bit positions in each track 41 corresponds to a specific combination. Based on the results of these determinations, the control signal generation circuit 252a generates a boost / shrink control signal. The boost / shrink control signal is a ternary signal that integrates the boost control signal and the shrink control signal.

[0139] The boost / shrink control signal is transferred to the preamplifier 24 via the seventh driver 256.

[0140] In the preamplifier 24, the 8th driver 245 receives the boost / control signal.

[0141] The boost / shrink control signal received by the eighth driver 245 is transferred to the modulation circuit 241. The modulation circuit 241 controls the fourth driver 242 based on the boost / shrink control signal.

[0142] Figure 12 shows an example of the waveform of the boost / shrink control signal for Modification Example 1. According to this figure, the boost / shrink control signal has three levels. In the boost / shrink control signal, the "H" level indicates an instruction to increase the amplitude of the recording current. The "L" level indicates an instruction to decrease the amplitude of the recording current. As with the example shown in Figure 8, this boost / shrink control signal increases or decreases the amplitude of the OSA portion.

[0143] (Modification 2) In the embodiment, it was assumed that two radially adjacent bit positions where a bit pair is written are aligned radially. However, even if control is performed to align these two bit positions radially, a circumferential misalignment may occur between them for some reason. If the amount of such misalignment exceeds a predetermined value, the recording quality of the data on the adjacent track may actually deteriorate due to the control of the recording current modulation.

[0144] Therefore, in Modification 2, the magnetic disk drive 1 stops controlling the modulation of the recording current according to the amount of circumferential displacement between the two bit positions. This prevents the recording quality of data on adjacent tracks from deteriorating due to the control of the modulation of the recording current. Modification 2 is described below. Note that Modification 2 can be used in combination with Modification 1.

[0145] Figures 13 and 14 illustrate an example of Modification 2, in which two radially adjacent bit positions are shifted circumferentially.

[0146] According to Figures 13 and 14, the bit position where α(i) is written is shifted by a displacement ε in the circumferential direction relative to the bit position where β(i) is written.

[0147] In the example in Figure 13, the displacement ε is relatively small. However, in the example in Figure 14, the displacement ε is relatively large, and the displacement ε is close to half the radial width (denoted as unit bit width) over which β(i) is written.

[0148] As shown in the example in Figure 14, if the displacement ε is large, modulating the recording current to increase its amplitude when writing α(i) may adversely affect the magnetization of the bit position where β(i+1) is written.

[0149] Therefore, a predetermined threshold (th) is applied to the amount of displacement ε. ε A threshold (which is expressed as) is set, and the positional displacement amount ε is set to a threshold th ε If the value is greater, the control that modulates the recording current is reduced.

[0150] For example, in the case shown in Figure 13, the displacement amount ε is the threshold th ε Because it is smaller than the above, when α(i) is written, the preamplifier 24 is instructed by the boost control signal to increase the amplitude of the recording current. In response to this instruction, the OSA portion when α(i) is written is increased.

[0151] In the case shown in Figure 14, the displacement amount ε is the threshold th ε It is larger than that. Accordingly, when α(i) is written, the boost control signal is kept at "L". Therefore, when α(i) is written, the control that increases the amplitude of the recording current is refrained from.

[0152] Furthermore, if the positional shift amount ε is an integer multiple or greater than an integer multiple of the unit bit width, a bit pair rearrangement is performed. More specifically, a bit pair is formed by the bit to be written and the bit of the adjacent track that is written to the bit position where the circumferential shift amount relative to the bit position where the bit to be written is smallest.

[0153] For example, in the example shown in Figure 15, the bit position where α(i) is written is separated from the bit position where β(i) is written by more than one bit width. However, the circumferential displacement relative to the bit position where β(i) is written is minimized at the bit position where α(i+2) is written. Therefore, a bit pair is formed by α(i+2) and β(i), and a determination is made as to whether or not to control the modulation of the recording current based on the positional displacement ε for this bit pair. Furthermore, the processing circuit compares the data sequences and the polarity of this bit pair.

[0154] Figure 16 is a flowchart showing an example of control according to the positional displacement amount ε in Modification 2. The series of operations shown in this figure are executed by a predetermined component (e.g., processor 26) within the SoC 30. Here, the SoC 30 is described as the main component of the series of operations. Furthermore, this figure shows the operation when writing to a target track from the first sector to the last sector.

[0155] First, the SoC30 initializes m, an index for counting sectors, to 0 (S301). Then, it turns on the control signal generation function (i.e., the boost control signal and shrink control signal according to the embodiment, or the boost / shrink control signal according to Modification 1) (S302). As a result, the RWC25 generates the control signals, enabling modulation of the recording current.

[0156] Next, the SoC30 performs a write operation on sector #m (S303). During the write operation on sector #m, the SoC30 monitors the misalignment amount ε (S304). The SoC30 may detect the misalignment amount ε each time a single bit is written to sector #m, or it may detect the misalignment amount ε each time data larger than one bit is written to sector #m. Furthermore, the method for detecting the misalignment amount ε is not limited to any particular method. For example, the SoC30 may be configured to detect the misalignment amount ε based on servo information.

[0157] During the monitoring of the misalignment amount ε, the SoC 30 determines whether the misalignment amount ε is greater than the threshold th ε (S305). If the misalignment amount ε becomes greater than the threshold th ε at any timing during the writing of sector #m (S305: Yes), the SoC 30 turns off the control signal generation function at the timing when the misalignment amount ε becomes greater than the threshold th ε (S306). As a result, the RWC 25 stops generating the control signal, and the modulation of the recording current is no longer performed.

[0158] If the misalignment amount ε is not greater than the threshold th ε (S305: No), the SoC 30 skips the process of S306.

[0159] When the writing of sector #m is completed, the SoC 30 determines whether the value of m is equal to the maximum value m max (S307). Note that m max corresponds to the number of sectors provided on the write target track, and sector #m max indicates the last sector of the write target track.

[0160] If the value of m is not equal to the maximum value m max (S307: No), the SoC 30 increments the value of m by 1 (S308), and the control transitions to S302.

[0161] Note that in S302, the control signal generation function is turned on. If the writing of the previous sector is completed without the control signal generation function being turned off, the SoC 30 skips the process of S302 and maintains the control signal generation function in the on state.

[0162] Thus, according to the second modification, the SoC 30 stops controlling the modulation of the recording current as the circumferential misalignment amount ε between two bit positions adjacent to each other in the radial direction becomes greater than the threshold th ε .

[0163] Therefore, it becomes possible to prevent deterioration of the recording quality of data on adjacent tracks due to modulation of the recording current when the positional displacement ε is greater than a predetermined value.

[0164] The amount of positional displacement ε is the threshold th ε When the value exceeds a certain level, the operation is not limited to stopping the modulation of the recording current.

[0165] Figure 17 is a flowchart showing another example of control according to the displacement amount ε in Modification 2. Note that explanations for the series of operations shown in this figure that are the same as those shown in Figure 16 are omitted.

[0166] In the example shown in Figure 17, the processing from S301 to S305 is performed, similar to the example shown in Figure 16. At some point during the writing of sector #m, the positional displacement amount ε is equal to the threshold th ε If the value becomes larger (S305: Yes), the SoC30 stops writing and performs a rewrite operation (S401). The rewrite operation involves stopping the write, waiting for the magnetic disk 11 to rotate, and then resuming the writing of the data at the location where the write was stopped. In this case, the write to sector #m is resumed from the beginning of sector #m.

[0167] Thus, in SoC30, the circumferential displacement ε between two radially adjacent bit positions is a threshold th ε As the value increases, data writing may be stopped, and after stopping the writing, the rotation of the magnetic disk 11 may be waited for before writing the data again.

[0168] Figure 18 is a flowchart showing yet another example of control according to the displacement amount ε in Modification 2. Note that explanations for the series of operations shown in this figure that are the same as those shown in Figure 16 are omitted.

[0169] In the example shown in Figure 18, the processing from S301 to S305 is performed, similar to the example shown in Figure 16. At some point during the writing of sector #m, the positional displacement amount ε is equal to the threshold th ε If the value becomes larger (S305: Yes), the SoC30 stops writing to sector #m and performs a sector slip operation (S501). The sector slip operation involves restarting writing from a different position than where the writing stopped, more precisely from the beginning of the next sector.

[0170] Thus, in SoC30, the circumferential displacement ε between two radially adjacent bit positions is a threshold th ε As the value increases, data writing may be stopped and a sector slip operation may be performed.

[0171] (Variation 3) In this embodiment, the recording current was modulated. The amplitude of the recording current affects the recording width in the bit being written, that is, the radial width of the magnetized area. For example, if the amplitude of the recording current is increased, the recording width is widened at the point in the track being written where the amplitude of the recording current is increased. If the amplitude of the recording current is decreased, the recording width is narrowed at the point in the track being written where the amplitude of the recording current is decreased. In other words, it can be considered that the recording width of the track being written is modulated by controlling the modulation of the recording current, thereby improving the recording quality of adjacent bits.

[0172] The method for modulating the recording width of the track to be written is not limited to the modulation of the recording current. Modification 3 describes a method for modulating the recording width of the track to be written using a method different from the modulation of the recording current. Note that Modification 3 is applicable not only to the embodiment but also to any of Modifications 1 and 2.

[0173] Energy-assisted recording is a known method for magnetizing magnetic disks. Energy-assisted recording is a method that enables magnetization of a magnetic disk even with a small recording current by supplying some form of energy to the disk.

[0174] Energy-assisted recording methods include microwave-assisted magnetic recording (MAMR) and heat-assisted magnetic recording (HAMR).

[0175] In microwave-assisted magnetic recording, the magnetic field required for magnetization of the magnetic disk is reduced by applying microwaves to the disk. In heat-assisted magnetic recording, the coercivity of the magnetic disk is reduced by locally heating of the disk by near-field light or the like.

[0176] When an energy-assisted recording method is employed, the magnetic head 22 is equipped with an assist element that can supply energy to the magnetic disk 11. The assist element is either an element that generates microwaves or an element that generates near-field light. The RWC 25 can control the recording width by controlling the amount of energy assist, i.e., the intensity of the microwaves or near-field light generated by the assist element. The larger the amount of energy assist, the larger the recording width can be increased with the RWC 25.

[0177] More specifically, the RWC25 has a configuration similar to that of the embodiment and generates control signals (boost control signal and shrink control signal). The preamplifier 24 changes the amount of energy assist in response to the received control signals. The preamplifier 24 increases the amount of energy assist in response to the boost control signal and decreases the amount of energy assist in response to the shrink control signal.

[0178] Thus, the processing circuit may be configured to modulate the recording width by controlling the amount of energy assist. Even when the recording width is modulated by controlling the amount of energy assist instead of modulating the recording current, the same effects as in the embodiment can be obtained.

[0179] In the embodiments and modifications 1-3, the SMR method was employed. The technology described in the embodiments and modifications 1-3 can also be applied to magnetic disk drives employing the CMR method.

[0180] [Note] According to the first embodiment and variations 1 to 3, the following embodiments are provided. (Note 1) A magnetic disk with multiple tracks, A magnetic head for writing data to and reading data from the magnetic disk, When writing data to the first track among the plurality of tracks by the magnetic head, the first track is a track adjacent to the second track, which is a track on which data has already been written, and the processing circuit modulates the radial recording width of the first data sequence according to a first combination which is a combination of the first data sequence, which is the data to be written to the first track, and the second data sequence, which is the data already written to the second track, and a second combination which is a combination of the polarity of the bit positions of the first track and the bit positions of the second track, which are radially adjacent to each other. A magnetic disk drive equipped with the following features. (Note 2) The processing circuit increases the radial recording width at the bit position of the first track when the second combinations correspond to a combination of the same polarity. The magnetic disk device described in Appendix 1. (Note 3) The processing circuit reduces the radial recording width at the bit position of the first track when the second combination corresponds to a combination of opposite polarities. The magnetic disk device described in Appendix 1. (Note 4) The aforementioned processing circuit is The first data pattern and the second data pattern are set. If the first data sequence matches the first data pattern and the second data sequence matches the second data pattern, the modulation of the recording width according to the second combination is performed. A magnetic disk device as described in any one of the appendices 1 through 3. (Note 5) A controller that stops controlling the modulation of the recording width when the amount of circumferential positional misalignment between the bit positions of the first track and the second track, which are adjacent to each other in the radial direction, exceeds a threshold value. A magnetic disk device further comprising any one of the appendices 1 to 4. (Note 6) A controller that stops writing data to the first track when the circumferential displacement between the bit positions of the first track and the second track, which are adjacent to each other in the radial direction, exceeds a threshold, waits for the magnetic disk to rotate after stopping the writing, and then resumes writing the data. A magnetic disk device further comprising any one of the appendices 1 to 4. (Note 7) A controller that stops writing data to the first track when the circumferential positional difference between the bit positions of the first track and the second track, which are adjacent to each other in the radial direction, exceeds a threshold, and then resumes writing data to the first track from a position different from the position where the writing stopped. A magnetic disk device further comprising any one of the appendices 1 to 4. (Note 8) The processing circuit modulates the recording width by modulating the amplitude of the recording current supplied to the magnetic head. A magnetic disk device as described in any one of the appendices 1 through 7. (Note 9) The magnetic head includes an assist element that supplies energy to the magnetic disk. The processing circuit modulates the recording width by controlling the amount of energy supplied to the magnetic disk by the assist element. A magnetic disk device as described in any one of the appendices 1 through 7. (Note 10) The processing circuit comprises a read / write channel and a preamplifier electrically connected to the read / write channel and the magnetic head. The read / write channel generates a control signal indicating whether or not to perform modulation of the recording width, and transfers the control signal to the preamplifier. A magnetic disk device as described in any one of the appendices 1 through 9.

[0181] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0182] 1 Magnetic disk drive, 2 Host, 11 Magnetic disk, 12 Spindle motor (SPM), 13 Lamp, 15 Actuator arm, 16 Voice coil motor (VCM), 21 Servo controller (SVC), 22 Magnetic head, 22r Read element, 22w Write element, 23 Hard disk controller (HDC), 24 Preamplifier, 25 Read / write channel (RWC), 26 Processor, 28 FROM, 29 DRAM, 42 Servo area, 43 Data area, 101 First data processing circuit, 102 First pre-compensation circuit, 103 Second data processing circuit, 104 Second pre-compensation circuit, 105 Polarity comparison circuit, 106 AND circuit, 241 Modulation circuit, 242 Fourth driver, 243 Fifth driver, 244 Sixth driver, 245 Eighth driver, 251 Media write data generation circuit, 252, 252a Control signal generation circuit, 253 Driver 1, 254; Driver 2, 255; Driver 3, 256; Driver 7.

Claims

1. A magnetic disk with multiple tracks, A magnetic head for writing data to and reading data from the magnetic disk, When writing data to the first track among the plurality of tracks by the magnetic head, the first track is a track adjacent to the second track, which is a track on which data has already been written, and the processing circuit modulates the radial recording width of the first data sequence according to a first combination which is a combination of the first data sequence, which is the data to be written to the first track, and the second data sequence, which is the data already written to the second track, and a second combination which is a combination of the polarity of the bit positions of the first track and the bit positions of the second track, which are radially adjacent to each other. A magnetic disk drive equipped with the following features.

2. The processing circuit increases the radial recording width at the bit position of the first track when the second combinations correspond to a combination of the same polarity. The magnetic disk device according to claim 1.

3. The processing circuit reduces the radial recording width at the bit position of the first track when the second combination corresponds to a combination of opposite polarities. The magnetic disk device according to claim 1.

4. The aforementioned processing circuit is A first data pattern and a second data pattern are set. If the first data sequence matches the first data pattern and the second data sequence matches the second data pattern, the modulation of the recording width according to the second combination is performed. The magnetic disk device according to claim 1.

5. A controller that stops controlling the modulation of the recording width when the amount of circumferential positional misalignment between the bit positions of the first track and the second track, which are adjacent to each other in the radial direction, exceeds a threshold value. The magnetic disk device according to claim 1, further comprising:

6. A controller that stops writing data to the first track when the circumferential positional misalignment between the bit positions of the first track and the second track, which are adjacent to each other in the radial direction, exceeds a threshold, waits for the magnetic disk to rotate after stopping the writing, and then resumes writing the data. The magnetic disk device according to claim 1, further comprising:

7. A controller that stops writing data to the first track when the circumferential positional difference between the bit positions of the first track and the second track, which are adjacent to each other in the radial direction, exceeds a threshold, and then resumes writing data to the first track from a position different from the position where the writing stopped. The magnetic disk device according to claim 1, further comprising:

8. The processing circuit modulates the recording width by modulating the amplitude of the recording current supplied to the magnetic head. A magnetic disk device according to any one of claims 1 to 7.

9. The magnetic head includes an assist element that supplies energy to the magnetic disk. The processing circuit modulates the recording width by controlling the amount of energy supplied to the magnetic disk by the assist element. A magnetic disk device according to any one of claims 1 to 7.

10. The processing circuit comprises a read / write channel and a preamplifier electrically connected to the read / write channel and the magnetic head. The read / write channel generates a control signal indicating whether or not to perform modulation of the recording width, and transfers the control signal to the preamplifier. A magnetic disk device according to any one of claims 1 to 7.

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