Magnetic disk device

Abstract

Embodiments of the present invention provide a disk drive with high recording quality. In the disk drive of the embodiment, the processing circuit modulates the recording width in the radial direction of the first data sequence according to a first combination and a second combination when writing data to the first track. The first track is a track adjacent to a second track, which is a track on which data has already been written. The first combination is a combination of the first data sequence as data written to the first track and the second data sequence as data already written to the second track. The second combination is a combination of the polarities of the bit positions of the first track and the second track, which are adjacent to each other in the radial direction.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2024-221846 (filed on December 18, 2024). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] This embodiment relates to a disk drive. Background Technology

[0003] In recent years, SMR (Shingled Magnetic Recording) has become the mainstream writing method for disk devices. In SMR, the track width is narrower compared to CMR (Conventional Magnetic Recording). Therefore, in SMR, compared to CMR, the recording quality of data on tracks adjacent to the write destination track is more significantly affected during the write operation. Summary of the Invention

[0004] Embodiments of the present invention provide a disk device with high recording quality.

[0005] The disk device according to the embodiment includes: a disk having a plurality of tracks; a read / write head for writing data to and reading data from the disk; and a processing circuit that, when writing data to a first track among the plurality of tracks by the read / write head, modulates the recording width of a first data sequence in the radial direction according to a first combination and a second combination, wherein the first track is a track adjacent to a second track among the plurality of tracks that has already been written with data, the first combination is a combination of the first data sequence as data written to the first track and a second data sequence as data already written to the second track, and the second combination is a combination of the polarities of the bit positions of the first track and the bit positions of the second track that are adjacent to each other in the radial direction. Attached Figure Description

[0006] Figure 1 This is a diagram illustrating an example of the configuration of the disk drive according to the first embodiment.

[0007] Figure 2 This is a schematic diagram illustrating an example of the configuration of the disk according to the first embodiment.

[0008] Figure 3 This is a schematic diagram illustrating the SMR method used in the disk device according to the first embodiment.

[0009] Figure 4This is a diagram illustrating an example of the detailed configuration of the RWC and preamplifier involved in the implementation.

[0010] Figure 5 This is a diagram illustrating an example of the detailed configuration of the control signal generation circuit involved in the embodiment.

[0011] Figure 6 This is a diagram illustrating an example of modulation that increases the amplitude of the recording current in a disk device according to an embodiment.

[0012] Figure 7 This is a diagram illustrating an example of modulation that reduces the amplitude of the recording current in a disk drive according to an embodiment.

[0013] Figure 8 This is a diagram illustrating an example of both modulation methods in a disk device according to an embodiment, which involves increasing the amplitude of the recording current and decreasing the amplitude of the recording current.

[0014] Figure 9 This is a flowchart illustrating an example of the operation involved in modulation that increases the amplitude of the recording current through the control signal generation circuit according to the embodiment.

[0015] Figure 10 This is a flowchart illustrating an example of the operation involved in modulation that reduces the amplitude of the recording current through the control signal generation circuit according to the embodiment.

[0016] Figure 11 This is a diagram showing the detailed configuration of the processing circuit involved in Modification Example 1.

[0017] Figure 12 This is a diagram illustrating an example of the waveform of the boost / shrink control signal involved in Variation 1.

[0018] Figure 13 This is a diagram used to illustrate an example in Variation 2 where two adjacent bit positions (bit positions) in the radial direction are deviated in the circumferential direction.

[0019] Figure 14 This is another diagram used to illustrate the example in Variation 2 where two adjacent positions in the radial direction are offset in the circumferential direction.

[0020] Figure 15 This is another diagram used to illustrate the example in Variation 2 where two adjacent positions in the radial direction are offset in the circumferential direction.

[0021] Figure 16 This is a flowchart illustrating an example of control corresponding to the position deviation involved in Variation 2.

[0022] Figure 17 This is a flowchart illustrating another example of control corresponding to the position deviation involved in Variation 2.

[0023] Figure 18 This is a flowchart illustrating yet another example of control corresponding to the position deviation involved in Variation 2.

[0024] Explanation of reference numerals in the attached figures

[0025] 1. Disk drive; 2. Host; 11. Disk; 12. Spindle motor (SPM); 13. Ramp; 15. Actuator arm; 16. Voice coil motor (VCM); 21. Servo controller (SVC); 22. Head; 22r (read element); 22w (write element); 23. Hard disk controller (HDC); 24. Preamplifier; 25. Read / write channel (RWC); 26. Processor; 28. FROM; 29. ​​DRAM; 42. Servo area; 43. Data area; 101. First data processing circuit. 102 First pre-compensation circuit, 103 Second data processing circuit, 104 Second pre-compensation circuit, 105 Polarity comparison circuit, 106 AND circuit, 241 Modulation circuit, 242 Fourth driver, 243 Fifth driver, 244 Sixth driver, 245 Eighth driver, 251 Media writing data generation circuit, 252, 252a Control signal generation circuit, 253 First driver, 254 Second driver, 255 Third driver, 256 Seventh driver. Detailed Implementation

[0026] Hereinafter, the disk device according to the embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0027] (Implementation Method)

[0028] Figure 1 This is a diagram showing an example of the configuration of the disk device 1 according to the first embodiment.

[0029] Disk device 1 is connected to host 2. Disk device 1 can receive access commands such as write commands or read commands from host 2.

[0030] The disk drive 1 includes a disk 11 on which a magnetic layer is formed. The disk drive 1 accesses the disk 11 according to access commands. The access includes writing data and reading data. In addition, the disk drive 1 may have multiple disks 11, but in the first embodiment, for the sake of explanation and illustration, it is assumed that the disk drive 1 has one disk 11.

[0031] Data writing and reading are performed via the read / write head 22. Specifically, in addition to the disk 11, the disk device 1 also includes a spindle motor (SPM) 12, a ramp 13, an actuator arm 15, a voice coil motor (VCM) 16, a servo controller (SVC) 21, a read / write head 22, a hard disk controller (HDC) 23, a preamplifier 24, a read / write channel (RWC) 25, a processor 26, a FROM (Flash Read-Only Memory) 28, and a DRAM (Dynamic Random Access Memory) 29.

[0032] The disk 11 rotates at a predetermined speed via the coaxially mounted SPM12.

[0033] SVC21 is an integrated circuit that functions as a driver for SPM12 and VCM16. Processor 26 controls the rotation of SPM12 and VCM16 via SVC21.

[0034] The read / write head 22 includes a write element 22w and a read element 22r. The read / write head 22 writes data to the disk 11 using the write element 22w. The read / write head 22 reads data from the disk 11 using the read element 22r. The read / write head 22 is mounted at the front end of the actuator arm 15. The read / write head 22 moves in the radial direction of the disk 11 via the VCM 16 driven by the SVC 21. Furthermore, either or both of the write element 22w and read element 22r of the read / write head 22 can be provided in multiples for a single read / write head 22.

[0035] When the disk 11 stops rotating, the read / write head 22 moves onto the ramp 13. The ramp 13 holds the read / write head 22 in a position separated from the disk 11.

[0036] The preamplifier 24 is an integrated circuit that performs data writing and reading via the read / write head 22. During a read operation, the preamplifier 24 amplifies and outputs the signal read from the disk 11 by the read / write head 22, supplying it to the read / write head 25. During a write operation, the preamplifier 24 amplifies the signal corresponding to the data to be written supplied from the read / write head 25, supplying it to the read / write head 22.

[0037] DRAM29 is used as a buffer for data transfer between the host 2 and the host 2. For example, DRAM29 is used to temporarily store data to be written or data read from disk 11.

[0038] In addition, DRAM29 is used by processor 26 as operational memory. DRAM29 is used as an area for loading firmware programs and as an area for temporarily storing various management data.

[0039] HDC23 controls the data transfer between the HDC23 and the host 2 via the I / F bus. HDC23 supplies write data received from the host 2 to RWC25 via DRAM29. HDC23 receives read data output from RWC25 via DRAM29 and sends the read data to the host 2.

[0040] RWC25 modulates the data of the write object supplied from HDC23 and supplies it to preamplifier 24. In addition, RWC25 performs demodulation, including error correction, on the signal read from disk 11 and supplied from preamplifier 24, and then outputs the signal as digital data to HDC23.

[0041] Processor 26 is, for example, a CPU (Central Processing Unit). FROM 28 and DRAM 29 are connected to processor 26.

[0042] The firmware program and various settings information are stored in FROM28. Alternatively, the firmware program can also be saved to disk 11.

[0043] The processor 26 controls the disk device 1 as a whole according to the firmware program stored in the FROM 28 or the disk 11. For example, the processor 26 loads the firmware program from the FROM 28 or the disk 11 into the DRAM 29, and executes the control of the SVC 21, the preamplifier 24, the RWC 25, the HDC 23, etc. according to the firmware program loaded into the DRAM 29.

[0044] In addition, some or all of the functions of the processor 26 can also be implemented by hardware circuits such as FPGA (Field-Programmable Gate Array) or ASIC (Application Specific Integrated Circuit).

[0045] HDC23, RWC25, and processor 26 constitute a SoC (System-On-a-Chip) 30. SoC 30 is an example of a controller. In addition to these elements, SoC 30 may also include other elements (such as FROM 28 or DRAM 29).

[0046] Figure 2This is a schematic diagram illustrating an example of the configuration of the disk 11 according to the first embodiment. In this diagram, an example of the rotation direction of the disk 11 is shown. The read / write head 22 moves relative to the disk 11 due to its rotation. Therefore, the write / read direction, that is, the direction in which data is written or read by the read / write head 22 along the circumferential direction, is the opposite direction to the rotation direction of the disk 11.

[0047] During the manufacturing process, servo information is written to disk 11, for example, via a servo writer or self-servo write (SSW). Figure 2 As an example of a configuration of servo areas where servo information is written, servo areas 42 are shown arranged radially. Data areas 43, where data can be written, are provided between the servo areas 42.

[0048] Multiple concentric tracks 41 are set in the radial direction of the disk 11.

[0049] Servo information includes servo markers, Gray code, burst pattern, and suffix. When writing and reading data from sectors, SoC 30 generates a Position Error Signal (PES) based on the servo information read by head 22 from servo region 42. PES represents the radial deviation from the center of the target track. Based on the PES obtained each time head 22 passes through servo region 42, SoC 30 performs head 22 positioning, i.e., seek control and tracking control. For example, before the write operation begins, SoC 30 performs seek control to move head 22 towards the target track 41. Then, from the start of the write operation until its completion, tracking control is performed to keep head 22 on the target track 41.

[0050] In multiple data areas 43, multiple sectors for data writing are configured along track 41.

[0051] Furthermore, multiple servo tracks, distinct from the multiple tracks 41, can be specified using servo information. In such cases, a correspondence between the multiple tracks 41 and the multiple servo tracks is generated during manufacturing and stored in a predetermined non-volatile storage area (e.g., FROM 28 or disk 11). The SoC 30 then performs positioning control (track seeking and tracking control) of the head 22 based on the servo information read by the head 22 and this correspondence.

[0052] As methods for writing data to a disk, there are known methods called SMR and CMR. In the first embodiment, the SoC 30 is configured to write data requested by the host 2 to the disk 11 in SMR mode.

[0053] Figure 3 This is a schematic diagram illustrating the SMR method used in the disk device 1 of the first embodiment. In the SMR method, each track 41 is configured such that, when writing data (denoted as first data) to a certain track 41 is performed, and then writing data (denoted as second data) to a track 41 adjacent to that track 41 in the radial direction is performed, a portion of the second data overlaps with the first data. That is, according to the SMR method, data from one of two adjacent tracks 41 in the radial direction of the disk 11 is written with a portion overlapping the data from the other of the two tracks 41.

[0054] For example, data on track #2 is written in a manner that overlaps with a portion of the data already written on track #1. Similarly, data on track #3 is written in a manner that overlaps with a portion of the data already written on track #2. That is, according to the SMR method, this process is repeated so that data on track 41 overlaps with a portion of the data already written on adjacent tracks. As a result, the track width TW is narrower than the width (WHw) of the writing element 22w, increasing the recording density.

[0055] According to the SMR method, since the track width TW is narrower than the width WHw of the writing element 22w, when a portion of the data in multiple tracks 41 is updated, the data in tracks adjacent to the updated data is corrupted. To prevent data corruption, the data in multiple tracks including the corrupted portion is updated together. The region of multiple tracks that are updated together is called the strip region.

[0056] Furthermore, according to the SMR method, it is specified that for multiple tracks 41 within a single band region, writing can only be performed from one predetermined end of the disk's outer side to the other predetermined end. Figure 3 In the example shown, writing is performed in units of track 41 from the outer peripheral end toward the inner peripheral end. SoC 30 can also be configured to perform writing in units of track 41 from the inner peripheral end toward the outer peripheral end. Alternatively, the writing order can be set individually for each band region.

[0057] In the following description, each track 41 contained in the band area will be assigned a track number corresponding to the arrangement order in the radial direction. In SMR mode, writing will be performed in units of track 41 according to the order of track numbers.

[0058] Furthermore, the CMR method involves writing data to two adjacent tracks 41 of the disk 11 in a radial direction without overlap. According to the CMR method, since the width of each track 41 is greater than or equal to the width (WHw) of the write element 22w, data at any location can be updated.

[0059] When data is written to a track 50 (denoted as the target track), the magnetic field of the read / write head 22 may interfere with data already written to adjacent tracks 50 (denoted as adjacent tracks). Due to this interference, the recording quality of the data on adjacent tracks may be degraded. Such interference to adjacent tracks caused by the write operation is known in ATI (Automatic Technology and Testing).

[0060] According to the SMR method, the impact of ATI is greater compared to the CMR method. Therefore, in the SMR method, during the write operation, it is desirable to control the recording current, that is, the current supplied to the write element 22w, by considering not only the recording quality of the data on the target track but also the recording quality of the data on adjacent tracks.

[0061] According to the embodiment, in order to improve the recording quality of data written to the target track and the recording quality of data on adjacent tracks in a balanced manner, the disk drive 1 operates as follows. The disk drive 1 modulates the recording current based on a combination of the data sequence written to the target track and the data sequence already written to adjacent tracks, and a combination of the polarity of the bit position of the adjacent target track and the bit position of the adjacent track in the radial direction. Modulating the recording current means either increasing the amplitude of the recording current compared to its original value, or decreasing the amplitude of the recording current compared to its original value. The original value refers to the value of the recording current amplitude determined solely based on the data written to the target track.

[0062] In order to enable modulation based on these combinations, the disk device 1 has the following configuration.

[0063] Figure 4 This diagram illustrates an example of the detailed configuration of the RWC25 and preamplifier 24 in the embodiment. Furthermore, the RWC25 and preamplifier 24 are examples of a processing circuit.

[0064] The RWC25 includes a media write data generation circuit 251, a control signal generation circuit 252, a first driver 253, a second driver 254, and a third driver 255. The preamplifier 24 includes a modulation circuit 241, a fourth driver 242, a fifth driver 243, and a sixth driver 244.

[0065] The media write data generation circuit 251 generates data to be written to the disk 11 by performing various modulations, including error correction coding, on the data to be written from the HDC 23. From then on, write data refers to the data generated by the media write data generation circuit 251 and written to the disk 11.

[0066] The write data generated by the media write data generation circuit 251 is transmitted as a binary differential signal to the preamplifier 24 via the first driver 253. The signal of the write data transmitted to the preamplifier 24 is denoted as the write data signal.

[0067] To ensure that the write data of the current target track can be referenced for write data of adjacent tracks in the future, the write data of the current target track is stored in a predetermined storage area. Figure 4 In the example shown, the write data of the current write target track generated by the media write data generation circuit 251 is transferred to DRAM 29, and the amount of one track 41 is stored in DRAM 29.

[0068] In addition, Figure 4 In the following description, track #n means the track to be written, and track #(n-1) means the adjacent track.

[0069] The media write data generation circuit 251 transmits the write data of track #n not only to the first driver 253 and DRAM 29, but also to the control signal generation circuit 252.

[0070] The control signal generation circuit 252 receives write data from track #n from the media write data generation circuit 251 and obtains write data from track #(n-1) from the DRAM 29. The control signal generation circuit 252 determines whether the combination of each data sequence between the write data of track #n and the write data of track #(n-1) conforms to a specific combination, and whether the combination of the polarity of the bit positions of each track 41 conforms to a specific combination. Based on the results of these determinations, the control signal generation circuit 252 generates an enhancement control signal and a reduction control signal. The enhancement control signal indicates whether to increase the amplitude of the recording current. The reduction control signal indicates whether to decrease the amplitude of the recording current.

[0071] exist Figure 4 In the example shown, both the boost control signal and the debuff control signal are transmitted as binary differential signals. The boost control signal is transmitted to the preamplifier 24 via the second driver 254. The debuff control signal is transmitted to the preamplifier 24 via the third driver 255.

[0072] In preamplifier 24, fifth driver 243 receives an enhancement control signal. Sixth driver 244 receives a reduction control signal.

[0073] The enhanced control signal received by the fifth driver 243 and the weakened control signal received by the sixth driver 244 are forwarded to the modulation circuit 241. The modulation circuit 241 controls the fourth driver 242 based on the enhanced and weakened control signals.

[0074] The fourth driver 242 receives the write data signal from RWC25. Based on the write data signal, the fourth driver 242 generates a waveform of the recording current supplied to the writing element 22w. At this time, the fourth driver 242 modulates the recording current under the control of the modulation circuit 241.

[0075] Figure 5 This is a diagram illustrating an example of the detailed configuration of the control signal generation circuit 252 in an embodiment.

[0076] The control signal generation circuit 252 includes a first data processing circuit 101, a first pre-compensation circuit 102, a second data processing circuit 103, a second pre-compensation circuit 104, a polarity comparison circuit 105, and an AND circuit 106.

[0077] Furthermore, in order to generate both enhanced and weakened control signals, the control signal generation circuit 252 includes a polarity comparison circuit 105 and an AND circuit 106 for each of the enhanced and weakened control signals. To avoid complicating the diagram, it will be described here that the control signal generation circuit 252 includes one polarity comparison circuit 105 and one AND circuit 106.

[0078] Write data for track #n is input to the first data processing circuit 101. Write data for track #(n-1) is input to the second data processing circuit 103. Write data is input synchronously to the first data processing circuit 101 and the second data processing circuit 103, one bit at a time, starting from the beginning of each write data entry. When the bits contained in the write data of track #n in a pair of adjacent bits in the radial direction are input to the first data processing circuit 101, the bits contained in the write data of track #(n-1) in that pair of bits are input to the second data processing circuit 103, thus synchronizing the input of write data of track #n to the first data processing circuit 101 and the input of write data of track #(n-1) to the second data processing circuit 103.

[0079] The first data processing circuit 101 transmits the write data of track #n to the polarity comparison circuit 105 in a 1-bit manner. The second data processing circuit 103 transmits the write data of track #(n-1) to the polarity comparison circuit 105 in a 1-bit manner.

[0080] The polarity comparison circuit 105 compares the polarity of the write position between the write data of track #n and the write data of track #(n-1), and outputs the comparison result as a binary signal. The polarity comparison circuit 105 compares the polarity of the write position of 1 bit of track #n with the polarity of the write position of 1 bit of track #(n-1) for each pair of adjacent bits in the radial direction.

[0081] Data is written to disk 11 as a binary signal. In disk 11, one bit of data is recorded in a region corresponding to one bit (an example of a bit position) on the recording surface of disk 11 by magnetizing it to a polarity that corresponds to the level of the binary signal, either positive or negative. That is, the level of the binary signal of the written data corresponds to the magnetization polarity of disk 11. The polarity comparison circuit 105 determines, through logical operations on the values ​​of the written data at track #n and track #(n-1), whether pairs of adjacent bit positions in the radial direction have the same polarity or different polarities.

[0082] The bits contained in the write data of track #n in a pair of adjacent bits in the radial direction are denoted as the write target bits, and the bits contained in the write data of track #(n-1) in the pair of bits are denoted as adjacent bits. In addition, pairs of adjacent bits in the radial direction are abbreviated as bit pairs.

[0083] The correspondence between the level and value of a binary signal can be arbitrarily determined by the designer. From now on, when describing binary signals, we will assume that the "H" level of a binary signal corresponds to the value "1", and the "L" level of a binary signal corresponds to the value "0".

[0084] The output method based on the determination result of the polarity comparison circuit 105 varies depending on the control signal of the generated object.

[0085] The polarity comparison circuit 105, used to enhance the generation of the control signal, sets the output signal to a "H" level signal when the polarity pairs of the bit positions to be written are of the same polarity, and sets the output signal to a "L" level signal when the polarity pairs of the bit positions are of different polarities. That is, the polarity comparison circuit 105 performs an XNOR logical operation on the bit pairs.

[0086] The polarity comparison circuit 105, used to reduce the generation of the control signal, sets the output signal to an "L" level signal when the polarity pairs of the bit positions to be written are of the same polarity, and sets the output signal to an "H" level signal when the polarity pairs of the bit positions are of different polarities. That is, the polarity comparison circuit 105 performs an XOR operation on the bit pairs.

[0087] The first data processing circuit 101 sequentially performs NRZI (Non Return to Zero Inversion) encoding on the write data of track #n. The write data of track #n, which has been NRZI encoded by the first data processing circuit 101, is sequentially input to the first pre-compensation circuit 102.

[0088] The second data processing circuit 103 sequentially performs NRZI encoding on the write data of track #(n-1). The write data of track #(n-1) that has been NRZI encoded by the second data processing circuit 103 is sequentially input to the second pre-compensation circuit 104.

[0089] Furthermore, in NRZI code, "0" indicates that the value of the written data (in other words, the polarity of the magnetization) is maintained without reversal, and "1" indicates that the value of the written data (in other words, the polarity of the magnetization) is reversed. The written data after NRZI encoding is denoted as an NRZI tag.

[0090] Whenever a single character of the NRZI tag for track #n is entered, the first pre-compensation circuit 102 compares the NRZI tag for track #n with a pre-defined fixed-length pattern PP(n). The first pre-compensation circuit 102 outputs the comparison result as a binary signal. The interval in the NRZI tag of track #(n-1) that is compared with the pattern PP(n) (hereinafter referred to as the comparison interval) is a fixed-length range including the position of the write target bit processed by the polarity comparison circuit 105. If the NRZI tag in the comparison interval matches the pattern PP(n), the first pre-compensation circuit 102 sets the output signal to "H" level. If the NRZI tag in the comparison interval does not match the pattern PP(n), the first pre-compensation circuit 102 sets the output signal to "L" level.

[0091] Whenever an NRZI tag of track #(n-1) with one symbol is input, the second pre-compensation circuit 104 compares the NRZI tag of track #(n-1) with a pre-set fixed-length pattern PP(n-1). The second pre-compensation circuit 104 outputs the comparison result as a binary signal. Regarding the NRZI tag of track #(n-1), similarly to the first pre-compensation circuit 102, a fixed-length interval including the positions of adjacent bits processed by the polarity comparison circuit 105 is defined as the comparison interval. If the NRZI tag in the comparison interval matches the pattern PP(n-1), the second pre-compensation circuit 104 sets the output signal to "H" level. If the NRZI tag in the comparison interval does not match the pattern PP(n-1), the second pre-compensation circuit 104 sets the output signal to "L" level.

[0092] Furthermore, the first pre-compensation circuit 102 and the second pre-compensation circuit 104 each have registers. The register of the first pre-compensation circuit 102 sets a mode PP(n), and the register of the second pre-compensation circuit 104 sets a mode PP(n-1). The first pre-compensation circuit 102 compares the NRZI tag in the comparison interval of track #n with the mode PP(n) set in the register. The second pre-compensation circuit 104 compares the NRZI tag in the comparison interval of track #(n-1) with the mode PP(n-1) set in the register. The timing for setting the mode PP for each register is arbitrary. Furthermore, the components for setting the mode PP for each register are not limited to specific components. For example, the processor 26 can also set each mode PP in the register according to each track 41 of the write destination. The mode used as the mode PP is arbitrary. The designer can determine the mode PP set in each register in a way that improves the recording quality of the data on the target track and adjacent tracks during the manufacturing process. The processor 26 sets a mode PP determined by the designer. The processor 26 can also be configured to change the mode PP set in each register according to the radius position of the disk 11, the read / write head 22, the set recording density, etc. An example of each mode PP will be described later.

[0093] The AND circuit 106 performs a logical product (logical multiplication) operation on the output signals from the first pre-compensation circuit 102, the second pre-compensation circuit 104, and the polarity comparator circuit 105. The AND circuit 106 outputs the result of the logical operation as a binary signal. The output signal from the AND circuit 106 can be either an enhanced control signal or a weakened control signal.

[0094] Next, an example of modulation of the recording current based on the RWC25 and the preamplifier 24 will be described.

[0095] Figure 6 This is a diagram illustrating an example of modulation that increases the amplitude of the recording current in the disk device 1 of an embodiment.

[0096] exist Figure 6 In this diagram, the α sequence represents the data sequence of the written data for track #n. The β sequence represents the data sequence of the written data for track #(n-1). When x is set to a natural number greater than or equal to 0, the x-th bit from the beginning of the written data for track #n is denoted as α(x), and the x-th bit from the beginning of the written data for track #(n-1) is denoted as β(x).

[0097] Furthermore, these written data represent amounts of data for one sector. Let the sectors for writing data on track #n and track #(n-1) be radially adjacent to each other. Therefore, the positions for writing α(x) and β(x) are radially adjacent.

[0098] x represents the position of the bit in the data being written. Alternatively, x can be considered to correspond to the order or time of writing to disk 11.

[0099] In the α and β sequences, bits with dotted shading have a value of "1", and bits with diagonal shading have a value of "0". As previously mentioned, disk 11 is magnetized to correspond to the polarity of the data value, either positive or negative. In one example, the value "1" corresponds to positive polarity, and the value "0" corresponds to negative polarity. However, the correspondence between values ​​and polarities is not limited to this.

[0100] exist Figure 6 The diagram illustrates the magnetization state when a β sequence is written into track #(n-1) and then an α sequence is written into track #n. Dotted lines represent positive magnetization, and diagonal lines represent negative magnetization.

[0101] The data sequence α(i-5) to α(i+5) is “11000101001”. Therefore, the NRZI tag generated by the first data processing circuit 101 based on this data sequence is “0100111101”.

[0102] The data sequence from β(i-5) to β(i+5) is “01110100111”. Therefore, the NRZI tag generated by the second data processing circuit 103 based on this data sequence is “1001110100”.

[0103] Furthermore, in this specification, the data sequences and NRZI tags are presented in chronological order.

[0104] In addition, Figure 6In the example shown, the pair of α(i) and β(i) is set as a bit pair in the processing based on the polarity comparison circuit 105, and the interval of the NRZI tag is generated based on the data sequence ranging from the 3 bits before the bit pair to the 2 bits after the bit pair. Figure 6 The intervals SC1 and SC2 are set as comparison intervals.

[0105] As mentioned earlier, modes PP(n) and PP(n-1) can be arbitrarily set according to the design. Here, modes PP(n) and PP(n-1) are set to represent writing data to the target bit and adjacent bits of 1T. Furthermore, "T" represents the length of the bit whose polarity is maintained without reversal. That is, writing data to the target bit of 1T means that the polarity is reversed immediately before and immediately after the target bit in the data sequence. Thus, "**11*" is set as mode PP(n). Similarly, data with adjacent bits of 1T means that the polarity is reversed immediately before and immediately after the adjacent bit. Thus, "**11*" is set as mode PP(n-1). Furthermore, in the description of mode PP, "*" represents a wildcard of 1 character. That is, the part of "*" can be either "1" or "0".

[0106] The bit position of α(i) is magnetized to positive polarity by writing α(i). The bit position of β(i) is also positive polarity. That is, the polarity pair of the bit positions of α(i) and β(i) are the same. Therefore, the polarity comparison circuit 105 outputs "1" as the result of the XOR logic operation.

[0107] The NRZI tag of the comparison interval SC1 involved in the write data of track #n is "01110". The NRZI tag of this comparison interval SC1 is consistent with "**11*" as the mode PP(n). Therefore, the first pre-compensation circuit 102 outputs "1" as the comparison result.

[0108] The NRZI tag of the comparison interval SC2 involved in the data written to track #(n-1) is "00111". The NRZI tag of this comparison interval SC2 is consistent with "**11*" as the pattern PP(n-1). Therefore, the second pre-compensation circuit 104 outputs "1" as the comparison result.

[0109] Regarding α(i), the AND circuit 106 receives "1" inputs from the polarity comparison circuit 105, the first pre-compensation circuit 102, and the second pre-compensation circuit 104. Therefore, the AND circuit 106 outputs "1" as an output signal (i.e., an enhanced control signal).

[0110] exist Figure 6The diagram shows the waveform of the write data signal for track #n, the waveform of the enhancement control signal transmitted in parallel with the write data signal for track #n, and the waveform of the recording current generated based on these signals.

[0111] When the enhancement control signal is "H" at the edge timing of the write data signal, the modulation circuit 241 controls the amplitude of the recording current to increase compared to the normal value. When the enhancement control signal is "L" at the edge timing of the write data signal, it does not control the amplitude of the recording current to increase compared to the normal value. In order to perform this operation, the control signal generation circuit 252 advances the transmission timing of the enhancement control signal slightly compared to the transmission timing of the write data signal.

[0112] exist Figure 6 In the example shown, the write data signal rises at the start of writing α(i) (timing t0). In order to ensure that the boost control signal has reached the "H" level at timing t0, the control signal generation circuit 252 changes the boost control signal from the "L" level to the "H" level at timing t1, which is slightly earlier than timing t0.

[0113] At the timing immediately following the data value inversion, the amplitude of the recording current is temporarily increased to quickly stabilize the magnetic field of the writing element 22W. In this recording current waveform, the portion where the recording current amplitude temporarily increases immediately after the data value inversion is known as OSA (Overshoot Amplitude). During the period from the OSA until the next data value inversion, the recording current amplitude is maintained at a constant value to maintain the magnetic field. This portion where the recording current amplitude is maintained at a constant value is called IW. In one embodiment, as an example, the OSA portion is modulated based on an enhancement control signal.

[0114] Based on the data write signal, the data values ​​at α(i-3), α(i), α(i+1), α(i+2), and α(i+5) are inverted. Therefore, when writing begins at α(i-3), α(i), α(i+1), α(i+2), and α(i+5), the amplitude increases due to the OSA. Furthermore, the OSA at α(i), where the amplitude of the recording current is increased by the enhanced control signal, has a larger amplitude than the other OSAs during data writes.

[0115] When modulation that increases the amplitude of the recording current is performed, the effect of ATI (Automatic Technical Indicator) on adjacent tracks at the modulation location on the target track becomes greater. However, the modulation that increases the amplitude of the recording current is implemented on the premise that the polarity pairs of adjacent bit positions in the radial direction are the same. Therefore, due to the enhanced ATI effect during the writing of the target bit, the recording quality of adjacent bits is improved. That is, the recording quality of bits written to adjacent tracks is improved.

[0116] In addition, at the location where this modulation is applied to the target track, the amplitude of the recording current is increased compared to the normal value, thus improving the recording quality of the bits written to the target track.

[0117] That is, it can improve the recording quality of data written to the target track and adjacent tracks in a balanced way.

[0118] Figure 7 This is a diagram illustrating an example of modulation that reduces the amplitude of the recording current in the disk device 1 of an embodiment.

[0119] Figure 7 The example shown is the point where the values ​​of each bit in the sequence of written data on track #(n-1) are reversed. Figure 6 The examples shown are different. Therefore, compared to… Figure 6 The same applies to the example shown. When α(i) is written, the first pre-compensation circuit 102 outputs "1" as the comparison result, and the second pre-compensation circuit 104 outputs "1" as the comparison result.

[0120] The bit position of α(i) is magnetized to positive polarity by writing α(i). The bit position of β(i) is negative polarity. That is, the polarity pair of the bit positions of α(i) and β(i) are different polarities. Therefore, the polarity comparison circuit 105 outputs "1" as the result of the XOR logic operation.

[0121] Regarding α(i), the AND circuit 106 receives "1" inputs from the polarity comparison circuit 105, the first pre-compensation circuit 102, and the second pre-compensation circuit 104. Therefore, the AND circuit 106 outputs "1" as an output signal (i.e., weakens the control signal).

[0122] When the modulation circuit 241 at the edge timing of the write data signal is at a weakening control signal of "H", it controls the amplitude of the recording current to decrease compared to its normal value. When the weakening control signal at the edge timing of the write data signal is at a weakening control signal of "L", it does not control the amplitude of the recording current to decrease compared to its normal value. In order to perform such an operation, the control signal generation circuit 252 advances the transmission timing of the weakening control signal slightly compared to the transmission timing of the write data signal.

[0123] exist Figure 7 In the example shown, the write data signal rises at the start of writing α(i) (timing t2). In order to ensure that the attenuation control signal has become "H" level at timing t2, the control signal generation circuit 252 changes the attenuation control signal from "L" level to "H" level at timing t3, which is slightly earlier than timing t2.

[0124] When the control signal is weakened to "H" at timing t2, the modulation circuit 241 reduces the amplitude of the recording current compared to its normal value. In this example, the modulation circuit 241 makes the amplitude of the OSA during the writing of data α(i) smaller than the amplitude of other OSAs.

[0125] When modulation that reduces the amplitude of the recording current is performed, the ATI (Automatic Transmission Interference) of adjacent tracks at the modulation location on the track to be written is minimal. Furthermore, the modulation that reduces the amplitude of the recording current is implemented based on the premise that the bit pairs are of opposite polarities. Therefore, it is possible to prevent the values ​​of bits already written to adjacent tracks from being reversed due to the influence of ATI. In other words, it is possible to suppress the degradation of recording quality of bits written to adjacent tracks.

[0126] In the writing operation for one track 41, both modulation that increases the amplitude of the recording current and modulation that decreases the amplitude of the recording current can be implemented.

[0127] Figure 8 This diagram illustrates an example of modulation that increases the amplitude of the recording current and modulation that decreases the amplitude of the recording current in the disk device 1 of the embodiment. In the example shown in this diagram, at a timing t5 slightly earlier than the writing timing t4 of α(i), the enhancement control signal is switched to the "H" level. Therefore, the amplitude of the OSA portion is increased during the writing of α(i). Conversely, at a timing t5 slightly earlier than the writing timing t7 of α(i+3), the weakening control signal is switched to the "H" level. Therefore, the amplitude of the OSA portion is decreased during the writing of α(i+3).

[0128] Figure 9 This is a flowchart illustrating an example of the operation involved in the modulation of the recording current amplitude by the control signal generation circuit 252 of the embodiment. Furthermore, the series of operations shown in this figure are repeatedly performed bit by bit for the write data of the target track. This figure shows the operation performed during the writing of a specific target bit.

[0129] In RWC25, the first pre-compensation circuit 102 determines whether the NRZI tag of the object interval SC1 generated based on the sequence of write data of the object track, or in other words, track #n, is consistent with the pattern PP(n) (S101).

[0130] The second pre-compensation circuit 104 determines whether the NRZI tag of the object interval SC2 generated based on the sequence of written data of the adjacent track, in other words track #(n-1), is consistent with the pattern PP(n-1) (S102).

[0131] In addition, the polarity comparison circuit 105 determines whether the polarity of the bit position being written and the adjacent bit is the same (S103).

[0132] Furthermore, for convenience, we assume that these three decisions are implemented in the order of S101, S102, and S103, but in reality, these three decisions are implemented simultaneously or almost simultaneously.

[0133] If the determination results of S101, S102, and S103 are all positive, the preamplifier 24 is instructed by circuit 106 to perform modulation that increases the amplitude of the recording current (S104). Specifically, the enhancement control signal is changed from the "L" level to the "H" level. Then, the operation ends.

[0134] If any one of S101, S102, and S103 results in a negative decision, no modulation to increase the amplitude of the recording current is instructed. Then, the operation ends.

[0135] Figure 10 This is a flowchart illustrating an example of the operation involved in the modulation of the recording current amplitude by the control signal generation circuit 252 of the embodiment. Furthermore, the series of operations shown in this figure are repeatedly performed bit-by-bit for writing data to the target track. This figure shows the operation performed during the writing of a specific target bit.

[0136] In RWC25, the first pre-compensation circuit 102 determines whether the NRZI tag of the object interval SC1 generated based on the sequence of write data of the object track, or in other words, track #n, is consistent with the pattern PP(n) (S201).

[0137] The second pre-compensation circuit 104 determines whether the NRZI tag of the object interval SC2 generated based on the sequence of written data of the adjacent track, in other words track #(n-1), is consistent with the pattern PP(n-1) (S202).

[0138] In addition, the polarity comparison circuit 105 determines whether the polarity of the bit position being written and the adjacent bit are different (S203).

[0139] exist Figure 10For convenience, it is also set that these three decisions are implemented in the order of S201, S202, and S203, but in reality, these three decisions are implemented simultaneously or almost simultaneously.

[0140] If the determination results of S201, S202, and S203 are all positive, the preamplifier 24 is instructed by circuit 106 to perform modulation that reduces the amplitude of the recording current (S204). Specifically, the attenuation control signal is changed from the "L" level to the "H" level. Then, the operation ends.

[0141] If any one of S201, S202, and S203 results in a negative decision, no modulation to reduce the amplitude of the recording current is instructed. Then, the operation ends.

[0142] In the above description, the first pre-compensation circuit 102 and the second pre-compensation circuit 104 respectively compare the NRZI-encoded write data with the pattern PP to determine whether the combination of the sequence of write data of the target track and the sequence of write data of adjacent tracks conforms to a specific combination. The first pre-compensation circuit 102 and the second pre-compensation circuit 104 may also be based not only on NRZI-encoded write data, but also on write data without NRZI encoding or write data with arbitrary encoding to determine whether the combination of the sequence of write data of the target track and the sequence of write data of adjacent tracks conforms to a specific combination.

[0143] Furthermore, as an example of a specific combination, a combination where both the target bit and adjacent bits are 1TB of data is written is given. Generally, when writing 1TB of data to a disk, the circumferential width of the magnetized data corresponding to its polarity is narrow, thus the recording quality of the data is prone to instability. As in the example above, when writing 1TB of data to both the target bit and adjacent bits, the processing circuit modulates the recording current corresponding to the polarity of the bit pair's write position, thereby improving the recording quality of the 1TB of data in both the target bit and adjacent bits.

[0144] Furthermore, specific combinations are not limited to the examples mentioned above. Designers can test various combinations and, based on the test results, designate any combination as a specific combination.

[0145] In addition, as an example of modulation of the recording current, the amplitude of a portion of the OSA was changed. The method of modulation of the recording current is not limited to this. The amplitude of the IW portion can also be changed in addition to, or in place of, the portion of the OSA.

[0146] As described above, according to the embodiment, the processing circuit (i.e., RWC25 and preamplifier 24) modulates the recording current supplied to the magnetic head 22 based on the combination of the sequence of write data to be written to the target track and the combination of the polarity of the bit position of the target track and the bit position of the adjacent track in the radial direction.

[0147] Therefore, not only can the recording quality of data written to the target track be improved, but the recording quality of data on adjacent tracks can also be improved. In other words, the recording quality is improved.

[0148] Furthermore, according to the implementation method, when the polarity combination of the bit position of the write target bit and the bit position of the adjacent bit is a combination with the same polarity, the processing circuit increases the amplitude of the recording current when writing the write target bit.

[0149] This allows for a balanced improvement in the recording quality of data written to the target track and adjacent tracks.

[0150] Furthermore, according to the implementation method, when the polarity combination of the bit position of the write target bit and the bit position of the adjacent bit is a combination of different polarities, the processing circuit reduces the amplitude of the recording current when writing the write target bit.

[0151] This allows for the suppression of recording quality degradation in bits written to adjacent tracks. In other words, the recording quality of adjacent tracks is improved.

[0152] Furthermore, according to the embodiment, mode PP(n) is set for the first pre-compensation circuit 102, and mode PP(n-1) is set for the second pre-compensation circuit 104. When the sequence of write data for the target track is consistent with mode PP(n) and the sequence of write data for adjacent tracks is consistent with mode PP(n-1), the processing circuit performs modulation of the recording current corresponding to the combination of the polarity of the bit position of the target bit and the bit position of the adjacent bit.

[0153] Thus, designers can optimize the combination of the sequences of written data during modulation to maximize the recording quality of the written data on the target track and the written data on adjacent tracks.

[0154] (Variation Example 1)

[0155] In this implementation, both the enhancement control signal and the reduction control signal are configured as binary signals. The configuration of each signal is not limited to this. As a variation 1, an example is given where the enhancement control signal and the reduction control signal are integrated into a single ternary control signal.

[0156] Figure 11 This is a diagram showing the detailed configuration of the processing circuit of Modified Example 1.

[0157] The RWC25 includes a media write data generation circuit 251, a control signal generation circuit 252a, and a seventh driver 256. The preamplifier 24 includes a fourth driver 242, a modulation circuit 241, and an eighth driver 245.

[0158] The components of the processing circuit in Modified Example 1 that are labeled with the same reference numerals as those in the Embodiment 1 have the same functions as those in the Embodiment 1. Therefore, the description of the components labeled with the same reference numerals as those in the Embodiment 1 is omitted.

[0159] The control signal generation circuit 252a receives write data from track #n from the media write data generation circuit 251 and obtains write data from track #(n-1) from the DRAM 29. The control signal generation circuit 252a determines whether the combination of each data sequence between the write data of track #n and the write data of track #(n-1) conforms to a specific combination, and whether the combination of the polarity of the bit positions of each track 41 conforms to a specific combination. Based on the results of these determinations, the control signal generation circuit 252a generates an enhancement / depression control signal. The enhancement / depression control signal is a three-valued signal that integrates the enhancement control signal and the depression control signal.

[0160] The boost / deboost control signal is transmitted to the preamplifier 24 via the 7th driver 256.

[0161] In the preamplifier 24, the 8th driver 245 receives the boost / deboost control signal.

[0162] The boost / deboost control signal received by the eighth driver 245 is transmitted to the modulation circuit 241. The modulation circuit 241 controls the fourth driver 242 based on the boost / deboost control signal.

[0163] Figure 12 This is a diagram illustrating an example of the waveform of the enhancement / decrease control signal in Modification 1. According to this diagram, the enhancement / decrease control signal has three levels. In the enhancement / decrease control signal, the "H" level indicates an indication to increase the amplitude of the recording current. The "L" level indicates an indication to decrease the amplitude of the recording current. Through this enhancement / decrease control signal, [the signal is controlled]... Figure 8 Similarly, in the example shown, the amplitude of a portion of the OSA is increased or decreased.

[0164] (Variation Example 2)

[0165] In this implementation, the two adjacent bit positions of the written bit pair are arranged radially. However, even if control is implemented to ensure that the two bit positions are arranged radially, there may sometimes be a circumferential deviation between the two bit positions for various reasons. If the amount of such deviation exceeds a predetermined value, the recording quality of data on adjacent tracks may sometimes deteriorate due to the control of the recording current modulation.

[0166] Therefore, in Modification 2, the disk drive 1 stops controlling the modulation of the recording current based on the positional deviation of the two bit positions in the circumferential direction. This prevents deterioration of the recording quality of data on adjacent tracks due to the control of the recording current modulation. Modification 2 will be described below. Furthermore, Modification 2 can be used in conjunction with Modification 1.

[0167] Figure 13 as well as Figure 14 This is a diagram used to illustrate the example in Variation Example 2 where two adjacent positions in the radial direction are deviated in the circumferential direction.

[0168] according to Figure 13 as well as Figure 14 The bit position written to α(i) is offset by a position deviation ε in the circumferential direction relative to the bit position written to β(i).

[0169] exist Figure 13 In the example, the positional deviation ε is relatively small. However, in Figure 14 In the example, the positional deviation ε is relatively large, and the positional deviation ε is close to about half of the width (denoted as unit bit width) in the radial direction of β(i) being written.

[0170] In such Figure 14 In cases like the example where the position deviation ε is large, if modulation that increases the amplitude of the recording current is performed during the writing of α(i), it is very likely to have an adverse effect on the magnetization of the bit position where β(i+1) has been written.

[0171] Therefore, a predetermined threshold (denoted as threshold th) is set for the position deviation ε. ε When the positional deviation ε is greater than the threshold th ε In this case, the control of the modulation recording current is suppressed.

[0172] For example, in Figure 13 In the case shown, the positional deviation ε is less than the threshold th. ε Therefore, during the writing of α(i), the preamplifier 24 is instructed to increase the amplitude of the recording current by amplifying the control signal. According to this instruction, the portion of the OSA during the writing of α(i) is increased.

[0173] exist Figure 14 In the case shown, the positional deviation ε is greater than the threshold th. ε Therefore, during the writing of α(i), the enhancement control signal is maintained at "L". Consequently, during the writing of α(i), the control that increases the amplitude of the recording current is suppressed.

[0174] Furthermore, when the position deviation ε is an integer multiple or greater than an integer multiple of the unit bit width, bit pair reassembly is performed. More specifically, a bit pair is formed by the bit to be written and the bit of the adjacent track written to the bit position with the smallest deviation in the circumferential direction relative to the bit position where the bit to be written is located.

[0175] For example, in Figure 15 In the example shown, the bit position where α(i) is written is separated from the bit position where β(i) is written by more than one bit width. However, the circumferential deviation relative to the bit position where β(i) is written becomes minimal at the bit position where α(i+2) is written. Therefore, a bit pair is formed by α(i+2) and β(i), and control is performed on this bit pair to determine whether to modulate the recording current based on the position deviation ε. Furthermore, the processing circuit compares the data sequence and polarity of this bit pair.

[0176] Figure 16 This is a flowchart illustrating an example of control corresponding to the position deviation amount ε involved in Modification Example 2. Furthermore, the series of actions shown in this figure are executed by predetermined components (e.g., processor 26) within the SoC 30. Here, the SoC 30 is described as the main body of this series of actions. Additionally, this figure shows the action of writing to the target track from the first sector to the last sector.

[0177] SoC30 first initializes m using 0 pairs as the index for counting sectors (S301). Then, it enables the generation function of control signals (i.e., the enhanced control signal and the weakened control signal in the embodiment, or the enhanced / weakened control signal in Modification 1) (S302). As a result, RWC25 generates control signals and is able to modulate the recording current.

[0178] Next, SoC 30 writes to sector #m (S303). During the writing of sector #m, SoC 30 monitors the position deviation ε (S304). SoC 30 can detect the position deviation ε whenever 1 bit is written to sector #m, or whenever data larger than 1 bit is written to sector #m. Furthermore, the method for detecting the position deviation ε is not limited to a specific method. In one example, SoC 30 can also be configured to detect the position deviation ε based on servo information.

[0179] In monitoring the position deviation ε, the SoC30 determines whether the position deviation ε is greater than the threshold th. ε (S305). At any timing during the write of sector #m, the position deviation ε becomes greater than the threshold th. ε In the case of a large deviation (S305: yes), the SoC30 becomes greater than the threshold th when the position deviation ε is larger than the threshold th. ε For large timing events, the control signal generation function is turned off (S306). As a result, RWC25 stops generating control signals and ceases modulation of the recording current.

[0180] The positional deviation ε is not greater than the threshold th ε In the case of (S305: No), SoC30 skips the processing of S306.

[0181] When the write operation of sector #m is complete, the SoC30 determines whether the value of m is equal to the maximum value m. max (S307). Furthermore, m max Corresponding to the number of sectors set in the write target track, sector #m max This indicates the last sector of the object track.

[0182] The value of m is not equal to the maximum value m. max In the case of (S307: No), SoC30 increases the value of m by 1 (S308), and the control moves to S302.

[0183] Furthermore, in S302, the control signal generation function is enabled. If the control signal generation function is not disabled and the write of the previous sector is completed, the SoC30 skips the processing of S302 and keeps the control signal generation function enabled.

[0184] Thus, according to Variation Example 2, the SoC 30 becomes more than the threshold th based on the position deviation ε of two adjacent bit positions in the radial direction in the circumferential direction. ε The control of the modulation of the recording current is large enough to stop recording.

[0185] Therefore, it is possible to prevent the deterioration of the recording quality of data on adjacent tracks caused by modulation of the recording current when the position deviation ε is greater than a predetermined value.

[0186] The position deviation ε becomes greater than the threshold th ε The operation of the large time is not limited to stopping the modulation of the recording current.

[0187] Figure 17 This is a flowchart illustrating another example of control corresponding to the position deviation ε in Modified Example 2. Furthermore, regarding the series of actions shown in this figure, for... Figure 16 For items that are identical to those shown, the description is omitted.

[0188] exist Figure 17 In the example shown, with Figure 16 The example shown also executes the processes S301 to S305. During any timing period of writing to sector #m, the position deviation ε becomes greater than the threshold th. ε In the case of a large error (S305: Yes), SoC30 stops writing and performs a rewrite process (S401). During the rewrite process, after stopping writing, it waits for the disk 11 to rotate, and then resumes writing the data from the areas where writing was stopped. In this case, writing to sector #m is resumed from the beginning of sector #m.

[0189] In this way, SoC30 can also become more than the threshold th based on the position deviation ε of two adjacent bit positions in the radial direction in the circumferential direction. ε The data writing process stops when the disk 11 is fully loaded. After the writing stops, the disk 11 is allowed to rotate before the data writing process resumes.

[0190] Figure 18 This is a flowchart illustrating yet another example of control corresponding to the position deviation ε involved in Variation Example 2. Furthermore, regarding the series of actions shown in this figure, for the... Figure 16 For items that are identical to those shown, the description is omitted.

[0191] exist Figure 18 In the example shown, with Figure 16 The example shown also executes the processes S301 to S305. During any timing period of writing to sector #m, the position deviation ε becomes greater than the threshold th. ε In the case of a large number of cases (S305: Yes), SoC30 stops writing to sector #m and performs sector sliding processing (S501). In sector sliding processing, after writing stops, writing resumes from a position different from where writing stopped, more precisely, at the beginning of the next sector.

[0192] In this way, SoC30 can also become more than the threshold th based on the position deviation ε of two adjacent bit positions in the radial direction in the circumferential direction. ε If the data writing is too large, stop writing data and perform sector sliding.

[0193] (Variation Example 3)

[0194] In this implementation, the recording current is modulated. The amplitude of the recording current affects the recording width in the target bit, that is, the width in the radial direction of the magnetized area. For example, when the amplitude of the recording current increases, the recording width becomes wider at locations where the amplitude of the recording current in the target track increases. When the amplitude of the recording current decreases, the recording width becomes narrower at locations where the amplitude of the recording current in the target track decreases. In other words, it can be considered that the recording width of the target track is modulated by controlling the modulation of the recording current, thereby improving the recording quality of adjacent bits.

[0195] The method for modulating the recording width of the target track is not limited to modulation of the recording current. As a variation 3, a method for modulating the recording width of the target track using a method different from modulation of the recording current will be described. Furthermore, variation 3 can be applied not only to the implementation method, but also to any of variations 1 and 2.

[0196] One known method for magnetizing a hard disk is energy-assisted recording. Energy-assisted recording magnetizes the disk by applying energy, even with a small recording current.

[0197] Energy-assisted recording methods include microwave-assisted magnetic recording (MAMR) and heat-assisted magnetic recording (HAMR).

[0198] Microwave-assisted magnetic recording reduces the magnetic field required for magnetization of the disk by applying microwaves. Heat-assisted magnetic recording reduces the coercivity of the disk by locally heating it using near-field light.

[0199] When using energy-assisted recording, the magnetic head 22 has an auxiliary element capable of applying energy to the disk 11. This auxiliary element can be a microwave-generating element or a near-field light-generating element. The RWC25 can control the recording width by controlling the amount of energy assistance, i.e., the intensity of the microwaves or near-field light generated by the auxiliary element. The RWC25 allows for a larger recording width with a greater amount of energy assistance.

[0200] More specifically, RWC25 has the same configuration as in the embodiment, generating control signals (both an amplifying control signal and a weakening control signal). Preamplifier 24 changes the energy assist amount based on the received control signals. Preamplifier 24 increases the energy assist amount based on the amplifying control signal and decreases the energy assist amount based on the weakening control signal.

[0201] Thus, the processing circuit can also be configured to modulate the recording width by controlling the energy assist amount. Even when the recording width is modulated by controlling the energy assist amount instead of the recording current, the same effect as in the implementation method can be obtained.

[0202] In the embodiments and variations 1 to 3, the SMR method was used. The technology described in the embodiments and variations 1 to 3 can also be applied to disk devices that employ the CMR method.

[0203] [Note] Based on the first embodiment and variations 1 to 3, the following technical solutions are provided.

[0204] (Postscript 1)

[0205] A disk drive, comprising:

[0206] A hard disk has multiple tracks.

[0207] A read / write head that writes data to and reads data from the disk; and

[0208] The processing circuit, when writing data to the first track of the plurality of tracks through the magnetic head, modulates the recording width of the first data sequence in the radial direction according to the first combination and the second combination, wherein the first track is a track adjacent to the second track, which is a track among the plurality of tracks that has already been written with data, the first combination is a combination of the first data sequence as the data written to the first track and the second data sequence as the data already written to the second track, and the second combination is a combination of the polarities of the bit positions of the first track and the second track that are adjacent to each other in the radial direction.

[0209] (Postscript 2)

[0210] According to the disk drive described in Appendix 1

[0211] When the second combination matches a combination with the same polarity, the processing circuit increases the recording width in the radial direction at the bit position of the first track.

[0212] (Note 3)

[0213] According to the disk drive described in Appendix 1

[0214] When the second combination meets the combination with different polarities, the processing circuit reduces the recording width in the radial direction at the bit position of the first track.

[0215] (Note 4)

[0216] The disk drive according to any one of Annexes 1 to 3,

[0217] The processing circuit,

[0218] Set the first data mode and the second data mode.

[0219] When the first data sequence is consistent with the first data pattern and the second data sequence is consistent with the second data pattern, modulation of the recording width corresponding to the second combination is performed.

[0220] (Note 5)

[0221] The disk drive according to any one of Annexes 1 to 4,

[0222] It also includes a controller that stops controlling the modulation of the recording width when the position deviation in the circumferential direction between the bit position of the first track and the bit position of the second track, which are adjacent to each other in the radial direction, becomes greater than a threshold.

[0223] (Note 6)

[0224] The disk drive according to any one of Annexes 1 to 4,

[0225] It also includes a controller that stops writing data to the first track when the deviation of the bit position of the first track adjacent to each other in the radial direction from the bit position of the second track in the circumferential direction becomes greater than a threshold. After the writing stops, it waits for the disk to rotate and then resumes writing the data.

[0226] (Note 7)

[0227] The disk drive according to any one of Annexes 1 to 4,

[0228] It also includes a controller that stops writing data to the first track when the position deviation in the circumferential direction between the bit position of the first track and the bit position of the second track, which are adjacent to each other in the radial direction, becomes greater than a threshold. After the writing stops, the controller restarts writing data to the first track from a position different from the position where the writing stopped.

[0229] (Postscript 8)

[0230] The disk drive according to any one of Annexes 1 to 7,

[0231] The processing circuit modulates the recording width by modulating the amplitude of the recording current supplied to the magnetic head.

[0232] (Note 9)

[0233] The disk drive according to any one of Annexes 1 to 7,

[0234] The read / write head has auxiliary elements for applying power to the disk.

[0235] The processing circuit modulates the recording width by controlling the amount of energy applied to the disk by the auxiliary element.

[0236] (Postscript 10)

[0237] The disk drive according to any one of Annexes 1 to 9,

[0238] The processing circuit includes a read / write channel and a preamplifier electrically connected to the read / write channel and the magnetic head.

[0239] The read / write channel generates a control signal indicating whether to perform modulation of the recording width, and transmits the control signal to the preamplifier.

[0240] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A disk drive, comprising: A hard disk has multiple tracks. A read / write head that writes data to and reads data from the disk; and The processing circuit, when writing data to the first track of the plurality of tracks through the magnetic head, modulates the recording width of the first data sequence in the radial direction according to the first combination and the second combination, wherein the first track is a track adjacent to the second track, which is a track among the plurality of tracks that has already been written with data, the first combination is a combination of the first data sequence as the data written to the first track and the second data sequence as the data already written to the second track, and the second combination is a combination of the polarities of the bit positions of the first track and the second track that are adjacent to each other in the radial direction.

2. The disk drive according to claim 1, When the second combination matches a combination with the same polarity, the processing circuit increases the recording width in the radial direction at the bit position of the first track.

3. The disk drive according to claim 1, When the second combination meets the combination with different polarities, the processing circuit reduces the recording width in the radial direction at the bit position of the first track.

4. The disk drive according to claim 1, The processing circuit, Set the first data mode and the second data mode. When the first data sequence is consistent with the first data pattern and the second data sequence is consistent with the second data pattern, modulation of the recording width corresponding to the second combination is performed.

5. The disk drive according to claim 1, It also includes a controller that stops controlling the modulation of the recording width when the position deviation in the circumferential direction between the bit position of the first track and the bit position of the second track, which are adjacent to each other in the radial direction, becomes greater than a threshold.

6. The disk drive according to claim 1, It also includes a controller that stops writing data to the first track when the deviation of the bit position of the first track adjacent to each other in the radial direction from the bit position of the second track in the circumferential direction becomes greater than a threshold. After the writing stops, it waits for the disk to rotate and then resumes writing the data.

7. The disk drive according to claim 1, It also includes a controller that stops writing data to the first track when the position deviation in the circumferential direction between the bit position of the first track and the bit position of the second track, which are adjacent to each other in the radial direction, becomes greater than a threshold. After the writing stops, the controller restarts writing data to the first track from a position different from the position where the writing stopped.

8. The disk drive according to any one of claims 1 to 7, The processing circuit modulates the recording width by modulating the amplitude of the recording current supplied to the magnetic head.

9. The disk drive according to any one of claims 1 to 7, The read / write head has auxiliary elements for applying power to the disk. The processing circuit modulates the recording width by controlling the amount of energy applied to the disk by the auxiliary element.

10. The disk drive according to any one of claims 1 to 7, The processing circuit includes a read / write channel and a preamplifier electrically connected to the read / write channel and the magnetic head. The read / write channel generates a control signal indicating whether to perform modulation of the recording width, and transmits the control signal to the preamplifier.

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