High-bandwidth optical interconnect architecture

Abstract

An embedded optical waveguide is provided for transmitting optical signals from a photonics die to a fiber optic connector that can be attached to the side of the package. [Solution] Embodiments disclosed herein include optical packages. In one embodiment, the optical package includes a package substrate and a photonic die coupled to the package substrate. In one embodiment, a compute die is coupled to the package substrate, where the photonic die is communicatively coupled to the compute die by a bridge in the package substrate. In one embodiment, the optical package further includes an optical waveguide embedded in the package substrate. In one embodiment, the first end of the optical waveguide is below the photonic die, and the second end of the optical waveguide is substantially coplanar with the edge of the package substrate.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor devices, and more particularly, to an interconnect architecture for high-bandwidth optical interconnects.

Background Art

[0002] Optical interconnects provide solutions for overcoming bottlenecks in high-speed electrical transmission, such as limited electrical I / O bandwidth and signal integrity issues. Optical transmission inherently has a higher limited bandwidth and higher noise immunity to electromagnetic interference (EMI) compared to electrical transmission. Currently, optical interconnects are connected to photonics dies using a V-groove approach. In such an architecture, the photonics die overhangs at the edge of the package substrate and includes V-grooves on the underside surface. Next, fibers are inserted into the V-grooves to make optical connections. This approach involves multiple assembly operations using an overhanging die, such as an epoxy and underfill process, an integrated heat spreader (IHS) attachment using the overhanging die, and warping of the package using the overhanging die. Since many of these processes require further development and are not mature, they lead to low yields and high development costs.

Brief Description of the Drawings

[0003] [Figure 1A] A plan view of an optical package having a photonics die overhanging at the edge of a package substrate.

[0004] [Figure 1B] A cross-sectional view of the optical package of FIG. 1A.

[0005] [Figure 2A] A plan view of an optical package having a photonics die entirely within the footprint of a package substrate according to one embodiment.

[0006] [Figure 2B] This is a cross-sectional view of an optical package having an optical waveguide embedded in a package substrate, according to one embodiment.

[0007] [Figure 2C] This is a cross-sectional view of an optical package having a lens on an embedded optical waveguide, according to one embodiment.

[0008] [Figure 2D] This is a cross-sectional view of an optical package having a separate optical waveguide embedded in a package substrate, according to one embodiment.

[0009] [Figure 3A] This is a cross-sectional view of a process for forming an optical package having an embedded optical waveguide, according to one embodiment. [Figure 3B] This is a cross-sectional view of a process for forming an optical package having an embedded optical waveguide, according to one embodiment. [Figure 3C] This is a cross-sectional view of a process for forming an optical package having an embedded optical waveguide, according to one embodiment. [Figure 3D] This is a cross-sectional view of a process for forming an optical package having an embedded optical waveguide, according to one embodiment. [Figure 3E] This is a cross-sectional view of a process for forming an optical package having an embedded optical waveguide, according to one embodiment. [Figure 3F] This is a cross-sectional view of a process for forming an optical package having an embedded optical waveguide, according to one embodiment. [Figure 3G] This is a cross-sectional view of a process for forming an optical package having an embedded optical waveguide, according to one embodiment. [Figure 3H] This is a cross-sectional view of a process for forming an optical package having an embedded optical waveguide, according to one embodiment.

[0010] [Figure 4A]Cross-sectional view of a process for forming an optical package having a lens over an embedded optical waveguide according to one embodiment. [Figure 4B] Cross-sectional view of a process for forming an optical package having a lens over an embedded optical waveguide according to one embodiment. [Figure 4C] Cross-sectional view of a process for forming an optical package having a lens over an embedded optical waveguide according to one embodiment.

[0011] [Figure 5A] Cross-sectional view of a process for forming an optical package having discrete optical waveguides embedded in a package substrate according to one embodiment. [Figure 5B] Cross-sectional view of a process for forming an optical package having discrete optical waveguides embedded in a package substrate according to one embodiment. [Figure 5C] Cross-sectional view of a process for forming an optical package having discrete optical waveguides embedded in a package substrate according to one embodiment. [Figure 5D] Cross-sectional view of a process for forming an optical package having discrete optical waveguides embedded in a package substrate according to one embodiment.

[0012] [Figure 6A] Planar view of an optical package having a glass patch over a package substrate according to one embodiment.

[0013] [Figure 6B] Cross-sectional view of the optical package in FIG. 6A having an embedded bridge providing electrical connection between a compute die and a photonics die according to one embodiment.

[0014] [Figure 6C] Cross-sectional view of the optical package in FIG. 6A having a high density routing layer for providing electrical connection between a compute die and a photonics die according to one embodiment.

[0015] [Figure 7A] Cross-sectional view of a process for forming a glass patch for an optical package having an embedded bridge and an embedded optical waveguide according to one embodiment. [Figure 7B] Cross-sectional view of a process for forming a glass patch for an optical package having an embedded bridge and an embedded optical waveguide according to one embodiment. [Figure 7C] Cross-sectional view of a process for forming a glass patch for an optical package having an embedded bridge and an embedded optical waveguide according to one embodiment. [Figure 7D] Cross-sectional view of a process for forming a glass patch for an optical package having an embedded bridge and an embedded optical waveguide according to one embodiment. [Figure 7E] Cross-sectional view of a process for forming a glass patch for an optical package having an embedded bridge and an embedded optical waveguide according to one embodiment. [Figure 7F] Cross-sectional view of a process for forming a glass patch for an optical package having an embedded bridge and an embedded optical waveguide according to one embodiment. [Figure 7G] Cross-sectional view of a process for forming a glass patch for an optical package having an embedded bridge and an embedded optical waveguide according to one embodiment. [Figure 7H] Cross-sectional view of a process for forming a glass patch for an optical package having an embedded bridge and an embedded optical waveguide according to one embodiment. [Figure 7I] Cross-sectional view of a process for forming a glass patch for an optical package having an embedded bridge and an embedded optical waveguide according to one embodiment.

[0016] [Figure 8A]This is a cross-sectional view of a process for forming a glass patch for an optical package having a high-density routing layer and an embedded optical waveguide, according to one embodiment. [Figure 8B] This is a cross-sectional view of a process for forming a glass patch for an optical package having a high-density routing layer and an embedded optical waveguide, according to one embodiment. [Figure 8C] This is a cross-sectional view of a process for forming a glass patch for an optical package having a high-density routing layer and an embedded optical waveguide, according to one embodiment. [Figure 8D] This is a cross-sectional view of a process for forming a glass patch for an optical package having a high-density routing layer and an embedded optical waveguide, according to one embodiment. [Figure 8E] This is a cross-sectional view of a process for forming a glass patch for an optical package having a high-density routing layer and an embedded optical waveguide, according to one embodiment. [Figure 8F] This is a cross-sectional view of a process for forming a glass patch for an optical package having a high-density routing layer and an embedded optical waveguide, according to one embodiment.

[0017] [Figure 9A] This is a plan view of an optical package having a glass package substrate according to one embodiment.

[0018] [Figure 9B] This is a cross-sectional view of an optical package in Figure 9A having an embedded bridge and optical waveguide according to one embodiment.

[0019] [Figure 9C] This is a cross-sectional view of an optical package in Figure 9A having a high-density routing layer and an optical waveguide, according to one embodiment.

[0020] [Figure 10A]This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with embedded bridges and optical waveguides, according to one embodiment. [Figure 10B] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with embedded bridges and optical waveguides, according to one embodiment. [Figure 10C] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with embedded bridges and optical waveguides, according to one embodiment. [Figure 10D] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with embedded bridges and optical waveguides, according to one embodiment. [Figure 10E] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with embedded bridges and optical waveguides, according to one embodiment. [Figure 10F] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with embedded bridges and optical waveguides, according to one embodiment. [Figure 10G] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with embedded bridges and optical waveguides, according to one embodiment. [Figure 10H] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with embedded bridges and optical waveguides, according to one embodiment. [Figure 10I] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with embedded bridges and optical waveguides, according to one embodiment. [Figure 10J] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with embedded bridges and optical waveguides, according to one embodiment. [Figure 10K] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with embedded bridges and optical waveguides, according to one embodiment. [Figure 10L]This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with embedded bridges and optical waveguides, according to one embodiment. [Figure 10M] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with embedded bridges and optical waveguides, according to one embodiment. [Figure 10N] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with embedded bridges and optical waveguides, according to one embodiment. [Figure 10O] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with embedded bridges and optical waveguides, according to one embodiment. [Figure 10P] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with embedded bridges and optical waveguides, according to one embodiment.

[0021] [Figure 11A] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with an embedded optical waveguide, according to one embodiment. [Figure 11B] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with an embedded optical waveguide, according to one embodiment. [Figure 11C] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with an embedded optical waveguide, according to one embodiment. [Figure 11D] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with an embedded optical waveguide, according to one embodiment. [Figure 11E] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with an embedded optical waveguide, according to one embodiment. [Figure 11F] This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with an embedded optical waveguide, according to one embodiment. [Figure 11G]This is a cross-sectional view of a process for forming an optical package having a multilayer glass substrate with an embedded optical waveguide, according to one embodiment.

[0022] [Figure 12] This is a cross-sectional view of an optical system having an optical waveguide embedded in a package substrate, according to one embodiment.

[0023] [Figure 13A] This is a cross-sectional view of an optical package having a photonics die directly coupled to a compute die, according to one embodiment.

[0024] [Figure 13B] This is a cross-sectional view of a photonic die having a grating coupler according to one embodiment.

[0025] [Figure 14A] This is a cross-sectional view of an optical package having a photonic die directly coupled to a compute die, according to an additional embodiment.

[0026] [Figure 14B] This is a cross-sectional view of a photonic die having a V-groove attachment according to one embodiment.

[0027] [Figure 14C] This is a cross-sectional view of a photonic die in Figure 14B, showing a V-shaped groove according to one embodiment.

[0028] [Figure 15A] This is a cross-sectional view of an optical package having a photonic die thermally coupled to an integrated heat spreader by a thermal block, according to one embodiment.

[0029] [Figure 15B] This is a cross-sectional view of an optical package having a photonic die and a thermal block beneath the photonic die, according to one embodiment.

[0030] [Figure 15C] This is a cross-sectional view of an optical package having a photonic die and a plurality of thermal pillars below the photonic die, according to one embodiment.

[0031] [Figure 16] This is a schematic diagram of a computing device constructed according to one embodiment. [Modes for carrying out the invention]

[0032] This specification describes interconnect architectures for high-bandwidth optical interconnects in various embodiments. In the following description, various aspects of exemplary implementations are described using terminology commonly used by those skilled in the art, in order to convey much of this research to others skilled in the art. However, it will be apparent to those skilled in the art that the invention may be carried out in only some of the embodiments described. For illustrative purposes, certain numbers, materials, and configurations are described to provide a deeper understanding of the exemplary implementations. However, it will be apparent to those skilled in the art that the invention may be carried out without using specific details. In other examples, well-known features are omitted or simplified so as not to obscure the exemplary implementations.

[0033] Various operations are described sequentially as several distinct operations in the manner that is most helpful in understanding the present invention; however, the order of the descriptions should not be interpreted as meaning that these operations are not necessarily dependent on an order. In particular, these operations do not need to be performed in the order they are presented.

[0034] Figure 1A is a plan view of the optical package 100, providing context for the embodiments disclosed herein. As shown, the package substrate 101 provides a base for arranging the compute die 105 and a plurality of photonic dies 110. The compute die 105 is coupled to the photonic dies 110 by a bridge 115. As shown, the package substrate 101 has an H-shaped footprint to allow the photonic dies 110 to overhang the edges of the package substrate 101. In Figure 1A, an integrated heat spreader (IHS) 107 is shown on the outer periphery of the package substrate 101. It should be noted that only the legs of the IHS 107 are shown so as not to block the view of the compute die 105 and photonic dies 110 below. As shown in the cross-sectional view in Figure 1B, the optical interconnect 111 and connector 112 are attached to the photonic dies 110 from below by V-grooves. As mentioned above, the need for the V-groove attachment increases the complexity of assembly.

[0035] Accordingly, embodiments disclosed herein provide an embedded optical waveguide for transmitting an optical signal from a photonics die to a fiber optic connector that can be attached laterally to a package. Therefore, no overhanging die is required. This allows the use of standard packaging process operations for assembling the optical package. The optical waveguide has a first end below the photonics die and a second end at the edge of the package substrate. The inclined surface at the first end of the optical waveguide reflects light, optically coupling the optical waveguide to the bottom surface of the photonics die. Therefore, a V-groove is not required in the photonics die for optically coupling the fiber to the photonics die.

[0036] In some embodiments, the optical waveguide is a separate waveguide embedded within the package substrate. In other embodiments, the optical waveguide may be fabricated during the manufacturing process flow of the package substrate. Various packaging architectures may be used to fabricate the embedded optical waveguide. In one embodiment, the optical waveguide is embedded within an organic package substrate. In another embodiment, the optical waveguide is embedded within a glass patch provided on top of the organic package substrate. In yet another embodiment, the optical waveguide is embedded within a package substrate comprising multiple glass layers.

[0037] Referring now to Figure 2A, a plan view of an optical package 200 according to one embodiment is shown. In one embodiment, the optical package 200 comprises a package substrate 201. The package substrate 201 may be an organic package substrate. The package substrate 201 may have a substantially rectangular footprint. A rectangular footprint is possible because the photonic die 210 does not need to overhang the package substrate 201, as shown in the H-type package substrate 101 in Figure 1A. In one embodiment, a compute die 205 is also provided on the package substrate 201. The compute die 205 may be any suitable die, such as a processor, graphics processor, system-on-a-chip (SoC), or similar. In one embodiment, the photonic die 210 enables the conversion between optical signals and electrical signals. In the exemplary embodiment, four photonic dies 210 are shown, but it should be understood that any number of photonic dies 210 may be included in the optical package 200.

[0038] In one embodiment, the IHS207 surrounds the outer periphery of the package substrate 201. To avoid obscuring the underlying components, the IHS207 in Figure 2A is shown without a lid. However, it should be understood that the lid portion of the IHS207 is thermally bonded to the upper surfaces of the compute die 205 and the photonics die 210.

[0039] In one embodiment, the optical interconnect 211 and connector 212 are coupled to the package substrate 201. In some embodiments, the optical interconnect 211 may include an optical fiber cable. The optical interconnect 211 is mounted on the edge surface of the package substrate 201. As shown in more detail below, the optical interconnect 211 is mounted to the package substrate 201 and optically coupled to an optical waveguide (not shown in Figure 2A) embedded in the package substrate 201.

[0040] Referring here to Figure 2B, a cross-sectional view of an optical package 200 according to one embodiment is shown. In one embodiment, the optical package comprises a package substrate 201 having a solder resist layer 202 on the package substrate 201. As shown, the compute die 205 and the photonic die 210 are connected to the package substrate by an interconnect 236. The interconnect 236 may be any preferred interconnect architecture, such as a first-level interconnect (FLI) architecture. In one embodiment, the photonic die 210 is entirely within the footprint of the package substrate 201; that is, the photonic die 210 has no overhang over the edges of the package substrate 201. In one embodiment, the interconnect 236 may be surrounded by an underfill 234.

[0041] In one embodiment, the photonic die 210 is communicatively coupled to the compute die 205 by an embedded bridge 215. The bridge 215 is embedded in the package substrate 201 and electrically coupled to the interconnect 236 by conductive features that pass through the solder resist layer 202. As shown in Figure 2B, an IHS 207 is attached to the package substrate 201 and thermally coupled to the upper surfaces of the compute die 205 and the photonic die 210. For example, a thermal interface material (TIM) (not shown) may be provided between the IHS 207 and the upper surfaces of the compute die 205 and the photonic die 210.

[0042] In one embodiment, the optical waveguide 230 is embedded in the package substrate 201. As used herein, an embedded component may refer to a component that is at least partially surrounded by another layer. For example, the bottom and side walls of the optical waveguide 230 are covered by the package substrate 201. In some embodiments, the embedded feature may have an uncovered top surface. For example, the top surface of the optical waveguide 230 is covered by solder resist 202 instead of the package substrate 201. The optical waveguide 230 may still be referred to as embedded within the package substrate 201 even if it does not have a top surface covered by the package substrate 201.

[0043] In one embodiment, the optical waveguide 230 may have a first end 231 and a second end 232. The first end 231 may be located beneath the photonic die 210. That is, the first end 231 is located beneath the photonic die 210 and within the footprint of the photonic die 210. The second end 232 may be located on the edge of the package substrate 201. An optical interconnect (not shown) may be attached to the edge of the package substrate 201 so as to be optically coupled to the optical waveguide 230.

[0044] In one embodiment, the first end 231 of the optical waveguide 230 may have an inclined surface. The inclined surface allows the optical signal to be coupled to the bottom surface of the photonic die 210. In particular, an optical path 221 passing through a solder resist layer 202 may be provided above the first end 231, allowing the optical signal to pass through the solder resist 202. In one embodiment, the optical path 221 may include a cladding layer 223 and a high refractive index core 222. In one embodiment, it is possible to prevent the underfill 234 from being ejected onto the optical path 221. For example, a dam 235 or similar can prevent the underfill 234 from being ejected between the optical path 221 and the underside of the photonic die 210.

[0045] In one embodiment, the optical waveguide 230 may include a high refractive index material. For example, the optical waveguide 230 may include polyimide, polyalkane, polycyanate, diazobenzoquinone, metal-centered (e.g., Fe, Al, Cu, etc.) dendritic polymer, high-density polycarbonate, polytifen, polythiadiazole, or polysulfone. In one embodiment, the optical waveguide 230 is in direct contact with the package substrate 201. That is, in some embodiments, there is no cladding layer on the optical waveguide 230. However, in other embodiments, a cladding layer (not shown) may be provided between the optical waveguide 230 and the package substrate 201. For example, a silver cladding layer or similar may be used to improve transmission efficiency.

[0046] Referring here to Figure 2C, a cross-sectional view of the optical package 200 according to an additional embodiment is shown. The optical package 200 may be substantially similar to the optical package 200 in Figure 2B, except that various lenses 237, 238, and 213 are added. Lens 237 may be provided on the optical path 221 to improve the efficiency of signal transmission between the photonic die 210 and the optical path 221. Additionally, a connector 247 having lenses 238 and 213 may be used to improve optical coupling between the second end 232 of the optical waveguide 230 and the optical interconnect 211 (such as an optical fiber cable).

[0047] Referring here to Figure 2D, a cross-sectional view of the optical package 200 according to an additional embodiment is shown. The optical package 200 in Figure 2D may be substantially similar to the optical package 200 in Figure 2B, except that a separate optical waveguide 240 is embedded in the package substrate 201. The optical waveguide 230 may be fabricated during the assembly of the optical package 200, while the optical waveguide 240 may be a separate optical waveguide inserted into the package substrate 201 using a pick-and-place process. The optical waveguide 240 may be manufactured to have improved optical transmission. For example, the optical waveguide 240 may include cladding 242 and a core 241. Additionally, a mirror 243 may be provided at the first end 231 to improve the transmission efficiency between the optical path 221 and the optical waveguide 240. The mirror 243 may also be inserted into the package substrate 201 using a pick-and-place process. In some embodiments, the mirror 243 may be integrated into the optical waveguide 240, resulting in only a single pick-and-place step being required.

[0048] Referring now to Figures 3A to 3H, a series of cross-sectional views illustrating the steps for assembling an optical package according to one embodiment are shown. The assembly shown in Figures 3A to 3H may result in the formation of an optical package substantially similar to the optical package 200 in Figure 2B.

[0049] Referring now to Figure 3A, a cross-sectional view of a package substrate 301 according to one embodiment is shown. The package substrate 301 may include a plurality of laminated organic layers. For clarity, conductive routing within the package substrate 301 is omitted. However, it should be understood that conductive routing (e.g., traces, vias, pads, etc.) may be provided within the package substrate 301 to provide electrical coupling between the top surface and the bottom surface of the package substrate 301.

[0050] In one embodiment, the bridge 315 may be embedded in the package substrate 301. The bridge 315 may enable high-density routing used to electrically couple the compute die to the photonic die in subsequent processing operations. In a particular embodiment, the bridge 315 is a silicon bridge having thin wire / space conductive routing provided on it. Vias 351 may provide an electrical connection between the top surface of the package substrate 301 and the bridge 315.

[0051] Referring now to Figure 3B, a cross-sectional view of the package substrate 301 after a trench 352 has been formed on the upper surface of the package substrate according to one embodiment. The trench 352 may extend to the edge of the package substrate 301. In one embodiment, the trench 352 may be formed using a laser drilling process, such as a CO2 laser drilling process. In some embodiments, dry etching is performed to clean the surface of the trench 352. For example, a fluorine-based gas used in the dry etching process may be sufficient to provide a smooth surface that minimizes light scattering. For example, the surface of the trench 352 may have a surface roughness of about 70 nm RMS or less.

[0052] In one embodiment, the trench 352 may include a tapered end 353. The tapered end 353 may have an angle of about 45°. Thus, the tapered end 353 can be used to reflect light perpendicular to the direction of the channel 352 in order to couple an optical signal to a photonic die covering it, which is provided in a subsequent processing operation.

[0053] Referring here to Figure 3C, a cross-sectional view of the package substrate 301 after an optical waveguide 330 has been formed in the trench 352 is shown according to one embodiment. The optical waveguide 330 may include a high refractive index material. The high refractive index material may be, but is not limited to, a paste-printable epoxy resin that can be filled into the trench 352, such as polyimide, polyalkane, polycyanate, diazobenzoquinone, metal-centered (e.g., iron, aluminum, copper, etc.) dendritic polymer, high-density polycarbonate, polytifen, polythiadiazole, or polysulfone.

[0054] In exemplary embodiments, the optical waveguide 330 is in direct contact with the package substrate 301. Such embodiments are made possible by the ability to form a smooth surface (e.g., 70 nm RMS or less) in the trench 352. However, in some embodiments, a thin cladding layer (such as silver) may be formed on the surface of the trench 352 to provide improved efficiency. For example, an immersion silver plating process may be used before the deposition of epoxy resin to form the optical waveguide 330. Such embodiments may allow internal total internal reflection over a wide wavelength range, resulting in very low attenuation. After the deposition of the optical waveguide 330, the surface of the package substrate 301 is polished to remove excess resin outside the trench 352. In one embodiment, the optical waveguide 330 includes a first end 331 and a second end 332. The first end 331 abuts against a tapered surface 353, and the second end 332 is at the edge of the package substrate 301.

[0055] Referring to Figure 3D, a cross-sectional view of the package substrate 301 is shown, according to one embodiment, after a solder resist layer 302 has been provided on the upper surface of the package substrate 301. In one embodiment, an optical path 321 is provided through the solder resist layer 302. The optical path 321 can be formed using a laser hole processing process. In one embodiment, the optical path 321 is provided on the first end 331 of the optical waveguide 330.

[0056] Referring here to Figure 3E, a cross-sectional view of the package substrate 301 after the optical path 321 has been filled is shown according to one embodiment. In one embodiment, the optical path 321 is filled with cladding 323 and core 322. The cladding 323 ensures low roughness (e.g., 70 nm RMS or less), reduces light scattering, and enables low optical signal loss. In one embodiment, the cladding 323 and core 322 materials may include, but are not limited to, polyimide, polyalkane, polycyanate, polyacrylate, polysiloxane, and low-density versions of thin metal layers such as copper, silver, gold, and aluminum. Additionally, polyperfluorocarbon polymers may be used as cladding 323.

[0057] Referring now to Figure 3F, a cross-sectional view of the package substrate 301 after the bridge 315 interconnect has been formed according to one embodiment is shown. In one embodiment, the interconnect may include vias 354 through the solder resist layer 302 and pads 353 on the solder resist layer 302. In one embodiment, the optical path 321 is protected by a mask layer (not shown) during the formation of the bridge 315 interconnect.

[0058] Referring now to Figure 3G, a cross-sectional view of the package substrate 301 is shown after the compute die 305 and photonic die 310 have been mounted on the package substrate 301 according to one embodiment. In one embodiment, the compute die 305 and photonic die 310 are mounted by FLI 336. In one embodiment, underfill 334 is ejected around the interconnect 336. A dam or similar may prevent the flow of underfill 334 over the optical path 321. Thus, an optical path is provided from the edge of the package substrate 301 to the bottom surface of the photonic die 310.

[0059] As shown, the photonic die 310 is entirely within the footprint of the underlying package substrate 301. That is, the photonic die 310 does not have any overhang over the edges of the package substrate 301. In one embodiment, the photonic die 310 may be positioned such that the first end 331 of the optical waveguide 330 is below (and within its footprint) the photonic die 310. Thus, the optical path 321 provides a vertical path from the optical waveguide 330 to the bottom surface of the photonic die 310. Therefore, the photonic die 310 does not require a V-groove connection.

[0060] Referring here to Figure 3H, a cross-sectional view of the package substrate 301 after the IHS 307 has been mounted on the package substrate 301 is shown according to one embodiment. In some embodiments, the IHS 307 may be thermally coupled to the compute die 305 and the photonics die 310 by a TIM (not shown). In one embodiment, an optical engine (not shown) may then be coupled to the second end 332 of the optical waveguide 330 using an optical connector from the side of the package substrate 301.

[0061] Referring to Figures 4A to 4C, a cross-sectional view of an operation for forming an optical package similar to the optical package 200 in Figure 2C, according to one embodiment, is shown. The processing of the optical package prior to Figure 4A is substantially the same as the processing operation shown in Figures 3A to 3F.

[0062] Referring now to Figure 4A, a cross-sectional view of a package substrate 401 according to one embodiment is shown. The package substrate 401 may include an embedded bridge 415 bonded to the upper surface of the solder resist layer 402 by pads 451, vias 452, and pads 453. In one embodiment, an embedded optical waveguide 430 having a first end 431 and a second end 432 is provided within the package substrate 401. An optical path 421 is provided above the first end 431 of the optical waveguide 430.

[0063] As shown in Figure 4A, a lens 437 may be provided above the optical path 421 of each optical waveguide 430. The lens 437 may be positioned using a pick-and-place process. By using the lens 437 above the optical path 421, optical coupling with the photonic die later positioned above the first end of the optical waveguide 430 may be improved.

[0064] Referring now to Figure 4B, a cross-sectional view of the package substrate 401 is shown after the compute die 405, photonic die 410, and IHS 407 have been mounted on the package substrate 401 according to one embodiment. As shown, the compute die 405 and photonic die 410 can be mounted on the pad 453 by FLI 436. FLI 436 can be surrounded by underfill 434. A dam (not shown) or similar can block the underfill 434 from flowing onto the lens 437. Thus, an optical path is provided from the edge of the package substrate 401 to the bottom surface of the photonic die 410.

[0065] Referring now to Figure 4C, a cross-sectional view of the package substrate 401 is shown after the connector 440 is attached to the edge of the package substrate 401 above the second end 432 of the optical waveguide 430, according to one embodiment. In one embodiment, the connector 440 may include a lens 438 just above the second end 432 of the optical waveguide 430. A second lens 413 may be provided adjacent to an optical interconnect 411, such as an optical fiber cable. This improves the optical transmission efficiency to the optical waveguide 430.

[0066] Referring now to Figures 5A to 5D, a series of cross-sectional views are shown illustrating the steps for forming an optical package having a separate embedded optical waveguide according to one embodiment. The resulting optical package in Figure 5D may be substantially similar to the optical package 200 in Figure 2D.

[0067] Referring now to Figure 5A, a cross-sectional view of a package substrate 501 according to one embodiment is shown. In one embodiment, the package substrate 501 includes a bridge 515 embedded in the package substrate 501. Vias 551 provide electrical connections from the bridge 515 to the upper surface of the package substrate 501. In one embodiment, trenches 552 are formed on the upper surface of the package substrate 501. Each trench 552 extends along the edge of the package substrate 501. In one embodiment, the trenches 552 may have a uniform depth along their length; that is, they may not have tapered ends as in the embodiments described above. However, in other embodiments, the trenches 552 may have tapered ends.

[0068] Referring here to Figure 5B, a cross-sectional view of the package substrate 501 is shown after the placement of a solder resist layer 502 having separate optical waveguides 540 and optical paths 521 according to one embodiment. In one embodiment, the separate optical waveguides 540 can be inserted into the trench 552 using a pick-and-place tool or similar. Since the optical waveguides 540 are separate components, they can be optimized to provide enhanced optical transmission efficiency. For example, the separate optical waveguides 540 may include cladding 542 and a core 541. In one embodiment, the first end 531 is tapered and may be adjacent to a mirror 543. The mirror 543 may also be a separate component picked and placed in the trench 552. In other embodiments, the mirror 543 may be formed as part of the separate optical waveguide 540. The second end 532 of the separate optical waveguide 540 may be at the edge of the package substrate 501. Since a pick-and-place process is used, paste printing and polishing of high refractive index materials can be omitted, simplifying the processing operation. In one embodiment, an optical path 521 may be provided on the first end 531 of a separate optical waveguide 540, passing through a solder resist layer 502. The optical path 521 may include cladding and a core similar to those described above.

[0069] Referring now to Figure 5C, a cross-sectional view of the package substrate 501 after the compute die 505 and photonic die 510 have been mounted on the package substrate 501 according to one embodiment. In one embodiment, the compute die 505 and photonic die 510 may be mounted on an FLI 536 surrounded by an underfill 534. A dam (not shown) or similar may be used to prevent the underfill 534 from flowing over the optical path 521. As shown, the first end 531 of a separate optical waveguide 540 is located below (within the footprint of) the photonic die 510. Thus, an optical path is provided from the edge of the package substrate 501 to the bottom surface of the photonic die 510.

[0070] Referring here to Figure 5D, a cross-sectional view of the package substrate 501 after the IHS 507 has been mounted on the package substrate 501 according to one embodiment. In one embodiment, the IHS 507 may be thermally coupled to the compute die 505 and the photonic die 510 by a TIM (not shown). Figures 5A to 5D show a process that does not depend on additional lenses (similar to the embodiments shown in Figures 4A to 4C), although it is understood that similar lenses may be optionally included to improve efficiency in the embodiments described with respect to Figures 5A to 5D.

[0071] In the embodiments described above, the optical waveguide is embedded in an organic package substrate. It is understood that the organic substrate may be prone to warping or other deformation. Therefore, the alignment of the optical path with respect to the photonic die may not be as precise as desired. Accordingly, additional embodiments disclosed herein include the use of a substrate with greater dimensional stability to provide improved alignment. In one embodiment, the optical waveguide is embedded in a glass material. In certain embodiments, the optical waveguide is provided in a glass patch bonded to an organic package substrate, or the optical waveguide is provided in a package substrate composed of multiple laminated glass layers.

[0072] Referring to Figures 6A to 8F, a series of diagrams illustrating optical packages utilizing glass patches are shown. The use of glass patches provides dimensional stability while still allowing routing on top of conventional organic package substrates. Thus, manufacturing complexity is simplified while still allowing the dimensional stability provided by the glass substrate.

[0073] Referring now to Figure 6A, a plan view of an optical package 600 according to an additional embodiment is shown. The optical package 600 includes a package substrate 601. The package substrate 601 may be a conventional organic package substrate 601. A glass patch 660 is provided on the package substrate 601. In one embodiment, a compute die 605 and a photonic die 610 are mounted on the glass patch 660. In one embodiment, an IHS 607 is mounted on the glass patch 660 and surrounds the compute die 605 and the photonic die 610. To avoid obscuring the underlying features, the cover portion of the IHS 607 is omitted.

[0074] In one embodiment, the optical interconnect 611 and connector 612 are coupled to the edge of the glass patch 660. The optical interconnect 611 is mounted on an embedded optical waveguide (not shown in Figure 6A) that provides optical coupling with the photonic die 610.

[0075] Referring now to Figure 6B, a cross-sectional view of an optical package 600 according to one embodiment is shown. In one embodiment, the optical package 600 includes a package substrate 601. The package substrate 601 may be an organic package substrate 601 having a core 604. However, in some embodiments, the package substrate 601 may not have a core. Conductive routing in the package substrate 601 and core 604 has been omitted so as not to obscure the embodiments disclosed herein. However, it is understood that the package substrate 601 includes conductive features such as pads, traces, vias and the like.

[0076] The package substrate 601 may be electrically coupled to the glass patch 660 by an interconnect 666. In one embodiment, the interconnect 666 may be coupled to a glass through-via (TGV) 665 by vias through a solder resist 664. The TGV 665 provides an electrical connection from the underside of the glass substrate 661 to the upper side of the glass substrate 661. In an exemplary embodiment, the TGV 665 is shown with substantially vertical sidewalls. However, in some embodiments, it is understood that the TGV 665 may have tapered sidewalls and form an hourglass shape. In one embodiment, the upper side of the TGV 665 may be electrically coupled to the compute die 605 by routing through a build-up layer 662 and a solder resist layer 663. FLI 636 may provide part of the connection between the compute die 605 and the TGV 665. In one embodiment, FLI 636 may be surrounded by an underfill 634.

[0077] In one embodiment, the compute die 605 may be communicatively coupled to the photonic die 610 by a bridge 615 embedded in the glass substrate 661. The bridge 615 may be, for example, silicon. The bridge 615 enables high-density routing of electrical signals between the photonic die 610 and the compute die 605. In one embodiment, via pads, traces, and the like may provide electrical routing through the build-up layer 662 and the solder resist layer 663.

[0078] In one embodiment, the photonic die 610 may be entirely within the footprint of the glass patch 660; that is, the photonic die 610 may not overhang the edges of the glass patch 660. Additionally, the photonic die 610 may be positioned above the first end 631 of the embedded optical waveguide 630. An optical path 621 through the build-up layer 662 and the solder resist layer 663 may provide optical coupling between the optical waveguide 630 and the photonic die 610. In one embodiment, the optical path 621 may include cladding 623 and a core 622 to improve optical transmission efficiency.

[0079] In one embodiment, each optical waveguide 630 has a first end 631 located below (within the footprint of) one of the photonic die 610s, and a second end 632 at the edge of the glass substrate 661. To reflect optical signals to and from the photonic die 610 positioned above, the first end 631 of the optical waveguide 630 may be tapered. For example, the tapered first end 631 may have an angle of about 45°. In one embodiment, the optical waveguide 630 may be a high refractive index material such as polyimide, polyalkane, polycyanate, diazobenzoquinone, metal-centered (e.g., iron, aluminum, copper, etc.) dendritic polymer, high-density polycarbonate, polytifene, polythiadiazole, or polysulfone, but is not limited to these. In an exemplary embodiment, the optical waveguide 630 is in direct contact with the glass substrate 661. In another embodiment, a cladding layer (e.g., silver) may be provided between the glass substrate 661 and the optical waveguide 630.

[0080] In one embodiment, the optical waveguide 630 is considered to be embedded in the glass substrate 661. That is, the glass substrate 661 may surround the bottom and side walls of the optical waveguide 630 (excluding the second end 632). The top surface of the optical waveguide 630 may be at least partially covered by a dielectric build-up layer 662 and / or a solder resist layer 663.

[0081] In exemplary embodiments, optical coupling from optical path 621 to photonic die 610 is provided through air. Due to the small distance, optical loss is minimal. However, in some embodiments, a lens may be provided above optical path 621, as in the embodiment shown in Figure 2C. A connector with a lens may also be provided at the second end 632 of optical waveguide 630, as in the embodiment in Figure 2C. In one embodiment, a dam (not shown) may be used to prevent underfill 634 from spreading above optical path 621. In one embodiment, optical waveguide 630 may also be replaced by a separate optical waveguide, as in the embodiment in Figure 2D.

[0082] Referring here to Figure 6C, a cross-sectional view of a glass patch 660 according to an additional embodiment is shown. The glass patch 660 may be coupled to an organic package substrate (not shown) similar to the embodiment shown in Figure 6B. Furthermore, the glass patch 660 in Figure 6C may be substantially similar to the glass patch 660 in Figure 6B, except for the interconnect method between the photonic die 610 and the compute die 605. Instead of using an embedded bridge architecture, the embodiment in Figure 6C utilizes a high-density routing stack 667. Due to the use of the glass substrate 661, it is possible to provide high-density routing using various patterning operations such as lithographically defined vias and / or zero-miss alignment via architectures. In particular, it should be noted that in some embodiments, as is typical in lithographically defined routing architectures, the vias in the high-density routing stack 667 have substantially vertical sidewalls. In certain embodiments, electrical features 668 provide routing between the photonic die 610 and the compute die 605.

[0083] Referring now to Figures 7A to 7I, a series of cross-sectional views are shown illustrating the process for forming a glass patch similar to the glass patch 660 in Figure 6B, according to one embodiment. Referring now to Figure 7A, a cross-sectional view of a glass substrate 761 is shown according to one embodiment. In one embodiment, the glass substrate 761 may have a thickness between approximately 300 μm and approximately 600 μm. Although shown as a single unit, it is understood that panels having multiple units may be formed substantially parallel to each other.

[0084] The TGV765 may be provided across the entire thickness of the glass substrate 761. As shown in Figure 7A, the TGV765 may have an hourglass-shaped profile or vertical profile sidewalls. The TGV765 may be formed using a laser drilling or etching process and subsequently filled (e.g., with copper) using a standard plating process. Excess copper may be removed in a polishing process. In one embodiment, the pad 771 is then provided on the TGV765 on the upper surface of the glass substrate 761 using a standard semi-additive process (SAP).

[0085] Referring here to Figure 7B, a cross-sectional view of the optical waveguide 730 after the bridge 715 has been embedded and the glass substrate 761 has been formed is shown according to one embodiment. In one embodiment, the cavity of the bridge 715 is formed using a laser and / or etching process, and the bridge 715 is set in the cavity. In one embodiment, the trench of the optical waveguide 730 may be formed using laser drilling, dry etching, and / or wet etching processes. As a result of the process of forming the trench of the optical waveguide 730, an inclined first end 731 may be formed. The inclined first end 731 may be about 45° in order to allow the optical signal to be routed out from above through the second end 732 of the optical waveguide 730. In an alternative embodiment, a mirror with an inclined surface may be placed at the first end 731 of the optical waveguide 730. In one embodiment, as a result of the process used to form the channel for the optical waveguide 730, a smooth surface (e.g., less than about 70 nm RMS) may be produced to minimize optical scattering and improve transmission efficiency.

[0086] In one embodiment, the optical waveguide 730 may be formed using a paste-printable high refractive index epoxy resin such as polyimide, polyalkane, polycyanate, diazobenzoquinone, metal-centered (e.g., iron, aluminum, copper, etc.) dendrite polymer, high-density polycarbonate, polytifen, polythiadiazole, or polysulfone, but is not limited to these. In one embodiment, the optical waveguide 730 is in direct contact with the glass substrate 761. However, in other embodiments, a cladding layer (e.g., silver) may be provided between the optical waveguide 730 and the glass substrate 761 to further improve efficiency by enabling internal total internal reflection over a wide range of wavelengths, resulting in very low attenuation. In some embodiments, a polishing step may be required to remove excess resin from the top surface of the glass substrate 761. In such cases, the pad 771 may be formed after the polishing step. Additionally, although an internal optical waveguide 730 is illustrated in Figure 7B, it is understood that a pre-existing optical waveguide 730 may also be inserted into a trench formed in the glass substrate 761. Such embodiments may make it possible to achieve even higher efficiency.

[0087] Referring here to Figure 7C, a cross-sectional view of the glass substrate 761 after the build-up layer 762 has been placed on the glass substrate 761 and patterned according to one embodiment. In one embodiment, the build-up layer 762 may be any typical build-up material having desired properties (e.g., low loss, low dielectric constant). The build-up layer 762 may be placed on the glass substrate 761 using a lamination process or similar. In one embodiment, the build-up layer 762 is patterned using a laser hole-making process. The laser hole-making process may include a first laser (e.g., a CO2 laser) for forming larger vias to the pad 771 and a second laser (e.g., a UV laser) for forming smaller vias to the pad of the bridge 715. The optical path 721 may also be holed above the first end 731 of the optical waveguide 730. Although shown substantially vertically, it is understood that the sidewalls of the optical path 721 may be tapered, as is common in laser hole-making apertures.

[0088] Referring here to Figure 7D, a cross-sectional view of the glass substrate 761 after the via openings have been filled with conductive material is shown according to one embodiment. In one embodiment, conductive vias 772 and pads 773 can be formed using a typical plating process. For example, after a seed layer is formed, plating and patterning may be performed to define the pads 773. Then, the remaining portion of the seed layer may be removed by flash etching. In one embodiment, the optical path 721 may be covered by a mask layer during the formation of the vias 772 and pads 773. Alternatively, the optical path 721 may be drilled after the formation of the vias 772 and pads 773.

[0089] Referring now to Figure 7E, a cross-sectional view of the glass substrate 761 after a solder resist layer 763 has been formed on the build-up layer 762 is shown according to one embodiment. In one embodiment, the solder resist layer 763 may be patterned and plated with a conductive material to form vias 774 and pads 775. Patterning and plating processes may be standard processes used in electronic packaging applications.

[0090] In one embodiment, after the formation of vias 774 and pads 775, an optical path 721 may be formed through the solder resist layer 763. In an exemplary embodiment, the optical path 721 is shown having openings in the build-up layer 762 and the solder resist layer 763 that are perfectly aligned with each other. However, there may be some misalignment between portions of the optical path 721 in the different layers. Additionally, the sidewalls of the optical path 721 in each of the build-up layer 762 and the solder resist layer 763 may have tapered sidewalls common to the laser-drilled holes.

[0091] Referring here to Figure 7F, a cross-sectional view of a glass substrate after the optical path 721 has been filled is shown according to one embodiment. In one embodiment, the optical path 721 is filled with resin using a dispenser. The resin can be any conventional epoxy resin having an inorganic filler. The filled resin is subsequently drilled, filled with cladding 723 and core 722, and then cured and polished. The cladding 723 ensures a low roughness (e.g., about 70 nm RMS or less) to minimize light scattering. Standard cladding 723 and core 722 materials can be used, but are not limited to these, such as polyimide, polyalkane, polycyanate, polyacrylate, polysiloxane, and low-density versions of thin metal layers such as copper, silver, gold, and aluminum. Additionally, polyperfluorocarbon polymers can be used as cladding 723.

[0092] Referring here to Figure 7G, a cross-sectional view of the glass substrate 761 after the compute die 705 and photonic die 710 have been mounted according to one embodiment. In one embodiment, the compute die 705 and photonic die 710 may be mounted using FLI 736. In one embodiment, FLI 736 is surrounded by underfill 734. A dam (not shown) or similar may prevent the underfill 734 from flowing over the optical path 721. The photonic die 710 may be communicatively coupled to the compute die 705 by an embedded bridge 715 and conductive features on top of the build-up layer 762 and solder resist layer 763.

[0093] As shown in Figure 7G, the photonic die 710 is entirely within the footprint of the glass substrate 761. That is, there is no portion of the photonic die 710 that extends beyond the edge of the glass substrate 761 and overhangs. Rather, optical coupling from the photonic die 710 to the edge of the glass substrate 761 is provided by the optical path 721 and the optical waveguide 730.

[0094] Referring now to Figure 7H, a cross-sectional view of the glass substrate 761 after backside processing is performed according to one embodiment. In one embodiment, the structure can be inverted and placed on a carrier (not shown) to expose the back surface of the glass substrate 761. A solder resist layer 764 is provided on the bottom surface of the glass substrate 761. Vias 776 and pads 777 can then be provided through and on the solder resist layer 764.

[0095] Referring here to Figure 7I, a cross-sectional view of the glass substrate 761 after the IHS 707 has been mounted on the photonic die 710 and compute die 705 according to one embodiment. In one embodiment, the IHS 707 may be thermally bonded to the photonic die 710 and compute die 705 by TIM (not shown). In some embodiments, the legs of the IHS 707 may be connected to a solder resist 763. In one embodiment, the glass patch may then be attached to an organic package substrate similar to that shown in Figure 6B.

[0096] Referring now to Figures 8A to 8F, a series of cross-sectional views are shown illustrating the process for forming a glass patch together with a high-density routing stack according to one embodiment. The glass patch in Figures 8A to 8F may be substantially the same as the glass patch shown and described with respect to Figure 6C.

[0097] Referring now to Figure 8A, a cross-sectional view of a glass substrate 861 according to one embodiment is shown. In one embodiment, the glass substrate 861 has a thickness between approximately 200 μm and approximately 600 μm. The TGV865 can pass through the entire thickness of the glass substrate 861. In an exemplary embodiment, the TGV865 is shown having substantially vertical sidewalls. In other embodiments, the TGV865 may have an hourglass shape.

[0098] In one embodiment, the optical waveguide 830 is embedded in a glass substrate 861. In one embodiment, trenches in the optical waveguide 830 may be formed using laser drilling, dry etching, and / or wet etching processes. As a result of the process of forming the trenches in the optical waveguide 830, an inclined first end 831 may be formed. The inclined first end 831 may be about 45° in order to allow optical signals to be routed out from above through a second end 832 of the optical waveguide 830. In an alternative embodiment, a mirror having an inclined surface may be placed at the first end 831 of the optical waveguide 830. In one embodiment, as a result of the process used to form a channel for the optical waveguide 830, a smooth surface (e.g., less than about 70 nm RMS) may be produced to minimize optical scattering and improve transmission efficiency.

[0099] In one embodiment, the optical waveguide 830 may be formed using a paste-printable high refractive index epoxy resin such as polyimide, polyalkane, polycyanate, diazobenzoquinone, metal-centered (e.g., iron, aluminum, copper, etc.) dendrite polymer, high-density polycarbonate, polytifen, polythiadiazole, or polysulfone, but is not limited to these. In one embodiment, the optical waveguide 830 is in direct contact with the glass substrate 861. However, in other embodiments, a cladding layer (e.g., silver) may be provided between the optical waveguide 830 and the glass substrate 861 to further improve efficiency by enabling internal total internal reflection over a wide range of wavelengths, resulting in very low attenuation. In some embodiments, a polishing step may be required to remove excess resin from the top surface of the glass substrate 861. Additionally, although the built-in optical waveguide 830 is described in Figure 8A, it is understood that a pre-existing optical waveguide may also be inserted into a trench formed in the glass substrate 861. Such embodiments may make it possible to obtain even higher efficiency.

[0100] Referring to Figure 8B, a cross-sectional view of the glass substrate 861 after a high-density routing stack 867 has been placed on the glass substrate 861 according to one embodiment. Because glass has high dimensional stability, finer patterning can be achieved compared to organic substrates. Therefore, the high-density routing stack 867 can be used to provide routing 868 between the photonic die and the compute die. In one embodiment, the routing 868 is formed from a high-precision photosensitive dielectric and can be produced using a self-aligned via method or a zero-miss alignment via method. As a result of using such via fabrication processes, vias with substantially vertical sidewalls can be produced, in contrast to the tapered sidewalls typical of laser drilling processes.

[0101] In one embodiment, the optical path 821 may be formed through a high-density routing stack 867. The optical path 821 may be formed using a laser drilling process or by using lithography. In one embodiment, the optical path 821 is provided above the first end 831 of the optical waveguide 830.

[0102] Referring here to Figure 8C, a cross-sectional view of the glass substrate 861 after the optical path 821 has been filled is shown according to one embodiment. In one embodiment, the optical path 821 is filled with resin using a dispenser. The resin can be any conventional epoxy resin having an inorganic filler. The filled resin is subsequently drilled, filled with cladding 823 and core 822, and then cured and polished. The cladding 823 ensures a low roughness (e.g., about 70 nm RMS or less) to minimize light scattering. Standard cladding 823 and core 822 materials can be used, but are not limited to these, such as polyimide, polyalkane, polycyanate, polyacrylate, polysiloxane, and low-density versions of thin metal layers such as copper, silver, gold, and aluminum. Additionally, polyperfluorocarbon polymers can be used as cladding 823.

[0103] Referring here to Figure 8D, a cross-sectional view of the glass substrate 861 after the compute die 805 and photonic die 810 have been mounted according to one embodiment. In one embodiment, the compute die 805 and photonic die 810 may be mounted using FLI 836. In one embodiment, FLI 836 is surrounded by underfill 834. A dam (not shown) or similar may prevent the underfill 834 from flowing over the optical path 821. The photonic die 810 may be communicatively coupled to the compute die 805 by routing 868 in a high-density routing stack 867.

[0104] As shown in Figure 8D, the photonic die 810 is entirely within the footprint of the glass substrate 861. That is, there is no portion of the photonic die 810 that extends beyond the edge of the glass substrate 861 and overhangs. Rather, optical coupling from the photonic die 810 to the edge of the glass substrate 861 is provided by the optical path 821 and the optical waveguide 830.

[0105] Referring now to Figure 8E, a cross-sectional view of the glass substrate 861 after backside processing is performed according to one embodiment. In one embodiment, the structure can be inverted and placed on a carrier (not shown) to expose the back surface of the glass substrate 861. A solder resist layer 864 is provided on the bottom surface of the glass substrate 861. Vias 876 and pads 877 can then be provided through and on the solder resist layer 864.

[0106] Referring now to Figure 8F, a cross-sectional view of the glass substrate 861 after the IHS807 has been mounted on the photonic die 810 and compute die 805 according to one embodiment. In one embodiment, the IHS807 may be thermally bonded to the photonic die 810 and compute die 805 by a TIM (not shown). In some embodiments, the legs of the IHS807 may be connected to a high-density routing layer 867. In one embodiment, the glass patch may then be attached to an organic package substrate similar to that shown in Figure 6B.

[0107] Referring now to Figure 9A, a plan view of an optical package 900 according to one embodiment is shown. In one embodiment, the optical package 900 comprises a package substrate 901. In one embodiment, the package substrate includes laminated glass layers. The glass layers may be bonded to each other by dielectric layers. In one embodiment, a compute die 905 and a photonic die 910 may be provided on the package substrate 901. An IHS 909 may be provided around the compute die 905 and the photonic die 910. As shown, an optical interconnect 911 and a connector 912 may be coupled to the edge of the package substrate 901.

[0108] The use of the glass package substrate 901 provides enhanced dimensional stability and coplanarity. This allows for improved alignment between the optical waveguide (not shown in Figure 9A) embedded within the package substrate 901 and the photonic die 910.

[0109] Referring here to Figure 9B, a cross-sectional view of an optical package 900 according to one embodiment is shown. In one embodiment, the optical package 900 comprises a package substrate 901. The package substrate 901 may include a plurality of glass layers 907 and a plurality of adhesive dielectric layers 908. To form the package substrate 901, the dielectric layers 908 enable the glass layers 907 to adhere to each other. In one embodiment, the package substrate 901 may include conductive routing 967. The conductive routing 967 may include traces, vias, pads and the like, which are embedded within the glass layers 907 and the dielectric layers 908. In one embodiment, a first solder resist layer 963 is provided on the upper surface of the package substrate 901, and a second solder resist layer 964 is provided on the bottom surface of the package substrate 901.

[0110] In one embodiment, a bridge 915 may be embedded in the package substrate 901. The bridge 915 may provide electrical coupling between the photonic die 910 and the compute die 905. In one embodiment, the photonic die 910 and the compute die 905 are attached to the package substrate 901 by an FLI 936. The FLI 936 may be surrounded by an underfill 934. In one embodiment, the photonic die 910 and the compute die 905 are thermally coupled to an IHS 909. For example, a TIM (not shown) may be provided between the IHS 909 and the photonic die 910 and the compute die 905.

[0111] In one embodiment, the optical waveguide 930 is embedded in the package substrate 901. For example, the optical waveguide 930 may be embedded in the top glass layer 907. The optical waveguide 930 may include a first end 931 located beneath (and within the footprint of) the photonic die 910. A second end 932 of the optical waveguide 930 may be located at the edge of the package substrate 901. In one embodiment, the first end 931 of the optical waveguide 930 is inclined (for example, at an angle of about 45°). The inclined first end 931 allows for the routing of optical signals from the photonic die 910 above to the edge of the package substrate 901 at the second end 932 of the optical waveguide 930.

[0112] In one embodiment, the optical waveguide 930 may include, but is not limited to, high refractive index materials such as polyimide, polyalkane, polycyanate, diazobenzoquinone, metal-centered (e.g., iron, aluminum, copper, etc.) dendrite polymer, high-density polycarbonate, polytifen, polythiadiazole, or polysulfone. In one embodiment, the optical waveguide 930 is in direct contact with the glass layer 907. However, in other embodiments, a cladding layer (e.g., silver) may be provided between the optical waveguide 930 and the glass layer 907 to further improve efficiency by enabling internal total internal reflection over a wide wavelength range, resulting in very low attenuation. Additionally, although the built-in optical waveguide 930 is described in Figure 9B, it is understood that, as in the embodiment shown in Figure 2D, a pre-existing optical waveguide may also be inserted into a trench formed in the glass layer 907. Such embodiments may make it possible to obtain even higher efficiency.

[0113] In one embodiment, an optical path 921 is provided on the first end 931 of an optical waveguide 930 through a first solder resist layer 963. In some embodiments, the optical path 921 may be filled. For example, the optical path 921 may be filled with cladding 923 and a core 922. The cladding 923 ensures a low roughness (e.g., about 70 nm RMS or less) to minimize light scattering. Standard cladding 923 and core 922 materials may be used, but are not limited to these, such as polyimide, polyalkane, polycyanate, polyacrylate, polysiloxane, and low-density versions of thin metal layers such as copper, silver, gold, and aluminum. Additionally, polyperfluorocarbon polymers may be used as cladding 923.

[0114] In one embodiment, a dam (not shown) or similar device prevents the underfill 934 from flowing over the optical path 921. Thus, the optical signal can pass through the air from the photonics die 910 to the optical path 921. To improve transmission efficiency, in some embodiments, lenses (for example, as in the embodiment in Figure 2C) may be provided over the optical path 921 and over the second end 932 of the optical waveguide 930.

[0115] Referring now to Figure 9C, a cross-sectional view of the optical package 900 according to an additional embodiment is shown. The optical package 900 in Figure 9C may be substantially similar to the optical package 900 in Figure 9B, except that the bridge 915 is removed. Instead, high-density routing for coupling the photonic die 910 to the compute die 905 is provided through routing 968 in the package substrate 901. Due to the high dimensional stability and coplanarity of the glass-based package substrate 901, it is possible to form high-density routing suitable for coupling the photonic die 910 to the compute die 905.

[0116] Referring to Figures 10A to 10P, a series of cross-sectional views are shown illustrating the process for forming an optical package similar to the optical package 900 in Figure 9B, according to one embodiment.

[0117] Referring now to Figure 10A, a cross-sectional view of a first glass layer 1007 and a first dielectric layer 1008 on a carrier 1071 according to one embodiment is shown. In one embodiment, the glass layer 1007 may have a thickness of about 40 μm or less. The dielectric layer 1008 may be an adhesive dielectric such as a build-up film, which may have a thickness of about 5 μm. In one embodiment, the first dielectric layer 1008 may be bonded to the carrier 1071 by a temporary release layer 1072.

[0118] Referring here to Figure 10B, a cross-sectional view of the structure after a via opening 1073 has been formed through the glass layer 1007 and the dielectric layer 1008 according to one embodiment. In one embodiment, the via opening 1073 is formed using a laser drilling process, a dry etching process, and / or a wet etching process. In the case of the laser or dry etching process, the dielectric 1008 is also drilled or etched. In the case of the wet etching process, a second operation, including laser drilling, may be required to open the via opening 1073 through the underlying dielectric layer 1008. In one embodiment, a desmear operation may also be used to clean the via opening 1073.

[0119] Referring now to Figure 10C, a cross-sectional view of the structure after a surface trench 1074 has been formed on the upper surface of the glass layer 1007 is shown according to one embodiment. A laser or chemical etching process may be used to form the surface trench 1074. In one embodiment, the surface trench 1074 may have a depth of about 15 μm.

[0120] Referring here to Figure 10D, a cross-sectional view of the structure after the conductive material has been filled into the via openings 1073 and surface trenches 1074 according to one embodiment is shown. In one embodiment, a seed layer (not shown) is applied to the surface (for example, using a sputtering process using titanium and / or copper). After the seed layer is formed, standard electroplating using lithography patterning is performed to fill the via openings 1073 and surface trenches 1074. In one embodiment, a planarization process may be used after plating to ensure that a flat surface is provided.

[0121] Referring now to Figure 10E, a cross-sectional view of the structure after the second glass layer 1007 has been provided is shown according to one embodiment. The second glass layer 1007 may be bonded to the underlying glass layer 1007 by a dielectric layer 1008. Patterning and plating processes similar to those described in Figures 10B to 10D may be implemented to provide conductive routing in the next layer.

[0122] Referring now to Figure 10F, a cross-sectional view of a structure after multiple glass layers have been laminated and patterned according to one embodiment is shown. The subsequent glass layer 1007 and dielectric layer 1008 may be patterned and plated using the same process as described in Figures 10B to 10D. The top glass layer 1007 in Figure 10F may be a layer in which bridges (not shown) are embedded.

[0123] Referring now to Figure 10G, a cross-sectional view of the structure after via openings 1073 and surface trenches 1074 have been formed in the uppermost glass layer 1007 and the dielectric layer 1008 according to one embodiment. The via openings 1073 and surface trenches 1074 can be formed using a process similar to that described with respect to Figures 10B and 10C.

[0124] Referring now to Figure 10H, a cross-sectional view of the structure after the via opening 1073 and surface trench 1074 have been filled with conductive material according to one embodiment. The conductive feature 1067 can be formed using a plating process similar to the process described above with respect to Figure 10D.

[0125] Referring here to Figure 10I, a cross-sectional view of the structure after the bridge 1015 has been embedded in the glass layer 1007 is shown according to one embodiment. In one embodiment, a trench is formed through the glass layer 1007 and the dielectric layer 1008. For example, the trench may be formed using a laser drilling process or an etching process. In one embodiment, the bridge 1015 is then placed in the trench (for example, using a pick-and-place process). Next, the dielectric layer 1008 is placed on top of the glass layer 1007 and the bridge 1015. The dielectric layer 1008 may fill the remaining portion of the trench. For example, as shown in Figure 10I, a dielectric material is provided between the sidewall of the bridge 1015 and the glass layer 1007. An additional glass layer 1007 may then be laminated on top of the dielectric layer 1008.

[0126] Referring now to Figure 10J, a cross-sectional view of the structure after the optical waveguide 1030 has been embedded in the uppermost glass layer 1007 is shown according to one embodiment. In one embodiment, the optical waveguide 1030 is first formed by forming a trench on the surface of the glass layer 1007. The trench extends along the edge of the glass layer 1007. The trench may be created using a laser drilling process, a dry etching process, or a wet etching process. In one embodiment, the surface of the trench may be smoothed to prevent light scattering (e.g., 70 nm RMS or less).

[0127] In one embodiment, the trench is filled with a paste-printable high refractive index epoxy resin, such as polyimide, polyalkane, polycyanate, diazobenzoquinone, metal-centered (e.g., iron, aluminum, copper, etc.) dendritic polymer, high-density polycarbonate, polytifen, polythiadiazole, or polysulfone, but is not limited to these. In one embodiment, the optical waveguide 1030 is in direct contact with the glass layer 1007. However, in other embodiments, a cladding layer (e.g., silver) may be provided between the optical waveguide 1030 and the glass layer 1007 to further improve efficiency by enabling internal total internal reflection over a wide wavelength range, resulting in very low attenuation. In some embodiments, a polishing step may be required to remove excess resin from the top surface of the glass layer 1007. Additionally, although a built-in optical waveguide 1030 is described in Figure 10J, it is understood that a pre-existing optical waveguide 1030 may also be inserted into a trench formed in the glass layer 1007. Such embodiments may make it possible to obtain even higher efficiency.

[0128] In one embodiment, the optical waveguide 1030 includes a first end 1031 and a second end 1032. The second end 1032 may be substantially coplanar with the edge of the glass layer 1007. In one embodiment, the first end 1031 may be inclined. For example, the inclination may be about 45°. The inclination of the first end 1031 allows optical signals entering the optical waveguide 1030 from above the first end 1031 to be reflected toward the second end 1032.

[0129] Referring now to Figure 10K, a cross-sectional view of the structure after a conductive connection with the bridge 1015 has been formed according to one embodiment is shown. In one embodiment, the conductive feature 1067 to the bridge 1015 can be formed using patterning and plating processes such as those described above.

[0130] Referring here to Figure 10L, a cross-sectional view of the structure after the solder resist layer 1063 has been placed on the top glass layer 1007 according to one embodiment is shown. In one embodiment, the optical path 1021 is formed through the solder resist layer 1063 on the first end 1031 of the optical waveguide 1030. In some embodiments, the optical path 1021 may be filled. For example, the optical path 1021 may be filled with cladding 1023 and core 1022. The cladding 1023 ensures a low roughness (e.g., about 70 nm RMS or less) to minimize light scattering. Standard cladding 1023 and core 1022 materials may be used, but are not limited to these, such as polyimide, polyalkane, polycyanate, polyacrylate, polysiloxane, and low-density versions of thin metal layers such as copper, silver, gold, and aluminum. Additionally, polyperfluorocarbon polymers may be used as cladding 1023.

[0131] Referring here to Figure 10M, a cross-sectional view of the structure after conductive routing has been formed through the solder resist layer 1063 according to one embodiment. In one embodiment, vias and pads 1068 can be formed through and on the solder resist layer 1063 using standard patterning and plating processes. In one embodiment, the optical path 1021 is protected by a mask layer (not shown) during the formation of conductive features in the solder resist layer 1063.

[0132] Referring here to Figure 10N, a cross-sectional view of the structure after the compute die 1005 and photonic die 1010 have been mounted on the pad 1068 according to one embodiment. The compute die 1005 and photonic die 1010 may be mounted on the pad 1068 using FLI 1036. In one embodiment, FLI 1036 is surrounded by underfill 1034. A dam (not shown) or similar may block the underfill 1034 from flowing over the optical path 1021. As shown, the photonic die 1010 is entirely within the footprint of the glass layer 1007. That is, there is no portion of the photonic die 1010 that overhangs the edge of the glass layer 1007.

[0133] Referring here to Figure 10O, a cross-sectional view of the structure after carrier removal and back-side processing according to one embodiment is shown. In one embodiment, the structure is transferred to a second carrier (not shown) attached to the upper side of the structure during back-side processing. In one embodiment, back-side processing includes the formation of a second solder resist layer 1064 on the bottom dielectric layer 1008. Conductive features (e.g., vias, pads, etc.) are then formed through and / or on the solder resist layer 1064 using standard packaging patterning and plating processes.

[0134] Referring now to Figure 10P, a cross-sectional view of the structure after the IHS1009 has been installed is shown according to one embodiment. In one embodiment, the IHS1009 can be thermally bonded to the photonic die 1010 and the compute die 1005 by TIM (not shown). In one embodiment, the IHS1009 is connected to the solder resist layer 1063.

[0135] Referring now to Figures 11A to 11G, a series of cross-sectional views are shown illustrating the process for forming an optical package similar to the optical package 900 in Figure 9C, according to an additional embodiment. The optical packages in Figures 11A to 11G are similar to the optical packages in Figures 10A to 10P, except that the conductive routing between the photonics die and the compute die is implemented with high-density routing instead of embedded bridges.

[0136] Referring now to Figure 11A, a cross-sectional view of a structure having multiple glass layers 1107 and dielectric layers 1108 on a carrier 1171 according to one embodiment is shown. In one embodiment, the bottom dielectric layer 1108 is bonded to the carrier by a temporary release layer 1172. Conductive routing 1167 is provided through the dielectric layer 1108 and the glass layer 1107. Conductive routing 1167 can be formed using patterning and plating processes such as those described above in Figures 10A to 10P.

[0137] In one embodiment, the conductive routing 1167 may further include high-density routing 1168. The high-density routing 1168 may be fabricated to provide electrical coupling between the photonics die and the compute die. The high-density routing 1168 is made possible by the high dimensional stability and coplanarity provided by the use of the glass layer 1107.

[0138] Referring now to Figure 11B, a cross-sectional view of the structure of the optical waveguide 1130 after its formation is shown according to one embodiment. In one embodiment, the optical waveguide 1130 is first formed by forming a trench on the surface of the glass layer 1107. The trench extends along the edge of the glass layer 1107. The trench may be created using a laser drilling process, a dry etching process, or a wet etching process. In one embodiment, the surface of the trench may be smoothed to prevent light scattering (e.g., 70 nm RMS or less).

[0139] In one embodiment, the trench is filled with a paste-printable high refractive index epoxy resin, such as polyimide, polyalkane, polycyanate, diazobenzoquinone, metal-centered (e.g., iron, aluminum, copper, etc.) dendrite polymer, high-density polycarbonate, polytifen, polythiadiazole, or polysulfone, but is not limited to these. In one embodiment, the optical waveguide 1130 is in direct contact with the glass layer 1107. However, in other embodiments, a cladding layer (e.g., silver) may be provided between the optical waveguide 1130 and the glass layer 1107 to further improve efficiency by enabling internal total internal reflection over a wide wavelength range, resulting in very low attenuation. In some embodiments, a polishing step may be required to remove excess resin from the top surface of the glass layer 1107. Additionally, although a built-in optical waveguide 1130 is described in Figure 11B, it is understood that a pre-existing optical waveguide 1130 can also be inserted into a trench formed in the glass layer 1107. Such embodiments may make it possible to obtain even higher efficiency.

[0140] In one embodiment, the optical waveguide 1130 includes a first end 1131 and a second end 1132. The second end 1132 may be substantially coplanar with the edge of the glass layer 1107. In one embodiment, the first end 1131 may be inclined. For example, the inclination may be about 45°. The inclination of the first end 1131 allows optical signals entering the optical waveguide 1130 from above the first end 1131 to be reflected toward the second end 1132.

[0141] Referring here to Figure 11C, a cross-sectional view of the structure after the solder resist layer 1163 has been placed on the top glass layer 1107 according to one embodiment is shown. In one embodiment, an optical path 1121 is formed through the solder resist layer 1163 on the first end 1131 of the optical waveguide 1130. In some embodiments, the optical path 1121 may be filled. For example, the optical path 1121 may be filled with cladding 1123 and a core 1122. The cladding 1123 ensures a low roughness (e.g., about 70 nm RMS or less) to minimize light scattering. Standard cladding 1123 and core 1122 materials may be used, but are not limited to these, such as polyimide, polyalkane, polycyanate, polyacrylate, polysiloxane, and low-density versions of thin metal layers such as copper, silver, gold, and aluminum. Additionally, polyperfluorocarbon polymers may be used as cladding 1123.

[0142] Referring here to Figure 11D, a cross-sectional view of the structure after conductive routing has been formed through the solder resist layer 1163 according to one embodiment. In one embodiment, vias and pads 1169 can be formed through and on the solder resist layer 1163 using standard patterning and plating processes. In one embodiment, the optical path 1121 is protected by a mask layer (not shown) during the formation of conductive features in the solder resist layer 1163.

[0143] Referring now to Figure 11E, a cross-sectional view of the structure after the compute die 1105 and photonic die 1110 have been mounted to the pad 1169 according to one embodiment. The compute die 1105 and photonic die 1110 may be mounted to the pad 1169 using FLI 1136. In one embodiment, FLI 1136 is surrounded by underfill 1134. A dam (not shown) or similar may block the underfill 1134 from flowing over the optical path 1121. As shown, the photonic die 1110 is entirely within the footprint of the glass layer 1107. That is, there is no portion of the photonic die 1110 that overhangs the edge of the glass layer 1107.

[0144] Referring now to Figure 11F, a cross-sectional view of the structure after carrier removal and back-side processing according to one embodiment is shown. In one embodiment, the structure is transferred to a second carrier (not shown) attached to the upper side of the structure during back-side processing. In one embodiment, back-side processing includes the formation of a second solder resist layer 1164 on the bottom dielectric layer 1108. Conductive features (e.g., vias, pads, etc.) are then formed through and / or on the solder resist layer 1164 using standard packaging patterning and plating processes.

[0145] Referring now to Figure 11G, a cross-sectional view of the structure after the IHS1109 has been installed is shown according to one embodiment. In one embodiment, the IHS1109 can be thermally bonded to the photonic die 1110 and the compute die 1105 by TIM (not shown). In one embodiment, the IHS1109 is connected to the solder resist layer 1163.

[0146] Referring now to Figure 12, an optical system 1290 according to one embodiment is shown. In one embodiment, the optical system 1290 includes a board 1291, such as a printed circuit board (PCB) or the like. In one embodiment, the optical package 1200 is attached to the board 1291 by an interconnect 1292, such as a solder ball, socket, or the like. In one embodiment, the optical package 1200 includes a compute die 1205 and a photonic die 1210 attached to a package substrate 1201. In one embodiment, the package substrate 1201 may be substantially the same as any of the above package substrates (e.g., an organic package substrate, a package substrate with a glass layer, or a glass patch on an organic substrate). In one embodiment, the photonic die 1210 is entirely within the footprint of the package substrate 1201; that is, the photonic die 1210 does not overhang at any edge of the package substrate 1201. In one embodiment, the photonics die 1210 may be communicatively coupled to the compute die by an interconnect (not shown) in the package substrate 1201. For example, the interconnect may include a high-density routing layer or an embedded bridge.

[0147] In one embodiment, the optical waveguide 1230 is embedded in the package substrate 1201. The first end 1231 is beneath the photonic die 1210, and the second end 1232 is at the edge of the package substrate 1201. An optical path 1221 through a solder resist layer provides optical coupling from the first end 1231 of the optical waveguide 1230 to the photonic die 1210. In some embodiments, the optical waveguide 1230 is an integrated optical waveguide 1230. In other embodiments, the optical waveguide 1230 is a separate optical waveguide 1230 embedded in the package substrate 1201. Although shown without a lens, in some embodiments, there may be a lens between the optical path 1221 and the photonic die 1210, and / or at the second end 1232 of the optical waveguide 1230.

[0148] Referring here to Figures 13A to 15C, a series of cross-sectional views of optical packages according to additional embodiments are shown. In exemplary embodiments, the photonic die is directly coupled to the compute die. That is, routing is provided on the photonic die instead of relying on embedded bridges or high-density routing in the package substrate. For example, FLI between the photonic die and the compute die provides electrical coupling between the photonic die and the compute die. This reduces the complexity of the package substrate.

[0149] Optical coupling with a photonic die can be implemented in various architectures. In one embodiment, a grating coupler is provided on the photonic die, enabling the routing of incoming optical signals to the photonic module and their conversion to electrical signals. In an alternative embodiment, a V-groove architecture is used to align optical fibers to the photonic module and convert the optical signals to electrical signals.

[0150] Referring here to Figure 13A, a cross-sectional view of an optical package 1300 according to one embodiment is shown. In one embodiment, the optical package 1300 comprises a package substrate 1301. The package substrate 1301 may be an organic package substrate including conductive routing. In one embodiment, a solder resist layer 1302 is provided on the package substrate 1301. A channel 1303 may be provided in the solder resist layer 1302. The channel 1303 may be sized to receive a photonic die 1310. Such a configuration may be referred to as an open cavity architecture. In one embodiment, the package substrate 1301 may be coupled to a board (not shown).

[0151] In one embodiment, the photonics die 1310 may include a photonics module 1313. The photonics module 1313 may include features suitable for receiving or transmitting optical signals, and features for converting between optical signals and electrical signals. In an exemplary embodiment, the photonics module 1313 is configured to receive an incoming optical signal 1312 from above. For example, the incoming optical signal 1312 may pass through an aperture 1306 in the IHS 1307.

[0152] In one embodiment, the photonics die 1310 is directly coupled to the compute die 1305. For example, the FLI 1336 may be provided on a pad 1314 of the photonics die 1310. That is, the photonics die 1310 can be coupled to the compute die 1305 without requiring an embedded bridge or high-density routing. In such a case, electrical signals generated by the photonics module 1313 can be transmitted to the compute die 1305 without passing through the package substrate 1301. To enable such direct coupling, the footprint of the compute die 1305 may at least partially overlap the footprint of the photonics die.

[0153] Referring here to Figure 13B, a cross-sectional view of a photonic die 1310 according to one embodiment is shown. In one embodiment, the photonic die 1310 may include a semiconductor substrate such as silicon. To receive an optical signal coming from above, the photonic module 1313 may include a grating coupler 1316. The grating coupler 1316 may be optically coupled to a III-V heterojunction 1318 by an optical waveguide 1317. The III-V heterojunction 1318 may enable the conversion of the optical signal into an electrical signal. In one embodiment, the electrical signal is routed to a pad 1314 through a conductive routing 1382 embedded in the substrate. The conductive routing 1382 may be high-density routing to enable a pad 1314 suitable for forming an FLI using a compute die 1305. In some embodiments, through-substrate vias 1383 may be provided so as to penetrate all or part of the thickness of the photonic die 1310. The through-board via 1383 may be used to supply power to a compute die (not shown in Figure 13B) that is placed on top of it.

[0154] Referring here to Figure 14A, a cross-sectional view of an optical package 1400 according to an additional embodiment is shown. As shown, the optical package 1400 includes a package substrate 1401 having a solder resist 1402. The package substrate 1401 may be an organic package substrate. In one embodiment, the package substrate 1401 may be bonded to a board (not shown). In one embodiment, a photonic die 1410 is provided on the package substrate 1401. That is, the photonic die 1410 may be located in a channel in the solder resist 1402. In one embodiment, the photonic die 1410 may receive an optical signal from an optical fiber 1411 inserted along a V-groove 1484. Since the optical signal is received from the side, an aperture may not be required on the upper IHS 1407. The optical signal is processed by a photonic module 1413 and converted into an electrical signal transmitted to a pad 1414.

[0155] In one embodiment, the photonic die 1410 is directly coupled to the compute die 1405 by an FLI 1436. As a result of the direct coupling between the photonic die 1410 and the compute die 1405, electrical signals may not need to pass through the package substrate 1401. In one embodiment, the footprint of the compute die 1405 may at least partially overlap the footprint of the photonic die 1410 in order to enable the connection of the FLI 1436.

[0156] Referring here to Figures 14B and 14C, a cross-sectional view of a photonic die 1410 according to one embodiment is shown. As shown, an optical fiber 1411 is set in a V-groove 1484. The structure of the V-groove is shown in Figure 14C. The optical fiber 1411 supplies an optical signal to a III-V heterojunction 1418. The III-V heterojunction 1418 can convert the optical signal into an electrical signal. In one embodiment, the electrical signal is routed to a pad 1414 through a conductive routing 1482 embedded in the substrate. The conductive routing 1482 may be high-density routing to enable a pad 1414 suitable for forming an FLI using a compute die 1405. In some embodiments, through-substrate vias 1483 may be provided to penetrate all or part of the thickness of the photonic die 1410. The through-substrate vias 1483 may be used to supply power to an overlying compute die (not shown in Figure 14B).

[0157] It is understood that the photonics modules in Figures 13A to 14C are heat-sensitive; that is, the photonics modules may not function properly at high temperatures. Typically, the photonics die can be thermally coupled to the IHS to remove thermal energy from the photonics die. However, by moving the photonics die downward into the package substrate 1501, a direct path to the IHS may not exist. Therefore, embodiments disclosed herein include additional thermal suppression features that enable thermal control of the photonics die.

[0158] Referring now to Figure 15A, a cross-sectional view of an optical package 1500 according to one embodiment is shown. The optical package 1500 may include a package substrate 1501 having a solder resist 1502. A photonic die 1510 that receives optical signals from an optical fiber 1511 is shown. The photonic die 1510 may be directly coupled to a compute die 1505 via an FLI. An IHS 1507 may be provided on top of the compute die 1505. Because the photonic die 1510 is low, it may not be possible for the IHS 1507 to be directly coupled to the photonic die 1510.

[0159] Therefore, a thermal block 1585 may be provided to enable thermal coupling between the photonics die 1510 and the IHS 1507. In certain embodiments, the thermal block 1585 may be provided on top of the photonics module 1513. The thermal block 1585 may be made of a thermally conductive material. In certain embodiments, the thermal block 1585 is a dummy silicon die; that is, a blank silicon die without functional circuits may be used. In alternative embodiments, the thermal block 1585 may include a thermoelectric cooling (TEC) device. The TEC device may be used to actively cool the photonics module 1513.

[0160] Referring here to Figure 15B, a cross-sectional view of the optical package 1500 according to an additional embodiment is shown. Instead of providing cooling to the IHS 1507 from above, a thermal block 1586 is provided through the package substrate 1501. In one embodiment, the thermal block 1586 may be provided below the photonics module 1513. The thermal block 1586 may be, but is not limited to, a thermally conductive material such as copper.

[0161] Referring now to Figure 15C, a cross-sectional view of the optical package 1500 according to an additional embodiment is shown. The optical package 1500 in Figure 15C is substantially similar to the optical package 1500 in Figure 15B, except that it has multiple thermally conductive pillars 1587 instead of a single thermal block 1586. The multiple thermally conductive pillars 1587 may include, but are not limited to, a thermally conductive material such as copper.

[0162] In Figures 15A to 15C, the thermal suppression feature is shown with an optical package similar to optical package 1400 in Figure 4A. However, it should be understood that the same thermal suppression feature can also be applied to an optical package similar to optical package 1300 in Figure 13A.

[0163] Figure 16 shows a computing device 1600 according to one implementation of the present invention. The computing device 1600 houses a board 1602. The board 1602 may include, but is not limited to, a processor 1604 and at least one communication chip 1606. The processor 1604 is physically and electrically coupled to the board 1602. In some implementation examples, at least one communication chip 1606 is also physically and electrically coupled to the board 1602. In further implementation examples, the communication chip 1606 is part of the processor 1604.

[0164] These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard disk drives, compact discs (CDs), digital multipurpose discs (DVDs), etc.).

[0165] The communication chip 1606 enables wireless communication for data transfer to and from the computing device 1600. The term “wireless” and its derivatives may be used to describe the use of modulated electromagnetic radiation through a non-solid medium, including circuits, devices, systems, methods, techniques, and communication channels. The term does not imply that the devices involved are entirely wireless, although this may not be the case in some embodiments. The communication chip 1606 may implement any of several wireless standards or protocols, including but not limited to Wi-Fi® (IEEE 802.11 family), WiMAX® (IEEE 802.16 family), IEEE 802.20, Long-Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM®, GPRS, CDMA, TDMA, DECT, Bluetooth®, their derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and later. The computing device 1600 may include multiple communication chips 1606. For example, the first communication chip 1606 may be dedicated to short-range wireless communication, such as Wi-Fi® and Bluetooth®, and the second communication chip 1606 may be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX®, LTE, Ev-DO, and others.

[0166] The processor 1604 of the computing device 1600 includes an integrated circuit die packaged within the processor 1604. In some implementations of the invention, the integrated circuit die of the processor may be part of an optical package including an embedded optical waveguide for routing optical signals from the edge of the package substrate to a photonic die covering it, as described in the embodiments herein. The term “processor” may refer to any or some device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory.

[0167] The communication chip 1606 also includes an integrated circuit die packaged within the communication chip 1606. According to another implementation of the invention, the integrated circuit die of the communication chip may be part of an optical package that includes an embedded optical waveguide for routing optical signals from the edge of the package substrate to a photonic die covering it, as described in the embodiments herein.

[0168] The above description of the illustrated implementation of the present invention, including that described in the abstract, is not exhaustive and does not limit the present invention to the exact form disclosed. Specific implementations and examples of the present invention are described herein for illustrative purposes, but as those skilled in the art will recognize, various equivalent modifications are possible within the scope of the present invention.

[0169] Based on the detailed description above, these modifications may be made to the present invention. The terms used in the following claims should not be construed as limiting the present invention to any specific implementation disclosed herein and in the claims. Rather, the scope of the present invention should be determined as a whole by the following claims, in accordance with established claim interpretation principles.

[0170] Example 1: An optical package comprising: a package substrate; a photonic die coupled to the package substrate; a compute die coupled to the package substrate, wherein the photonic die is communicatively coupled to the compute die by a bridge in the package substrate; and an optical waveguide embedded in the package substrate, wherein the first end of the optical waveguide is below the photonic die and the second end of the optical waveguide is substantially coplanar with the edge of the package substrate.

[0171] Example 2: The optical package of Example 1, with the first end of the optical waveguide being inclined.

[0172] Example 3: An optical package of Example 1 or Example 2, further comprising a solder resist on a package substrate; and an optical path from the first end of an optical waveguide through the solder resist.

[0173] Example 4: The optical package of Example 3, with the optical path including cladding and core.

[0174] Example 5: An optical package of Example 4, wherein the cladding comprises polyimide, polyalkane, polycyanate, polyacrylate, polysiloxane, metallic material, or polyperfluorocarbon polymer.

[0175] Example 6: The optical package of Example 4, further comprising a first lens on the core and a second lens on the second end of the optical waveguide.

[0176] Example 7: An optical package of Examples 1-6 in which the optical path to the photonic die enters the photonic die on the surface of the photonic die facing the package substrate.

[0177] Example 8: Optical packages of Examples 1-7, where the optical waveguide is in direct contact with the package substrate.

[0178] Example 9: The optical package of Example 8, wherein the surface of the package substrate in contact with the optical waveguide has a surface roughness of approximately 70 nm RMS or smoother.

[0179] Example 10: The optical waveguide is an optical package of Example 8, comprising polyimide, polyalkane, polycyanate, diazobenzoquinone, metal-centered dendritic polymer, high-density polycarbonate, polytifen, polythiadiazole, or polysulfone.

[0180] Example 11: An optical package like those in Examples 1-10, where the optical waveguide is a separate component embedded in the package substrate.

[0181] Example 12: The optical package of Example 11, further comprising a mirror at the first end of the optical waveguide, wherein the mirror is inclined.

[0182] Example 13: An optical package of Examples 1-12, further comprising a silver coating between the optical waveguide and the package substrate.

[0183] Example 14: An optical package from Examples 1-13, where the photonic die is entirely within the footprint of the package substrate.

[0184] Example 15: An optical package of Examples 1-14, further comprising underfill between the photonic die and the package substrate, and between the compute die and the package substrate; and an underfill dam to prevent the underfill from flowing over the first end of the optical waveguide.

[0185] Example 16: Optical package comprising: a package substrate; a trench on the upper surface of the package substrate, wherein the trench has a first end and a second end positioned at the edge of the package substrate; a solder resist on the upper surface of the package substrate; and an opening through the solder resist, wherein the opening is located above the first end of the trench.

[0186] Example 17: The optical package of Example 16, in which the trench is filled with a material having a refractive index greater than 1.0.

[0187] Example 18: The trench is an optical package of Example 16 or Example 17 having a surface roughness of approximately 70 nm RMS or less.

[0188] Example 19: An optical package of Examples 16-18, in which the aperture is filled with cladding and a core.

[0189] Example 20: An optical package of Examples 16-19, further comprising a photonic die on a package substrate, where the photonic die is entirely within the footprint of the package substrate and is positioned over an opening through a solder resist.

[0190] Example 21: An optical package of Example 20, further comprising a compute die on a package substrate, where a photonic die is communicatively coupled to the compute die by a bridge embedded in the package substrate.

[0191] Example 22: Optical packages from Examples 16-21, where the package substrate footprint is rectangular.

[0192] Example 23: An optical package of Examples 16-21, further including a separate optical waveguide positioned in a trench.

[0193] Example 24: An optical system comprising a board; a package substrate coupled to the board; a compute die coupled to the package substrate; a photonic die coupled to the package substrate; and an optical waveguide embedded in the package substrate, wherein the first end of the optical waveguide is below the photonic die and the second end of the optical waveguide is at the edge of the package substrate.

[0194] Example 25: The optical system of Example 24, where the first end of the optical waveguide is inclined.

[0195] Example 26: An optical package comprising: a package substrate; a patch on the package substrate, wherein the patch includes a glass substrate; a photonic die on the glass substrate; a compute die on the glass substrate; and an optical waveguide embedded in the glass substrate, wherein the optical waveguide has a first end below the photonic die and a second end at the edge of the glass substrate.

[0196] Example 27: An optical package of Example 26, in which a photonic die is communicatively coupled to a compute die by a bridge embedded in a glass substrate.

[0197] Example 28: An optical package of Example 26 or Example 27, further comprising a high-density routing stack on a glass substrate, wherein the photonic die is communicatively coupled to the compute die by interconnects in the high-density routing stack.

[0198] Example 29: The optical package of Example 28, further comprising an optical path through a high-density routing stack, the optical path being above the first end of the optical waveguide.

[0199] Example 30: Optical package of Example 29, where the optical path includes cladding and core.

[0200] Example 31: Optical waveguides comprising polyimide, polyalkane, polycyanate, diazobenzoquinone, metal-centered dendritic polymer, high-density polycarbonate, polytifen, polythiadiazole, or polysulfone, as per the optical packages of Examples 26-30.

[0201] Example 32: Optical package of Examples 26-31, where the first end of the optical waveguide is inclined.

[0202] Example 33: An optical package of Examples 26-32, further comprising an organic layer on a glass substrate and a solder resist layer on the organic layer.

[0203] Example 34: The optical package of Example 33, further comprising an optical path through an organic layer and a solder resist layer, wherein the optical path is located above the first end of an optical waveguide.

[0204] Example 35: Optical package of Example 34, where the optical path includes cladding and core.

[0205] Example 36: An optical package of Examples 26-34, further comprising vias through the thickness of the glass substrate, the vias being electrically coupled to the package substrate.

[0206] Example 37: An optical package comprising: a glass substrate; a photonic die on the glass substrate, where the photonic die is entirely within the footprint of the glass substrate; a compute die on the glass substrate, where the compute die is communicatively coupled to the photonic die; and an optical waveguide embedded in the glass substrate, where the optical waveguide has a first end below the photonic die and a second end at the edge of the glass substrate.

[0207] Example 38: An optical package of Example 37, in which a photonic die is communicatively coupled to a compute die by a bridge embedded in a glass substrate.

[0208] Example 39: An optical package of Example 37 or Example 38, further comprising a high-density routing stack on a glass substrate, wherein the photonic die is communicatively coupled to the compute die by interconnects in the high-density routing stack.

[0209] Example 40: An optical package of Examples 37-39, further comprising vias extending through the entire thickness of the glass substrate.

[0210] Example 41: Optical package of Examples 37-40, with a tapered first end.

[0211] Example 42: Optical package of Example 41, with a taper of 45°.

[0212] Example 43: Optical waveguides comprising polyimide, polyalkane, polycyanate, diazobenzoquinone, metal-centered dendritic polymer, high-density polycarbonate, polytifen, polythiadiazole, or polysulfone, as per the optical packages of Examples 37-42.

[0213] Example 44: Optical packages of Examples 37-43, with a silver layer between the optical waveguide and the glass substrate.

[0214] Example 45: An optical package of Examples 37-44, further comprising underfill between the photonic die and the glass substrate, and between the compute die and the glass substrate, wherein the underfill is blocked from being placed above the first end of the optical waveguide.

[0215] Example 46: An optical package of Examples 37-45, further comprising a package substrate bonded to a glass substrate.

[0216] Example 47: An optical package of Example 46, where the package substrate includes a core layer.

[0217] Example 48: An optical system comprising: a board; a package substrate coupled to the board; and a patch coupled to the package substrate, the patch including a glass substrate; a photonic die on the glass substrate, the photonic die being entirely within the footprint of the glass substrate; a compute die on the glass substrate, the compute die being communicatively coupled to the photonic die; and an optical waveguide embedded in the glass substrate, the optical waveguide having a first end below the photonic die and a second end at the edge of the glass substrate.

[0218] Example 49: The optical system of Example 48, in which a photonic die is communicatively coupled to a compute die by a bridge embedded in a glass substrate.

[0219] Example 50: The optical system of Example 48, further comprising a high-density routing stack on a glass substrate, wherein the photonic die is communicatively coupled to the compute die by interconnects in the high-density routing stack.

[0220] Example 51: An optical package comprising a package substrate, where the package substrate includes a plurality of glass layers; and a plurality of dielectric layers, where the plurality of glass layers and the plurality of dielectric layers are stacked alternately; a photonic die on the package substrate; a compute die on the package substrate; and an optical waveguide embedded in the package substrate, where the optical waveguide has a first end below the photonic die and a second end at the edge of the package substrate.

[0221] Example 52: The optical package of Example 51, in which the optical waveguide is embedded in one of several glass layers.

[0222] Example 53: An optical package of Example 52, in which the optical waveguide is embedded in the glass layer closest to the photonic die.

[0223] Example 54: An optical package of Examples 51-53, further comprising multiple conductive paths from a first surface of the package substrate to a second surface of the package substrate.

[0224] Example 55: An optical package of Examples 51-54, in which the photonic die is communicatively coupled to the compute die by a bridge embedded in the package substrate.

[0225] Example 56: An optical package of Examples 51-54, in which the photonic die is communicatively coupled to the compute die by an interconnect embedded in the package substrate.

[0226] Example 57: Optical package of Examples 51-56, where the photonic die is entirely within the footprint of the package substrate.

[0227] Example 58: An optical package of Examples 51-56, further comprising a solder resist on a package substrate; and an optical path through a solder resist on the first end of an optical waveguide.

[0228] Example 59: Optical package of Example 58, in which the optical path includes cladding and core.

[0229] Example 60: Optical package of Examples 51-59, where the first end of the optical waveguide is tapered.

[0230] Example 61: Optical packages of Examples 51-60, in which the optical waveguide comprises polyimide, polyalkane, polycyanate, diazobenzoquinone, metal-centered dendritic polymer, high-density polycarbonate, polytifen, polythiadiazole, or polysulfone.

[0231] Example 62: An optical package of Examples 51-61, in which conductive traces and pads in the package substrate are embedded in multiple glass layers, and vias pass through the glass layers and dielectric layers.

[0232] Example 63: An optical package of Examples 51-62, further comprising underfill between the photonic die and the package substrate, and between the compute die and the package substrate, wherein the underfill is blocked from being positioned above the first end of the optical waveguide.

[0233] Example 64: An optical package comprising: a package substrate, where the package substrate comprises a plurality of glass layers; a photonic die on the package substrate, where the photonic die is entirely within the footprint of the package substrate; a compute die on the package substrate, where the photonic die is communicably coupled to the compute die; and an optical waveguide, where the optical waveguide provides an optical path from the edge of the package substrate to below the photonic die.

[0234] Example 65: The optical package of Example 64, wherein the optical waveguide includes a first end below the photonic die and a second end at the edge of the package substrate, the first end being tapered.

[0235] Example 66: Solder resist on a package substrate; optical package of Example 65, further comprising an optical path through solder resist on the first end of an optical waveguide.

[0236] Example 67: Optical package of Example 66, where the optical path includes cladding and core.

[0237] Example 68: An optical package of Examples 64-67, in which multiple glass layers are bonded together by multiple dielectric layers.

[0238] Example 69: Optical waveguides comprising polyimide, polyalkane, polycyanate, diazobenzoquinone, metal-centered dendritic polymer, high-density polycarbonate, polytifen, polythiadiazole, or polysulfone, as per the optical packages of Examples 64-68.

[0239] Example 70: An optical package of Examples 64-69, in which the photonic die is communicatively coupled to the compute die by a bridge embedded in the package substrate.

[0240] Example 71: An optical package of Examples 64-69, in which the photonic die is communicatively coupled to the compute die by an interconnect embedded in the package substrate.

[0241] Example 72: An optical package of Examples 64-71, further comprising underfill between the photonic die and the package substrate, and between the compute die and the package substrate, wherein the underfill is positioned above the ends of the optical waveguide beneath the photonic die.

[0242] Example 73: An optical system comprising a board; and an optical package coupled to the board, wherein the optical package comprises a package substrate, wherein the package substrate comprises a plurality of glass layers; a photonic die on the package substrate, wherein the photonic die is entirely within the footprint of the package substrate; a compute die on the package substrate, wherein the photonic die is communicably coupled to the compute die; and an optical waveguide, wherein the optical waveguide provides an optical path from the edge of the package substrate to below the photonic die.

[0243] Example 74: The optical system of Example 73, in which the photonic die is communicatively coupled to the compute die by a bridge embedded in the package substrate.

[0244] Example 75: The optical system of Example 73, in which a photonic die is communicatively coupled to a compute die by an interconnect embedded in the package substrate.

[0245] Example 76: An optical package comprising: a package substrate; a photonics die on the package substrate, where the photonics die includes a photonics module and conductive routing having interconnect pads; and a compute die on the package substrate, where the footprint of the compute die overlaps the footprint of the photonics die and the interconnect pads on the photonics die are coupled to the compute die by first-level interconnects (FLIs).

[0246] Example 77: The optical package of Example 76, further comprising an integrated heat spreader (IHS) thermally coupled to the compute die.

[0247] Example 78: The optical package of Example 77, further comprising an aperture through the IHS.

[0248] Example 79: The optical package of Example 78, wherein the light source is configured to pass through an aperture optically coupled to the photonics module.

[0249] Example 80: The optical package of Example 79, wherein the photonics module includes a grating coupler and a III-V heterojunction.

[0250] Example 81: The optical package of Example 76, further comprising an optical fiber optically coupled to the photonics module.

[0251] Example 82: The optical package of Example 81, wherein the optical fiber is set in a V-groove on the photonics die.

[0252] Example 83: The optical package of Examples 76 - 82, wherein the photonics die is disposed in a cavity through a solder resist on the package substrate.

[0253] Example 84: The optical package of Examples 76 - 83, wherein the photonics die further includes through-substrate vias through the thickness of the photonics die.

[0254] Example 85: An optical package of Examples 76-84, further comprising a thermally conductive block embedded in the package substrate beneath the photonics module.

[0255] Example 86: An optical package of Examples 76-85, further comprising an array of thermally conductive pillars embedded in the package substrate beneath the photonics module.

[0256] Example 87: An optical package of Examples 76-86, further comprising a dummy silicon die on top of the photonics module, the dummy silicon die being thermally coupled to an integrated heat spreader.

[0257] Example 88: An optical package of Examples 76-87, further comprising a thermoelectric cooler on top of the photonics module, the thermoelectric cooler being thermally coupled to an integrated heat spreader.

[0258] Example 89: A photonic die comprising: a substrate; an optical coupler; a photonic module, where the photonic module includes a III-V heterojunction for converting optical signals into electrical signals; an electrical routing electrically coupled to the photonic module; and conductive pads on the surface of the substrate, where the conductive pads are electrically coupled to the electrical routing.

[0259] Example 90: The optical coupler is a grating coupler, a photonic die from Example 89.

[0260] Example 91: A photonic die from Example 90, in which a grating coupler is optically coupled to a photonic module by a silicon waveguide.

[0261] Example 92: The photonic die of Example 89, wherein the optical coupler includes a V-groove configured to receive an optical fiber.

[0262] Example 93: A photonic die of Examples 89-92, further comprising through-vias extending through the thickness of the substrate.

[0263] Example 94: The photonic die of Examples 89-93, further comprising a dummy silicon die mounted on the photonic module.

[0264] Example 95: The photonic die of Examples 89-94, further comprising a thermoelectric cooler mounted on the photonic module.

[0265] Example 96: An optical system comprising a board; a package substrate on the board; a photonic die on the package substrate; and a compute die on the package substrate, wherein the footprint of the photonic die at least partially overlaps the footprint of the compute die.

[0266] Example 97: The optical system of Example 96, wherein the photonic die is electrically coupled to the compute die by a first-level interconnect.

[0267] Example 98: The optical system of Example 96 or Example 97, wherein the photonic die includes an optical coupler.

[0268] Example 99: The optical system of Example 98, wherein the optical coupler is a grating coupler.

[0269] Example 100: The optical system of Example 98, wherein the optical coupler includes a V-groove configured to receive an optical fiber. [Other possible claims] (Item 1) A package substrate; A photonic die coupled to the package substrate; A compute die coupled to the package substrate, wherein the photonic die is communicatively coupled to the compute die by a bridge in the package substrate; and An optical waveguide embedded in the package substrate, wherein a first end of the optical waveguide is under the photonic die and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate. An optical package comprising the above. (Item 2) The optical package as described in item 1, wherein the first end of the optical waveguide is inclined. (Item 3) Solder resist on the aforementioned package substrate; and The optical path from the first end of the optical waveguide through the solder resist An optical package as described in item 1 or 2, further comprising the following: (Item 4) The optical path is an optical package as described in item 3, including cladding and a core. (Item 5) The optical package according to item 4, wherein the cladding comprises polyimide, polyalkane, polycyanate, polyacrylate, polysiloxane, metallic material, or polyperfluorocarbon polymer. (Item 6) The first lens on the core; and The second lens above the second end of the optical waveguide The optical package described in item 4 further includes the features described. (Item 7) The optical package according to item 1 or 2, wherein the optical path to the photonic die enters the photonic die on the surface of the photonic die facing the package substrate. (Item 8) The optical waveguide is in direct contact with the package substrate, as described in item 1 or 2. (Item 9) The optical package according to item 8, wherein the surface of the package substrate in contact with the optical waveguide has a surface roughness of approximately 70 nm RMS or smoother. (Item 10) The optical waveguide comprises polyimide, polyalkane, polycyanate, diazobenzoquinone, metal-centered dendritic polymer, high-density polycarbonate, polytifen, polythiadiazole, or polysulfone, as described in item 8. (Item 11) The optical package according to item 1 or 2, wherein the optical waveguide is a separate component embedded in the package substrate. (Item 12) The optical package according to item 11, further comprising a mirror at the first end of the optical waveguide, wherein the mirror is inclined. (Item 13) The optical package according to item 1 or 2, further comprising a silver coating between the optical waveguide and the package substrate. (Item 14) The optical package according to item 1 or 2, wherein the photonic die is entirely located within the footprint of the package substrate. (Item 15) Underfill between the photonic die and the package substrate, and between the compute die and the package substrate; and An underfill dam that prevents the underfill from flowing over the first end of the optical waveguide. An optical package as described in item 1 or 2, further comprising the following: (Item 16) Package substrate; A trench on the upper surface of the package substrate, wherein the trench has a first end and a second end positioned at the edge of the package substrate; Solder resist on the upper surface of the package substrate; and, An opening through the solder resist, wherein the opening is located above the first end of the trench. An optical package equipped with [specific features / features]. (Item 17) The optical package according to item 16, wherein the trench is filled with a material having a refractive index greater than 1.0. (Item 18) The trench has a surface roughness of approximately 70 nm RMS or less, as described in item 16 or 17 of the optical package. (Item 19) The optical package according to item 16 or 17, wherein the opening is filled with cladding and a core. (Item 20) A photonic die on the package substrate, wherein the photonic die is located entirely within the footprint of the package substrate, and the photonic die is positioned above the opening through the solder resist. The optical package described in item 16 or 17, further comprising: (Item 21) A compute die on the aforementioned package substrate, wherein the photonics die is communicatively coupled to the compute die by a bridge embedded in the package substrate. The optical package described in item 20 further includes the features described therein. (Item 22) The optical package described in item 16 or 17, wherein the footprint of the package substrate is rectangular. (Item 23) The optical package according to item 16 or 17, further comprising a separate optical waveguide positioned in the trench. (Item 24) board; Package substrate coupled to the aforementioned board; A compute die coupled to the aforementioned package substrate; A photonic die coupled to the package substrate; and, An optical waveguide is embedded in the package substrate, where the first end of the optical waveguide is located beneath the photonics die, and the second end of the optical waveguide is located at the edge of the package substrate. An optical system equipped with [the following features]. (Item 25) The optical system according to item 24, wherein the first end of the optical waveguide is inclined.

Claims

1. Package substrate; A photonic die bonded to the aforementioned package substrate; A compute die coupled to the package substrate, wherein the photonics die is communicatively coupled to the compute die by a bridge in the package substrate; and An optical waveguide embedded in the package substrate, wherein the first end of the optical waveguide is located beneath the photonics die, and the second end of the optical waveguide is substantially coplanar with the edge of the package substrate. An optical package equipped with [specific features / features].

2. The optical package according to claim 1, wherein the first end of the optical waveguide is inclined.

3. Solder resist on the aforementioned package substrate; and The optical path from the first end of the optical waveguide through the solder resist The optical package according to claim 1 or 2, further comprising:

4. The optical package according to claim 3, wherein the optical path includes cladding and a core.

5. The optical package according to claim 4, wherein the cladding comprises polyimide, polyalkane, polycyanate, polyacrylate, polysiloxane, metallic material, or polyperfluorocarbon polymer.

6. The first lens on the core; and The second lens above the second end of the optical waveguide The optical package according to claim 4, further comprising:

7. The optical package according to any one of claims 1 to 6, wherein the optical path to the photonic die enters the photonic die on the surface of the photonic die facing the package substrate.

8. The optical package according to any one of claims 1 to 7, wherein the optical waveguide is in direct contact with the package substrate.

9. The optical package according to claim 8, wherein the surface of the package substrate in contact with the optical waveguide has a surface roughness of about 70 nm RMS or smoother.

10. The optical package according to claim 8, wherein the optical waveguide comprises polyimide, polyalkane, polycyanate, diazobenzoquinone, metal-centered dendritic polymer, high-density polycarbonate, polytifen, polythiadiazole, or polysulfone.

11. The optical package according to any one of claims 1 to 10, wherein the optical waveguide is a separate component embedded in the package substrate.

12. The optical package according to claim 11, further comprising a mirror at the first end of the optical waveguide, wherein the mirror is inclined.

13. The optical package according to any one of claims 1 to 12, further comprising a silver coating between the optical waveguide and the package substrate.

14. The optical package according to any one of claims 1 to 13, wherein the photonic die is located entirely within the footprint of the package substrate.

15. Underfill between the photonic die and the package substrate, and between the compute die and the package substrate; and, An underfill dam that prevents the underfill from flowing over the first end of the optical waveguide. The optical package according to any one of claims 1 to 14, further comprising the above.

16. Package substrate; A trench on the upper surface of the package substrate, wherein the trench has a first end and a second end positioned at the edge of the package substrate; Solder resist on the upper surface of the package substrate; and, An opening through the solder resist, wherein the opening is located above the first end of the trench. An optical package equipped with [specific features / features].

17. The optical package according to claim 16, wherein the trench is filled with a material having a refractive index greater than 1.

0.

18. The optical package according to claim 16 or 17, wherein the trench has a surface roughness of about 70 nm RMS or less.

19. The optical package according to any one of claims 16 to 18, wherein the opening is filled with cladding and a core.

20. A photonic die on the package substrate, wherein the photonic die is located entirely within the footprint of the package substrate, and the photonic die is positioned above the opening through the solder resist. The optical package according to any one of claims 16 to 19, further comprising the above.

21. A compute die on the aforementioned package substrate, wherein the photonics die is communicatively coupled to the compute die by a bridge embedded in the package substrate. The optical package according to claim 20, further comprising:

22. The optical package according to any one of claims 16 to 21, wherein the footprint of the package substrate is rectangular.

23. The optical package according to any one of claims 16 to 21, further comprising a separate optical waveguide positioned in the trench.

24. board; Package substrate coupled to the aforementioned board; A compute die bonded to the aforementioned package substrate; A photonic die bonded to the package substrate; and, An optical waveguide is embedded in the package substrate, where the first end of the optical waveguide is located beneath the photonics die, and the second end of the optical waveguide is located at the edge of the package substrate. An optical system equipped with [the following features].

25. The optical system according to claim 24, wherein the first end of the optical waveguide is inclined.

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