Gaming machine

Abstract

The objective is to achieve efficient control processing. [Solution] In the display control process, a first process is executed to set the lower part of the address of the number of game balls to be displayed in the first pair register. The display creation process consists of a second process to set the address of a predetermined display table in the second pair register, a third process to set the lower address value of the decimal data of the number of game balls in the first register, a fourth process to set the lower address value of a predetermined output buffer in the second register, a fifth process to set the first repetition number in the third register, a sixth process to repeat multiple processes the number of times specified by the first repetition number, a seventh process to set a second repetition number that is one less than the first repetition number in the third register, an eighth process to set the address of a predetermined output buffer in the second pair register, a ninth process, a tenth process, and an eleventh process, which are repeated the number of times specified by the second repetition number.

Claims

1. A gaming machine comprising: a gaming control board equipped with a gaming control microprocessor for controlling the progress of the game; a frame-side control board equipped with a frame-side control microprocessor for performing various controls based on commands from the gaming control board; a first operating unit; and a display device visible to the player, The aforementioned game control microprocessor is A CPU for game control, A first program executed by the game control CPU, and a game control ROM in which information referenced by the first program is stored, A game control RAM capable of storing information updated by the first program, It comprises a general-purpose register for game control, a data register for game control, and a flag register for game control. The aforementioned frame-side control microprocessor is CPU for frame control, A second program executed by the CPU for frame control, and a frame control ROM in which information referenced by the second program is stored, A frame-side RAM capable of storing information updated by the second program, It comprises a general-purpose register on the frame side, a data register on the frame side, and a flag register on the frame side. The CPU for controlling the frame side is, The display device is controllable, In the display control process, which is a process that controls the content to be displayed on the display device, A first process involves setting the lower part of the address of the number of game balls to be displayed in a first pair register using two general-purpose registers on the frame side, After the first process, a decimal conversion process is performed to convert the value of the number of game balls for display into a decimal value, which is the game ball count decimal data. The following process is executed: a display creation process that creates display data for the decimal data of the number of game balls, The aforementioned display creation process is: A second process involves setting the address of a predetermined display table in a second pair of registers using two general-purpose registers on the frame side, A third process involves setting the lower address value of the decimal data of the number of game balls in the first register of the general-purpose registers on the frame side, A fourth process involves setting the lower address value of a predetermined output buffer into the second register among the general-purpose registers on the frame side, A fifth process in which the first number of repetitions is set in the third register of the general-purpose registers on the frame side, After the fifth process, a sixth process is performed in which multiple processes are repeated the number of times specified in the first iteration, A seventh process in which a second number of repetitions, which is one less than the first number of repetitions, is set in the third register, An eighth process of setting the address of the predetermined output buffer in the second pair register, After the eighth process, the ninth process, the tenth process, and the eleventh process are repeated a number of times equal to the second repetition count. The ninth process described above is the process of taking the logical AND of the content stored at the address of the predetermined output buffer and the first value. The tenth process is a process in which, if the logical AND becomes the second value, the contents stored at the address of the predetermined output buffer are cleared. The 11th process is the process of adding 1 to the value of the lower address among the addresses of the predetermined output buffers stored in the second pair register. A gaming machine characterized by the following features.

2. A gaming machine comprising: a gaming control board equipped with a gaming control microprocessor for controlling the progress of the game; a frame-side control board equipped with a frame-side control microprocessor for performing various controls based on commands from the gaming control board; and a display device visible to the player, The aforementioned game control microprocessor is A CPU for game control, A first program executed by the game control CPU, and a game control ROM in which information referenced by the first program is stored, A game control RAM capable of storing information updated by the first program, It comprises a general-purpose register for game control, a data register for game control, and a flag register for game control. The aforementioned frame-side control microprocessor is CPU for frame control, A second program executed by the CPU for frame control, and a frame control ROM in which information referenced by the second program is stored, A frame-side RAM capable of storing information updated by the second program, It comprises a general-purpose register on the frame side, a data register on the frame side, and a flag register on the frame side. The aforementioned CPU for game control is The display device is controllable, In the display control process, which is a process that controls the content to be displayed on the display device, A first process involves setting the lower part of the address of the number of game balls to be displayed in a first pair of registers using two of the aforementioned general-purpose registers for game control, After the first process, a decimal conversion process is performed to convert the value of the number of game balls for display into a decimal value, which is the game ball count decimal data. The following process is executed: a display creation process that creates display data for the decimal data of the number of game balls, The aforementioned display creation process is: A second process involves setting the address of a predetermined display table in a second pair of registers using two of the aforementioned general-purpose registers for game control, A third process involves setting the lower address value of the decimal data of the number of game balls in the first register of the general-purpose registers for game control, A fourth process involves setting the lower address value of a predetermined output buffer into a second register among the general-purpose registers for game control, A fifth process in which the first number of repetitions is set in the third register of the general-purpose registers for game control, After the fifth process, a sixth process is performed in which multiple processes are repeated the number of times specified in the first iteration, A seventh process in which a second number of repetitions, which is one less than the first number of repetitions, is set in the third register, An eighth process of setting the address of the predetermined output buffer in the second pair register, After the eighth process, the ninth process, the tenth process, and the eleventh process are repeated a number of times equal to the second repetition count. The ninth process described above is the process of taking the logical AND of the content stored at the address of the predetermined output buffer and the first value. The tenth process is a process in which, if the logical AND becomes the second value, the contents stored at the address of the predetermined output buffer are cleared. The 11th process is the process of adding 1 to the value of the lower address among the addresses of the predetermined output buffers stored in the second pair register. A gaming machine characterized by the following features.

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