Indication device

Abstract

The present invention provides a display device having a data link structure that enables bezel reduction. [Solution] The display device according to the embodiment of the present disclosure includes a display area and a non-display area outside the display area, the display area includes an upper display area, a lower display area, and an intermediate display area between the upper display area and the lower display area, the non-display area may include a substrate including a pad area further adjacent to the upper display area than the intermediate display area, and a plurality of data lines disposed in the display area, the nth data line of which may include an nth upper data line disposed in the upper display area and extending in a first direction, an nth lower data line disposed in the lower display area and extending in a first direction, and an nth bypass link line that passes through the intermediate display area and electrically connects the nth upper data line and the nth lower data line.

Description

Technical Field

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[0005]

[0001] Embodiments of the present disclosure relate to a display device.

Background Art

[0002] Recently, a display panel of a display device may include a display area where an image is displayed and a non-display area where an image is not displayed. Here, the non-display area may sometimes be referred to as a bezel. The smaller the size of the non-display area of the display panel, the easier it may be to increase the size of the display area, realize display devices in various shapes, or apply them to various uses. It is not easy to reduce the size of the non-display area due to the shape of the display device or the signal wiring arranged on the display panel.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present disclosure can provide a display device having a data link structure capable of reducing bezels.

[0004] Embodiments of the present disclosure can provide a display device having a power supply wiring structure capable of improving display driving performance and enabling low-power driving.

[0005] [[ID=so]]Embodiments of the present disclosure can provide a display device having a data link structure capable of reducing bezels and a related power supply wiring structure, thereby enabling process optimization. H

[0006] Embodiments of the present disclosure can provide a display device of a heterogeneous integrated display type having a data link structure capable of reducing bezels.

[0007] Embodiments of this disclosure can provide a display device as a wearable device having a data link structure that enables bezel reduction. Here, the wearable device may include virtual reality (VR) devices, augmented reality (AR) devices, mixed reality (MR) devices, or extended reality (XR) devices.

[0008] The problems of the embodiments of this disclosure are not limited to those mentioned herein, and other problems not mentioned herein will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0009] A display device according to an embodiment of the present disclosure includes a display area and a non-display area outside the display area, the display area includes an upper display area, a lower display area, and an intermediate display area between the upper and lower display areas, the non-display area includes a substrate including a pad area adjacent to the upper display area from the intermediate display area, and a plurality of data lines arranged in the display area, the nth data line of the plurality of data lines may include an nth upper data line arranged in the upper display area and extending in a first direction, an nth lower data line arranged in the lower display area and extending in a first direction, and an nth bypass link line that passes through the intermediate display area and electrically connects the nth upper data line and the nth lower data line.

[0010] At the first boundary line between the upper display area and the middle display area, the width of the middle display area may narrow as you approach the center of the middle display area. At the second boundary line between the lower display area and the middle display area, the width of the middle display area may narrow as you approach the center of the middle display area.

[0011] The nth bypass link line may include an nth upper link line located in the display area, electrically connected to the nth upper data line, and extending in a second direction different from the first direction; an nth lower link line located in the display area, electrically connected to the nth lower data line, and extending in the second direction; and an nth intermediate link line located in the display area, electrically connecting the nth upper link line and the nth lower link line, and extending in the first direction.

[0012] A display device according to an embodiment of the present disclosure may include a substrate including a display area, a first signal wiring disposed on the substrate, extending in a first direction within the display area and located within a first metal layer, and a second signal wiring disposed on the substrate, extending in a second direction different from the first direction within the display area and located within a second metal layer different from the first metal layer.

[0013] According to embodiments of this disclosure, a display device having a data link structure that enables bezel reduction can be provided by designing the data lines or link lines for connecting them to be arranged in the display area.

[0014] According to embodiments of this disclosure, a power wiring structure in which power wiring is arranged in a mesh pattern within the display area can reduce the resistance of the power wiring, improve the power supply characteristics via the power wiring, thereby improving display driving performance and providing a display device that can be driven with low power.

[0015] According to embodiments of this disclosure, by having a data link structure that enables bezel reduction and a power supply wiring structure that works in conjunction with it, it is not necessary to separately form the data link structure and the power supply wiring structure, thus providing a display device that enables process optimization.

[0016] According to embodiments of this disclosure, it is possible to provide a heterogeneous integrated display type display device having a data link structure that enables bezel reduction.

[0017] According to an embodiment of the present disclosure, a display device as a wearable device having a data link structure capable of reducing bezels can be provided.

[0018] The effects of the embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

Brief Description of the Drawings

[0019] The content of the present disclosure will be more fully understood from the following detailed description and the accompanying drawings. The detailed description and the accompanying drawings are provided for illustrative purposes only and do not limit the content of the present disclosure. [Figure 1] A display device according to an embodiment of the present disclosure is shown. [Figure 2] An equivalent circuit of sub-pixels of a display panel according to an embodiment of the present disclosure is shown. [Figure 3] An arrangement structure of data lines of a display panel according to an embodiment of the present disclosure is shown. [Figure 4] A detailed area included in the waist area of a display panel according to an embodiment of the present disclosure is shown. [Figure 5] A cross-sectional view of a display panel according to an embodiment of the present disclosure. [Figure 6] A plan view of a display panel according to an embodiment of the present disclosure. [Figure 7] A plan view of a display panel according to an embodiment of the present disclosure. [Figure 8] A plan view of a display panel according to an embodiment of the present disclosure. [Figure 9] An enlarged plan view of a first area of a display panel according to an embodiment of the present disclosure. [Figure 10] An enlarged plan view of a second area of a display panel according to an embodiment of the present disclosure. [Figure 11] An enlarged plan view of first to fourth connection areas in a first area and a second area of a display panel according to an embodiment of the present disclosure. [Figure 12]An enlarged plan view of the first to fourth connection regions in the first and second regions of a display panel according to an embodiment of the present disclosure. [Figure 13] An enlarged plan view of the first to fourth connection regions in the first and second regions of a display panel according to an embodiment of the present disclosure. [Figure 14] An enlarged plan view of the first to fourth connection regions in the first and second regions of a display panel according to an embodiment of the present disclosure. [Figure 15] A cross-sectional view of the first to fourth main regions in the first to fourth connection regions. [Figure 16] A cross-sectional view of the first to fourth main regions in the first to fourth connection regions. [Figure 17] A cross-sectional view of the first to fourth main regions in the first to fourth connection regions. [Figure 18] A cross-sectional view of the first to fourth main regions in the first to fourth connection regions. [Figure 19] A cross-sectional view of the first to fourth main regions in the first to fourth connection regions. [Figure 20] A cross-sectional view of the first to fourth main regions in the first to fourth connection regions. [Figure 21] A cross-sectional view of the first to fourth main regions in the first to fourth connection regions. [Figure 22] A cross-sectional view of the first to fourth main regions in the first to fourth connection regions. [Figure 23] Shows a detailed region included in the waist region of a display panel according to an embodiment of the present disclosure. [Figure 24] Shows the structure of a non-display region within the first region of a display panel according to an embodiment of the present disclosure.

Embodiments for Carrying Out the Invention

[0020] Hereinafter, some embodiments of this disclosure will be described in detail with reference to illustrative drawings. In assigning reference numerals to components in each drawing, the same reference numeral may be used for the same component whenever possible, even if it is shown in other drawings. In describing this disclosure, if it is determined that a specific description of a relevant known configuration or function would obscure the gist of this disclosure, such detailed description will be omitted. Where the terms “includes,” “has,” “consists of,” etc., used herein, other parts may be added unless “only” is used. When a component is expressed singularly, it may include multiple components unless otherwise explicitly stated.

[0021] Furthermore, in describing the components of this disclosure, terms such as 1, 2, A, B, (a), (b), etc., may be used. These terms are used solely to distinguish a component from other components, and do not limit the nature, order, sequence, or number of such components.

[0022] In descriptions of the positional relationships of components, when it is stated that two or more components are “linked,” “joined,” or “connected,” it should be understood that while two or more components can be directly “linked,” “joined,” or “connected,” it is also possible for two or more components to be further “interposed” with other components before being “linked,” “joined,” or “connected.” Here, the other components may be included in one or more of the two or more components that are “linked,” “joined,” or “connected” to each other.

[0023] On the other hand, if numerical values ​​or corresponding information (e.g., levels) relating to components are mentioned, even without further explicit mention, these numerical values ​​or corresponding information may be interpreted as including a range of errors that can occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0024] Various embodiments of this disclosure will be described in detail below with reference to the attached drawings.

[0025] Figure 1 shows a display device 100 according to an embodiment of the present disclosure.

[0026] The display device 100 according to the embodiments of this disclosure may include a display panel 110 and a drive circuit 120, etc.

[0027] The display panel 110 may include a substrate 111 and a plurality of subpixels SP formed on the substrate 111.

[0028] The substrate 111 may include a display area DA on which video can be displayed and a non-display area NDA on which video cannot be displayed. The display area DA and the non-display area NDA may be areas of the display panel 110. That is, the display panel 110 may include a display area DA and a non-display area NDA. Here, the non-display area NDA is also called a bezel.

[0029] The substrate 111 can be divided into multiple regions. For example, the substrate 111 may include a first region A1, a second region A2, and a third region A3. The first region A1 may include a pad region PA. The second region A2 may be located furthest from the pad region PA among the first to third regions A1, A2, and A3. The third region A3 may be located between the first region A1 and the second region A2.

[0030] The display area DA may include an upper display area DA_TOP contained in the first area A1, a lower display area DA_BOT contained in the second area A2, and an intermediate display area DA_MID contained in the third area A3. That is, the substrate 111 may include a first area A1 containing the upper display area DA_TOP, a second area A2 containing the lower display area DA_BOT, and a third area A3 containing the intermediate display area DA_MID. The first area A1 may include a pad area PA.

[0031] The non-display area (NDA) is an outer area of ​​the display area (DA) and may include a pad area (PA) adjacent to the upper display area (DA_TOP) rather than the intermediate display area (DA_MID).

[0032] The substrate 111 may be a flexible substrate.

[0033] The substrate 111 may have an upper edge line TEL, a lower edge line BEL, a first boundary line BL1, and a second boundary line BL2.

[0034] The upper edge line TEL and the lower edge line BEL may be cutting lines of the substrate 111. The upper edge line TEL may be the edge line of the substrate 111 near the pad area PA, and the lower edge line BEL may be the edge line of the substrate 111 on the opposite side of the upper edge line TEL.

[0035] The substrate 111 can be bent near the upper edge line TEL. Therefore, the pad area PA and the components connected to it (drive circuit 120, flexible printed circuit board 130, printed circuit board 140) can be located beneath the substrate 111.

[0036] The first boundary line BL1 is a virtual line indicating the boundary between the upper display area DA_TOP and the intermediate display area DA_MID, and the second boundary line BL2 may be a virtual line indicating the boundary between the lower display area DA_BOT and the intermediate display area DA_MID.

[0037] Multiple subpixels SP can be placed in the display area DA. Multiple subpixels SP can be placed in each of the upper display area DA_TOP, the middle display area DA_MID, and the lower display area DA_BOT.

[0038] In the display device 100 according to the embodiment of this disclosure, the third region A3 may include an inwardly recessed waist region WA. That is, one side of the third region A3 may be inwardly recessed.

[0039] Within the third region A3, the waist region WA can mean the region between the valley line Lv and the edge EDG of the substrate 111. The valley line Lv may be a virtual line extending in the first direction through the point where the substrate 111 is most deeply indented (Pv, hereinafter referred to as the "valley point").

[0040] For example, at the first boundary line BL1 between the upper display area DA_TOP and the intermediate display area DA_MID, the width of the intermediate display area DA_MID may narrow as you approach its center. Similarly, at the second boundary line BL2 between the lower display area DA_BOT and the intermediate display area DA_MID, the width of the intermediate display area DA_MID may narrow as you approach its center. Here, width can refer to the length in the first direction.

[0041] For example, the maximum width of the intermediate display area DA_MID may be smaller than the maximum width of the upper display area DA_TOP and the maximum width of the lower display area DA_BOT.

[0042] In the display device 100 according to the embodiments of this disclosure, the drive circuit 120 can be electrically connected to the pad area PA within the non-display area NDA. For example, the drive circuit 120 is mounted on a flexible printed circuit board 130, and one side of the flexible printed circuit board 130 can be connected to the pad area PA of the substrate 111. Here, the flexible printed circuit board 130 may also be called a flexible printed circuit or circuit film. A printed circuit board 140 may be connected to the other side of the flexible printed circuit board 130.

[0043] The drive circuit 120 can be implemented as an integrated circuit. The drive circuit 120 may include a data drive circuit that supplies data signals corresponding to the video signal to the subpixels SP in the display panel 110.

[0044] The display device 100 according to embodiments of this disclosure may further include a gate drive circuit that supplies gate signals to subpixels SP in the display panel 110. In one example, the gate drive circuit may be located outside the display panel 110. In another example, the gate drive circuit may be located inside the display panel 110. A gate drive circuit located inside the display panel 110 is called a gate-in-panel (GIP) type and can be located on a substrate 111. A gate drive circuit located inside the display panel 110 can also be called a gate-in-panel circuit. For example, a gate-in-panel circuit can be located in a non-display area (NDA).

[0045] If the gate drive circuit is located outside the display panel 110, the gate drive circuit may be included in the drive circuit 120, or it may exist separately from the drive circuit 120.

[0046] The display device 100 according to the embodiments of this disclosure may further include a controller for controlling the drive circuit 120 and the gate drive circuit. For example, the controller may be mounted on a printed circuit board 140.

[0047] The display device 100 according to the embodiments of this disclosure may further include a non-display area (NDA) of the display panel 110 and a case member that covers the circuit configuration (e.g., a drive circuit 120, a flexible printed circuit board 130, and a printed circuit board 140). For example, the case member may include a mounting member that can be worn on the user's face (e.g., eyeglass temples, a headband, etc.).

[0048] On the other hand, for example, the display device 100 according to the embodiment of the present disclosure may have the shape of eyeglasses. For example, the display device 100 according to the embodiment of the present disclosure may be a heterogeneous integrated display device or an eyeglass-type wearable device. If the display device 100 according to the embodiment of the present disclosure is an eyeglass-type wearable device, the user can wear the display device 100 like eyeglasses. As a result, the waist region WA of the display device 100 can correspond to the part that rests on the user's nose, and the upper edge line TEL of the first region A1 and the lower edge line BEL of the second region A2 can be adjacent to both of the user's ears.

[0049] For example, the display device 100 according to the embodiments of this disclosure may be at least one wearable device from among virtual reality (VR) devices, augmented reality (AR) devices, mixed reality (MR) devices, and extended reality (XR) devices. For example, if the display device 100 is a wearable device that can be worn on a user's face, the surface on which the image is displayed among the two surfaces of the display device 100 may be the surface opposite to the surface closer to the user wearing the display device 100. In this case, the image displayed on the display device 100 worn by the user can be shown to other users in the vicinity of the wearer. As another example, if the display device 100 is a wearable device that can be worn on a user's face, the surface on which the image is displayed among the two surfaces of the display device 100 may be the surface closer to the user wearing the display device 100. As another example, if the display device 100 is a wearable device that can be worn on the user's face, then of the two surfaces of the display device 100, the surface on which the image is displayed can be both the surface closer to the user wearing the display device 100 and the surface on the opposite side.

[0050] Figure 2 shows the equivalent circuit of a subpixel SP of the display panel 110 according to an embodiment of the present disclosure.

[0051] Each subpixel SP of the display device 100 according to the embodiments of this disclosure may include a light-emitting element ED and a subpixel circuit SPC for driving the light-emitting element ED.

[0052] The light-emitting element (ED) may be an organic-based organic light-emitting diode (OLED), an inorganic-based light-emitting diode (LED), or a quantum dot light-emitting element, but is not limited to these. For the sake of explanation, the following explanation will use the case where the light-emitting element (ED) is an organic light-emitting diode (OLED) as an example.

[0053] The subpixel circuit SPC may include multiple transistors for driving the light-emitting element ED and at least one capacitor. The subpixel circuit SPC can drive the light-emitting element ED by supplying a drive current to the light-emitting element ED at predetermined timings. The light-emitting element ED can emit light when driven by the drive current.

[0054] Multiple transistors included in the subpixel circuit SPC may include a drive transistor DT for driving the light-emitting element ED and a scan transistor ST that is turned on or off in response to a scan signal SC.

[0055] The drive transistor DT can supply drive current to the light-emitting element ED. The scan transistor ST can be configured to control the electrical state of the corresponding node in the subpixel circuit SPC, or to control the state or operation of the drive transistor DT. At least one capacitor may include a storage capacitor Cst to maintain a constant voltage between frames.

[0056] To drive the subpixel SP, a video signal such as the data signal Vdata and a type of gate signal such as the scan signal SC can be applied to the subpixel SP. Furthermore, a common drive signal, including the drive voltage VDD and base voltage VSS, can be applied to the subpixel SP.

[0057] The light-emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The intermediate layer EL can be placed between the pixel electrode PE and the common electrode CE. For example, the pixel electrode PE may be an electrode placed in each subpixel SP, and the common electrode CE may be an electrode commonly placed in multiple subpixels SP. As an example, the pixel electrode PE may be the anode electrode and the common electrode CE may be the cathode electrode. As another example, the pixel electrode PE may be the cathode electrode and the common electrode CE may be the anode electrode. In the following explanation, for convenience, we will use the case where the pixel electrode PE is the anode electrode and the common electrode CE is the cathode electrode as an example.

[0058] If the light-emitting element ED is an organic light-emitting element, the intermediate layer EL may include a light-emitting layer EML, a first common intermediate layer COM1 between the pixel electrode PE and the light-emitting layer EML, and a second common intermediate layer COM2 between the light-emitting layer EML and the common electrode CE. The first common intermediate layer COM1 and the second common intermediate layer COM2 together can be called the common intermediate layer EL_COM.

[0059] The light-emitting layer (EML) can be placed for each subpixel (SP) or commonly across multiple subpixels (SP), and the common intermediate layer (EL_COM) can also be commonly across multiple subpixels (SP). However, it is not limited to these arrangements.

[0060] The light-emitting layer (EML) can be placed in each light-emitting region or in common across multiple light-emitting regions, and the common intermediate layer (EL_COM) can be placed in common across multiple light-emitting and non-light-emitting regions. However, it is not limited to these arrangements.

[0061] For example, the first common intermediate layer COM1 may include a hole injection layer (HIL), an electron blocking layer (EBL), and a hole transfer layer (HTL), and the second common intermediate layer COM2 may include an electron transfer layer (ETL), a hole blocking layer (HBL), and an electron injection layer (EIL), but is not limited thereto. The hole injection layer HIL injects holes from the pixel electrode PE to the hole transfer layer HTL, the hole transfer layer HTL transports holes to the light-emitting layer EML, the electron injection layer EIL injects electrons from the common electrode CE to the electron transfer layer ETL, and the electron transfer layer ETL transports electrons to the light-emitting layer EML.

[0062] For example, the common electrode CE can be electrically connected to the base voltage line VSSL. A base voltage VSS, which is a type of common voltage, can be applied to the common electrode CE via the base voltage line VSSL. The pixel electrode PE can be electrically connected directly or indirectly (via other transistors) to the first node Na of the drive transistor DT of each subpixel SP. In this disclosure, the base voltage VSS may also be referred to as the first common voltage, low potential power supply voltage, or low potential voltage, and the base voltage line VSSL may also be referred to as the first common voltage wiring, low potential power supply voltage line, or low potential voltage line.

[0063] Each light-emitting element ED can be composed of the superposition of a pixel electrode PE, an emissive layer EML within the intermediate layer EL, and a common electrode CE. Each light-emitting element ED can form a predetermined light-emitting region. For example, the light-emitting region of each light-emitting element ED may include the superposition of the pixel electrode PE, the emissive layer EML within the intermediate layer EL, and the common electrode CE.

[0064] The drive transistor DT may be a drive transistor for supplying drive current to the light-emitting element ED. The drive transistor DT may be connected between the drive voltage line VDDL and the light-emitting element ED.

[0065] The drive transistor DT may include a first node Na, a second node Nb, and a third node Nc. The first node Na may be electrically connected to the light-emitting element ED, the second node Nb may be to which a data signal Vdata is applied, and the third node Nc may be to which a drive voltage VDD, which is another type of common voltage from the drive voltage line VDDL, is applied. The drive transistor DT may be connected on the first node Na and the third node Nc. In this disclosure, the drive voltage VDD may also be referred to as the second common voltage, high potential power supply voltage, or high potential voltage, and the drive voltage line VDDL may also be referred to as the second common voltage wiring, high potential power supply voltage line, or high potential voltage line.

[0066] In a drive transistor DT, the second node Nb is the gate node, the first node Na is either the source node or the drain node, and the third node Nc may be either the drain node or the source node. For the sake of explanation, in the following, in a drive transistor DT, the second node Nb may be the gate node, the first node Na may be the source node, and the third node Nc may be the drain node. However, it is not limited to this.

[0067] The scan transistor ST included in the subpixel circuit SPC shown in Figure 2 may be a switching transistor that transmits the data signal Vdata, which is the video signal, to the second node Nb, which is the gate node of the drive transistor DT.

[0068] The scan transistor ST is controlled on / off by a scan signal SC, which is a type of gate signal applied via a scan line SCL, which is a type of gate line GL, and can control the electrical connection between the second node Nb of the drive transistor DT and the data line DL. The drain or source electrode of the scan transistor ST may be electrically connected to the data line DL, the source or drain electrode of the scan transistor ST may be electrically connected to the second node Nb of the drive transistor DT, and the gate electrode of the scan transistor ST may be electrically connected to the scan line SCL.

[0069] The storage capacitor Cst may be electrically connected between the first node Na and the second node Nb of the drive transistor DT. The storage capacitor Cst may include at least one capacitor electrode electrically connected to or corresponding to the first node Na of the drive transistor DT, and at least one capacitor electrode electrically connected to or corresponding to the second node Nb of the drive transistor DT.

[0070] The storage capacitor Cst may be an external capacitor intentionally designed outside the drive transistor DT, rather than a parasitic capacitor (e.g., Cgs, Cgd) which is an internal capacitor that may exist between the first node Na and the second node Nb of the drive transistor DT. However, it is not limited to this.

[0071] The drive transistor DT and the scan transistor ST may each be either an n-type or p-type transistor, but are not limited to this. For example, one of the drive transistor DT and the scan transistor ST may be either an n-type or a p-type transistor.

[0072] The display panel 110 may have a top-emission structure or a bottom-emission structure. When the display panel 110 has a top-emission structure, at least a portion of the subpixel circuit SPC can overlap with at least a portion of the light-emitting element ED in the vertical direction. This can increase the area of ​​the light-emitting region and improve the aperture ratio. When the display panel 110 has a bottom-emission structure, the subpixel circuit SPC does not need to overlap with the light-emitting element ED in the vertical direction.

[0073] The subpixel circuit SPC may have a 2T (Transistor) 1C (Capacitor) structure, as shown in Figure 2, including two transistors DT and ST and one capacitor Cst, and may optionally include one or more transistors or one or more capacitors.

[0074] The type and number of gate signals supplied to the subpixel SP can vary depending on the structure of the subpixel circuit SPC. Furthermore, the type and number of common drive signals supplied to the subpixel SP can also vary depending on the configuration of the subpixel circuit SPC.

[0075] Since the circuit elements within each subpixel SP (e.g., light-emitting elements ED, which are realized with organic light-emitting diodes (OLEDs) containing organic materials) are vulnerable to external moisture and oxygen, the display panel 110 may further include a sealing layer placed on the light-emitting elements ED. The sealing layer can prevent external moisture and oxygen from penetrating the circuit elements (e.g., light-emitting elements ED). The sealing layer can be configured in various forms to prevent the light-emitting elements ED from coming into contact with moisture and oxygen. For example, the sealing layer may consist of two or more layers in which organic and inorganic films are alternately stacked. However, it is not limited to this.

[0076] The display device 100 may further include a touch sensor layer on which a touch sensor is formed, and a touch sensing circuit that senses the touch sensor formed on the touch sensor layer and determines whether or not a touch is present or the touch coordinates, in order to provide a touch sensing function.

[0077] Figure 3 shows the data line arrangement structure of the display panel 110 according to an embodiment of the present disclosure. However, in the following description, Figures 1 and 2 will also be referred to.

[0078] The display panel 110 may include a first region A1 and a second region A2, and a third region A3 between the first region A1 and the second region A2. The first region A1 may be a region to which circuit configurations (e.g., a drive circuit 120, a flexible printed circuit board 130, a printed circuit board 140, etc.) are connected. The width BTW of the portion of the first region A1 corresponding to the upper edge line TEL may be smaller than that of other portions.

[0079] The display panel 110 may include multiple data lines DL for transmitting data signals Vdata to multiple subpixels SP. Multiple data lines DL may be arranged in the display area DA.

[0080] Depending on the shape of the substrate 111 of the display panel 110 (for example, the shape of eyeglasses), the multiple data lines DL may include a plurality of first data lines DL1 that do not pass through the waist region WA, and a plurality of second data lines DL2 that pass through the waist region WA.

[0081] Each of the multiple first data lines DL1 can be connected to a first data link line DLL1 that extends from the pad area PA through the upper edge line TEL to the upper display area DA_TOP, and can be positioned extending in a first direction within the upper display area DA_TOP.

[0082] Each of the multiple first data lines DL1 may extend in the first direction and be positioned without curving in all of the upper display area DA_TOP, the middle display area DA_MID, and the lower display area DA_BOT.

[0083] Each of the multiple second data lines DL2 can be connected to a second data link line DLL2 that extends from the pad area PA through the upper edge line TEL to the upper display area DA_TOP, and can be positioned extending in the first direction within the upper display area DA_TOP.

[0084] However, each of the multiple second data lines DL2 can be positioned curving inward so that it is positioned on the inwardly recessed substrate 111 when passing through the waist region WA within the intermediate display region DA_MID.

[0085] When each of the multiple second data lines DL2 is curved as it passes through the waist region WA, it can pass through the hidden region NDA contained within the waist region WA. As a result, each of the multiple second data lines DL2 may include an upper data line DL2_DA_TOP located in the upper display region DA_TOP, a lower data line DL2_DA_BOT located in the lower display region DA_BOT, and a bypass data line DL2_NDA that connects the upper data line DL1_DA_TOP and the lower data line DL2_DA_BOT and is located in the hidden region NDA.

[0086] As mentioned above, each of the multiple second data lines DL2 is curved and positioned in the waist region WA, and as the bypass data line DL2_NDA of each of the multiple second data lines DL2 is positioned in the hidden region NDA, the size of the hidden region NDA included in the waist region WA may increase.

[0087] Consequently, if the display device 100 according to the embodiment of this disclosure is a glasses-type wearable device, an increase in the size of the non-display area NDA included in the waist area WA may result in a decrease in the design quality of the display device 100 or make it inconvenient to wear the display device 100.

[0088] Figure 4 shows the detail area included in the waist area WA of the display panel 110 according to the embodiment of the present disclosure.

[0089] The hidden area NDA included in the waist area WA may include a data link area DLLA where multiple bypass data lines DL2_NDA of multiple second data lines DL2 are located, a drive power wiring area PLA where drive power wiring is located, a gate-in-panel circuit area GIPA where a gate-in-panel circuit, which is a gate-in-panel type gate drive circuit, is located, a base voltage wiring area VSSA where a base voltage line VSSL is located, and a crack stopper area CSA where a crack stopper structure is located.

[0090] The drive power supply wiring area PLA may contain gate drive-related link wiring connected to the gate-in-panel circuit, and drive power supply wiring for transmitting various drive power supplies (e.g., initialization voltage, reference voltage, etc.) to the subpixel SP.

[0091] The non-display area NDA included in the waist area WA may further include a connection area CLA where the drive power wiring located in the drive power wiring area PLA is extended and gate lines are located to transmit the gate signal output from the gate-in-panel circuit to the subpixel SP.

[0092] The non-display area NDA included in the waist area WA may further include a first empty space FA1 between the base voltage wiring area VSSA and the crack stopper area CSA, and a second empty space FA2 between the crack stopper area CSA and the trimming line. Here, the trimming line may correspond to the cutting line of the substrate 111.

[0093] As mentioned above, each of the multiple second data lines DL2 is positioned in a curved manner within the waist region WA, and the bypass data line DL2_NDA of each of the multiple second data lines DL2 is positioned within the hidden region NDA, so that the hidden region NDA contained within the waist region WA can contain a large data link region DLLA.

[0094] Figure 5 is a cross-sectional view of the display panel 110 according to an embodiment of the present disclosure. Figure 5 is a cross-sectional view taken along the XY lines of Figure 3.

[0095] The display panel 110 according to the embodiments of this disclosure may include a display area DA and a non-display area NDA.

[0096] The display panel 110 according to the embodiments of this disclosure may include a substrate 111, a buffer layer 520 disposed on the substrate 111, a gate insulating layer 530 disposed on the buffer layer 520, an interlayer insulating layer 540 disposed on the gate insulating layer 530, a planarizing layer 550 disposed on the interlayer insulating layer 540, a light-emitting element ED disposed on the planarizing layer 550 and located in the display area DA, and a sealing layer 580 disposed on the light-emitting element ED.

[0097] The substrate 111 may be single-layer or multilayer. If the substrate 111 is multilayer, it may include a first substrate 511, an intermediate substrate layer 512, and a second substrate 513. The intermediate substrate layer 512 may be located between the first substrate 511 and the second substrate 513. For example, the first substrate 511 and the second substrate 513 may each be polyimide (PI) layers, but are not limited thereto. The intermediate substrate layer 512 may also be an inorganic insulating layer, but are not limited thereto. The intermediate substrate layer 512 can block the charge from affecting the transistors located on the second substrate 513 via the polyimide layer of the second substrate 513 when the first substrate 511, which is a polyimide layer, is charged.

[0098] Furthermore, the intermediate substrate layer 512 can block moisture components from penetrating the first substrate 511 and permeating to the upper layer. For example, the intermediate substrate layer 512 can consist of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), or it can be formed from a bilayer of silicon dioxide (SiO2) and silicon nitride (SiNx). However, it is not limited to these.

[0099] The buffer layer 520 may be single-layer or multi-layer, but is not limited to this. If the buffer layer 520 is multi-layer, it may include a first buffer layer 521 and a second buffer layer 522.

[0100] The display panel 110 may further include a transistor TFT and a storage capacitor Cst, which are arranged on the buffer layer 520. The transistor TFT may include an active layer ACT, a gate electrode G, a source electrode S, and a drain electrode D. The storage capacitor Cst may include a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2.

[0101] The active layer ACT of the transistor TFT is placed on the buffer layer 520, and the gate insulating layer 530 may be placed on the active layer ACT of the transistor TFT.

[0102] The gate electrode G of the transistor TFT is located on the gate insulating layer 530 and can overlap with at least a portion of the active layer ACT.

[0103] The interlayer insulating layer 540 may include a first interlayer insulating layer 541 and a second interlayer insulating layer 542. The first interlayer insulating layer 541 may be placed on the gate electrode G of a transistor TFT. The second interlayer insulating layer 542 may be placed on the first interlayer insulating layer 541.

[0104] The source electrode S and drain electrode D of the transistor TFT can be placed on the second interlayer insulating layer 542. The source electrode S of the transistor TFT can be connected to a portion of the active layer ACT through holes in the second interlayer insulating layer 542 and the first interlayer insulating layer 541, and the drain electrode D of the transistor TFT can be connected to another portion of the active layer ACT of the transistor TFT through other holes in the second interlayer insulating layer 542 and the first interlayer insulating layer 541.

[0105] The first capacitor electrode CAPE1 can be placed on the gate insulating layer 530, and the second capacitor electrode CAPE2 can be placed on the first interlayer insulating layer 541 and superimposed on the first capacitor electrode CAPE1.

[0106] The first capacitor electrode CAPE1 can be placed in the same metal layer as the gate electrode G of the transistor TFT, and the second capacitor electrode CAPE2 can be placed between the gate electrode G of the transistor TFT and the source / drain electrodes S and D.

[0107] The planarization layer 550 can be placed on the second interlayer insulating layer 542.

[0108] The light-emitting element ED can be placed on the planarization layer 550 and may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE.

[0109] The pixel electrode PE is placed on the planarization layer 550 and can be electrically connected to the source electrode S or drain electrode D of the transistor TFT through holes in the planarization layer 550.

[0110] Bank 560 is positioned on the planarization layer 550 and the pixel electrode PE and may have light-emitting holes EH that expose a portion of the pixel electrode PE. The light-emitting holes EH of bank 560 may correspond to the light-emitting region of the light-emitting element ED.

[0111] The intermediate layer EL can be positioned on bank 560, in contact with the upper surface of the pixel electrode PE within the light-emitting hole EH of bank 560.

[0112] The common electrode CE can be placed on the intermediate layer EL.

[0113] The sealing layer 580 can be placed on the common electrode CE. The sealing layer 580 may include a first sealing layer 581, a second sealing layer 582, and a third sealing layer 583. The first sealing layer 581 and the third sealing layer 583 may be inorganic layers, and the second sealing layer 582 may be an organic layer.

[0114] The display panel 110 may further include a first dam DAM1 positioned outside the second sealing layer 582. For example, the first dam DAM1 may include a plurality of dam constituent layers 550a, 560a, and 570a. For example, the plurality of dam constituent layers 550a, 560a, and 570a may include a first dam constituent layer 550a, a second dam constituent layer 560a, and a third dam constituent layer 570a. The first dam constituent layer 550a may contain the same organic insulating material as the flattening layer 550, the second dam constituent layer 560a may contain the same organic insulating material as the bank 560, and the third dam constituent layer 570a may contain the same organic insulating material as the spacer that can be placed on the bank 560.

[0115] The display panel 110 may further include a second dam DAM2 located outside the first dam DAM1. For example, the second dam DAM2 may include multiple dam layers 550b, 560b, and 570b, similar to the first dam DAM1.

[0116] The first sealing layer 581 is positioned on the common electrode CE, but may extend beyond the top of the first dam DAM1 and the second dam DAM2 to the outside of the second dam DAM2.

[0117] The third sealing layer 583 is positioned on the second sealing layer 582, but extends outward beyond the second sealing layer 582, and together with the first sealing layer 581, can extend past the tops of the first dam DAM1 and the second dam DAM2, and extend to the outside of the second dam DAM2.

[0118] The display panel 110 may further include a base voltage line VSSL to which the base voltage VSS is applied, and a connection pattern CP that electrically connects the common electrode CE and the base voltage line VSSL.

[0119] The base voltage line VSSL can be positioned between the second interlayer insulating layer 542 and the planarization layer 550. The base voltage line VSS can be positioned below the planarization layer 550 and can extend below the first dam DAM1.

[0120] The connection pattern CP can be positioned between bank 560 and the planarization layer 550. For example, the connection pattern CP can be located in the non-display area NDA. The connection pattern CP can extend from the top surface of the planarization layer 550 along the side surface of the planarization layer 550 and be electrically connected to the base voltage line VSSL.

[0121] Bank 560 may have additional connection holes CH. For example, the connection holes CH of Bank 560 may be located in a hidden area NDA.

[0122] The common electrode CE can be extended from the display area DA to a portion of the non-display area NDA. In the non-display area NDA, the common electrode CE can be electrically connected to the upper surface of the connection pattern CP via the connection hole CH of bank 560.

[0123] The display panel 110 may further include a lower shielding metal BSM that overlaps with the active layer ACT of the transistor TFT. The lower shielding metal BSM may be located between the substrate 111 and the buffer layer 520, or between the first buffer layer 521 and the second buffer layer 522.

[0124] The display panel 110 can include various metal layers. For example, the display panel 110 can include a lower shield metal layer BSML on which the lower shield metal BSM is located, a gate metal layer GML on which the gate electrode G of the transistor TFT and the first capacitor electrode CAPE1 of the storage capacitor Cst are located, a capacitor electrode metal layer TML on which the second capacitor electrode CAPE2 of the storage capacitor Cst is located, a source-drain metal layer SDML on which the source electrode S and drain electrode D of the transistor TFT are located, a pixel electrode metal layer PEML on which the pixel electrode PE is located, and a common electrode metal layer CEML on which the common electrode CE is located.

[0125] On the other hand, as described above with reference to Figures 3 and 4, the shape of the display panel 110 allows the size of the non-display area NDA included in the waist area WA to increase as data lines (bypass data lines) to which data signals are applied are arranged. As a result, if the display device 100 according to the embodiment of this disclosure is a glasses-type wearable device, the design quality of the display device 100 may be reduced or the display device 100 may become inconvenient to wear.

[0126] Therefore, embodiments of the present disclosure can provide a "bezel-reducing data link structure" that can reduce the size of the non-display area NDA included in the waist area WA of the display panel 110. Embodiments of the present disclosure can provide a power wiring structure that can improve display driving performance. Embodiments of the present disclosure can provide a power wiring structure that is linked to the bezel-reducing data link structure.

[0127] The following describes a signal structure that enables bezel reduction according to embodiments of the present disclosure. A data link structure that enables bezel reduction according to embodiments of the present disclosure and a power supply wiring structure linked to the data link structure that enables bezel reduction will be described. However, the following description will also refer to Figures 1 to 5.

[0128] Figures 6 to 8 are plan views of the display panel 110 according to an embodiment of the present disclosure, Figure 9 is an enlarged plan view of the first region A1 of the display panel 110 according to an embodiment of the present disclosure, and Figure 10 is an enlarged plan view of the second region A2 of the display panel 110 according to an embodiment of the present disclosure.

[0129] Figure 6 is a plan view showing together a data link structure and a power supply wiring structure that enable bezel reduction according to an embodiment of the present disclosure; Figure 7 is a plan view from Figure 6 with the power supply wiring structure omitted and showing only the data link structure that enables bezel reduction; and Figure 8 is a plan view from Figure 6 with the data link structure that enables bezel reduction omitted and showing only the power supply wiring structure.

[0130] Figure 9 is an enlarged plan view of the first region A1 in Figure 6, and Figure 10 is an enlarged plan view of the second region A2 in Figure 6.

[0131] Referring to Figures 6 to 8, the substrate 111 of the display panel 110 may include a first region A1, a second region A2, and a third region A3. The third region A3 may be located between the first region A1 and the second region A2. The first region A1 is the region between the upper edge line TEL and the first boundary line BL1, the third region A3 is the region between the first boundary line BL1 and the second boundary line BL2, and the second region A2 may be the region between the second boundary line BL2 and the lower edge line BEL. The first region A1 and the second region A2 may be defined by a data link structure.

[0132] The substrate 111 may include a display area DA and a non-display area NDA outside the display area DA.

[0133] The display area DA can include an upper display area DA_TOP, an intermediate display area DA_MID, and a lower display area DA_BOT. The intermediate display area DA_MID can be located between the upper display area DA_TOP and the lower display area DA_BOT.

[0134] The upper display area DA_TOP is contained within the first area A1, the lower display area DA_BOT is contained within the second area A2, and the intermediate display area DA_MID may be contained within the third area A3.

[0135] The display area DA can contain multiple data lines DL.

[0136] The substrate 111 may include a waist region WA that is part of the third region A3. The waist region WA may be a region within the third region A3 in which the substrate 111 is recessed inward.

[0137] According to the data link structure that enables bezel reduction in the embodiments of this disclosure, the display area DA of the substrate 111 may further include a data link structure connected to all or part of a plurality of data lines DL. This eliminates the need to place a bypass data line DL2_NDA in the non-display area NDA within the waist area WA of the substrate 111. Therefore, the size of the non-display area NDA within the waist area WA of the substrate 111 can be reduced.

[0138] Multiple data lines DL can be classified into a "first data line group GR1" which has a bypass link line DL_BLL that bypasses the waist area WA within the display area DA, and a "second data line group GR2" which does not need to bypass the waist area WA within the display area DA, and therefore extends linearly in the first direction and does not have a bypass link line DL_BLL.

[0139] Among multiple data lines DL, each data line DL belonging to the first data line group GR1 may include an upper data line DL_TOP, a lower data line DL_BOT, and a bypass link line DL_BLL.

[0140] The bypass link line DL_BLL may be positioned to bypass the inwardly recessed waist region WA within the intermediate display region DA_MID.

[0141] The upper data line DL_TOP of each data line DL belonging to the first data line group GR1 is located in the upper display area DA_TOP and can extend in the first direction.

[0142] The lower data line DL_BOT of each data line DL belonging to the first data line group GR1 is located in the lower display area DA_BOT and can extend in the first direction.

[0143] The bypass link line DL_BLL of each data line DL belonging to the first data line group GR1 passes through the intermediate display area DA_MID and can electrically connect the upper data line DL_TOP and the lower data line DL_BOT.

[0144] Here, the first and second directions are different directions, and may even be relative directions. In one example, the first direction may be vertical and the second direction may be horizontal. In another example, the first direction may be horizontal and the second direction may be vertical. However, for the sake of explanation, we will use the example where the first direction is vertical and the second direction is horizontal. But we are not limited to this.

[0145] The bypass link line DL_BLL of each data line DL belonging to the first data line group GR1 may include an upper link line, a lower link line, and an intermediate link line.

[0146] The upper link line is located in the display area DA, electrically connected to the upper data line DL_TOP, and can extend in a second direction different from the first direction.

[0147] The lower link line is located in the display area DA, electrically connected to the lower data line DL_BOT, and can extend in a second direction.

[0148] The intermediate link line is located in the display area DA, electrically connects the upper link line and the lower link line, and can extend in the first direction. One end of the intermediate link line VLIA_DATA(n) can be electrically connected to the upper link line. The other end of the intermediate link line can be electrically connected to the lower link line.

[0149] The upper link line can be placed in the upper display area DA_TOP. The lower link line can be placed in the lower display area DA_BOT. The intermediate link line can pass through the intermediate display area DA_MID in the first direction.

[0150] In the following, the data link structure capable of reducing the bezel according to the embodiments of this disclosure will be explained again, taking the nth data line DL(n) and the (n-1)th data line DL(n-1) as examples from among a plurality of data lines DL. The nth data line DL(n) may be a data line (signal wiring) for transmitting the nth data signal, and the (n-1)th data line DL(n-1) may be a data line (signal wiring) for transmitting the (n-1)th data signal.

[0151] Referring to Figures 6, 7, 11, 12, 13, and 14, the nth data line DL(n) can include the nth upper data line DL(n)_TOP, the nth lower data line DL(n)_BOT, and the nth bypass link line DL(n)_BLL.

[0152] The nth upper data line DL(n)_TOP is located in the upper display area DA_TOP and can extend in the first direction.

[0153] The nth lower data line DL(n)_BOT is located in the lower display area DA_BOT and can extend in the first direction.

[0154] The nth bypass link line DL(n)_BLL can be positioned to bypass the inwardly recessed waist region WA within the intermediate display region DA_MID.

[0155] The nth bypass link line DL(n)_BLL can be positioned according to the shape of the waist region WA. The nth bypass link line DL(n)_BLL may be positioned in a bent form. The nth bypass link line DL(n)_BLL can pass through the intermediate display region DA_MID and electrically connect the nth upper data line DL(n)_TOP and the nth lower data line DL(n)_BOT.

[0156] Referring to Figures 6 and 7, the nth bypass link line DL(n)_BLL can include the nth upper link line HLIA_DATA(n)_TOP, the nth lower link line HLIA_DATA(n)_BOT, and the nth intermediate link line VLIA_DATA(n).

[0157] The nth upper link line HLIA_DATA(n)_TOP is located in the display area DA and is electrically connected to the nth upper data line DL(n)_TOP at the first connection point CNT_DATA(n)_1, and can extend in a second direction different from the first direction.

[0158] The nth lower link line HLIA_DATA(n)_BOT is located in the display area DA and is electrically connected to the nth lower data line DL(n)_BOT at the fourth connection point CNT_DATA(n)_4, and can extend in the second direction.

[0159] The nth intermediate link line VLIA_DATA(n) is located in the display area DA and can extend in the first direction, electrically connecting the nth upper link line HLIA_DATA(n)_TOP and the nth lower link line HLIA_DATA(n)_BOT.

[0160] One end of the nth intermediate link line VLIA_DATA(n) can be electrically connected to the nth upper link line HLIA_DATA(n)_TOP at the second connection point CNT_DATA(n)_2. The other end of the nth intermediate link line VLIA_DATA(n) can be electrically connected to the nth lower link line HLIA_DATA(n)_BOT at the third connection point CNT_DATA(n)_3.

[0161] The nth upper link line HLIA_DATA(n)_TOP may be located in the upper display area DA_TOP. The nth lower link line HLIA_DATA(n)_BOT may be located in the lower display area DA_BOT. The nth intermediate link line HLIA_DATA(n) may pass through the intermediate display area DA_MID in the first direction.

[0162] The (n-1)th data line DL(n-1) may include the (n-1)th upper data line DL(n-1)_TOP, the (n-1)th lower data line DL(n-1)_BOT, and the (n-1)th bypass link line DL(n-1)_BLL.

[0163] The (n-1)th upper data line DL(n-1)_TOP is located in the upper display area DA_TOP and can extend in the first direction.

[0164] The (n-1)th lower data line DL(n-1)_BOT is located in the lower display area DA_BOT and can extend in the first direction.

[0165] The (n-1)th bypass link line DL(n-1)_BLL passes through the intermediate display area DA_MID and can electrically connect the (n-1)th upper data line DL(n-1)_TOP and the (n-1)th lower data line DL(n-1)_BOT.

[0166] The (n-1)th bypass link line DL(n-1)_BLL may include the (n-1)th upper link line HLIA_DATA(n-1)_TOP, the (n-1)th middle link line VLIA_DATA(n-1), and the (n-1)th lower link line HLIA_DATA(n-1)_BOT.

[0167] The (n-1)th upper link line HLIA_DATA(n-1)_TOP is located in the display area DA, electrically connected to the (n-1)th upper data line DL(n-1)_TOP, and can extend in a second direction different from the first direction.

[0168] The (n-1)th lower link line HLIA_DATA(n-1)_BOT is located in the display area DA, electrically connected to the (n-1)th lower data line DL(n-1)_BOT, and can extend in a second direction.

[0169] The (n-1)th intermediate link line VLIA_DATA(n-1) is located in the display area DA and can electrically connect the (n-1)th upper link line HLIA_DATA(n-1)_TOP and the (n-1)th lower link line HLIA_DATA(n-1)_BOT.

[0170] One end of the (n-1)th intermediate link line VLIA_DATA(n-1) may be electrically connected to the (n-1)th upper link line HLIA_DATA(n-1)_TOP. The other end of the (n-1)th intermediate link line VLIA_DATA(n-1) may be electrically connected to the (n-1)th lower link line HLIA_DATA(n-1)_BOT.

[0171] The (n-1)th upper link line HLIA_DATA(n-1)_TOP is located in the upper display area DA_TOP, the (n-1)th lower link line HLIA_DATA(n-1)_BOT is located in the lower display area DA_BOT, and the (n-1)th intermediate link line HLIA_DATA(n-1) can pass through the intermediate display area DA_MID in the first direction.

[0172] As mentioned above, the multiple data lines DL can be classified into a first data line group GR1, which has a bypass link line to bypass the waist area WA within the display area DA, and a second data line group GR2, which does not need to bypass the waist area WA within the display area DA, and therefore extends linearly in the first direction and does not have a bypass link line.

[0173] The data lines DL included in the first data line group GR1 include bypass link lines and can therefore be arranged in a curved manner by the bypass link lines rather than in a straight line or substantially straight line. For example, the first data line group GR1 may include the nth data line DL(n), the (n-1)th data line DL(n-1), and so on, where n can be a natural number greater than or equal to 1.

[0174] The data lines DL included in the second data line group GR2 do not include bypass link lines and can therefore be arranged in a straight line or substantially in a straight line. The data lines DL included in the second data line group GR2 can pass through the upper display area DA_TOP, the intermediate display area DA_MID, and the lower display area DA_BOT while extending in the first direction. For example, the second data line group GR2 may include the (n+a)th data line DL(n+a), the (n+a+1)th data line DL(n+a+1), and the (n+a+2)th data line DL(n+a+2), etc., where n is a natural number greater than or equal to 1, and a can be a natural number greater than or equal to 1.

[0175] Referring to Figures 6 and 7, the display area DA may include the upper link area HLIA_TOP_ZONE where the nth upper link line HLIA_DATA(n)_TOP and the (n-1)th upper link line HLIA_DATA(n-1)_TOP are located, the lower link area HLIA_BOT_ZONE where the nth lower link line HLIA_DATA(n)_BOT and the (n-1)th lower link line HLIA_DATA(n-1)_BOT are located, and the intermediate link area VLIA_ZONE where the nth intermediate link line VLIA_DATA(n) and the (n-1)th intermediate link line VLIA_DATA(n-1) are located.

[0176] The upper link region HLIA_TOP_ZONE may be included in the upper display region DA_TOP. The lower link region HLIA_BOT_ZONE may be included in the lower display region DA_BOT. The intermediate link region VLIA_ZONE may be included in the upper display region DA_TOP, the intermediate display region DA_MID, and the lower display region DA_BOT.

[0177] For example, the upper link region HLIA_TOP_ZONE may have the shape of a first triangle, the lower link region HLIA_BOT_ZONE may have the shape of a second triangle, and the intermediate link region VLIA_ZONE may have the shape of a rectangle.

[0178] For example, the shape of the first triangle in the upper link region HLIA_TOP_ZONE and the shape of the second triangle in the lower link region HLIA_BOT_ZONE may be symmetrical to each other based on the intermediate display region DA_MID. The intermediate link region VLIA_ZONE may have a trapezoidal shape.

[0179] Referring to Figures 6 and 8, the display panel 110 according to the embodiment of the present disclosure may further include power supply wiring VSSL arranged in a mesh-like manner in the display area DA. For example, the power supply wiring VSSL may be a base voltage line VSSL that transmits a base voltage VSS to a subpixel SP. The base voltage VSS may be a type of common voltage whose voltage level is constant over time.

[0180] By arranging the power wiring VSSL in a mesh pattern within the display area DA, the resistance of the power wiring VSSL can be reduced. This allows for a stable supply of power to the subpixels via the power wiring VSS, thereby improving display driving performance.

[0181] A power wiring VSSL can include multiple horizontal power wirings HLIA_VSS and multiple vertical power wirings VLIA_VSS.

[0182] Multiple horizontal power cables HLIA_VSS can include multiple upper horizontal power cables HLIA_VSS_TOP and multiple lower horizontal power cables HLIA_VSS_BOT. Multiple vertical power cables VLIA_VSS can include multiple upper vertical power cables VLIA_VSS_TOP and multiple lower vertical power cables VLIA_VSS_BOT.

[0183] Referring to Figures 6 to 8, each of the multiple upper horizontal power cables HLIA_VSS_TOP can be located in the upper display area DA_TOP, on the same row as the nth upper link line HLIA_DATA(n)_TOP, separated from the nth upper link line HLIA_DATA(n)_TOP, and extending in a second direction.

[0184] Each of the multiple upper vertical power lines VLIA_VSS_TOP can be located in the upper display area DA_TOP, in the same column as the nth intermediate link line VLIA_DATA(n), spaced apart from the nth intermediate link line VLIA_DATA(n), and extending in the first direction.

[0185] Each of the multiple lower lateral power wirings HLIA_VSS_BOT can be located in the lower display area DA_BOT, on the same row as the nth lower link line HLIA_DATA(n)_BOT, spaced apart from the nth lower link line HLIA_DATA(n)_BOT, and extending in a second direction.

[0186] Each of the multiple lower vertical power supply lines VLIA_VSS_BOT is located in the lower display area DA_BOT and is positioned in the same column as the nth intermediate link line VLIA_DATA(n), but can be positioned separately from the nth intermediate link line VLIA_DATA(n) and extending in the first direction.

[0187] Referring to Figures 6 to 8, the upper horizontal power supply cable HLIA_VSS_TOP can intersect with the (n-1)th intermediate link line VLIA_DATA(n-1). The upper vertical power supply cable VLIA_VSS_TOP can intersect with the (n-1)th upper link line HLIA_DATA(n-1)_TOP. The lower horizontal power supply cable HLIA_VSS_BOT can intersect with the (n-1)th intermediate link line VLIA_DATA(n-1). The lower vertical power supply cable VLIA_VSS_BOT can intersect with the (n-1)th lower link line HLIA_DATA(n-1)_BOT.

[0188] The (n-1)th upper data line DL(n-1)_TOP can be positioned on the side (e.g., the left side) of the nth upper data line DL(n)_TOP in the second direction, and the (n-1)th lower data line DL(n-1)_BOT can be positioned on the side (e.g., the left side) of the nth lower data line DL(n)_BOT in the second direction.

[0189] The (n-1)th upper link line HLIA_DATA(n-1)_TOP can be positioned on the side (e.g., the top side) of the nth upper link line HLIA_DATA(n)_TOP in the first direction. The (n-1)th intermediate link line VLIA_DATA(n-1) can be positioned on the side (e.g., the right side) of the nth intermediate link line VLIA_DATA(n) in the second direction. The (n-1)th lower link line HLIA_DATA(n-1)_BOT can be positioned on the side (e.g., the bottom side) of the nth lower link line HLIA_DATA(n)_BOT in the first direction.

[0190] The upper vertical power supply wiring VLIA_VSS_TOP and the lower vertical power supply wiring VLIA_VSS_BOT can each be placed between two adjacent data lines among multiple data lines DL.

[0191] As mentioned above, the substrate 111 may include an inwardly recessed waist region WA. In this regard, the multiple data lines DL can be classified into a first data line group GR1 having a bypass link line DL_BLL that bypasses the waist region WA within the display region DA, and a second data line group GR2 that does not bypass the waist region WA within the display region DA, is arranged linearly in the first direction, and does not have a bypass link line DL_BLL.

[0192] The first data line group GR1 may include the nth data line DL(n) and the (n-1)th data line DL(n-1). The second data line group GR2 may pass through the upper display area DA_TOP, the middle display area DA_MID, and the lower display area DA_BOT while extending in the first direction.

[0193] As mentioned above, the first data line group GR1 and the second data line group GR2 differ in line shape and line arrangement, and the metal layers formed may also differ. For example, multiple data lines DL belonging to the first data line group GR1 may consist of two or more metal layers. Multiple data lines DL belonging to the second data line group GR2 may consist of one metal layer.

[0194] Figures 11 to 14 are enlarged plan views of the first to fourth connection areas CA1, CA2, CA3, and CA4 in the first area A1 and second area A2 of the display panel 110 according to the embodiment of this disclosure.

[0195] Figure 11 is an enlarged plan view of the first connection area CA1 within the first area A1 in Figure 6, Figure 12 is an enlarged plan view of the second connection area CA2 within the first area A1 in Figure 6, Figure 13 is an enlarged plan view of the third connection area CA3 within the second area A2 in Figure 6, and Figure 14 is an enlarged plan view of the fourth connection area CA4 within the second area A2 in Figure 6.

[0196] Referring to Figure 11, the first connection region CA1 may have the (n-1)th upper data line DL(n-1)_TOP and the nth upper data line DL(n)_TOP extending in the first direction (vertical direction). The (n-1)th upper data line DL(n-1)_TOP may have the (n-1)th data signal Vdata(n-1) applied to it, and the nth upper data line DL(n)_TOP may have the nth data signal Vdata(n) applied to it.

[0197] A vertical power supply cable VLIA_VSS extending in the first direction may be placed on each side of the (n-1)th upper data line DL(n-1)_TOP and the nth upper data line DL(n)_TOP. The vertical power supply cable VLIA_VSS extending in the first direction may be placed between the (n-1)th upper data line DL(n-1)_TOP and the nth upper data line DL(n)_TOP.

[0198] The lateral power wiring HLIA_VSS and the nth upper link line HLIA_DATA(n)_TOP can each be positioned in the second direction (lateral direction). The lateral power wiring HLIA_VSS and the nth upper link line HLIA_DATA(n)_TOP can be positioned on the same line (same row) and spaced apart from each other. The lateral power wiring HLIA_VSS and the nth upper link line HLIA_DATA(n)_TOP can be positioned within the same metal layer.

[0199] The horizontal power cable HLIA_VSS can intersect the (n-1)th upper data line DL(n)_TOP and the vertical power cable VLIA_VSS.

[0200] The lateral power wiring HLIA_VSS and the vertical power wiring VLIA_VSS can be electrically connected via the power connection point CNT_VSS. The lateral power wiring HLIA_VSS and the vertical power wiring VLIA_VSS may be located in different metal layers.

[0201] The nth upper link line HLIA_DATA(n)_TOP can intersect with the nth upper data line DL(n)_TOP and the vertical power supply wiring VLIA_VSS.

[0202] The nth upper data line DL(n)_TOP can be electrically connected to the nth upper link line HLIA_DATA(n)_TOP at the first connection point CNT_DATA(n)_1. The nth upper data line DL(n)_TOP and the nth upper link line HLIA_DATA(n)_TOP may be located in different metal layers.

[0203] The nth data signal Vdata(n), input to the nth upper data line DL(n)_TOP, may be output to the nth upper link line HLIA_DATA(n)_TOP. The nth data signal Vdata(n), input to the nth upper data line DL(n)_TOP, may be supplied to the subpixel SP connected to the nth upper data line DL(n)_TOP.

[0204] A subpixel SP connected to the nth upper data line DL(n)_TOP can be located at the top of the waist region WA.

[0205] Referring to Figure 12, the second connection region CA2 may have the (n+a)th data line DL(n+a) and the (n+a+1)th data line DL(n+a+1) extending in the first direction. The (n+a)th data line DL(n+a) may have the (n+a)th data signal Vdata(n+a) applied to it, and the (n+a+1)th data line DL(n+a+1) may have the (n+a+1)th data signal Vdata(n+a+1) applied to it.

[0206] The vertical power wiring VLIA_VSS is positioned between the (n+a)th data line DL(n+a) and the (n+a+1)th data line DL(n+a+1), and can extend in the first direction.

[0207] The nth intermediate link line VLIA_DATA(n) is located between the (n+a)th data line DL(n+a) and the (n+a+1)th data line DL(n+a+1), and can extend in the first direction.

[0208] Between the (n+a)th data line DL(n+a) and the (n+a+1)th data line DL(n+a+1), the nth intermediate link line VLIA_DATA(n) and the vertical power supply wiring VLIA_VSS may be located on the same line (same column), but may be separated from each other.

[0209] The (n-1)th intermediate link line VLIA_DATA(n-1) can be further positioned on the side (right side) of the (n+a+1)th data line DL(n+a+1) and extend in the first direction.

[0210] The nth upper link line HLIA_DATA(n)_TOP and the lateral power wiring HLIA_VSS can each be positioned in a second direction. The nth upper link line HLIA_DATA(n)_TOP and the lateral power wiring HLIA_VSS can be positioned on the same line (same row) and spaced apart from each other. The nth upper link line HLIA_DATA(n)_TOP and the lateral power wiring HLIA_VSS can be positioned within the same metal layer.

[0211] The nth upper link line HLIA_DATA(n)_TOP can intersect with the (n+a)th data line DL(n+a) and the vertical power supply line VLIA_VSS.

[0212] The nth upper link line HLIA_DATA(n)_TOP can be electrically connected to the nth intermediate link line VLIA_DATA(n) at the second connection point CNT_DATA(n)_2. The nth upper link line HLIA_DATA(n)_TOP and the nth intermediate link line VLIA_DATA(n) may be located in different metal layers.

[0213] The nth data signal Vdata(n), input to the nth upper link line HLIA_DATA(n)_TOP, can be output to the nth intermediate link line VLIA_DATA(n).

[0214] The lateral power wiring HLIA_VSS may intersect with the (n+a+1)th data line DL(n+a+1) and the (n-1)th intermediate link line VLIA_DATA(n-1). The lateral power wiring HLIA_VSS may be located in a different metal layer from the (n+a+1)th data line DL(n+a+1) and the (n-1)th intermediate link line VLIA_DATA(n-1). The lateral power wiring HLIA_VSS may be electrically isolated from the (n+a+1)th data line DL(n+a+1) and the (n-1)th intermediate link line VLIA_DATA(n-1).

[0215] Referring to Figure 13, the third connection region CA3 may have the (n+a)th data line DL(n+a) and the (n+a+1)th data line DL(n+a+1) extending in the first direction. The (n+a)th data line DL(n+a) may have the (n+a)th data signal Vdata(n+a) applied to it, and the (n+a+1)th data line DL(n+a+1) may have the (n+a+1)th data signal Vdata(n+a+1) applied to it.

[0216] The nth intermediate link line VLIA_DATA(n) is located between the (n+a)th data line DL(n+a) and the (n+a+1)th data line DL(n+a+1), and can extend in the first direction.

[0217] The vertical power wiring VLIA_VSS is positioned between the (n+a)th data line DL(n+a) and the (n+a+1)th data line DL(n+a+1), and can extend in the first direction.

[0218] Between the (n+a)th data line DL(n+a) and the (n+a+1)th data line DL(n+a+1), the nth intermediate link line VLIA_DATA(n) and the vertical power supply wiring VLIA_VSS are located on the same line (same column), but can be spaced apart from each other.

[0219] The (n-1)th intermediate link line VLIA_DATA(n-1) can be further positioned on the side (right side) of the (n+a+1)th data line DL(n+a+1) and extend in the first direction.

[0220] The nth lower link line HLIA_DATA(n)_BOT and the lateral power wiring HLIA_VSS can each be positioned in a second direction. The nth lower link line HLIA_DATA(n)_BOT and the lateral power wiring HLIA_VSS can be positioned on the same line (same row) and spaced apart from each other. The nth lower link line HLIA_DATA(n)_BOT and the lateral power wiring HLIA_VSS can be positioned within the same metal layer.

[0221] The nth lower link line HLIA_DATA(n)_BOT can intersect with the (n+a)th data line DL(n+a) and the nth intermediate link line VLIA_DATA(n).

[0222] The nth lower link line HLIA_DATA(n)_BOT can be electrically connected to the nth intermediate link line VLIA_DATA(n) at the third connection point CNT_DATA(n)_3. The nth lower link line HLIA_DATA(n)_BOT and the nth intermediate link line VLIA_DATA(n) may be located in different metal layers.

[0223] The nth data signal Vdata(n), input to the nth intermediate link line VLIA_DATA(n), can be output to the nth lower link line HLIA_DATA(n)_BOT.

[0224] The lateral power wiring HLIA_VSS may intersect with the (n+a+1)th data line DL(n+a+1) and the (n-1)th intermediate link line VLIA_DATA(n-1). The lateral power wiring HLIA_VSS may be located in a different metal layer from the (n+a+1)th data line DL(n+a+1) and the (n-1)th intermediate link line VLIA_DATA(n-1). The lateral power wiring HLIA_VSS may be electrically isolated from the (n+a+1)th data line DL(n+a+1) and the (n-1)th intermediate link line VLIA_DATA(n-1).

[0225] Referring to Figure 14, the fourth connection region CA4 may have an (n-1)th lower data line DL(n-1)_BOT and an nth lower data line DL(n)_BOT extending in the first direction (vertical direction). The (n-1)th lower data line DL(n-1)_BOT may have the (n-1)th data signal Vdata(n-1), and the nth lower data line DL(n)_BOT may have the nth data signal Vdata(n).

[0226] A vertical power supply wiring VLIA_VSS extending in the first direction may be placed on each side of the (n-1)th lower data line DL(n-1)_BOT and the nth lower data line DL(n)_BOT. The vertical power supply wiring VLIA_VSS extending in the first direction may be placed between the (n-1)th lower data line DL(n-1)_BOT and the nth lower data line DL(n)_BOT.

[0227] The lateral power wiring HLIA_VSS and the nth lower link line HLIA_DATA(n)_BOT can each be positioned in the second direction (lateral direction). The lateral power wiring HLIA_VSS and the nth lower link line HLIA_DATA(n)_BOT can be positioned on the same line (same row) and spaced apart from each other. The lateral power wiring HLIA_VSS and the nth lower link line HLIA_DATA(n)_BOT can be positioned within the same metal layer.

[0228] The lateral power cable HLIA_VSS can intersect with the (n-1)th lower data line DL(n-1)_BOT and the vertical power cable VLIA_VSS.

[0229] The lateral power wiring HLIA_VSS and the vertical power wiring VLIA_VSS can be electrically connected via the power connection point CNT_VSS. The lateral power wiring HLIA_VSS and the vertical power wiring VLIA_VSS may be located in different metal layers.

[0230] The nth lower link line HLIA_DATA(n)_BOT can intersect with the nth lower data line DL(n)_BOT and the vertical power supply wiring VLIA_VSS.

[0231] The nth lower link line HLIA_DATA(n)_BOT can be electrically connected to the nth lower data line DL(n)_BOT at the fourth connection point CNT_DATA(n)_4. The nth lower link line HLIA_DATA(n)_BOT and the nth lower data line DL(n)_BOT may be located in different metal layers.

[0232] The nth data signal Vdata(n), input to the nth lower link line HLIA_DATA(n)_BOT, can be output to the nth lower data line DL(n)_BOT. The nth data signal Vdata(n), input to the nth lower data line DL(n)_BOT, can be supplied to the subpixel SP connected to the nth lower data line DL(n)_BOT.

[0233] A subpixel SP connected to the nth lower data line DL(n)_BOT can be located at the bottom of the waist region WA.

[0234] Figures 15 to 18 are cross-sectional views of the first to fourth main regions 1100, 1200, 1300, and 1400 in the first to fourth connection regions CA1, CA2, CA3, and CA4, respectively.

[0235] The laminated structures in the cross-sectional views of Figures 15 to 18 may be similarly included in the laminated structure in the cross-sectional view of Figure 5. Therefore, a description of the same laminated structure in the cross-sectional view of Figure 5 is omitted.

[0236] Signal wiring extending in a first direction (e.g., vertically) and signal wiring extending in a second direction (e.g., horizontally) may be arranged in different metal layers.

[0237] Signal wiring extending in a first direction (e.g., longitudinal direction) may be arranged within a first metal layer, and signal wiring extending in a second direction (e.g., transverse direction) may be arranged within a second metal layer different from the first metal layer.

[0238] Referring to Figures 15 to 18, the nth upper data line DL(n)_TOP, the nth lower data line DL(n)_BOT, and the nth intermediate link line VLIA_DATA(n) can be placed within the first metal layer ML1. However, in the following explanation, Figures 5 and 11 to 14 will be referred to together, and explanations that overlap with the explanations in Figures 5 and 11 to 14 will be omitted.

[0239] Referring to Figures 15 to 18, the nth upper link line HLIA_DATA(n)_TOP and the nth lower link line HLIA_DATA(n)_BOT can be located within the second metal layer ML2. The second metal layer ML2 may be a different metal layer from the first metal layer ML1. For example, the second metal layer ML2 may be a metal layer closer to the substrate 111 than the first metal layer ML1. As another example, the second metal layer ML2 may be a metal layer further away from the substrate 111 than the first metal layer ML1.

[0240] Referring to Figures 15 to 18, the upper vertical power supply wiring VLIA_VSS_TOP and the lower vertical power supply wiring VLIA_VSS_BOT can be arranged within the first metal layer ML1 together with the nth upper data line DL(n)_TOP, the nth lower data line DL(n)_BOT, and the nth intermediate link line VLIA_DATA(n).

[0241] Referring to Figures 15 to 18, the upper lateral power supply wiring HLIA_VSS_TOP and the lower lateral power supply wiring HLIA_VSS_BOT can be placed together with the nth upper link line HLIA_DATA(n)_TOP and the nth lower link line HLIA_DATA(n)_BOT within a second metal layer ML2, which is different from the first metal layer ML1.

[0242] Of the first metal layer ML1 and the second metal layer ML2, one may be a source-drain metal layer SDML on which the source or drain electrode of the transistor in the display region DA is located, and the other may be a gate metal layer GML on which the gate electrode of the transistor in the display region DA is located.

[0243] For example, the first metal layer ML1 may be a source-drain metal layer SDML, and the second metal layer ML2 may be a gate metal layer GML. Another example is that the first metal layer ML1 may be a gate metal layer GML, and the second metal layer ML2 may be a source-drain metal layer SDML. Figures 15 to 18 show an example where the first metal layer ML1 is a source-drain metal layer SDML and the second metal layer ML2 is a gate metal layer GML.

[0244] The source-drain metal layer SDML, corresponding to the first metal layer ML1, can be located between the interlayer insulating layer 540 and the planarizing layer 550.

[0245] The gate metal layer GML, corresponding to the second metal layer ML2, can be located between the gate insulating layer 530 and the interlayer insulating layer 540.

[0246] Referring to Figure 15, the (n-1)th upper data line DL(n-1)_TOP and the nth upper data line DL(n)_TOP can be placed on the interlayer insulating layer 540.

[0247] The (n-1)th upper data line DL(n-1)_TOP and the nth upper data line DL(n)_TOP can be superimposed on the first pixel electrode PE1 of the first subpixel and the second pixel electrode PE2 of the second subpixel, respectively.

[0248] The first pixel electrode PE1 of the first subpixel and the second pixel electrode PE2 of the second subpixel can be placed on the planarization layer 550. A bank 560 can be placed on top of a portion of each of the first pixel electrode PE1 of the first subpixel and the second pixel electrode PE2 of the second subpixel.

[0249] The first pixel electrode PE1 of the first subpixel may be electrically connected to the first source electrode S1 or the first drain electrode D1 of the first transistor of the first subpixel. The second pixel electrode PE2 of the second subpixel may be electrically connected to the second source electrode S2 or the second drain electrode D2 of the second transistor of the second subpixel.

[0250] The (n-1)th upper data line DL(n-1)_TOP and the nth upper data line DL(n)_TOP can be placed together within the source-drain metal layer SDML corresponding to the first metal layer ML1.

[0251] The source-drain metal layer SDML corresponding to the first metal layer ML1 may be a metal layer on which the first source electrode S1 or first drain electrode D1 of the first transistor of the first subpixel and the second source electrode S2 or second drain electrode D2 of the second transistor of the second subpixel are disposed.

[0252] The vertical power supply wiring VLIA_VSS may be placed together with the (n-1)th upper data line DL(n-1)_TOP and the nth upper data line DL(n)_TOP within the source-drain metal layer SDML corresponding to the first metal layer ML1.

[0253] The lateral power supply line HLIA_VSS and the nth upper link line HLIA_DATA(n)_TOP may be placed together within the gate metal layer GML corresponding to the second metal layer ML2.

[0254] The gate metal layer GML, corresponding to the second metal layer ML2, may be a metal layer on which the first gate electrode of the first transistor of the first subpixel and the second gate electrode of the second transistor of the second subpixel are located.

[0255] The nth upper data line DL(n)_TOP can be electrically connected to the nth upper link line HLIA_DATA(n)_TOP via a first contact hole in the interlayer insulation layer 540. The first contact hole in the interlayer insulation layer 540 can be located at a first connection point CNT_DATA(n)_1.

[0256] The vertical power wiring VLIA_VSS can be electrically connected to the horizontal power wiring HLIA_VSS via a first power contact hole in the interlayer insulation layer 540. The first power contact hole in the interlayer insulation layer 540 can be located at the first power connection point CNT_VSS.

[0257] Referring to Figure 16, the nth intermediate link line VLIA_DATA(n), the (n-1)th intermediate link line VLIA_DATA(n-1), the (n+a)th data line DL(n+a), and the (n+a+1)th data line DL(n+a+1) can be placed on the interlayer insulating layer 540.

[0258] The nth intermediate link line VLIA_DATA(n) and the (n-1)th intermediate link line VLIA_DATA(n-1) can be superimposed on the third pixel electrode PE3 of the third subpixel and the fourth pixel electrode PE4 of the fourth subpixel, respectively.

[0259] The third pixel electrode PE3 of the third subpixel and the fourth pixel electrode PE4 of the fourth subpixel can be placed on the planarization layer 550. A bank 560 can be placed above a portion of each of the third pixel electrode PE3 of the third subpixel and the fourth pixel electrode PE4 of the fourth subpixel.

[0260] The third pixel electrode PE3 of the third subpixel can be electrically connected to the third source electrode S3 or the third drain electrode D3 of the third transistor of the third subpixel. The fourth pixel electrode PE4 of the fourth subpixel can be electrically connected to the fourth source electrode S4 or the fourth drain electrode D4 of the fourth transistor of the fourth subpixel.

[0261] The nth intermediate link line VLIA_DATA(n) and the (n-1)th intermediate link line VLIA_DATA(n-1) can be placed together within the source-drain metal layer SDML corresponding to the first metal layer ML1.

[0262] The source-drain metal layer SDML, corresponding to the first metal layer ML1, may be a metal layer on which the third source electrode S3 or third drain electrode D3 of the third transistor of the third subpixel and the fourth source electrode S4 or fourth drain electrode D4 of the fourth transistor of the fourth subpixel are located.

[0263] The (n+a)th data line DL(n+a) and the (n+a+1)th data line DL(n+a+1) can be placed together with the nth intermediate link line VLIA_DATA(n) and the (n-1)th intermediate link line VLIA_DATA(n-1) within the source-drain metal layer SDML corresponding to the first metal layer ML1.

[0264] The nth upper link line HLIA_DATA(n)_TOP and the lateral power wiring HLIA_VSS can be placed together within the gate metal layer GML corresponding to the second metal layer ML2.

[0265] The gate metal layer GML, corresponding to the second metal layer ML2, may be a metal layer on which the third gate electrode of the third transistor of the third subpixel and the fourth gate electrode of the fourth transistor of the fourth subpixel are located.

[0266] The nth intermediate link line VLIA_DATA(n) can be electrically connected to the nth upper link line HLIA_DATA(n)_TOP via a second contact hole in the interlayer insulation layer 540. The second contact hole in the interlayer insulation layer 540 can be located at a second connection point CNT_DATA(n)_2.

[0267] Referring to Figure 17, the nth intermediate link line VLIA_DATA(n), the (n-1)th intermediate link line VLIA_DATA(n-1), the (n+a)th data line DL(n+a), and the (n+a+1)th data line DL(n+a+1) can be placed on the interlayer insulating layer 540.

[0268] The nth intermediate link line VLIA_DATA(n) and the (n-1)th intermediate link line VLIA_DATA(n-1) can be superimposed on the fifth pixel electrode PE5 of the fifth subpixel and the sixth pixel electrode PE6 of the sixth subpixel, respectively.

[0269] The fifth pixel electrode PE5 of the fifth subpixel and the sixth pixel electrode PE6 of the sixth subpixel can be placed on the planarization layer 550. A bank 560 can be placed on top of a portion of each of the fifth pixel electrode PE5 of the fifth subpixel and the sixth pixel electrode PE6 of the sixth subpixel.

[0270] The fifth pixel electrode PE5 of the fifth subpixel can be electrically connected to the fifth source electrode S5 or the fifth drain electrode D5 of the fifth transistor of the fifth subpixel. The sixth pixel electrode PE6 of the sixth subpixel can be electrically connected to the sixth source electrode S6 or the sixth drain electrode D6 of the sixth transistor of the sixth subpixel.

[0271] The nth intermediate link line VLIA_DATA(n) and the (n-1)th intermediate link line VLIA_DATA(n-1) can be placed together within the source-drain metal layer SDML corresponding to the first metal layer ML1.

[0272] The source-drain metal layer SDML, corresponding to the first metal layer ML1, may be a metal layer on which the fifth source electrode S5 or fifth drain electrode D5 of the fifth transistor of the fifth subpixel and the sixth source electrode S6 or sixth drain electrode D6 of the sixth transistor of the sixth subpixel are located.

[0273] The (n+a)th data line DL(n+a) and the (n+a+1)th data line DL(n+a+1) can be placed together with the nth intermediate link line VLIA_DATA(n) and the (n-1)th intermediate link line VLIA_DATA(n-1) within the source-drain metal layer SDML corresponding to the first metal layer ML1.

[0274] The nth lower link line HLIA_DATA(n)_BOT and the lateral power supply wiring HLIA_VSS can be placed together within the gate metal layer GML corresponding to the second metal layer ML2.

[0275] The gate metal layer GML, corresponding to the second metal layer ML2, may be a metal layer on which the fifth gate electrode of the fifth transistor in the fifth subpixel and the sixth gate electrode of the sixth transistor in the sixth subpixel are located.

[0276] The nth intermediate link line VLIA_DATA(n) can be electrically connected to the nth lower link line HLIA_DATA(n)_BOT via a third contact hole in the interlayer insulation layer 540. The third contact hole in the interlayer insulation layer 540 can be located at a third connection point CNT_DATA(n)_3.

[0277] Referring to FIG. 18, the (n - 1)-th lower data line DL(n - 1)_BOT and the n-th lower data line DL(n)_BOT can be disposed on the interlayer insulating layer 540.

[0278] (n - 1)-th lower data line DL(n - 1)_BOT and the n-th lower data line DL(n)_BOT can be respectively overlapped with the 8th pixel electrode PE8 of the 8th sub-pixel and the 7th pixel electrode PE7 of the 7th sub-pixel.

[0279] The 7th pixel electrode PE7 of the 7th sub-pixel and the 8th pixel electrode PE8 of the 8th sub-pixel can be disposed on the planarization layer 550. A bank 560 can be disposed on the upper part of each of the 7th pixel electrode PE7 of the 7th sub-pixel and the 8th pixel electrode PE8 of the 8th sub-pixel.

[0280] The 7th pixel electrode PE7 of the 7th sub-pixel can be electrically connected to the 7th source electrode S7 or the 7th drain electrode D7 of the 7th transistor of the 7th sub-pixel. The 8th pixel electrode PE8 of the 8th sub-pixel can be electrically connected to the 8th source electrode S8 or the 8th drain electrode D8 of the 8th transistor of the 8th sub-pixel.

[0281] (n - 1)-th lower data line DL(n - 1)_BOT and the n-th lower data line DL(n)_BOT can be disposed together in the source-drain metal layer SDML corresponding to the first metal layer ML1. Here, the source-drain metal layer SDML corresponding to the first metal layer ML1 can be the metal layer in which the 7th source electrode S7 or the 7th drain electrode D7 of the 7th transistor of the 7th sub-pixel and the 8th source electrode S8 or the 8th drain electrode D8 of the​​​The vertical power supply wiring VLIA_VSS may be placed together with the (n-1)th lower data line DL(n-1)_BOT and the nth lower data line DL(n)_BOT within the source-drain metal layer SDML corresponding to the first metal layer ML1.

[0283] The lateral power supply line HLIA_VSS and the nth lower link line HLIA_DATA(n)_BOT can be placed together within the gate metal layer GML corresponding to the second metal layer ML2. Here, the gate metal layer GML corresponding to the second metal layer ML2 may be the metal layer on which the seventh gate electrode of the seventh transistor of the seventh subpixel and the eighth gate electrode of the eighth transistor of the eighth subpixel are located.

[0284] The nth lower data line DL(n)_BOT can be electrically connected to the nth lower link line HLIA_DATA(n)_BOT via a fourth contact hole in the interlayer insulation layer 540. The fourth contact hole in the interlayer insulation layer 540 can be located at a fourth connection point CNT_DATA(n)_4.

[0285] The vertical power wiring VLIA_VSS can be electrically connected to the horizontal power wiring HLIA_VSS via a fourth power contact hole in the interlayer insulation layer 540. The fourth power contact hole in the interlayer insulation layer 540 can be located at the fourth power connection point CNT_VSS.

[0286] Figures 19 to 22 are cross-sectional views of the first to fourth main regions in the first to fourth connection regions.

[0287] Referring to Figures 19 to 22, the nth upper data line DL(n)_TOP, the nth lower data line DL(n)_BOT, and the nth intermediate link line VLIA_DATA(n) can be placed within the first metal layer ML1.

[0288] Referring to Figures 19 to 22, the nth upper link line HLIA_DATA(n)_TOP and the nth lower link line HLIA_DATA(n)_BOT can be located within a second metal layer ML2, which is different from the first metal layer ML1.

[0289] The cross-sectional views in Figures 19 to 22 correspond to the cross-sectional views in Figures 15 to 18, respectively. The only difference is the type of the second metal layer ML2 where the signal wiring (lateral wiring) extending in the second direction is located; everything else is the same. Therefore, explanations that are identical to those for the cross-sectional views in Figures 15 to 18 are omitted.

[0290] Referring to Figures 19 to 22, the upper vertical power supply wiring VLIA_VSS_TOP and the lower vertical power supply wiring VLIA_VSS_BOT can be arranged within the first metal layer ML1 together with the nth upper data line DL(n)_TOP, the nth lower data line DL(n)_BOT, and the nth intermediate link line VLIA_DATA(n).

[0291] Referring to Figures 19 to 22, the upper lateral power supply wiring HLIA_VSS_TOP and the lower lateral power supply wiring HLIA_VSS_BOT can be placed together with the nth upper link line HLIA_DATA(n)_TOP and the nth lower link line HLIA_DATA(n)_BOT within a second metal layer ML2, which is different from the first metal layer ML1.

[0292] Of the first metal layer ML1 and the second metal layer ML2, one may be a source-drain metal layer SDML on which the source or drain electrode of a transistor in the display region DA is located, and the other may be a capacitor electrode metal layer TML on which one of two or more capacitor electrodes constituting a storage capacitor in the display region DA is located.

[0293] For example, the first metal layer ML1 may be a source-drain metal layer SDML, and the second metal layer ML2 may be a capacitor electrode metal layer TML. Another example is that the first metal layer ML1 may be a capacitor electrode metal layer TML, and the second metal layer ML2 may be a source-drain metal layer SDML. Figures 19 to 22 show an example where the first metal layer ML1 is a source-drain metal layer SDML and the second metal layer ML2 is a capacitor electrode metal layer TML.

[0294] The source-drain metal layer SDML, corresponding to the first metal layer ML1, can be located between the interlayer insulating layer 540 and the planarization layer 550. The capacitor electrode metal layer TML, corresponding to the second metal layer ML2, can be located between the first interlayer insulating layer 541 and the second interlayer insulating layer 542.

[0295] The first contact hole to which the nth upper data line DL(n)_TOP and the nth upper link line HLIA_DATA(n)_TOP are electrically connected may be a contact hole in the second interlayer insulating layer 542.

[0296] The second contact hole to which the nth intermediate link line VLIA_DATA(n) and the nth upper link line HLIA_DATA(n)_TOP are electrically connected may be a contact hole in the second interlayer insulating layer 542.

[0297] A third contact hole, to which the nth intermediate link line VLIA_DATA(n) and the nth lower link line HLIA_DATA(n)_BOT are electrically connected, may be a contact hole in the second interlayer insulating layer 542.

[0298] The fourth contact hole to which the nth lower data line DL(n)_BOT and the nth lower link line HLIA_DATA(n)_BOT are electrically connected may be a contact hole in the second interlayer insulating layer 542.

[0299] The power contact hole where the vertical power wiring VLIA_VSS and the horizontal power wiring HLIA_VSS are electrically connected can be a contact hole in the second interlayer insulating layer 542.

[0300] Above, the data link structure capable of bezel reduction according to the embodiment of the present disclosure and the power wiring structure associated therewith have been described. Below, the data link structure capable of bezel reduction according to the embodiment of the present disclosure and the power wiring structure associated therewith will be briefly described.

[0301] The display device 100 according to the embodiment of the present disclosure can include a substrate 111 including a display area DA, a first signal wiring disposed on the substrate 111, extending in a first direction from the display area DA, and disposed within the first metal layer ML1, and a second signal wiring disposed on the substrate 111, extending in a second direction different from the first direction from the display area DA, and disposed within a second metal layer ML2 different from the first metal layer ML1.

[0302] The display device 100 according to the embodiment of the present disclosure can further include a third signal wiring disposed on the substrate 111, extending in a first direction from the display area DA, and disposed within the first metal layer ML1, a fourth signal wiring disposed on the substrate 111, extending in a second direction from the display area DA, and disposed within the second metal layer ML2, and a fifth signal wiring disposed on the substrate 111, extending in a first direction from the display area DA, and disposed within the first metal layer ML1.

[0303] The first to fifth signal wirings can be electrically connected. The second signal wiring can electrically connect the first signal wiring and the third signal wiring. The third signal wiring can electrically connect the second signal wiring and the fourth signal wiring. The fourth signal wiring can electrically connect the third signal wiring and the fifth signal wiring.

[0304] The first signal wire, the third signal wire, and the fifth signal wire are each wires extending in the first direction, and the second signal wire and the fourth signal wire may each be wires extending in the second direction. Here, the first direction and the second direction may be different directions and may be relative directions. In one example, the first direction may be the vertical direction and the second direction may be the horizontal direction. In another example, the first direction may be the horizontal direction and the second direction may be the vertical direction. For the sake of explanation, the following explanation will use the example that the first direction is the vertical direction and the second direction is the horizontal direction. However, it is not limited to this.

[0305] For example, if the first direction is vertical and the second direction is horizontal, the first signal wire, the third signal wire, and the fifth signal wire may each be vertical wires extending in the first direction (vertical), and the second signal wire and the fourth signal wire may each be horizontal wires extending in the second direction (horizontal). As another example, if the first direction is horizontal and the second direction is vertical, the first signal wire, the third signal wire, and the fifth signal wire may each be horizontal wires extending in the first direction (horizontal), and the second signal wire and the fourth signal wire may each be vertical wires extending in the second direction (vertical).

[0306] For example, in Figures 6 to 22, the nth upper data line DL(n)_TOP may be the first signal line, the nth upper link line HLIA_DATA(n)_TOP may be the second signal line, the nth intermediate link line VLIA_DATA(n) may be the third signal line, the nth lower link line HLIA_DATA(n)_BOT may be the fourth signal line, and the nth lower data line DL(n)_BOT may be the fifth signal line.

[0307] The substrate 111 may include an inwardly recessed waist region WA. The waist region WA may be located on one side of the third signal trace.

[0308] For example, the display device 100 according to the embodiments of this disclosure may be at least one wearable device from among virtual reality (VR) devices, augmented reality (AR) devices, mixed reality (MR) devices, and extended reality (XR) devices.

[0309] Figure 23 shows the detail area included in the waist area WA of the display panel 110 according to an embodiment of the present disclosure.

[0310] Referring to Figure 23, if the display panel 110 according to the embodiment of the present disclosure has a data link structure that enables bezel reduction, the data link structure may be located within the display area DA, and the non-display area NDA included in the waist area WA does not need to have wiring to which data signals are applied.

[0311] If the display panel 110 according to the embodiment of this disclosure has a data link structure that enables bezel reduction, the non-display area NDA included in the waist area WA does not include the data link area DLLA.

[0312] If the display panel 110 according to an embodiment of the present disclosure has a data link structure that enables bezel reduction, the non-display area NDA included in the waist area WA may include at least one of the following: a drive power wiring area PLA where drive power wiring is arranged; a gate-in-panel circuit area GIPA where a gate-in-panel (GIP) type gate drive circuit, which is arranged in a gate-in-panel circuit; a base voltage wiring area VSSA where a base voltage line VSSL is arranged; and a crack stopper area CSA where a crack stopper structure is arranged.

[0313] The drive power wiring area PLA can accommodate gate drive-related link wiring connected to the gate-in-panel circuit, and drive power wiring for transmitting various drive power supplies (e.g., initialization voltage, reference voltage, etc.) to the subpixel SP.

[0314] The non-display area NDA included in the waist area WA may further include a connection area CLA where the drive power wiring located in the drive power wiring area PLA is extended and gate lines are located to transmit the gate signal output from the gate-in-panel circuit to the subpixel SP.

[0315] The non-display area NDA included in the waist area WA may further include a first empty space FA1 between the base voltage wiring area VSSA and the crack stopper area CSA, and a second empty space FA2 between the crack stopper area CSA and the trimming line. Here, the trimming line may correspond to the cutting line of the substrate 111.

[0316] The non-display area NDA included in the waist area WA may further include a connection area CLA where the drive power wiring located in the drive power wiring area PLA is extended and gate lines are located to transmit the gate signal output from the gate-in-panel circuit to the subpixel SP.

[0317] Figure 24 shows the structure of the non-display area NDA within the first area A1 of the display panel 110 according to an embodiment of the present disclosure.

[0318] Figure 24 is a plan view of the uppermost region UMA within the first region A1 in Figure 1. The uppermost region UMA may include a non-display region NDA outside the display region DA.

[0319] The non-display area (NDA) within the uppermost region (UMA) may include a first link region (LA1) where multiple first links (LINK1) are located, an outer circuit region (OCA) where test transistors (AP TFT) and electrostatic discharge pattern structures (ESD) are located, a second link region (LA2) where multiple second links (LINK2) are located, and a pad region (PA) where multiple pads (PAD) are located.

[0320] Multiple first links LINK1 can be electrically connected to multiple data lines DL located in the display area DA. Multiple second links LINK2 can be electrically connected to multiple first links LINK1.

[0321] The display device according to the embodiment of this disclosure can be described as follows.

[0322] A display device according to an embodiment of the present disclosure includes a display area and a non-display area outside the display area, the display area includes an upper display area, a lower display area, and an intermediate display area between the upper and lower display areas, and the non-display area may include a substrate including a pad area adjacent to the upper display area more than the intermediate display area, and a plurality of data lines arranged in the display area.

[0323] The nth data line among multiple data lines may include an nth upper data line located in the upper display area and extending in the first direction, an nth lower data line located in the lower display area and extending in the first direction, and an nth bypass link line that passes through the intermediate display area and electrically connects the nth upper data line and the nth lower link line.

[0324] At the first boundary line between the upper display area and the middle display area, the width of the middle display area may narrow as you approach the center of the middle display area. At the second boundary line between the lower display area and the middle display area, the width of the middle display area may narrow as you approach the center of the middle display area.

[0325] The nth bypass link line can be positioned to bypass the inwardly recessed waist region within the intermediate display area.

[0326] The maximum width of the intermediate display area may be smaller than the maximum width of the upper display area and the maximum width of the lower display area.

[0327] The nth bypass link line may include an nth upper link line located in the display area, electrically connected to the nth upper data line, and extending in a second direction different from the first direction; an nth lower link line located in the display area, electrically connected to the nth lower data line, and extending in the second direction; and an nth intermediate link line located in the display area, electrically connecting the nth upper link line and the nth lower link line, and extending in the first direction.

[0328] The nth upper link line is positioned in the upper display area, the nth lower link line is positioned in the lower display area, and the nth intermediate link line can pass through the intermediate display area in the first direction.

[0329] Each of two or more data lines, including the nth data line among multiple data lines, may include an upper data line located in the upper display area and extending in the first direction, a lower data line located in the lower display area and extending in the first direction, and a bypass link line that passes through the intermediate display area and electrically connects the upper data line and the lower data line.

[0330] Each bypass link line of two or more data lines may include an upper link line located in the display area, electrically connected to the upper data line and extending in a second direction different from the first direction; a lower link line located in the display area, electrically connected to the lower data line and extending in the second direction; and an intermediate link line located in the display area, electrically connecting the upper and lower link lines and extending in the first direction.

[0331] The display area may include an upper link area where the upper link lines included in each bypass link line of two or more data lines are located, a lower link area where the lower link lines included in each bypass link line of two or more data lines are located, and an intermediate link area where the intermediate link lines included in each bypass link line of two or more data lines are located.

[0332] The upper link region is included in the upper display region, the lower link region is included in the lower display region, and the intermediate link region may be included in the upper display region, the intermediate display region, and the lower display region. For example, the upper link region may have the shape of a first triangle, the lower link region may have the shape of a second triangle, and the intermediate link region may have the shape of a quadrilateral. For example, the shapes of the first triangle and the second triangle may be symmetrical to each other based on the intermediate display region. The intermediate link region may have the shape of a trapezoid.

[0333] The display device according to the embodiments of this disclosure may further include power supply wiring arranged in a mesh pattern within the display area. A voltage can be applied to the power supply wiring such that the voltage level is constant over time. For example, the voltage applied to the power supply wiring may be the voltage applied to a common electrode.

[0334] The power wiring may include upper horizontal power wiring located in the upper display area, in the same row as the nth upper link line, spaced apart from the nth upper link line, and extending in a second direction; upper vertical power wiring located in the upper display area, in the same column as the nth intermediate link line, spaced apart from the nth intermediate link line, and extending in a first direction; lower horizontal power wiring located in the lower display area, in the same row as the nth lower link line, spaced apart from the nth lower link line, and extending in a second direction; and lower vertical power wiring located in the lower display area, in the same column as the nth intermediate link line, but spaced apart from the nth intermediate link line, and extending in a first direction.

[0335] The upper horizontal power wiring can cross the (n-1)th intermediate link line. The upper vertical power wiring can cross the (n-1)th upper link line. The lower horizontal power wiring can cross the (n-1)th intermediate link line. The lower vertical power wiring can cross the (n-1)th lower link line.

[0336] The (n-1)th upper link line can be positioned on the side of the nth upper link line in the first direction. The (n-1)th intermediate link line can be positioned on the side of the nth intermediate link line in the second direction. The (n-1)th lower link line can be positioned on the side of the nth lower link line in the first direction.

[0337] The upper vertical power wiring and the lower vertical power wiring can each be placed between two adjacent data lines among multiple data lines.

[0338] The upper and lower vertical power wiring can be arranged within the first metal layer together with the nth upper data line, the nth lower data line, and the nth intermediate link line. The upper and lower vertical power wiring, the nth upper data line, the nth lower data line, and the nth intermediate link line may be vertical wiring.

[0339] The upper and lower lateral power wiring, along with the nth upper and nth lower link lines, may be placed within a second metal layer. The second metal layer may be a different metal layer from the first metal layer. In one example, the second metal layer may be a metal layer closer to the substrate than the first metal layer. In another example, the second metal layer may be a metal layer further from the substrate than the first metal layer. The upper and lower lateral power wiring, the nth upper link line, and the nth lower link line may be lateral wiring.

[0340] A longitudinal wiring including the nth upper data line, the nth lower data line, and the nth intermediate link line can be placed within the first metal layer. A transverse wiring including the nth upper link line and the nth lower link line can be placed within the second metal layer.

[0341] As an example, one of the first and second metal layers may be a source-drain metal layer on which the source or drain electrode of the transistor in the display area is located, and the other may be a gate metal layer on which the gate electrode of the transistor in the display area is located.

[0342] As another example, one of the first and second metal layers may be a source-drain metal layer on which the source or drain electrode of a transistor in the display area is located, and the other may be a capacitor electrode metal layer on which one of two or more capacitor electrodes constituting a storage capacitor in the display area is located.

[0343] The substrate may include an inwardly recessed waist region.

[0344] Multiple data lines can be classified into a first data line group having a bypass link line that bypasses the waist area within the display area, and a second data line group not having a bypass link line that bypasses the waist area within the display area. The first data line group may contain an nth data line. Data lines included in the second data line group may be arranged in a straight line. Data lines included in the second data line group may pass through the upper display area, the middle display area, and the lower display area while extending in the first direction.

[0345] The substrate may include a first region including an upper display area, a second region including a lower display area, and a third region including an intermediate display area.

[0346] The first region may include a pad region. The third region may include an inwardly recessed waist region. The non-display region included in the waist region does not need to contain wiring to which data signals are applied.

[0347] The non-display area included in the waist region may include at least one of the following: a drive power wiring area where drive power wiring is located; a gate in panel circuit area where gate in panel circuits are located; a base voltage wiring area where base voltage wiring is located; and a crack stopper area where crack stopper structures are located.

[0348] The display device is a glasses-type wearable device, and the waist area can correspond to the position of the user's nose. For example, the waist area can correspond to the part that rests on the user's nose.

[0349] A display device according to an embodiment of the present disclosure may include a substrate including a display area, a first signal wiring disposed on the substrate, extending in a first direction within the display area and located within a first metal layer, and a second signal wiring disposed on the substrate, extending in a second direction different from the first direction within the display area and located within a second metal layer different from the first metal layer.

[0350] The display device according to the embodiments of the present disclosure may further include a third signal wiring disposed on a substrate, extending in a first direction in the display area and located within a first metal layer; a fourth signal wiring disposed on a substrate, extending in a second direction in the display area and located within a second metal layer; and a fifth signal wiring disposed on a substrate, extending in a first direction in the display area and located within a first metal layer.

[0351] The third to fifth signal lines can be electrically connected. For example, the first to fifth signal lines may be data lines to which data signals are applied.

[0352] The substrate may include an inwardly recessed waist region. The waist region may be located on one side of the third signal trace.

[0353] According to embodiments of this disclosure, a display device having a data link structure that enables bezel reduction can be provided by designing the display area to arrange data lines or link lines for connecting them.

[0354] According to embodiments of this disclosure, a power wiring structure in which power wiring is arranged in a mesh pattern within the display area can reduce the resistance of the power wiring, improve the power supply characteristics via the power wiring, thereby improving display driving performance and providing a display device that can be driven with low power.

[0355] According to embodiments of this disclosure, by having a data link structure that enables bezel reduction and a power supply wiring structure that works in conjunction with it, it is not necessary to separately form the data link structure and the power supply wiring structure, thus providing a display device that enables process optimization.

[0356] According to embodiments of this disclosure, it is possible to provide a heterogeneous integrated display type display device having a data link structure that enables bezel reduction.

[0357] According to embodiments of this disclosure, a display device as a wearable device having a data link structure capable of reducing the bezel can be provided. Here, the wearable device may include virtual reality (VR) devices, augmented reality (AR) devices, mixed reality (MR) devices, or extended reality (XR) devices.

[0358] The above description is merely illustrative of the technical concept of this disclosure, and any person with ordinary skill in the art to which this disclosure belongs could make various modifications and variations without departing from the essential characteristics of this disclosure. Furthermore, the embodiments shown in this disclosure are for illustrative purposes only and not to limit the technical concept of this disclosure, and therefore the scope of the technical concept of this disclosure is not limited by these embodiments. [Explanation of Symbols]

[0359] 100:Display device 110: Display Panel 111: Circuit board 120: Drive circuit 130: Flexible Printed Circuit Board 140: Printed circuit board A1: First area A2: Second domain A3: Third Domain WA: West Area DA_TOP:Top display area DA_MID: Intermediate display area DA_BOT: Bottom display area

Claims

1. A substrate, and a non-display area outside the display area, wherein the display area includes an upper display area, a lower display area, and an intermediate display area between the upper and lower display areas, and the non-display area includes a pad area closer to the upper display area than the intermediate display area, and Multiple data lines arranged in the aforementioned display area Includes, Of the aforementioned multiple data lines, the nth data line is: The nth upper data line, which is located in the upper display area and extends in the first direction, The nth lower data line is located in the lower display area and extends in the first direction, and A display device including an nth bypass link line that passes through the intermediate display area and electrically connects the nth upper data line and the nth lower data line.

2. At the first boundary line between the upper display area and the intermediate display area, the width of the intermediate display area narrows as you approach the center of the intermediate display area. At the second boundary line between the lower display area and the intermediate display area, the width of the intermediate display area narrows as you approach the center of the intermediate display area. The display device according to claim 1, wherein the nth bypass link line is arranged to bypass a recessed waist region within the intermediate display area.

3. The nth bypass link line is, An nth upper link line is positioned in the display area, electrically connected to the nth upper data line, and extends in a second direction different from the first direction, An nth lower link line is positioned in the display area, electrically connected to the nth lower data line, and extends in the second direction, The display device according to claim 1, comprising an nth intermediate link line arranged in the display area, electrically connecting the nth upper link line and the nth lower link line, and extending in the first direction.

4. The display device according to claim 3, wherein the nth upper link line is located in the upper display area, the nth lower link line is located in the lower display area, and the nth intermediate link line passes through the intermediate display area in the first direction.

5. Each of the two or more data lines among the plurality of data lines, including the nth data line, An upper data line is arranged in the upper display area and extends in the first direction, A lower data line is arranged in the lower display area and extends in the first direction, It includes a bypass link line that passes through the intermediate display area and electrically connects the upper data line and the lower data line, Each of the two or more data lines mentioned above has a bypass link line, An upper link line is positioned in the display area, electrically connected to the upper data line, and extends in a second direction different from the first direction. A lower link line is positioned in the display area, electrically connected to the lower data line, and extends in the second direction, Arranged in the display area, electrically connecting the upper link line and the lower link line, and including an intermediate link line extending in the first direction, The aforementioned display area is The upper link region in which the upper link lines included in each of the two or more bypass link lines are located, The lower link region in which the lower link lines included in each of the two or more data lines are arranged, The intermediate link region includes an intermediate link line in which an intermediate link line is located within each of the two or more bypass link lines of the aforementioned data lines, The aforementioned upper link area is included in the aforementioned upper display area, The aforementioned lower link area is included in the aforementioned lower display area, The display device according to claim 1, wherein the intermediate link region is included in the upper display region, the intermediate display region, and the lower display region.

6. The upper link region has the shape of a first triangle, The lower link region has the shape of a second triangle, The display device according to claim 5, wherein the intermediate link region has a rectangular shape.

7. The shape of the first triangle and the shape of the second triangle are symmetrical with respect to the intermediate display area. The display device according to claim 6, wherein the intermediate link region has a trapezoidal shape.

8. The display device according to claim 3, further comprising power supply wiring arranged in a mesh pattern within the display area and to which a certain level of voltage is applied.

9. The aforementioned power supply wiring is An upper lateral power wiring located in the upper display area, in the same row as the nth upper link line, spaced apart from the nth upper link line, and extending in the second direction, An upper vertical power wiring located in the upper display area, in the same row as the nth intermediate link line, spaced apart from the nth intermediate link line, and extending in the first direction, A lower lateral power wiring is located in the lower display area, in the same row as the nth lower link line, spaced apart from the nth lower link line, and extending in the second direction, and The display device according to claim 8, further comprising a lower vertical power supply wiring located in the lower display area, in the same row as the nth intermediate link line, spaced apart from the nth intermediate link line, and extending in the first direction.

10. The aforementioned upper horizontal power supply wiring intersects with the (n-1)th intermediate link line, The aforementioned upper vertical power wiring intersects with the (n-1)th upper link line, The aforementioned lower horizontal power wiring intersects with the (n-1)th intermediate link line, The aforementioned lower vertical power supply wiring intersects with the (n-1)th lower link line, The (n-1)th upper link line is positioned on the side of the nth upper link line in the first direction, The (n-1)th intermediate link line is positioned on the side of the nth intermediate link line in the second direction. The display device according to claim 9, wherein the (n-1)th lower link line is positioned on the side of the nth lower link line in the first direction.

11. The display device according to claim 9, wherein the upper vertical power wiring and the lower vertical power wiring are each arranged between two adjacent data lines among the plurality of data lines.

12. The upper vertical power wiring and the lower vertical power wiring are arranged within the first metal layer together with the nth upper data line, the nth lower data line, and the nth intermediate link line. The display device according to claim 9, wherein the upper horizontal power wiring and the lower horizontal power wiring are arranged together with the nth upper link line and the nth lower link line in a second metal layer different from the first metal layer.

13. The nth upper data line, the nth lower data line, and the nth intermediate link line are arranged within the first metal layer. The display device according to claim 4, wherein the nth upper link line and the nth lower link line are arranged in a second metal layer different from the first metal layer.

14. Of the first metal layer and the second metal layer, One is a source-drain metal layer on which the source electrode or drain electrode of the transistor within the display area is arranged. The display device according to claim 13, wherein the other is a gate metal layer on which the gate electrodes of the transistors in the display area are arranged.

15. Of the first metal layer and the second metal layer, One is a source-drain metal layer on which the source electrode or drain electrode of the transistor within the display area is arranged. The display device according to claim 13, wherein the other is a capacitor electrode metal layer on which one of two or more capacitor electrodes constituting the storage capacitor in the display area is arranged.

16. The substrate includes an inwardly recessed waist region, The aforementioned multiple data lines are, A first data line group having a bypass link line that bypasses the waist region within the display area, A second data line group that does not have a bypass link line that bypasses the waist region within the display region, The first data line group includes the nth data line, The display device according to claim 1, wherein the data lines included in the second data line group pass through the upper display area, the intermediate display area, and the lower display area while extending in the first direction.

17. The aforementioned substrate is The first region including the upper display area, A second region including the lower display area, and A third region located between the first region and the second region, including the intermediate display region, The third region includes an inwardly recessed waist region, The nth bypass link line is arranged according to the shape of the waist region, The display device according to claim 1, wherein no wiring to which a data signal is applied is arranged in the non-display area included in the waist region.

18. The display device according to claim 17, wherein the display device is a glasses-type wearable device or a heterogeneous integrated display device, and the waist region corresponds to the position of the user's nose.

19. A substrate including a display area, A first signal wiring is disposed on the substrate, extends in a first direction within the display area, and is located within the first metal layer, and A display device comprising a second signal wiring disposed on the substrate, extending in a second direction different from the first direction in the display area, and disposed within a second metal layer different from the first metal layer.

20. A third signal wiring is disposed on the substrate, extends in the first direction within the display area, and is located within the first metal layer. A fourth signal wiring is disposed on the substrate, extends in the second direction within the display area, and is located within the second metal layer, and The system further includes a fifth signal wiring that is disposed on the substrate, extends in the first direction within the display area, and is located within the first metal layer. The first, second, third, fourth, and fifth signal wirings are electrically connected. The substrate includes an inwardly recessed waist region, The display device according to claim 19, wherein the waist region is located on one side of the third signal wiring.

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