Electronic devices

Abstract

To provide a novel electronic device. [Solution] The device comprises a housing, a display device, a calculation unit, a gaze detection unit, and a motion detection unit. The display device has display elements, pixel circuits, a drive circuit, and a function circuit. The motion detection unit has the function of detecting the movement of the housing. The gaze detection unit has the function of detecting the gaze point according to the gaze toward the display device. The calculation unit has the function of performing drawing processing according to the movement of the housing, and the function of dividing the display unit of the display device into multiple regions according to the gaze point. The pixel circuits have the function of controlling the emission of light from the display elements. The drive circuit has the function of controlling the pixel circuits. The function circuit has the function of controlling the drive circuits according to multiple regions. The display device has a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are each provided on different layers. The first layer has a drive circuit and a function circuit. The second layer has a pixel circuit. The third layer has a display element.

Description

[Technical Field]

[0001] One aspect of the present invention relates to an electronic device. Another aspect of the present invention relates to a wearable electronic device equipped with a display device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them. [Background technology]

[0003] In recent years, HMD (Head-Mounted Display) type electronic devices suitable for applications such as virtual reality (VR) and augmented reality (AR) have become widespread. Because HMDs can display images in a 360-degree field of view around the user in response to the user's head movements, gaze, or actions, users can experience a high level of immersion and realism.

[0004] An HMD (Head-Mounted Display) is configured to enlarge an image displayed on a display device using optical elements, and the user then views the enlarged image. In this case, there is a risk of the housing becoming larger due to the inclusion of optical elements, or a risk that the user may perceive pixels as more easily visible, resulting in a strong sense of graininess. Therefore, the display device needs to be high-resolution and / or miniaturized. For example, Patent Document 1 discloses an HMD with fine pixels by using transistors capable of high-speed driving. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2000-2856 [Overview of the project] [Problems that the invention aims to solve]

[0006] An HMD-type electronic device is required to have high rendering processing capabilities according to the movement of the user's head, the user's line of sight, or operations. When a display device with high definition and miniaturization is driven by an arithmetic circuit having high rendering processing capabilities, there is a risk that power consumption will increase. In addition, an arithmetic circuit having high rendering processing capabilities needs to include a heat dissipation mechanism for cooling the arithmetic circuit, which may lead to an increase in the size of the electronic device.

[0007] Alternatively, in a configuration where a functional circuit such as an application processor for driving a display device is provided in a region overlapping with the display unit, in the case of a display device with high definition and miniaturization, there is a risk that the rendering processing capabilities will be insufficient.

[0008] One aspect of the present invention aims to provide an electronic device with reduced power consumption. Or, one aspect of the present invention aims to provide an electronic device with reduced size and weight. Or, one aspect of the present invention aims to provide an electronic device with excellent rendering processing capabilities. Or, one aspect of the present invention aims to provide a novel electronic device.

[0009] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems can be extracted from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0010] One aspect of the present invention is an electronic device comprising a housing, a display device, a calculation unit, a gaze detection unit, and a motion detection unit, wherein the display device comprises a display element, a pixel circuit, a drive circuit, and a function circuit, the motion detection unit has the function of detecting the movement of the housing, the gaze detection unit has the function of detecting a gaze point corresponding to the gaze toward the display device, the calculation unit has the function of performing drawing processing according to the movement of the housing and the function of dividing the display area of ​​the display device into multiple regions according to the gaze point, the pixel circuit has the function of controlling the emission of light from the display element, the drive circuit has the function of controlling the pixel circuit, and the function circuit has the function of controlling the drive circuit according to multiple regions.

[0011] One aspect of the present invention is an electronic device comprising a housing, a display device, a calculation unit, a gaze detection unit, and a motion detection unit, wherein the display device comprises a display element, a pixel circuit, a drive circuit, and a function circuit, the motion detection unit has the function of detecting the movement of the housing, the gaze detection unit has the function of detecting a gaze point corresponding to the gaze toward the display device, the calculation unit has the function of performing drawing processing according to the movement of the housing and the function of dividing the display area of ​​the display device into multiple regions according to the gaze point, the pixel circuit has the function of controlling the emission of light from the display element, the drive circuit has the function of controlling the pixel circuit, and the function circuit has the function of controlling the drive circuit according to multiple regions, and the display device comprises a first layer, a second layer, and a third layer, the first layer, the second layer, and the third layer being provided on different layers, the first layer having a drive circuit and a function circuit, the second layer having a pixel circuit, and the third layer having a display element.

[0012] In one embodiment of the present invention, an electronic device is preferred in which the first layer has a first transistor having a semiconductor layer with silicon in the channel formation region, and the second layer has a second transistor having a semiconductor layer with a metal oxide in the channel formation region.

[0013] In one embodiment of the present invention, an electronic device is preferred in which the metal oxide comprises In, element M (where M is Al, Ga, Y, or Sn), and Zn.

[0014] In one embodiment of the present invention, an electronic device is preferred in which the display element has an organic EL element, and the organic EL element is a display element formed using a photolithography method.

[0015] In one embodiment of the present invention, an electronic device is preferred in which the drive circuit has a gate driver circuit and a source driver circuit.

[0016] In one embodiment of the present invention, the display unit is divided into a plurality of sections, and one of the plurality of sections has a source driver circuit and a gate driver circuit, wherein the source driver circuit has a plurality of source lines electrically connected, and the gate driver circuit has a plurality of gate lines electrically connected, which is preferable for an electronic device.

[0017] In one embodiment of the present invention, an electronic device is preferred in which the control of the drive circuit according to multiple regions in the functional circuit is controlled by different driving frequencies for each section.

[0018] Further embodiments of the present invention are described in the following descriptions of embodiments and in the drawings. [Effects of the Invention]

[0019] One aspect of the present invention can provide an electronic device that achieves low power consumption. Alternatively, one aspect of the present invention can provide an electronic device that is miniaturized and lightweight. Alternatively, one aspect of the present invention can provide an electronic device with excellent drawing processing capabilities. Alternatively, one aspect of the present invention can provide a novel electronic device.

[0020] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawing]

[0021] [Figure 1]Figures 1A and 1B illustrate an example of the configuration of an electronic device. [Figure 2] Figures 2A and 2B illustrate examples of the configuration of an electronic device. [Figure 3] Figures 3A and 3B illustrate an example of a display device configuration. [Figure 4] Figure 4 illustrates an example of a display device configuration. [Figure 5] Figure 5 illustrates an example of the operation of an electronic device. [Figure 6] Figures 6A and 6B illustrate examples of the configuration of an electronic device. [Figure 7] Figures 7A and 7B illustrate examples of the configuration of an electronic device. [Figure 8] Figures 8A and 8B illustrate examples of the configuration of an electronic device. [Figure 9] Figures 9A and 9B illustrate an example of the configuration of a display device. [Figure 10] Figures 10A to 10D illustrate examples of the configuration of a display device. [Figure 11] Figures 11A to 11D illustrate examples of the configuration of a display device. [Figure 12] Figure 12 is a diagram illustrating the method of driving the display device. [Figure 13] Figures 13A and 13B illustrate an example of a display device configuration. [Figure 14] Figures 14A and 14B illustrate an example of a display device configuration. [Figure 15] Figures 15A and 15B illustrate an example of a display device configuration. [Figure 16] Figures 16A and 16B illustrate an example of the configuration of a display device. [Figure 17] Figure 17 illustrates an example of a display device configuration. [Figure 18] Figure 18 illustrates an example of a display device configuration. [Figure 19] Figures 19A to 19C illustrate examples of the configuration of a display device. [Figure 20] Figure 20A is a diagram illustrating the classification of crystal structures. Figure 20B is a diagram illustrating the XRD spectrum of the CAAC-IGZO film. Figure 20C is a diagram illustrating the micro-electron diffraction pattern of the CAAC-IGZO film. [Figure 21] Figures 21A to 21D illustrate examples of the configuration of a display element. [Figure 22] Figures 22A to 22D illustrate examples of the configuration of a display element. [Figure 23] Figures 23A and 23B illustrate examples of the configuration of a display element. [Modes for carrying out the invention]

[0022] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different forms, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0023] Furthermore, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings.

[0024] Furthermore, unless otherwise specified in this specification, off-current refers to the drain current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state in an n-channel transistor is defined as the voltage V between the gate and source. gs The threshold voltage V th Lower than (in p-channel transistors, V th This refers to a state that is higher than [a certain value].

[0025] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the active layer of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0026] (Embodiment 1) One aspect of the present invention describes an electronic device according to one aspect of the present invention. The electronic device according to one aspect of the present invention can also be suitably used as a wearable electronic device for VR and AR applications.

[0027] <Example of electronic device configuration> Figure 1A is a perspective view of a glasses-type (goggle-type) electronic device 100, which is an example of a wearable electronic device. The electronic device 100 shown in Figure 1A illustrates how a pair of display devices 10_L and 10_R, a motion detection unit 101, a gaze detection unit 102, a calculation unit 103, and a communication unit 104 are housed in a housing 105.

[0028] Figure 1B is a block diagram of the electronic device 100 shown in Figure 1A. Similar to Figure 1A, the electronic device 100 includes display devices 10_L and 10_R, a motion detection unit 101, a gaze detection unit 102, a calculation unit 103, and a communication unit 104, which transmit and receive various signals to and from each other via bus wiring BW. Display devices 10_L and 10_R each have a display element 61, a pixel circuit 51, a drive circuit 30, and a function circuit 40, respectively.

[0029] The motion detection unit 101 has the function of detecting the movement of the housing 105, that is, the movement of the user's head wearing the electronic device 100. The motion detection unit 101 can use, for example, a motion sensor using MEMS technology. As the motion sensor, a 3-axis motion sensor or a 6-axis motion sensor can be used. The information regarding the movement of the housing 105 detected by the motion detection unit 101 may be referred to as first information, first data, or motion data.

[0030] The gaze detection unit 102 has the function of detecting the direction of the user's gaze to determine which object in the images displayed on the display devices 10_L and 10_R the user is fixated on (point of gaze). The information regarding the point of gaze detected by the gaze detection unit 102 may be referred to as second information, second data, or gaze data. The second information can be acquired using known eye-tracking methods. For example, the second information can be acquired using methods such as the Pupil Center Corneal Reflection method or the Bright / Dark Pupil Effect method. For example, this can be done using measurement methods such as lasers or ultrasound.

[0031] The arithmetic unit 103 has a function to perform drawing processing in accordance with the movement of the housing 105. The drawing processing in the arithmetic unit 103 in accordance with the movement of the housing 105 is performed using first information and 360-degree omnidirectional image data input from the outside via the communication unit 104. The 360-degree omnidirectional image data is data generated by a 360° camera (omnidirectional camera) or computer graphics. Specifically, the arithmetic unit 103 processes the 360-degree omnidirectional image data according to the first information to obtain image data that can be displayed on the display devices 10_L and 10_R.

[0032] Furthermore, the calculation unit 103 has the function of dividing the display units of the display devices 10_L and 10_R into multiple regions according to the gaze point. The calculation unit 103 has the function of determining the size and shape of the multiple regions, which will be described later, from information regarding the direction of the gaze. Specifically, the calculation unit 103 determines the gaze point according to the second information and determines the first to third regions, etc., on the display unit of the display device with the gaze point as the center.

[0033] The arithmetic unit 103 can use a central processing unit (CPU), as well as other microprocessors such as a DSP (Digital Signal Processor) or a GPU (Graphics Processing Unit), either individually or in combination. Furthermore, these microprocessors may be implemented using PLDs (Programmable Logic Devices) such as FPGAs (Field Programmable Gate Arrays) or FPAAs (Field Programmable Analog Arrays).

[0034] The arithmetic unit 103 interprets and executes instructions from various programs by the processor, thereby performing various data processing or program control. Programs that can be executed by the processor may be stored in the processor's memory area or in a separately provided storage unit. As the storage unit, for example, a storage device using non-volatile memory elements such as flash memory, MRAM (Magnetoresistive Random Access Memory), PRAM (Phase Change RAM), ReRAM (Resistive RAM), or FeRAM (Ferroelectric RAM), or a storage device using volatile memory elements such as DRAM (Dynamic RAM) or SRAM (Static RAM) may be used.

[0035] The communication unit 104 has the function of communicating with external devices wirelessly or via wired connection to acquire various data such as image data. The communication unit 104 can, for example, be equipped with a high-frequency circuit (RF circuit) to transmit and receive RF signals. A high-frequency circuit is a circuit that converts electromagnetic signals and electrical signals in frequency bands defined by the laws of each country, and uses these electromagnetic signals to communicate wirelessly with other communication devices. When performing wireless communication, communication protocols or technologies that can be used include communication standards such as LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Division Multiple Access 2000), WCDMA (Wideband Code Division Multiple Access: registered trademark), or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), and ZigBee (registered trademark). Additionally, it is possible to use third-generation mobile communication systems (3G), fourth-generation mobile communication systems (4G), or fifth-generation mobile communication systems (5G) as defined by the International Telecommunication Union (ITU).

[0036] Furthermore, the communication unit 104 may have external ports such as a terminal for LAN (Local Area Network) connection, a terminal for receiving digital broadcasts, and a terminal for connecting an AC adapter.

[0037] Each display device 10_L and 10_R has a display element 61, a pixel circuit 51, a drive circuit 30, and a function circuit 40, respectively. The pixel circuit 51 has the function of controlling the light emission of the display element 61. The drive circuit 30 has the function of controlling the pixel circuit 51. The function circuit 40 has the function of controlling the drive circuit 30 according to the size and shape of multiple areas in the display section of the display device, which are determined by the calculation unit 103 from information regarding the direction of the gaze.

[0038] Information on multiple regions in the display unit of the display device, determined by the calculation unit 103 from information on the direction of the gaze, is used for driving that varies the driving frequency for each region, and / or driving that varies the resolution for each region. For example, it is used when the function circuit 40 controls the drive circuit 30 to vary the driving frequency for each region. The function circuit 40 is configured to control the drive circuit 30 so that the driving frequency is higher or the display is of higher resolution in regions close to the gaze point, and so that the driving frequency is lower or the display is of lower resolution in regions far from the gaze point. By suppressing the update frequency of image data in areas far from the gaze point, the electronic device 100 can reduce the power consumption required for display. Therefore, the electronic device 100 can achieve low power consumption.

[0039] The functional circuit 40 is integrated with the drive circuit 30. This allows for a shorter wiring length between the functional circuit 40 and the drive circuit 30, and reduces the charging and discharging of the wiring that the functional circuit 40 uses to provide control signals to the drive circuit 30 in response to changes in the operating range.

[0040] Because the functional circuit 40 is located in an area that overlaps with the pixel circuit 51 and the display element 61, it is difficult to perform computationally intensive calculations on it. In one aspect of the present invention, by providing a calculation unit 103 separately from the functional circuit 40, computationally intensive calculations such as drawing processing in response to the movement of the housing 105 and dividing the display units of the display devices 10_L and 10_R into multiple areas according to the point of gaze can be entrusted to the calculation unit 103. Furthermore, by having the functional circuit handle processing such as controlling the drive circuit 30 in response to changes in the area, the calculation unit 103 can achieve miniaturization of the circuit and lower power consumption. In particular, in wearable electronic devices, power consumption is high due to the calculations for drawing processing, which are performed within a limited period of time due to the movement of the user's head and gaze. On the other hand, in one aspect of the present invention, the functional circuit that outputs control signals for the drive circuit 30 according to the area can be separated and integrated with the display device 10 to enable distributed computation processing. As a result, the load is not concentrated on a single calculation unit, the load on the calculation unit can be suppressed, and overall power consumption can be reduced.

[0041] Figure 2A is a perspective view showing the rear, bottom, and right side of the electronic device 100.

[0042] In Figure 2A, the housing 105 of the electronic device 100 includes, for example, a pair of display devices 10_L and 10_R and a calculation unit 103, as well as a mounting section 106, a buffer member 107, a pair of lenses 108, etc. The pair of display devices 10_L and 10_R are each provided inside the housing 105 in a position where they can be seen through the lenses 108.

[0043] Furthermore, the housing 105 shown in Figure 2A is provided with an input terminal 109 and an output terminal 110. The input terminal 109 can be connected to a cable that supplies image signals (image data) from a video output device or other device, or power to charge a battery provided inside the housing 105. The output terminal 110 functions, for example, as an audio output terminal, and earphones, headphones, etc., can be connected to it.

[0044] Furthermore, it is preferable that the housing 105 has a mechanism that allows adjustment of the left and right positions of the lens 108 and the display devices 10_L and 10_R so that they are in the optimal position according to the user's eye position. It is also preferable that the housing 105 has a mechanism that adjusts the focus by changing the distance between the lens 108 and the display devices 10_L and 10_R.

[0045] The cushioning member 107 is the part that comes into contact with the user's face (forehead, cheeks, etc.). By ensuring that the cushioning member 107 is in close contact with the user's face, light leakage can be prevented, thereby enhancing the sense of immersion. It is preferable to use a soft material for the cushioning member 107 so that it comes into close contact with the user's face when the user wears the electronic device 100. Using such a material is preferable because it feels good against the skin and prevents the user from feeling cold when wearing it in cold seasons. It is preferable to make the components that come into contact with the user's skin, such as the cushioning member 107 or the attachment part 106, removable so that they can be easily cleaned or replaced.

[0046] An electronic device according to one aspect of the present invention may further include an earphone 106A. The earphone 106A has a communication unit (not shown) and has a wireless communication function. The earphone 106A can output audio data through its wireless communication function. The earphone 106A may also have a vibration mechanism in order to function as a bone conduction earphone.

[0047] Furthermore, the earphone 106A can be configured to be directly connected to the mounting part 106 or connected via a wire, as shown in the earphone 106B in Figure 2B. The earphone 106B and the mounting part 106 may also have magnets. This allows the earphone 106B to be fixed to the mounting part 106 by magnetic force, making storage easier and preferable.

[0048] <Example of display device configuration> The configuration of the display device 10 applicable to the display devices 10_L and 10_R shown in Figures 1A and 1B will be explained with reference to Figures 3A, 3B, and 4.

[0049] Figure 3A is a schematic perspective view of a display device 10 applicable to the display devices 10_L and 10_R shown in Figures 1A and 1B.

[0050] The display device 10 has a substrate 11 and a substrate 12. The display device 10 has a display unit 13 which is composed of elements provided between the substrate 11 and the substrate 12. The display unit 13 is the area in the display device 10 that displays images. The display unit 13 is the area where pixels are provided, which are composed of pixel circuits and display elements connected to the pixel circuits.

[0051] In this specification, the term "element" may sometimes be replaced with "device." For example, display elements, light-emitting elements, and liquid crystal elements may be replaced with, for example, display devices, light-emitting devices, and liquid crystal devices.

[0052] The display device 10 receives various signals and power potentials from the outside via the terminal section 14, and can display information on the display section 13. Multiple layers are provided between the substrate 11 and the substrate 12, and each layer is provided with transistors for circuit operation or display elements that emit light. The multiple layers are provided with pixel circuits that have the function of controlling the light emission of the display elements, drive circuits that have the function of controlling the pixel circuits, functional circuits that have the function of controlling the drive circuits, and so on.

[0053] Figure 3B shows a schematic perspective view illustrating the configuration of each layer provided between substrate 11 and substrate 12.

[0054] A layer 20 is provided on the substrate 11. The layer 20 is provided with a drive circuit 30 and a functional circuit 40. The layer 20 has a transistor 21 (also called a Si transistor) having silicon in the channel formation region 22. The substrate 11 is, for example, a silicon substrate. A silicon substrate is preferred because it has higher thermal conductivity compared to a glass substrate.

[0055] The transistor 21 can be, for example, a transistor having single-crystal silicon in its channel formation region. In particular, using a transistor having single-crystal silicon in its channel formation region as the transistor provided in layer 20 allows for a large on-current of the transistor. Therefore, it is preferable because it allows the circuit of layer 20 to be driven at high speed. Furthermore, since Si transistors can be formed with microfabrication such as a channel length of 3 nm to 10 nm, the display device 10 can be equipped with an accelerator such as a CPU or GPU, an application processor, etc., integrated with the display unit.

[0056] The drive circuit 30 includes, for example, a gate driver circuit, a source driver circuit, etc. It may also include an arithmetic circuit, a memory circuit, or a power supply circuit, etc. Since the gate driver circuit, source driver circuit, and other circuits can be arranged on top of the display unit 13, the width of the non-display area (also called a frame) on the outer periphery of the display unit 13 of the display device 10 can be made extremely narrow compared to the case where these circuits and the display unit 13 are arranged side by side, thereby realizing a compact display device 10. Furthermore, when the drive circuit 30 is arranged on the outer periphery of the display unit 13 of the display device 10, the gate driver circuit and source driver circuit are arranged in a concentrated manner on the outer periphery. However, in one aspect of the present invention, the drive circuit 30 can be divided into multiple parts and arranged in the area overlapping with the display unit 13.

[0057] The functional circuit 40 has, for example, the functions of an application processor for controlling each circuit in the display device 10 and for generating signals for controlling each circuit. The functional circuit 40 may also have circuits for correcting image data, such as CPUs and GPUs. The functional circuit 40 may also have LVDS (Low Voltage Differential Signaling) circuits, MIPI (Mobile Industry Processor Interface) circuits, and / or D / A (Digital to Analog) conversion circuits, etc., which function as interfaces for receiving image data etc. from outside the display device 10. The functional circuit 40 may also have circuits for compressing and decompressing image data, and / or power supply circuits, etc.

[0058] As mentioned above, the functional circuit 40 has the function of driving the drive circuit 30 at different drive frequencies for each of the multiple regions on the display section of the display device determined by the point of gaze, and / or driving at different resolutions for each region. When the gate driver circuit and source driver circuit are divided into multiple sections and arranged, the drive frequencies can be individually changed, and / or the resolution can be changed for each region. Since the drive frequency or the amount of image data can be reduced at locations far from the point of gaze, power consumption can be reduced. Since the functional circuit 40 is provided integrated with the drive circuit 30, the charging and discharging of the wiring that the functional circuit 40 provides to control the drive circuit 30 in response to changes in the region can be reduced.

[0059] A layer 50 is provided on layer 20. Layer 50 is provided with a plurality of pixel circuits 51. Layer 50 has a channel formation region 54 containing a transistor 52 (also called an OS transistor) having a metal oxide (also called an oxide semiconductor). Layer 50 can be configured by stacking it on layer 20. It is also possible to form layer 50 on a separate substrate and then bond it together.

[0060] As the OS transistor 52, it is preferable to use a transistor having an oxide containing at least one of indium, element M (where element M is aluminum, gallium, yttrium, or tin), and zinc in the channel formation region. Such an OS transistor has the characteristic of having a very low off-current. Therefore, it is preferable to use an OS transistor, especially as a transistor provided in a pixel circuit, because it can retain the analog data written to the pixel circuit for a long period of time.

[0061] A layer 60 is provided on layer 50. A substrate 12 is provided on layer 60. The substrate 12 is preferably a light-transmitting substrate or a layer made of a light-transmitting material. A plurality of display elements 61 are provided on layer 60. Layer 60 can be configured to be stacked on layer 50. As the display elements 61, for example, organic electroluminescent elements (also called organic EL elements) can be used. However, the display elements 61 are not limited to this, and for example, inorganic EL elements made of inorganic materials may be used. Note that "organic EL elements" and "inorganic EL elements" are sometimes collectively referred to as "EL elements". The display elements 61 may have inorganic compounds such as quantum dots. For example, quantum dots can be used in the light-emitting layer of the display element 61 to function as a light-emitting material.

[0062] As shown in Figure 3B, a display device 10 according to one aspect of the present invention can have a stacked configuration of a display element 61, a pixel circuit 51, a drive circuit 30, and a function circuit 40, which allows for an extremely high aperture ratio (effective display area ratio) of pixels. For example, the aperture ratio of pixels can be 40% or more and less than 100%, preferably 50% or more and 95%, and more preferably 60% or more and 95%. Furthermore, it is possible to arrange pixels at an extremely high density, which allows for an extremely high pixel resolution. For example, in the display section of the display device 10 (the area where the pixel circuit 51 and the display element 61 are stacked and provided), pixels can be arranged with a resolution of 20000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and a resolution of 20000 ppi or less, or 30000 ppi or less.

[0063] Because such a display device 10 is extremely high-resolution, it can be suitably used in VR devices such as head-mounted displays, or in glasses-type AR devices. For example, even in a configuration where the display part of the display device 10 is viewed through an optical element such as a lens, the display device 10 has an extremely high-resolution display part, so even when the display part is magnified with a lens, pixels are not visible, and a highly immersive display can be achieved.

[0064] In the display device 10, if a material having single-crystal silicon is used as the transistor 21 in the layer 20, the size of the display section 13 can be 0.1 inches or more and 5 inches or less diagonally, preferably 0.5 inches or more and 3 inches or less diagonally, and more preferably 1 inch or more and 2 inches or less. In one embodiment of the present invention, the width of the frame can be made extremely narrow, so for example, if the size of the substrate 11 on which the layer 20 is provided is 1 inch diagonally, it is possible to extract about four times the amount of light compared to a size of 0.5 inches diagonally, which is preferable.

[0065] A specific example of the configuration of the drive circuit 30 and the function circuit 40 will be explained with reference to Figure 4. The display device 10 shown in Figure 4 is a block diagram illustrating the pixel circuit 51, the multiple wires connecting the drive circuit 30 and the function circuit 40, and the bus wiring within the display device 10.

[0066] In the display device 10 shown in Figure 4, layer 50 has multiple pixel circuits 51 arranged in a matrix.

[0067] Furthermore, in the display device 10 shown in Figure 4, layer 20 contains a drive circuit 30 and a function circuit 40. The drive circuit 30 includes, as an example, a source driver circuit 31, a digital-to-analog conversion circuit 32, a gate driver circuit 33, and a level shifter 34. The function circuit 40 includes, as an example, a memory device 41, a GPU (AI accelerator) 42, an EL correction circuit 43, a timing controller 44, a CPU 45, a sensor controller 46, and a power supply circuit 47. The function circuit 40 has the functions of an application processor.

[0068] Furthermore, in the display device 10 shown in Figure 4, the circuits included in the drive circuit 30 and the circuits included in the function circuit 40 are electrically connected to a bus wiring BSL, for example.

[0069] The source driver circuit 31, for example, has the function of transmitting image data to the pixel circuit 51. Therefore, the source driver circuit 31 is electrically connected to the pixel circuit 51 via wiring SL. It is preferable to provide multiple source driver circuits 31. By arranging the source driver circuits 31 in each section of the display unit where the pixel circuit 51 is provided, it is possible to configure the display unit to drive at different drive frequencies for each section.

[0070] The digital-to-analog conversion circuit 32, for example, has the function of converting image data that has been digitally processed by a GPU, correction circuit, etc. (described later) into analog data. The image data converted to analog data is transmitted to the pixel circuit 51 via the source driver circuit 31. The digital-to-analog conversion circuit 32 may be included in the source driver circuit 31, or the image data may be transmitted in the order of source driver circuit 31, digital-to-analog conversion circuit 32, and then pixel circuit 51.

[0071] The gate driver circuit 33, for example, has the function of selecting the pixel circuit to which the image data will be transmitted in the pixel circuit 51. Therefore, the gate driver circuit 33 is electrically connected to the pixel circuit 51 via wiring GL. It is preferable that multiple gate driver circuits 33 are provided, corresponding to the source driver circuit 31. By arranging multiple gate driver circuits 33 in each section of the display unit where the pixel circuit 51 is provided, it is possible to configure the display unit to drive at different drive frequencies for each section.

[0072] The level shifter 34, for example, has the function of converting the level of the signal input to the source driver circuit 31, the digital-to-analog conversion circuit 32, the gate driver circuit 33, etc., to an appropriate level.

[0073] The storage device 41, for example, has the function of storing image data to be displayed on the pixel circuit 51. The storage device 41 can be configured to store the image data as either digital or analog data.

[0074] Furthermore, when image data is stored in the storage device 41, it is preferable that the storage device 41 be a non-volatile memory. In this case, for example, a NAND type memory can be used as the storage device 41.

[0075] Furthermore, when storing temporary data generated by the GPU 42, EL correction circuit 43, CPU 45, etc., in the storage device 41, it is preferable that the storage device 41 be volatile memory. In this case, for example, SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory) can be used as the storage device 41.

[0076] For example, the GPU42 has the function of processing image data read from the storage device 41 for output to the pixel circuit 51. In particular, because the GPU42 is configured to perform parallel pipeline processing, it can process image data to be output to the pixel circuit 51 at high speed. The GPU42 can also function as a decoder for restoring encoded images.

[0077] Furthermore, the functional circuit 40 may include multiple circuits that can improve the display quality of the display device 10. For example, such circuits may include correction circuits (color adjustment, brightness adjustment) that detect color unevenness in the displayed image and correct the color unevenness to produce an optimal image. Also, if an organic EL light-emitting device is used as the display element, the functional circuit 40 may include an EL correction circuit. As an example, the functional circuit 40 includes an EL correction circuit 43.

[0078] Furthermore, artificial intelligence may be used for the image correction described above. For example, the current flowing through the pixel circuit (or the voltage applied to the pixel circuit) may be monitored and acquired, the displayed image may be acquired using an image sensor, and the current (or voltage) and the image may be treated as input data for an artificial intelligence calculation (e.g., an artificial neural network), and the output result may be used to determine whether or not the image has been corrected.

[0079] Furthermore, artificial intelligence calculations can be applied not only to image correction but also to image data upconversion (downconversion). For example, the GPU 42 in Figure 4 has blocks for performing various correction calculations (color uniformity correction 42a, upconversion 42b, etc.).

[0080] Algorithms for upconverting image data can be selected from methods such as the Nearest neighbor method, Bilinear method, Bicubic method, RAISR (Rapid and Accurate Image Super-Resolution) method, ANR (Anchored Neighborhood Regression) method, A+ method, and SRCNN (Super-Resolution Convolutional Neural Network) method.

[0081] The upconversion process may be configured to change the algorithm used for upconversion for each section of the display unit of the display device 10, corresponding to the area determined by the point of focus. This configuration can shorten the upconversion processing time.

[0082] The timing controller 44 has, for example, a function to arbitrarily set the drive frequency for displaying an image. For example, when displaying a still image on the display device 10, the timing controller 44 can be used to lower the drive frequency for driving. Alternatively, for example, source driver circuits 31 and gate driver circuits 33 can be arranged for each section of the display unit in the display device 10, and the drive frequency can be controlled for each section of the display unit. In this case, the timing controller 44 can be used to set different drive frequencies for each gate driver circuit 33 and source driver circuit 31 in each section of the display unit, allowing different drive frequencies for different regions.

[0083] The CPU 45 has functions to perform general-purpose processing, such as executing an operating system, controlling data, performing various calculations, or executing programs. The CPU 45 also has the role of issuing commands, for example, to write or read image data from the storage device 41, correct image data, and operate sensors, which will be described later. In addition, the CPU 45 may also have the function of transmitting control signals to at least one of the circuits included in the functional circuit 40.

[0084] The sensor controller 46, for example, has the function of controlling the sensor. In Figure 4B, the wiring SNCL is shown as the wiring for electrically connecting to the sensor.

[0085] The sensor in question may be, for example, a touch sensor that can be provided on the display unit. Alternatively, the sensor may be, for example, an illuminance sensor.

[0086] The power supply circuit 47 has the function of generating voltage to supply to circuits such as the pixel circuit 51, the drive circuit 30, and the function circuit 40, as an example. The power supply circuit 47 may also have the function of selecting which circuits to supply voltage to. For example, the power supply circuit 47 can reduce the overall power consumption of the display device 10 by stopping the voltage supply to the CPU 45, GPU 42, etc., during the period when a still image is being displayed.

[0087] As described above, one aspect of the present invention allows for a display device configuration in which a display element, a pixel circuit, a drive circuit, and a function circuit are stacked. The peripheral circuits, the drive circuit and the function circuit, can be arranged in overlapping positions with the pixel circuit, and the width of the bezel can be made extremely narrow, resulting in a miniaturized display device. Furthermore, by stacking the circuits in one aspect of the present invention, the wiring connecting each circuit can be shortened, resulting in a lightweight display device. In addition, one aspect of the present invention allows for a display unit with increased pixel resolution, resulting in a display device with superior display quality.

[0088] <Examples of electronic device operation> An example of the operation of the electronic device 100 will be explained using diagrams. Figure 5 is a flowchart illustrating an example of the operation of the electronic device 100.

[0089] The motion detection unit 101 acquires first information (data) regarding the movement of the housing 105 (step S11).

[0090] In the gaze detection unit 102, second information (data) regarding the gaze point G corresponding to the gaze is acquired (step S12).

[0091] In the calculation unit 103, 360-degree omnidirectional image data drawing processing is performed based on first information regarding the movement of the housing 105 (step S13).

[0092] Step S13 will be explained with a specific example. The schematic diagram shown in Figure 6A illustrates a user 112 located at the center of the 360-degree panoramic image data 111. The user can see the image 114A in the direction 113A displayed on the display device 10 of the electronic device 100.

[0093] Furthermore, the schematic diagram shown in Figure 6B illustrates how user 112 moves their head from the schematic diagram in Figure 6A to view image 114B in direction 113B. As image 114A changes to image 114B in response to the movement of the housing of the electronic device 100, user 112 can recognize the space represented by 360-degree omnidirectional image data 111.

[0094] As shown in Figures 6A and 6B, the user 112 moves the housing of the electronic device 100 in conjunction with the movement of their head. The images obtained from the 360-degree panoramic image data 111, which are displayed in accordance with the movement of the electronic device 100, can be processed with high rendering processing capabilities, allowing the user 112 to perceive a virtual space that is consistent with the space of the real world.

[0095] In the calculation unit 103, based on the second information, multiple regions corresponding to the gaze point G are determined for the display area of ​​the display device (step S14). For example, a first region containing the gaze point G is determined, a second region adjacent to the first region is determined, and the area outside the second region is determined to be the third region.

[0096] Step S14 will be explained with a specific example.

[0097] Generally, the human field of vision, although varying from person to person, can be broadly classified into the following five areas: The discriminative field of vision is the area where visual functions such as visual acuity and color discrimination are best, and it refers to the area within approximately 5° of the center of the field of vision. The effective field of vision is the area where specific information can be instantly identified by eye movements alone, and it refers to the area within approximately 30° horizontally and 20° vertically of the center of the field of vision, adjacent to the discriminative field of vision. The stable fixation field of vision is the area where specific information can be identified effortlessly with head movements, and it refers to the area within approximately 90° horizontally and 70° vertically of the center of the field of vision, adjacent to the effective field of vision. The guided field of vision is the area where the presence of a specific object can be perceived, but the ability to identify it is low, and it refers to the area within approximately 100° horizontally and 85° vertically of the center of the field of vision, adjacent to the stable fixation field of vision. The auxiliary visual field is an area where the ability to identify specific objects is significantly low, and where the presence of a stimulus can only be perceived. It refers to the area adjacent to the guided visual field, within approximately 100° to 200° horizontally and 85° to 130° vertically from the center of the visual field.

[0098] From the above, it is clear that image quality from the discrimination field to the effective field of view is important in images displayed by electronic devices. In particular, image quality in the discrimination field is crucial.

[0099] Figure 7A is a schematic diagram showing a user 112 observing an image 114 displayed on the display unit 10 of the electronic device 100 from the front (image display surface). The image 114 shown in Figure 7A also corresponds to the display unit. The point of fixation G, which is in the line of sight 113 of the user 112, is also shown on the image 114. In this specification, the region containing the discrimination field of view on the image 114 is referred to as the "first region S1," and the region containing the effective field of view is referred to as the "second region S2." Furthermore, the region containing the stable field of fixation, the guidance field of view, and / or the auxiliary field of view is referred to as the "third region S3."

[0100] In Figure 7A, the boundary (contour) between the first region S1 and the second region S2 is shown as a curve, but this is not the only option. As shown in Figure 7B, the boundary (contour) between the first region S1 and the second region S2 may be a rectangle or a polygon. It may also be a shape that combines straight lines and curves. Alternatively, the display unit of the display device 10 may be divided into two regions, with the region containing the discrimination field of view and the effective field of view designated as the first region S1, and the remaining region as the second region S2. In this case, the third region S3 is not formed.

[0101] Figure 8A is a top view of the image 114 displayed on the display unit of the display device 10 of the electronic device 100, and Figure 8B is a side view of the image 114 displayed on the display unit of the display device 10 of the electronic device 100. In this specification, the horizontal angle of the first region S1 is denoted as "angle θx1," and the horizontal angle of the second region S2 is denoted as "angle θx2" (see Figure 8A). In this specification, the vertical angle of the first region S1 is denoted as "angle θy1," and the vertical angle of the second region S2 is denoted as "angle θy2" (see Figure 8B).

[0102] For example, by setting angles θx1 to 10° and θy1 to 10°, the area of ​​the first region S1 can be expanded. In this case, a portion of the effective field of view is included in the first region S1. Also, for example, by setting angles θx2 to 45° and θy2 to 35°, the area of ​​the second region S2 can be expanded. In this case, a portion of the stable field of view is included in the second region S2.

[0103] Note that the position of the point of focus G may fluctuate slightly due to user 112 fluctuations. For this reason, angles θx1 and θy1 are preferably between 5° and 20°. By setting the area of ​​the first region S1 to be wider than the discrimination field of view, the operation of the display device 10 becomes stable and the visibility of the image is improved.

[0104] When user 112's gaze 113 moves, the first and second regions also move. For example, if the amount of change in gaze 113 exceeds a certain amount, it is determined that gaze 113 is moving. When the amount of change in gaze 113 falls below a certain amount, it is determined that the movement of gaze 113 has stopped, and the first to third regions are determined.

[0105] In the functional circuit 40, the drive circuit 30 is controlled according to multiple regions (first to third regions) (step S15). An example of the configuration of the drive circuit 30 that is controlled according to multiple regions will be described later.

[0106] <Example of pixel circuit configuration> Figures 9A and 9B show an example configuration of the pixel circuit 51 and the display element 61 connected to the pixel circuit 51. Figure 9A is a diagram showing the connections of each element, and Figure 9B is a diagram schematically showing the hierarchical relationship between the layer 20 containing the drive circuit, the layer 50 containing the multiple transistors of the pixel circuit, and the layer 60 containing the light-emitting element.

[0107] The pixel circuit 51 shown as an example in Figures 9A and 9B comprises transistors 52A, 52B, 52C, and a capacitor 53. Transistors 52A, 52B, and 52C can be composed of OS transistors. Each OS transistor of transistors 52A, 52B, and 52C preferably has a back gate electrode, in which case the back gate electrode can be configured to receive the same signal as the gate electrode, or to receive a different signal from the gate electrode.

[0108] Transistor 52B comprises a gate electrode electrically connected to transistor 52A, a first terminal electrically connected to the display element 61, and a second terminal electrically connected to wiring ANO. Wiring ANO is a wire that provides a potential for supplying current to the display element 61.

[0109] Transistor 52A includes a first terminal electrically connected to the gate electrode of transistor 52B, a second terminal electrically connected to wiring SL which functions as a source line, and a gate electrode that has the function of controlling a conduction state or a non-conduction state based on the potential of wiring GL1 which functions as a gate line.

[0110] Transistor 52C comprises a first terminal electrically connected to wiring V0, a ​​second terminal electrically connected to display element 61, and a gate electrode that controls a conduction or non-conduction state based on the potential of wiring GL2 which functions as a gate wire. Wiring V0 is a wiring for supplying a reference potential and a wiring for outputting the current flowing through the pixel circuit 51 to the drive circuit 30 or the function circuit 40.

[0111] Capacitor 53 includes an electrode electrically connected to the gate electrode of transistor 52B and an electrode electrically connected to the second terminal of transistor 52C.

[0112] The display element 61 includes a first terminal electrically connected to the first terminal of the transistor 52B, and a second terminal electrically connected to the wiring VCOM. The wiring VCOM is a wire that provides a potential for supplying current to the display element 61.

[0113] This allows the intensity of light emitted by the display element 61 to be controlled according to the image signal applied to the gate electrode of transistor 52B. Furthermore, variations in the gate-source voltage of transistor 52B can be suppressed by the reference potential of the wiring V0 provided via transistor 52C.

[0114] Furthermore, the wiring V0 can output a current value that can be used to set pixel parameters. More specifically, wiring V0 can function as a monitor line to output the current flowing through transistor 52B or the current flowing through display element 61 to the outside. The current output to wiring V0 is converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A / D converter or the like and output to a functional circuit 40, etc.

[0115] In one aspect of the present invention, the display element described refers to a self-emissive display element such as an organic light-emitting diode (OLED). The display element electrically connected to the pixel circuit can be a self-emissive light-emitting element such as an LED (light-emitting diode), micro-LED, QLED (quantum-dot light-emitting diode), or semiconductor laser.

[0116] In the configuration shown as an example in Figure 9B, the wiring electrically connecting the pixel circuit 51 and the drive circuit 30 can be shortened, thereby reducing the wiring resistance. As a result, data can be written at high speed, and the display device 10 can be driven at high speed. This allows for a sufficient frame duration even with a large number of pixel circuits 51 in the display device 10, thus increasing the pixel density of the display device 10. Furthermore, increasing the pixel density of the display device 10 improves the resolution of the image displayed by the display device 10. For example, the pixel density of the display device 10 can be set to 1000 ppi or more, or 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 10 can be used as a display device for AR or VR, and can be suitably applied to electronic devices where the distance between the display unit and the user is close, such as HMDs.

[0117] Figures 9A and 9B show a pixel circuit 51 having a total of three transistors as an example, but the present invention is not limited to this. Below, examples of pixel circuit configurations and driving methods applicable to the pixel circuit 51 will be described.

[0118] The pixel circuit 51A shown in Figure 10A includes transistors 52A and 52B, and capacitor 53. Figure 10A also shows a display element 61 connected to the pixel circuit 51A. Wirings SL, GL, ANO, and VCOM are electrically connected to the pixel circuit 51A.

[0119] Transistor 52A's gate is electrically connected to wiring GL, one of its source and drain is electrically connected to wiring SL, the other of which is electrically connected to the gate of transistor 52B and one of the electrodes of capacitor 53. Transistor 52B's source and drain are electrically connected to wiring ANO, the other of which is electrically connected to the anode of display element 61. Capacitor 53's other electrode is electrically connected to the anode of display element 61. Display element 61's cathode is electrically connected to wiring VCOM.

[0120] The pixel circuit 51B shown in Figure 10B is a configuration in which a transistor 52C is added to the pixel circuit 51A. Furthermore, wiring V0 is electrically connected to the pixel circuit 51B.

[0121] The pixel circuit 51C shown in Figure 10C is an example in which transistors 52A and 52B of the pixel circuit 51A are replaced with transistors in which a pair of gates are electrically connected. Similarly, the pixel circuit 51D shown in Figure 10D is an example in which the same transistor is replaced with the same transistor in the pixel circuit 51B. This increases the current that the transistors can supply. While transistors with a pair of gates electrically connected are used here, this is not the only option. Alternatively, transistors with a pair of gates that are electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates and the source are electrically connected.

[0122] The pixel circuit 51E shown in Figure 11A is configured by adding a transistor 52D to the above-mentioned pixel circuit 51B. Furthermore, three wires (wires GL1, GL2, and GL3) that function as gate lines are electrically connected to the pixel circuit 51E.

[0123] Transistor 52D has its gate electrically connected to wiring GL3, and one of its source and drain is electrically connected to the gate of transistor 52B, while the other is electrically connected to wiring V0. Also, the gate of transistor 52A is electrically connected to wiring GL1, and the gate of transistor 52C is electrically connected to wiring GL2.

[0124] By simultaneously making transistors 52C and 52D conduct, the source and gate of transistor 52B become at the same potential, making transistor 52B non-conducting. This allows the current flowing to the display element 61 to be forcibly interrupted. Such a pixel circuit is suitable for display methods that alternate between display periods and off periods.

[0125] The pixel circuit 51F shown in Figure 11B is an example in which a capacitor 53A is added to the above pixel circuit 51E. Capacitor 53A functions as a retaining capacitor.

[0126] The pixel circuit 51G shown in Figure 11C and the pixel circuit 51H shown in Figure 11D are examples of applying a transistor having a pair of gates to the above-mentioned pixel circuit 51E or pixel circuit 51F, respectively. Transistors 52A, 52C, and 52D are transistors in which a pair of gates are electrically connected, while transistor 52B is a transistor in which one of the gates is electrically connected to the source.

[0127] Next, an example of a driving method for a display device to which the pixel circuit 51E is applied will be described. Note that the same driving method can also be applied to display devices to which the pixel circuits 51F, 51G, and 51H are applied.

[0128] Figure 12 shows a timing chart for the driving method of a display device to which the pixel circuit 51E is applied. Here, the potential changes of the gate lines of the k-th row, wiring GL1[k], wiring GL2[k], and wiring GL3[k], and the gate lines of the k+1-th row, wiring GL1[k+1], wiring GL2[k+1], and wiring GL3[k+1] are shown. Figure 12 also shows the timing of the signal applied to wiring SL, which functions as a source line.

[0129] This example shows a driving method that divides one horizontal period into an on-time period and an off-time period. Also, the horizontal period in row k and the horizontal period in row k+1 are shifted by the gate line selection period.

[0130] During the k-th row's illumination period, a high-level potential is first applied to wires GL1[k] and GL2[k], and a source signal is applied to wire SL. This causes transistors 52A and 52C to conduct, and the potential corresponding to the source signal is written from wire SL to the gate of transistor 52B. Subsequently, a low-level potential is applied to wires GL1[k] and GL2[k], causing transistors 52A and 52C to become non-conductive, and the gate potential of transistor 52B is maintained.

[0131] Next, the process transitions to the illumination period of the (k+1)th row, and data is written using the same procedure as described above.

[0132] Next, we will explain the blackout period. During the blackout period for row k, a high-level potential is applied to wiring GL2[k] and wiring GL3[k]. This causes transistors 52C and 52D to conduct, and the same potential is supplied to the source and gate of transistor 52B, so almost no current flows through transistor 52B. As a result, the display element 61 turns off. All subpixels located in row k turn off. The subpixels in row k remain off until the next illumination period.

[0133] Next, the process transitions to the blackout period for row k+1, and as described above, all subpixels in row k+1 become black.

[0134] Thus, a driving method that includes periods of the light being off during a horizontal display period, rather than being continuously lit during the horizontal display period, can also be called duty cycle driving. By using duty cycle driving, the afterimage phenomenon when displaying videos can be reduced, thereby enabling the realization of display devices with high video display performance. In particular, in VR devices, reducing afterimages can alleviate so-called VR sickness.

[0135] In duty cycle operation, the ratio of the lighting period to the horizontal period can be called the duty cycle. For example, a duty cycle of 50% means that the lighting period and the off period are of equal length. The duty cycle can be freely set and can be adjusted as appropriate within a range of, for example, higher than 0% and less than or equal to 100%.

[0136] Furthermore, a configuration different from the pixel circuit described above will be explained with reference to Figures 13A and 13B.

[0137] Figure 13A shows the elements of a pixel circuit and a block diagram of a pixel having a light-emitting element. The pixel shown in Figure 13A has a switching transistor (Switching Tr), a driving transistor (Driving Tr), a light-emitting element (LED), and memory (Memory).

[0138] The memory is supplied with data_W. In addition to the display data Data, the supply of data_W to the pixels increases the current flowing to the light-emitting elements, allowing the display device to display high brightness.

[0139] Figure 13B shows a specific circuit diagram of the pixel circuit.

[0140] The pixel circuit 52I shown in Figure 13B includes transistors 52_w, 52A, 52B, 52C, capacitors 53_s, and 53_w. Figure 13B also illustrates the display element 61 connected to the pixel circuit 52I.

[0141] One of the sources or drains of transistor 52_w is electrically connected to one electrode of capacitor 53_w. The other electrode of capacitor 53_w is electrically connected to one of the sources or drains of transistor 52A. One of the sources or drains of transistor 52A is electrically connected to the gate of transistor 52B. The gate of transistor 52B is electrically connected to one electrode of capacitor 53_s. The other electrode of capacitor 53_s is electrically connected to one of the sources or drains of transistor 52B. One of the sources or drains of transistor 52B is electrically connected to one of the sources or drains of transistor 52C. One of the sources or drains of transistor 52C is electrically connected to one electrode of display element 61. Each transistor shown in Figure 13B has a back gate electrically connected to the gate, but the connection of the back gate is not limited to this. Also, a back gate may not be provided for the transistor.

[0142] Here, node NM is the node to which the other electrode of capacitor 53_w, one of the source or drain of transistor 52A, the gate of transistor 52B, and one electrode of capacitor 53_s are connected. Also, node NA is the node to which the other electrode of capacitor 53_s, one of the source or drain of transistor 52B, one of the source or drain of transistor 52C, and one electrode of display element 61 are connected.

[0143] The gate of transistor 52_w is electrically connected to wiring GL1. The gate of transistor 52C is electrically connected to wiring GL1. The gate of transistor 52A is electrically connected to wiring GL2. The other end of the source or drain of transistor 52_w is electrically connected to wiring SL1. The other end of the source or drain of transistor 52C is electrically connected to wiring V0. The other end of the source or drain of transistor 52A is electrically connected to wiring SL2.

[0144] The source or drain of transistor 52B is electrically connected to wiring ANO. The other electrode of display element 61 is electrically connected to wiring VCOM.

[0145] Wirings GL1 and GL2 can function as signal lines for controlling the operation of the transistor. Wiring SL1 can function as a signal line for supplying image signals to pixels. Wiring SL2 can function as a signal line for writing data to the memory circuit MEM. Wiring SL2 can function as a signal line for supplying correction signals to pixels. Wiring V0 can function as a monitor line for acquiring the electrical characteristics of transistor 52B. Furthermore, by supplying a specific potential from wiring V0 to the other electrode of capacitor 53_s via transistor 52C, the writing of the image signal can also be stabilized.

[0146] Transistors 52A and 52B, and capacitor 53_w constitute the memory circuit MEM. Node NM is a memory node, and by making transistor 52_w conduct, the signal supplied to wiring SL2 can be written to node NM. By using an OS transistor with an extremely low off-current for transistor 52A, the potential of node NM can be maintained for a long time.

[0147] In a pixel, the signal written to node NM is capacitively coupled with the image signal supplied from wiring SL1 and can be output to node NA. The transistor 52_w may have a pixel selection function.

[0148] <Example of drive circuit configuration> Figure 14A shows an example of a drive circuit 30 that is arranged to overlap with the pixel circuit 51. The drive circuit 30 includes a source driver circuit 31 and a gate driver circuit 33. Multiple pixel circuits 51 (not shown) are divided into multiple sections 59. Each section 59 is provided in the section that overlaps with the source driver circuit 31 and the gate driver circuit 33. The source driver circuit 31 and the gate driver circuit 33 can be divided into any section of the layer 20 and arranged corresponding to the section 59.

[0149] Figure 14B shows an enlarged view of section 59. In Figure 14B, multiple wiring lines SL and multiple wiring lines GL are shown with dashed lines.

[0150] In Figure 14B, multiple vertically extending wirings SL are each electrically connected to a source driver circuit 31. Similarly, multiple horizontally extending wirings GL are each electrically connected to a gate driver circuit 33. Wirings SL and GL are each electrically connected to multiple pixel circuits 51.

[0151] In this way, by providing multiple source driver circuits 31 and gate driver circuits 33 directly below the pixel circuit 51, the lengths of wiring SL and wiring GL can be made extremely short. As a result, the load on wiring SL and wiring GL is reduced, so the time and power required for charging and discharging can be made extremely small, enabling high-speed driving. In addition, since the image can be rewritten for each section 59, it is possible to rewrite the data only for parts of the image that have changed, and retain the data for images that have not changed, thereby reducing power consumption.

[0152] Furthermore, since the pixel circuit 51 is composed of OS transistors with extremely low off-current, the data written to the pixels can be retained for a long period of time. Therefore, the display drive frequency can be set arbitrarily (made variable). Also, since the display device 10 can be driven for each section 59, the drive frequency can also be set for each section 59 in some cases.

[0153] In one embodiment of the present invention, a display device in an electronic device has a configuration in which pixel circuits and functional circuits are stacked, and by making the driving frequencies of the sections 59 corresponding to the regions (first to third regions) corresponding to the movement of the gaze different, power consumption can be effectively reduced.

[0154] For example, as shown in Figure 15A, multiple sections 59 (16 sections in a 4x4 grid in the figure) corresponding to image 114 are illustrated. Figure 15A also illustrates the first to third regions S1 to S3 centered on the point of focus G. In this case, the sections are divided into section 59A, which overlaps with the first region S1 and second region S2 near the user's point of focus G, and section 59B, which overlaps with the third region S3, which is farther from the user's point of focus G (see Figure 15B).

[0155] In the functional circuit 40, the power consumption required for displaying locations far from the gaze point G can be reduced by controlling the drive frequency of section 59A to be higher than that of section 59B, thereby achieving lower power consumption. The functional circuit 40 is provided integrated with the drive circuit 30. Therefore, the wiring length between the functional circuit 40 and the drive circuit 30 can be shortened, and the charging and discharging of the wiring that the functional circuit 40 provides to control the drive circuit 30 in response to changes in the region can be reduced.

[0156] Furthermore, in one embodiment of the present invention, the display device can have a configuration in which the pixel circuit and the functional circuit are stacked, so that a defective pixel can be detected using the functional circuit provided at the bottom of the screen circuit. By using this information about the defective pixel, display defects caused by the defective pixel can be corrected and a normal display can be achieved.

[0157] Some of the correction methods illustrated below may be performed by circuits located outside the display device. Furthermore, some of the correction methods may be performed by the functional circuit 40 of the display device 10.

[0158] The following shows examples of more specific correction methods. Figure 16A is a flowchart illustrating the correction method described below.

[0159] First, the correction operation is started in step S1.

[0160] Next, in step S2, the pixel current is read. For example, each pixel can be driven to output current to the monitor line electrically connected to the pixel.

[0161] The current readout operation can be performed simultaneously in multiple sections 59. Because the screen is divided, the current readout operation for all pixels can be performed in a very short time.

[0162] Next, in step S3, the read current is converted into a voltage. At this point, if the signal will be handled in a later process, it can be converted into digital data in step S3. For example, analog data can be converted into digital data using an analog-to-digital converter (ADC).

[0163] Next, in step S4, pixel parameters for each pixel are obtained based on the acquired data. Examples of pixel parameters include the threshold voltage or field-effect mobility of the drive transistor, the threshold voltage of the light-emitting element, and the current value at a predetermined voltage.

[0164] Next, in step S5, a determination is made for each pixel based on its pixel parameters to determine whether it is abnormal or not. For example, if the value of a pixel parameter exceeds (or falls below) a predetermined threshold, that pixel is determined to be an abnormal pixel.

[0165] Anomalies include dark spots, which are significantly less bright than the input data potential, and bright spots, which are significantly more bright than the input data potential.

[0166] In step S5, the address of the abnormal pixel and the type of defect can be identified and obtained.

[0167] Next, in step S6, a correction process is performed.

[0168] An example of the correction process will be explained using Figure 16B. Figure 16B schematically shows a pixel consisting of a set of 3x3 pixel circuits 51 and display elements 61. Here, the central pixel is assumed to be pixel 151, which has a dark spot defect. Figure 16B schematically shows a state in which pixel 151 is turned off and the surrounding pixels 150 are lit at a predetermined brightness.

[0169] A dark spot defect is a defect in which, even if a correction is applied to increase the data potential input to the pixel, the pixel's brightness is unlikely to reach normal levels. Therefore, as shown in Figure 16B, a correction is applied to increase the brightness of the pixels 150 surrounding the pixel 151 with the dark spot defect. This allows for the display of a normal image even when a dark spot defect occurs.

[0170] In the case of bright pixel defects, the brightness of the surrounding pixels can be reduced to make the bright pixel defects less noticeable.

[0171] In particular, with high-resolution display devices (e.g., 1000 ppi or higher), it is difficult to distinguish and visually identify each individual pixel. Therefore, using correction methods that compensate for abnormal pixels with surrounding pixels is especially effective.

[0172] On the other hand, it is preferable to correct pixels where abnormalities such as dark spots or bright spots occur by not inputting a data potential.

[0173] In this way, correction parameters can be set for each pixel. By applying the correction parameters to the input image data, corrected image data can be generated to display an optimal image on the display device 10.

[0174] Furthermore, because variations exist in pixel parameters not only in abnormal pixels and the pixels surrounding them, but also in pixels that were not identified as abnormal, when an image is displayed, inconsistencies caused by these variations may be visible. Therefore, for pixels that were not identified as abnormal, correction parameters can be set to cancel (level out) the variations in pixel parameters. For example, a reference value can be set based on the median or average value of the pixel parameters for some or all pixels, and a correction value can be set as the correction parameter for a given pixel to cancel out the difference from the reference value for the pixel parameters of that pixel.

[0175] Furthermore, for pixels surrounding an abnormal pixel, it is preferable to set correction data that takes into account both a correction amount to compensate for the abnormal pixel and a correction amount to cancel out variations in pixel parameters.

[0176] Next, in step S7, the correction operation is terminated.

[0177] From this point forward, the image can be displayed based on the correction parameters obtained through the above correction operation and the input image data.

[0178] Furthermore, a neural network may be used as one of the steps in the correction process. In such a neural network, correction parameters can be determined based on inference results obtained through machine learning, for example. For instance, when correction parameters are determined using a neural network, high-precision correction can be performed to make abnormal pixels less noticeable without using a detailed correction algorithm.

[0179] The above is an explanation of the correction method.

[0180] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be appropriately combined with other configuration examples or drawings, etc., at least in part.

[0181] (Embodiment 2) In this embodiment, an example of the cross-sectional configuration of a display device 10, which is one aspect of the present invention, will be described.

[0182] Figure 17 is a cross-sectional view showing an example of the configuration of the display device 10. The display device 10 has a substrate 11 and a substrate 12, and the substrate 11 and the substrate 12 are bonded together by a sealing material 712.

[0183] A single-crystal semiconductor substrate, such as a single-crystal silicon substrate, can be used as the substrate 11. Alternatively, a semiconductor substrate other than a single-crystal semiconductor substrate may be used as the substrate 11.

[0184] Transistors 441 and 601 are provided on the substrate 11. Transistors 441 and 601 can be the same as the transistor 21 provided on layer 20 as shown in Embodiment 1.

[0185] The transistor 441 consists of a conductor 443 that functions as a gate electrode, an insulator 445 that functions as a gate insulator, and a part of the substrate 11, and has a semiconductor region 447 including a channel formation region, a low-resistance region 449a that functions as either a source region or a drain region, and a low-resistance region 449b that functions as either a source region or a drain region. The transistor 441 may be either a p-channel or an n-channel type.

[0186] Transistor 441 is electrically isolated from other transistors by the element isolation layer 403. Figure 17 shows the case where transistor 441 and transistor 601 are electrically isolated by the element isolation layer 403. The element isolation layer 403 can be formed using the LOCOS (Local Oxidation of Silicon) method or the STI (Shallow Trench Isolation) method, etc.

[0187] In this case, the transistor 441 shown in Figure 17 has a convex semiconductor region 447. Furthermore, the sides and top surface of the semiconductor region 447 are covered by a conductor 443 via an insulator 445. Note that Figure 17 does not show how the conductor 443 covers the sides of the semiconductor region 447. In addition, a material that adjusts the work function can be used for the conductor 443.

[0188] A transistor with a convex semiconductor region, such as transistor 441, can be called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator in contact with the upper part of the convex portion, functioning as a mask for forming the convex portion. Furthermore, while Figure 17 shows a configuration where a portion of the substrate 11 is processed to form the convex portion, a semiconductor with a convex shape may also be formed by processing an SOI substrate.

[0189] Note that the configuration of transistor 441 shown in Figure 17 is just one example, and the system is not limited to this configuration. An appropriate configuration may be used depending on the circuit configuration or the way the circuit operates. For example, transistor 441 may be a planar transistor.

[0190] Transistor 601 can have the same configuration as transistor 441.

[0191] On the substrate 11, in addition to the element isolation layer 403, transistors 441 and 601, insulators 405, 407, 409, and 411 are provided. Conductors 451 are embedded in insulators 405, 407, 409, and 411. Here, the height of the upper surface of the conductor 451 and the height of the upper surface of the insulator 411 can be made to be approximately the same.

[0192] Insulators 421 and 214 are provided on the conductor 451 and on the insulator 411, respectively. The conductor 453 is embedded in the insulator 421 and in the insulator 214. Here, the height of the upper surface of the conductor 453 and the height of the upper surface of the insulator 214 can be made to be approximately the same.

[0193] An insulator 216 is provided on the conductor 453 and on the insulator 214. The conductor 455 is embedded in the insulator 216. Here, the height of the upper surface of the conductor 455 and the height of the upper surface of the insulator 216 can be made to be approximately the same.

[0194] Insulators 222, 224, 254, 280, 274, and 281 are provided on the conductor 455 and on the insulator 216. The conductor 305 is embedded in insulators 222, 224, 254, 280, 274, and 281. Here, the height of the upper surface of the conductor 305 and the height of the upper surface of the insulator 281 can be made to be approximately the same.

[0195] An insulator 361 is provided on the conductor 305 and on the insulator 281. Conductors 317 and 337 are embedded in the insulator 361. Here, the height of the upper surface of the conductor 337 and the height of the upper surface of the insulator 361 can be made to be approximately the same.

[0196] An insulator 363 is provided on the conductor 337 and on the insulator 361. Conductors 347, 353, 355, and 357 are embedded in the insulator 363. Here, the height of the upper surfaces of conductors 353, 355, and 357 can be made to be approximately the same as the height of the upper surface of the insulator 363.

[0197] Connecting electrodes 760 are provided on the conductor 353, conductor 355, conductor 357, and insulator 363. An anisotropic conductor 780 is provided so as to be electrically connected to the connecting electrodes 760, and an FPC (Flexible Printed Circuit) 716 is provided so as to be electrically connected to the anisotropic conductor 780. Various signals and the like are supplied to the display device 10 from outside the display device 10 via the FPC 716.

[0198] As shown in Figure 17, the low-resistance region 449b, which functions as either the source region or the drain region of transistor 441, is electrically connected to the FPC 716 via conductors 451, 453, 455, 305, 317, 337, 347, 353, 355, 357, connecting electrode 760, and anisotropic conductor 780. Here, Figure 17 shows three conductors, conductors 353, 355, and 357, which have the function of electrically connecting the connecting electrode 760 and the conductor 347, but the present invention is not limited to these. There may be one, two, or four or more conductors that have the function of electrically connecting the connecting electrode 760 and the conductor 347. By providing multiple conductors that have the function of electrically connecting the connecting electrode 760 and the conductor 347, the contact resistance can be reduced.

[0199] A transistor 750 is provided on the insulator 214. Transistor 750 can be the transistor 52 provided on layer 50 as shown in Embodiment 1. For example, it can be the transistor provided on the pixel circuit 51. An OS transistor can preferably be used for transistor 750. OS transistors have the characteristic of having an extremely small off-current. Therefore, the retention time of image data, etc. can be extended, and the frequency of refresh operations can be reduced. Therefore, the power consumption of the display device 10 can be reduced.

[0200] Conductors 301a and 301b are embedded in insulators 254, 280, 274, and 281, respectively. Conductor 301a is electrically connected to either the source or drain of transistor 750, and conductor 301b is electrically connected to the other source or drain of transistor 750. Here, the height of the upper surfaces of conductors 301a and 301b can be made to be approximately the same as the height of the upper surface of insulator 281.

[0201] Conductors 311, 313, 331, capacitor 790, 333, and 335 are embedded in the insulator 361. Conductors 311 and 313 are electrically connected to the transistor 750 and function as wiring. Conductors 333 and 335 are electrically connected to the capacitor 790. Here, the height of the upper surfaces of conductors 331, 333, and 335 can be made to be approximately the same as the height of the upper surface of the insulator 361.

[0202] Conductors 341, 343, and 351 are embedded in the insulator 363. Here, the height of the upper surface of conductor 351 and the height of the upper surface of insulator 363 can be made to be approximately the same.

[0203] Insulators 405, 407, 409, 411, 421, 214, 280, 274, 281, 361, and 363 may function as interlayer films and as planarizing films that cover the uneven surface beneath them. For example, the upper surface of insulator 363 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0204] As shown in Figure 17, the capacitor 790 has a lower electrode 321 and an upper electrode 325. An insulator 323 is provided between the lower electrode 321 and the upper electrode 325. In other words, the capacitor 790 has a laminated structure in which an insulator 323, which functions as a dielectric, is sandwiched between a pair of electrodes. Although Figure 17 shows an example in which the capacitor 790 is provided on an insulator 281, the capacitor 790 may be provided on an insulator different from the insulator 281.

[0205] Figure 17 shows an example in which conductors 301a, 301b, and 305 are formed in the same layer. It also shows an example in which conductors 311, 313, 317, and the lower electrode 321 are formed in the same layer. Furthermore, it shows an example in which conductors 331, 333, 335, and 337 are formed in the same layer. It also shows an example in which conductors 341, 343, and 347 are formed in the same layer. In addition, it shows an example in which conductors 351, 353, 355, and 357 are formed in the same layer. By forming multiple conductors in the same layer, the manufacturing process of the display device 10 can be simplified, thereby reducing the manufacturing cost of the display device 10. Note that these may be formed in different layers and may be made of different types of materials.

[0206] The display device 10 shown in Figure 17 has a display element 61. The display element 61 has a conductor 772, an EL layer 786, and a conductor 788. The EL layer 786 has an organic compound or an inorganic compound such as a quantum dot.

[0207] Materials that can be used in organic compounds include fluorescent materials or phosphorescent materials. Materials that can be used in quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell type quantum dot materials, and core-type quantum dot materials.

[0208] The conductor 772 is electrically connected to the source or drain of the transistor 750 via conductors 351, 341, 331, 313, and 301b. The conductor 772 is formed on the insulator 363 and functions as a pixel electrode.

[0209] The conductor 772 can be made of a material that is transparent to visible light or a material that is reflective to visible light. As a transparent material, for example, an oxide material containing indium, zinc, tin, etc., may be used. As a reflective material, for example, a material containing aluminum, silver, etc., may be used.

[0210] Although not shown in Figure 17, the display device 10 may be equipped with optical components (optical substrates) such as polarizing members, phase difference members, and anti-reflective members.

[0211] On the substrate 12 side, a light-shielding layer 738 and an insulator 734 in contact with them are provided. The light-shielding layer 738 has the function of blocking light emitted from adjacent areas. Alternatively, the light-shielding layer 738 has the function of preventing ambient light from reaching the transistor 750, etc.

[0212] In the display device 10 shown in Figure 17, an insulator 730 is provided on the insulator 363. Here, the insulator 730 can be configured to cover a portion of the conductor 772. Furthermore, the display element 61 has a light-transmitting conductor 788 and can be a top-emission type light-emitting element.

[0213] The light-shielding layer 738 is provided so as to have an area that overlaps with the insulator 730. The light-shielding layer 738 is covered with the insulator 734. The space between the display element 61 and the insulator 734 is filled with a sealing layer 732.

[0214] Furthermore, the structure 778 is provided between the insulator 730 and the EL layer 786. Also, the structure 778 is provided between the insulator 730 and the insulator 734.

[0215] Figure 18 shows a modified version of the display device 10 shown in Figure 17. The display device 10 shown in Figure 18 differs from the display device 10 shown in Figure 17 in that it has a colored layer 736. The colored layer 736 is provided so as to have an area that overlaps with the display element 61. By providing the colored layer 736, the color purity of the light extracted from the display element 61 can be increased. As a result, the display device 10 can display high-resolution images. Furthermore, since, for example, all of the display elements 61 of the display device 10 can be light-emitting elements that emit white light, it is not necessary to form the EL layer 786 by painting, and the display device 10 can be made high-resolution.

[0216] The display element 61 can have a microcavity structure. Thereby, light of a predetermined color (e.g., RGB) can be extracted without providing a coloring layer, and the display device 10 can perform color display. By adopting a configuration without a coloring layer, light absorption by the coloring layer can be suppressed. Thereby, the display device 10 can display a high-brightness image, and the power consumption of the display device 10 can be reduced. Even when the EL layer 786 is formed in an island shape for each pixel or in a stripe shape for each pixel column, i.e., by painting, a configuration without a coloring layer can be adopted. The brightness of the display device 10 is, for example, 500 cd / m 2 or more, preferably 1000 cd / m 2 or more and 10000 cd / m 2 or less, more preferably 2000 cd / m 2 or more and 5000 cd / m 2 or less can be set.

[0217] <Configuration Example of OS Transistor> FIGS. 19A, 19B, and 19C are top views and cross-sectional views of the transistor 750 and the periphery of the transistor 750 that can be used in a display device according to an aspect of the present invention. The transistor 750 can be applied to a display device according to an aspect of the present invention.

[0218] FIG. 19A is a top view of the transistor 750. FIGS. 19B and 19C are cross-sectional views of the transistor 750. Here, FIG. 19B is a cross-sectional view of the portion indicated by the one-dot chain line A1 - A2 in FIG. 19A, and is also a cross-sectional view in the channel length direction of the transistor �50. FIG. 19C is a cross-sectional view of the portion indicated by the one-dot chain line A3 - A4 in FIG. 19A, and is also a cross-sectional view in the channel width direction of the transistor 750. In the top view of FIG. 19A, some elements are omitted for clarity of the drawing.

[0219] As shown in Figure 19, the transistor 750 includes a metal oxide 230a disposed on a substrate (not shown), a metal oxide 230b disposed on the metal oxide 230a, conductors 242a and 242b disposed on the metal oxide 230b at a distance from each other, an insulator 280 disposed on the conductors 242a and 242b with an opening formed between the conductors 242a and 242b, a conductor 260 disposed in the opening, an insulator 250 disposed between the metal oxide 230b, conductor 242a, conductor 242b, insulator 280, and conductor 260, and a metal oxide 230c disposed between the metal oxide 230b, conductor 242a, conductor 242b, insulator 280, and insulator 250. Here, as shown in Figures 19B and 19C, it is preferable that the upper surface of the conductor 260 substantially coincides with the upper surfaces of the insulator 250, insulator 254, metal oxide 230c, and insulator 280. In the following, metal oxide 230a, metal oxide 230b, and metal oxide 230c may be collectively referred to as metal oxide 230. Also, conductors 242a and conductors 242b may be collectively referred to as conductor 242.

[0220] In the transistor 750 shown in Figure 19, the sides of the conductors 242a and 242b facing the conductor 260 have a generally vertical shape. However, the transistor 750 shown in Figure 19 is not limited to this, and the angle between the side and bottom surfaces of the conductors 242a and 242b may be 10° to 80°, preferably 30° to 60°. Furthermore, the opposing sides of the conductors 242a and 242b may have multiple surfaces.

[0221] As shown in Figure 19, it is preferable that an insulator 254 is placed between the insulator 224, metal oxide 230a, metal oxide 230b, conductor 242a, conductor 242b, and metal oxide 230c and the insulator 280. Here, it is preferable that the insulator 254 is in contact with the side surface of the metal oxide 230c, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the metal oxide 230a and metal oxide 230b, and the top surface of the insulator 224, as shown in Figures 19B and 19C.

[0222] In the transistor 750, a configuration is shown in which three layers of metal oxide 230a, metal oxide 230b, and metal oxide 230c are stacked in the region where the channel is formed (hereinafter also referred to as the channel formation region) and in its vicinity. However, the present invention is not limited to this. For example, a two-layer structure of metal oxide 230b and metal oxide 230c, or a stacked structure of four or more layers, may be provided. Also, in the transistor 750, the conductor 260 is shown as a two-layer stacked structure. However, the present invention is not limited to this. For example, the conductor 260 may be a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the metal oxide 230a, metal oxide 230b, and metal oxide 230c may have a stacked structure of two or more layers.

[0223] For example, if the metal oxide 230c has a layered structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has the same composition as metal oxide 230b and the second metal oxide has the same composition as metal oxide 230a.

[0224] Here, the conductor 260 functions as the gate electrode of the transistor, and the conductors 242a and 242b function as the source electrode or drain electrode, respectively. As described above, the conductor 260 is formed to be embedded in the opening of the insulator 280 and in the region sandwiched between the conductors 242a and 242b. Here, the arrangement of the conductors 260, 242a, and 242b is selected in a self-aligned manner with respect to the opening of the insulator 280. In other words, in the transistor 750, the gate electrode can be positioned in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 260 can be formed without providing a positional margin, the occupied area of ​​the transistor 750 can be reduced. This makes it possible to make the display device high-resolution. It also makes it possible to make the display device narrow-bezel.

[0225] As shown in Figure 19, it is preferable that the conductor 260 has a conductor 260a provided inside the insulator 250 and a conductor 260b provided so as to be embedded inside the conductor 260a.

[0226] The transistor 750 preferably includes an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on top of the insulator 214, a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on top of the insulator 216 and the conductor 205, and an insulator 224 disposed on top of the insulator 222. It is preferable that a metal oxide 230a is disposed on top of the insulator 224.

[0227] It is preferable that insulators 274 and 281, which function as interlayer films, are placed on top of the transistor 750. Here, it is preferable that insulator 274 is placed in contact with the upper surfaces of the conductor 260, insulator 250, insulator 254, metal oxide 230c, and insulator 280.

[0228] It is preferable that insulators 222, 254, and 274 have a function to suppress the diffusion of at least one of the hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). For example, it is preferable that insulators 222, 254, and 274 have lower hydrogen permeability than insulators 224, 250, and 280. It is also preferable that insulators 222 and 254 have a function to suppress the diffusion of at least one of the oxygen (e.g., oxygen atoms, oxygen molecules, etc.). For example, it is preferable that insulators 222 and 254 have lower oxygen permeability than insulators 224, 250, and 280.

[0229] Here, insulator 224, metal oxide 230, and insulator 250 are separated from insulators 280 and 281 by insulators 254 and 274. Therefore, it is possible to suppress the mixing of impurities such as hydrogen, or excess oxygen, contained in insulators 280 and 281, into insulators 224, metal oxide 230a, metal oxide 230b, and insulator 250.

[0230] It is preferable that a conductor 240 (conductor 240a and conductor 240b) is provided that is electrically connected to the transistor 750 and functions as a plug. In addition, an insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 that functions as a plug. That is, the insulator 241 is provided in contact with the inner wall of the opening of the insulator 254, insulator 280, insulator 274, and insulator 281. Alternatively, a first conductor of the conductor 240 may be provided in contact with the side surface of the insulator 241, and a second conductor of the conductor 240 may be provided further inside. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be made to be approximately the same. Although the transistor 750 shows a configuration in which the first conductor and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or as a laminated structure of three or more layers. When the structure has a laminated structure, ordinal numbers may be assigned to distinguish them according to the order of formation.

[0231] In transistor 750, it is preferable to use a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) for the metal oxide 230 (metal oxide 230a, metal oxide 230b, and metal oxide 230c) that includes the channel formation region. For example, it is preferable to use a metal oxide with a band gap of 2 eV or more, preferably 2.5 eV or more, as the metal oxide that forms the channel formation region of metal oxide 230.

[0232] The above metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that it contains indium (In) and zinc (Zn). In addition, it is preferable that it contains element M. As element M, one or more of the following can be used: aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), or cobalt (Co). In particular, it is preferable that element M is one or more of aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn). Furthermore, it is even more preferable that element M contains either Ga or Sn, or both.

[0233] Furthermore, as shown in Figure 19B, the thickness of the metal oxide 230b in the region that does not overlap with the conductor 242 may be thinner than the thickness of the metal oxide 230b in the region that overlaps with the conductor 242. This is formed by removing a portion of the upper surface of the metal oxide 230b when forming the conductors 242a and 242b. When a conductive film that will become the conductor 242 is deposited on the upper surface of the metal oxide 230b, a region with low resistance may be formed near the interface with the conductive film. In this way, by removing the region with low resistance located between the conductors 242a and 242b on the upper surface of the metal oxide 230b, it is possible to prevent the formation of a channel in that region.

[0234] According to one aspect of the present invention, a display device with a small size transistor and high resolution can be provided. Alternatively, a display device with a large on-current transistor and high brightness can be provided. Alternatively, a display device with a fast-operating transistor and fast operation can be provided. Alternatively, a display device with a stable electrical characteristic transistor and high reliability can be provided. Alternatively, a display device with a small off-current transistor and low power consumption can be provided.

[0235] A detailed configuration of a transistor 750 that can be used in a display device according to one aspect of the present invention will be described.

[0236] The conductor 205 is arranged so as to have an overlapping region with the metal oxide 230 and the conductor 260. Furthermore, it is preferable that the conductor 205 is embedded in the insulator 216.

[0237] The conductor 205 comprises conductor 205a, conductor 205b, and conductor 205c. Conductor 205a is provided in contact with the bottom surface and side wall of an opening provided in the insulator 216. Conductor 205b is provided so as to be embedded in a recess formed in conductor 205a. Here, the upper surface of conductor 205b is lower than the upper surface of conductor 205a and the upper surface of the insulator 216. Conductor 205c is provided in contact with the upper surface of conductor 205b and the side surface of conductor 205a. Here, the height of the upper surface of conductor 205c is approximately equal to the height of the upper surface of conductor 205a and the upper surface of the insulator 216. In other words, conductor 205b is enclosed by conductors 205a and 205c.

[0238] It is preferable to use conductive materials for conductors 205a and 205c that have the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use conductive materials that have the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0239] By using a conductive material having a function of reducing the diffusion of hydrogen for the conductors 205a and 205c, it is possible to suppress impurities such as hydrogen contained in the conductor 205b from diffusing into the metal oxide 230 through the insulator 224 or the like. Further, by using a conductive material having a function of suppressing the diffusion of oxygen for the conductors 205a and 205c, it is possible to suppress the conductor 205b from being oxidized and the conductivity from decreasing. As the conductive material having a function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used. Therefore, for the conductor 205a, the above conductive material may be used as a single layer or a laminate. For example, the conductor 205a may use titanium nitride.

[0240] Further, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor 205b. For example, the conductor 205b may use tungsten.

[0241] Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. Also, the conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In that case, by changing the potential applied to the conductor 205 independently without linking it to the potential applied to the conductor 260, the V th of the transistor 750 can be controlled. In particular, by applying a negative potential to the conductor 205, the V th of the transistor 750 can be made greater than 0V, and the off-current can be reduced. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0V than when no potential is applied.

[0242] The conductor 205 should be larger than the channel-forming region in the metal oxide 230. In particular, as shown in Figure 19C, it is preferable that the conductor 205 extends to the region outside the end that intersects the channel width direction of the metal oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 are superimposed on the outside of the side surface in the channel width direction of the metal oxide 230, with an insulator in between.

[0243] With the above configuration, the channel-forming region of the metal oxide 230 can be electrically surrounded by the electric field of the conductor 260, which functions as the first gate electrode, and the electric field of the conductor 205, which functions as the second gate electrode.

[0244] As shown in Figure 19C, the conductor 205 is extended to function as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided beneath the conductor 205.

[0245] The insulator 214 preferably functions as a barrier insulating film that suppresses the ingress of impurities such as water or hydrogen into the transistor 750 from the substrate side. Therefore, it is preferable to use an insulating material for the insulator 214 that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities are less permeable). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen is less permeable).

[0246] For example, it is preferable to use aluminum oxide or silicon nitride as the insulator 214. This suppresses the diffusion of impurities such as water or hydrogen from the substrate side to the transistor 750 side beyond the insulator 214. Alternatively, it suppresses the diffusion of oxygen contained in the insulator 224, etc., toward the substrate side beyond the insulator 214.

[0247] The insulators 216, 280, and 281, which function as interlayer films, preferably have a lower dielectric constant than insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wiring can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide may be used as insulators 216, 280, and 281.

[0248] Insulators 222 and 224 function as gate insulators.

[0249] Here, it is preferable that the insulator 224 in contact with the metal oxide 230 desorbs oxygen upon heating. In this specification, the oxygen that is desorbed upon heating is sometimes referred to as excess oxygen. For example, the insulator 224 may be silicon oxide or silicon oxide nitride, etc., as appropriate. By providing an oxygen-containing insulator in contact with the metal oxide 230, the oxygen deficiency in the metal oxide 230 can be reduced, and the reliability of the transistor 750 can be improved.

[0250] Specifically, it is preferable to use an oxide material in which some oxygen is desorbed upon heating as the insulator 224. An oxide that desorbs oxygen upon heating is one in which the amount of oxygen desorbed, converted to oxygen atoms, is 1.0 × 10¹⁶ as determined by TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 Preferably 1.0 × 10 19 atoms / cm 3 More preferably 2.0 × 10 19 atoms / cm 3 The above, or 3.0 × 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C to 700°C, or 100°C to 400°C.

[0251] As shown in Figure 19C, the thickness of the insulator 224 in the region that does not overlap with the insulator 254 and does not overlap with the metal oxide 230b may be thinner than the thickness of the other regions. In the insulator 224, it is preferable that the thickness of the region that does not overlap with the insulator 254 and does not overlap with the metal oxide 230b is such that the above-mentioned oxygen can diffuse sufficiently.

[0252] The insulator 222, like the insulator 214, preferably functions as a barrier insulating film that suppresses the ingress of impurities such as water or hydrogen into the transistor 750 from the substrate side. For example, it is preferable that the insulator 222 has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the metal oxide 230, and the insulator 250 with the insulator 222, the insulator 254, and the insulator 274, it is possible to suppress the ingress of impurities such as water or hydrogen into the transistor 750 from the outside.

[0253] Furthermore, it is preferable that the insulator 222 has a function to suppress the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule) (i.e., it is difficult for the above-mentioned oxygen to permeate it). For example, it is preferable that the insulator 222 has lower oxygen permeability than the insulator 224. It is preferable that the insulator 222 has a function to suppress the diffusion of oxygen or impurities, thereby reducing the diffusion of oxygen contained in the metal oxide 230 to the substrate side. In addition, it is possible to suppress the reaction of the conductor 205 with oxygen contained in the insulator 224 or the metal oxide 230.

[0254] The insulator 222 may be an insulator containing an oxide of either or both aluminum and hafnium, which are insulating materials. Preferably, the insulator containing an oxide of either or both aluminum and hafnium is an aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the metal oxide 230 or the incorporation of impurities such as hydrogen from the periphery of the transistor 750 into the metal oxide 230.

[0255] Alternatively, for these insulators, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added. Or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the above insulators and used.

[0256] Insulator 222 may use, for example, a single layer or a laminate of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba,Sr)TiO3 (BST). As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator functioning as the gate insulator, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0257] Note that insulator 222 and insulator 224 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used. For example, a configuration may be adopted in which an insulator similar to insulator 224 is provided under insulator 222.

[0258] Metal oxide 230 has metal oxide 230a, metal oxide 230b on metal oxide 230a, and metal oxide 230c on metal oxide 230b. By having metal oxide 230a under metal oxide 230b, diffusion of impurities from the structure formed below metal oxide 230a to metal oxide 230b can be suppressed. Also, by having metal oxide 230c on metal oxide 230b, diffusion of impurities from the structure formed above metal oxide 230c to metal oxide 230b can be suppressed.

[0259] Furthermore, it is preferable that the metal oxide 230 has a layered structure of multiple oxide layers with different atomic ratios of each metal atom. For example, if the metal oxide 230 contains at least indium (In) and element M, it is preferable that the ratio of the number of atoms of element M contained in metal oxide 230a to the total number of atoms of all elements constituting metal oxide 230a is higher than the ratio of the number of atoms of element M contained in metal oxide 230b to the total number of atoms of all elements constituting metal oxide 230b. It is also preferable that the atomic ratio of element M contained in metal oxide 230a to In is higher than the atomic ratio of element M contained in metal oxide 230b to In. Here, metal oxide 230c can be any metal oxide that can be used in metal oxide 230a or metal oxide 230b.

[0260] It is preferable that the energy at the lower end of the conduction band of metal oxide 230a and metal oxide 230c is higher than the energy at the lower end of the conduction band of metal oxide 230b. In other words, it is preferable that the electron affinity of metal oxide 230a and metal oxide 230c is smaller than the electron affinity of metal oxide 230b. In this case, it is preferable that metal oxide 230c is a metal oxide that can be used for metal oxide 230a. Specifically, it is preferable that the ratio of the number of atoms of element M contained in metal oxide 230c to the total number of atoms of all elements constituting metal oxide 230c is higher than the ratio of the number of atoms of element M contained in metal oxide 230b to the total number of atoms of all elements constituting metal oxide 230b. It is also preferable that the atomic ratio of element M contained in metal oxide 230c to In is higher than the atomic ratio of element M contained in metal oxide 230b to In.

[0261] Here, at the junctions of metal oxide 230a, metal oxide 230b, and metal oxide 230c, the energy level at the lower end of the conduction band changes smoothly. In other words, the energy level at the lower end of the conduction band at the junctions of metal oxide 230a, metal oxide 230b, and metal oxide 230c can be said to change continuously or be continuously joined. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between metal oxide 230a and metal oxide 230b, and at the interface between metal oxide 230b and metal oxide 230c.

[0262] Specifically, a mixed layer with a low defect level density can be formed by having metal oxide 230a and metal oxide 230b, and metal oxide 230b and metal oxide 230c, all having a common element other than oxygen (which serves as the main component). For example, if metal oxide 230b is In-Ga-Zn oxide, then In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc., may be used as metal oxide 230a and metal oxide 230c. Furthermore, metal oxide 230c may be in a layered structure. For example, a layered structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide, or a layered structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide can be used. In other words, a layered structure of In-Ga-Zn oxide and an oxide that does not contain In may be used as metal oxide 230c.

[0263] Specifically, for metal oxide 230a, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or 1:1:0.5 may be used. For metal oxide 230b, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:3 or 3:1:2 may be used. For metal oxide 230c, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4, In:Ga:Zn = 4:2:3, Ga:Zn = 2:1, or Ga:Zn = 2:5 may be used. Furthermore, specific examples of layered structures for metal oxide 230c include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], and a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide.

[0264] In this case, the main carrier pathway is metal oxide 230b. By configuring metal oxide 230a and metal oxide 230c as described above, the defect level density at the interface between metal oxide 230a and metal oxide 230b, and at the interface between metal oxide 230b and metal oxide 230c, can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 750 can obtain high on-current and high frequency characteristics. Furthermore, if metal oxide 230c is in a stacked structure, in addition to the effect of reducing the defect level density at the interface between metal oxide 230b and metal oxide 230c as described above, it is expected that the diffusion of constituent elements of metal oxide 230c to the insulator 250 side will be suppressed. More specifically, by making metal oxide 230c in a stacked structure and positioning an oxide that does not contain In on top of the stacked structure, it is possible to suppress In that could diffuse to the insulator 250 side. Since insulator 250 functions as a gate insulator, if In diffuses, it will result in poor transistor characteristics. Therefore, by using a layered structure for the metal oxide 230c, it becomes possible to provide a highly reliable display device.

[0265] A conductor 242 (conductor 242a and conductor 242b) that functions as a source electrode and a drain electrode is provided on the metal oxide 230b. It is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum as the conductor 242, or an alloy containing the above metal elements, or an alloy combining the above metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0266] By providing the conductor 242 in contact with the metal oxide 230, the oxygen concentration in the vicinity of the conductor 242 in the metal oxide 230 may be reduced. In addition, a metal compound layer containing the metal in the conductor 242 and the components of the metal oxide 230 may be formed in the vicinity of the conductor 242 in the metal oxide 230. In such a case, the carrier density increases in the region of the metal oxide 230 near the conductor 242, and this region becomes a low-resistance region.

[0267] Here, the region between the conductor 242a and the conductor 242b is formed by superimposing it on the opening of the insulator 280. This allows the conductor 260 to be positioned self-aligned between the conductor 242a and the conductor 242b.

[0268] The insulator 250 functions as a gate insulator. It is preferable that the insulator 250 be placed in contact with the upper surface of the metal oxide 230c. The insulator 250 can be silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies. In particular, silicon oxide and silicon oxide nitride are preferred because they are stable with respect to heat.

[0269] Similar to the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0270] A metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable that the metal oxide suppresses oxygen diffusion from the insulator 250 to the conductor 260. This suppresses the oxidation of the conductor 260 by oxygen from the insulator 250.

[0271] The metal oxide may function as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. By making the gate insulator a laminated structure of insulator 250 and the metal oxide, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator.

[0272] Specifically, metal oxides containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used. In particular, it is preferable to use insulators containing oxides of aluminum, hafnium, or both, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0273] Although the conductor 260 is shown as a two-layer structure in Figure 19, it may also be a single-layer structure or a laminated structure of three or more layers.

[0274] It is preferable to use a conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0275] The conductor 260a has the function of suppressing oxygen diffusion, thereby preventing the conductor 260b from oxidizing due to oxygen contained in the insulator 250 and reducing its conductivity. It is preferable to use a conductive material that has the function of suppressing oxygen diffusion, such as tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0276] The conductor 260b is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. The conductor 260b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0277] As shown in FIGS. 19A and 19C, in a region that does not overlap with the conductor 242 of the metal oxide 230b, in other words, in the channel formation region of the metal oxide 230, the side surfaces of the metal oxide 230 are arranged to be covered with the conductor 260. Thereby, it becomes easier for the electric field of the conductor 260 that functions as the first gate electrode to act on the side surfaces of the metal oxide 230. Therefore, the on-current of the transistor 750 can be increased and the frequency characteristics can be improved.

[0278] The insulator 254 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from being mixed into the transistor 750 from the insulator 280 side, similar to the insulator 214 and the like. For example, it is preferable that the insulator 254 has lower hydrogen permeability than the insulator 224. Further, as shown in FIGS. 19B and 19C, the insulator 254 preferably contacts the side surfaces of the metal oxide 230c, the upper surfaces and side surfaces of the conductors 242a and 242b, the upper surfaces and side surfaces of the metal oxides 230a and 230b, and the upper surface of the insulator 224. With such a configuration, it is possible to suppress hydrogen contained in the insulator 280 from entering the metal oxide 230 from the upper surfaces or side surfaces of the conductors 242a, 242b, metal oxides 230a, 230b, and insulator 224.

[0279] Furthermore, the insulator 254 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). For example, it is preferable that the insulator 254 has lower oxygen permeability than the insulator 280 or the insulator 224.

[0280] The insulator 254 is preferably deposited using a sputtering method. By depositing the insulator 254 using a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the vicinity of the region of the insulator 224 that is in contact with the insulator 254. This allows oxygen to be supplied from this region to the metal oxide 230 via the insulator 224. Here, the insulator 254 has a function to suppress upward diffusion of oxygen, thereby preventing oxygen from diffusing from the metal oxide 230 to the insulator 280. In addition, the insulator 222 has a function to suppress downward diffusion of oxygen, thereby preventing oxygen from diffusing from the metal oxide 230 to the substrate side. In this way, oxygen is supplied to the channel formation region of the metal oxide 230. This reduces oxygen deficiency in the metal oxide 230 and suppresses normally-on formation of the transistor.

[0281] As the insulator 254, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed as a film. It is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) as the insulator containing an oxide of one or both of aluminum and hafnium.

[0282] The insulator 224, insulator 250, and metal oxide 230 are covered by the hydrogen barrier insulator 254, so the insulator 280 is separated from the insulator 224, metal oxide 230, and insulator 250 by the insulator 254. This prevents impurities such as hydrogen from entering the transistor 750 from the outside, thus providing the transistor 750 with good electrical characteristics and reliability.

[0283] The insulator 280 is provided on the insulator 224, the metal oxide 230, and the conductor 242 via the insulator 254. For example, the insulator 280 is preferably silicon oxide, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0284] It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. Furthermore, the upper surface of the insulator 280 may be flattened.

[0285] The insulator 274 preferably functions as a barrier insulating film that suppresses the incorporation of impurities such as water or hydrogen into the insulator 280 from above, similar to the insulator 214. For example, the insulator 274 can be an insulator that can be used for the insulator 214, insulator 254, etc.

[0286] It is preferable to provide an insulator 281, which functions as an interlayer film, on top of the insulator 274. It is preferable that the insulator 281, like the insulator 224, has a reduced concentration of impurities such as water or hydrogen in the film.

[0287] Conductors 240a and 240b are placed in the openings formed in insulators 281, 274, 280, and 254. Conductors 240a and 240b are provided facing each other with conductor 260 in between. The height of the upper surfaces of conductors 240a and 240b may be on the same plane as the upper surface of insulator 281.

[0288] Furthermore, an insulator 241a is provided in contact with the inner wall of the opening of insulators 281, 274, 280, and 254, and a first conductive portion of conductor 240a is formed in contact with its side surface. Conductor 242a is located in at least a portion of the bottom of the opening, and conductor 240a is in contact with conductor 242a. Similarly, an insulator 241b is provided in contact with the inner wall of the opening of insulators 281, 274, 280, and 254, and a first conductive portion of conductor 240b is formed in contact with its side surface. Conductor 242b is located in at least a portion of the bottom of the opening, and conductor 240b is in contact with conductor 242b.

[0289] It is preferable that the conductors 240a and 240b are made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, the conductors 240a and 240b may be arranged in a laminated structure.

[0290] When the conductor 240 has a laminated structure, it is preferable to use a conductor that has the function of suppressing the diffusion of impurities such as water or hydrogen, as described above, for the conductors that come into contact with the metal oxide 230a, metal oxide 230b, conductor 242, insulator 254, insulator 280, insulator 274, and insulator 281. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, the conductive material that has the function of suppressing the diffusion of impurities such as water or hydrogen may be used in a single layer or a laminate. By using this conductive material, it is possible to suppress the absorption of oxygen added to the insulator 280 by the conductors 240a and 240b. In addition, it is possible to suppress the mixing of impurities such as water or hydrogen from the layer above the insulator 281 into the metal oxide 230 through the conductors 240a and 240b.

[0291] For insulators 241a and 241b, any insulator that can be used for insulator 254, for example, may be used. Since insulators 241a and 241b are provided in contact with insulator 254, it is possible to suppress the mixing of impurities such as water or hydrogen from insulator 280, etc., into the metal oxide 230 through conductors 240a and 240b. Furthermore, it is possible to suppress the absorption of oxygen contained in insulator 280 into conductors 240a and 240b.

[0292] Although not shown in the figures, conductors that function as wiring may be placed in contact with the upper surfaces of conductor 240a and conductor 240b. It is preferable that the conductors functioning as wiring are made of a conductive material mainly composed of tungsten, copper, or aluminum. Furthermore, the conductors may have a laminated structure; for example, they may be laminates of titanium or titanium nitride with the conductive material. The conductors may also be formed to be embedded in openings provided in the insulator.

[0293] <Materials that make up a transistor> This section describes the constituent materials that can be used in transistors.

[0294] [substrate] As a substrate for forming a transistor, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include silicon, germanium, and other semiconductor substrates, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates on which elements are provided may be used. Elements provided on a substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0295] [Insulator] Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0296] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0297] Examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxide nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxide nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0298] Examples of insulators with low dielectric constant include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with voids, or resins.

[0299] Transistors using oxide semiconductors can have their electrical characteristics stabilized by surrounding them with an insulator (insulator 214, insulator 222, insulator 254, and insulator 274, etc.) that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, metal nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon oxide nitride, or silicon nitride can be used.

[0300] The insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating. For example, by having a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating is in contact with the metal oxide 230, the oxygen deficiency of the metal oxide 230 can be compensated for.

[0301] [conductor] It is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0302] Multiple conductors formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining a material containing the aforementioned metal element with a conductive material containing oxygen. Alternatively, a laminated structure may be formed by combining a material containing the aforementioned metal element with a conductive material containing nitrogen. Furthermore, a laminated structure may be formed by combining a material containing the aforementioned metal element with a conductive material containing oxygen and a conductive material containing nitrogen.

[0303] Furthermore, when using a metal oxide for the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0304] In particular, it is preferable to use a conductive material containing metal elements and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-added indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0305] <Classification of crystal structures in oxide semiconductors> The classification of crystal structures in oxide semiconductors will be explained using Figure 20A. Figure 20A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0306] As shown in Figure 20A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous semiconductors. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite). Note that single crystal, polycrystal, and completely amorphous semiconductors are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal semiconductors.

[0307] The structure within the thick frame shown in Figure 20A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" or "Crystal" states.

[0308] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 20B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 20B will simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 20B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 20B is 500 nm.

[0309] As shown in Figure 20B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ=31°. As shown in Figure 20B, the peak near 2θ=31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0310] The crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 20C. Figure 20C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 20C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. Furthermore, in nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0311] As shown in Figure 20C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0312] [Structure of oxide semiconductors] Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 20A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), amorphous oxide semiconductors, etc.

[0313] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0314] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0315] Each of the above-mentioned crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of that crystalline region will be less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0316] In In-M-Zn oxide (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. The In layer may also contain element M. The In layer may also contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0317] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the peak indicating c-axis orientation (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0318] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0319] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the sparse arrangement of oxygen atoms in the ab-plane direction, or because the bond distance between atoms changes due to the substitution of metal atoms.

[0320] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more effectively than In oxide.

[0321] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0322] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0323] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0324] [Oxide semiconductor configuration] Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0325] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing the metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0326] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0327] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0328] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0329] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0330] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0331] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on ), high field-effect mobility (μ), and good switching operation can be achieved.

[0332] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0333] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0334] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0335] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. For example, the carrier concentration of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm-3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0336] High-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films have a low defect level density, which may result in a low trap level density.

[0337] Charges trapped in the trap levels of oxide semiconductors can take a long time to disappear and sometimes behave like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high density of trap levels may exhibit unstable electrical properties.

[0338] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0339] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0340] In oxide semiconductors, the presence of silicon or carbon, which are Group 14 elements, leads to the formation of defect levels in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentration obtained by SIMS) are 2 × 10⁻¹⁰. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0341] When alkali metals or alkaline earth metals are present in oxide semiconductors, they can form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0342] In oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in oxide semiconductors obtained by SIMS should be set to 5 × 10⁻¹⁰. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0343] Hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. When hydrogen fills these vacancies, electrons, which act as carriers, can be generated. Furthermore, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the hydrogen content in oxide semiconductors as much as possible. Specifically, in oxide semiconductors, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶.20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0344] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0345] <Example configuration of display element 61> The EL layer 786 of the display element 61 can be composed of multiple layers, such as layer 4420, light-emitting layer 4411, and layer 4430, as shown in Figure 21A. Layer 4420 may include, for example, a layer containing a material with high electron injection properties (electron injection layer) and a layer containing a material with high electron transport properties (electron transport layer). Light-emitting layer 4411 may include, for example, a light-emitting compound. Layer 4430 may include, for example, a layer containing a material with high hole injection properties (hole injection layer) and a layer containing a material with high hole transport properties (hole transport layer).

[0346] A configuration having a layer 4420, an emissive layer 4411, and a layer 4430 provided between a pair of electrodes can function as a single emissive unit, and in this specification, the configuration shown in Figure 21A is referred to as a single structure.

[0347] Furthermore, Figure 21B shows a modified example of the EL layer 786 of the display element 61 shown in Figure 21A. Specifically, the display element 61 shown in Figure 21B includes a layer 4430-1 on a conductor 772, a layer 4430-2 on layer 4430-1, a light-emitting layer 4411 on layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on layer 4420-1, and a conductor 788 on layer 4420-2. For example, when the conductor 772 is the anode and the conductor 788 is the cathode, layer 4430-1 functions as a hole injection layer, layer 4430-2 functions as a hole transport layer, layer 4420-1 functions as an electron transport layer, and layer 4420-2 functions as an electron injection layer. Alternatively, when conductor 772 is used as the cathode and conductor 788 as the anode, layer 4430-1 functions as an electron injection layer, layer 4430-2 functions as an electron transport layer, layer 4420-1 functions as a hole transport layer, and layer 4420-2 functions as a hole injection layer. This layer structure allows for efficient injection of carriers into the light-emitting layer 4411 and improves the efficiency of carrier recombination within the light-emitting layer 4411.

[0348] Furthermore, as shown in Figure 21C, a configuration in which multiple light-emitting layers (light-emitting layers 4411, 4412, and 4413) are provided between layer 4420 and layer 4430 is also a variation of the single structure.

[0349] Furthermore, as shown in Figure 21D, a configuration in which multiple light-emitting units (EL layers 786a, 786b) are connected in series via an intermediate layer (charge generation layer) 4440 is referred to as a tandem structure in this specification. In this specification, the configuration shown in Figure 21D is referred to as a tandem structure, but it is not limited to this, and for example, a tandem structure may also be called a stack structure. By using a tandem structure, a light-emitting element capable of high-brightness emission can be made.

[0350] Furthermore, in Figures 21C and 21D, as shown in Figure 21B, layer 4420 and layer 4430 may be a laminated structure consisting of two or more layers.

[0351] The light-emitting color of the display element 61 can be red, green, blue, cyan, magenta, yellow, or white, depending on the material constituting the EL layer 786. Furthermore, the color purity can be further enhanced by adding a microcavity structure to the display element 61.

[0352] A light-emitting element that emits white light preferably has a configuration that includes two or more types of light-emitting materials in the light-emitting layer. To obtain white light emission, light-emitting materials should be selected such that the light emitted by each of the two or more materials is complementary in color.

[0353] The light-emitting layer preferably contains two or more light-emitting materials that emit light such as R (red), G (green), B (blue), Y (yellow), and O (orange). Alternatively, it is preferable that the layer contains two or more light-emitting materials, and the light emitted by each light-emitting material contains spectral components of two or more colors from R, G, and B.

[0354] <Method for forming the display element 61> The following describes the method for forming the display element 61.

[0355] Figure 22A shows schematic top views of display elements 61_R, 61_G, and 61_B applicable to the display element 61. Display element 61_R is a light-emitting element that emits red light, display element 61_G is a light-emitting element that emits green light, and display element 61_B is a light-emitting element that emits blue light. In Figure 22A, the symbols R, G, and B are added within the light-emitting area of ​​each light-emitting element for easy distinction. The configuration shown in Figure 22A may also be called an SBS (Side By Side) structure. Furthermore, although the configuration shown in Figure 22A is exemplified as having three colors, red (R), green (G), and blue (B), it is not limited to this. For example, a configuration with four or more colors may also be used.

[0356] The display elements 61_R, 61_G, and 61_B are each arranged in a matrix. Figure 22A shows a so-called stripe arrangement, in which light-emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light-emitting elements is not limited to this; other arrangement methods such as delta arrangement and zigzag arrangement may be applied, and a pentile arrangement can also be used.

[0357] As the display elements 61_R, 61_G, and 61_B, it is preferable to use organic EL devices such as OLED (Organic Light Emitting Diode) or QLED (Quantum-dot Light Emitting Diode). Examples of light-emitting materials for EL elements include fluorescent materials, phosphorescent materials, inorganic compounds (such as quantum dot materials), and thermally activated delayed fluorescence (TADF) materials.

[0358] Figure 22B is a schematic cross-sectional view corresponding to the dashed line A1-A2 in Figure 22A.

[0359] Figure 22B shows cross-sections of the display elements 61_R, 61_G, and 61_B. Each of the display elements 61_R, 61_G, and 61_B is provided on the substrate 751 and has a conductor 772 that functions as a pixel electrode and a conductor 788 that functions as a common electrode.

[0360] Display element 61_R has an EL layer 786R between conductor 772 and conductor 788. The EL layer 786R has a light-emitting organic compound that emits light having a peak in at least the red wavelength range. The EL layer 786G of display element 61_G has a light-emitting organic compound that emits light having a peak in at least the green wavelength range. The EL layer 786B of display element 61_B has a light-emitting organic compound that emits light having a peak in at least the blue wavelength range.

[0361] Each of the EL layers 786R, 786G, and 786B may have, in addition to a layer containing a light-emitting organic compound (light-emitting layer), one or more of the following: an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

[0362] A conductor 772 is provided for each light-emitting element. A conductor 788 is provided as a continuous layer common to each light-emitting element. A conductive film that is transparent to visible light is used for either the conductor 772 or the conductor 788 which functions as a common electrode, and a conductive film that is reflective is used for the other. By making the conductor 772 transparent and the conductor 788 reflective, a bottom-emission type display device can be made. Conversely, by making the conductor 772 reflective and the conductor 788 transparent, a top-emission type display device can be made. Furthermore, by making both the conductor 772 and the conductor 788 transparent, a dual-emission type display device can be made.

[0363] An insulating layer 755 is provided covering the end of the conductor 772. Preferably, the end of the insulating layer 755 is tapered.

[0364] Each of the EL layers 786R, 786G, and 786B has a region in contact with the upper surface of the conductor 772 and a region in contact with the surface of the insulating layer 755. The edges of the EL layers 786R, 786G, and 786B are located on the insulating layer 755.

[0365] As shown in Figure 22B, a gap is provided between the two EL layers between light-emitting elements of different colors. It is preferable that the EL layers 786R, 786G, and 786B are arranged so that they do not touch each other. This effectively prevents current from flowing through two adjacent EL layers, which can cause unintended light emission (also known as crosstalk). Therefore, contrast can be enhanced, and a display device with high display quality can be realized.

[0366] EL layer 786R, EL layer 786G, and EL layer 786B can be fabricated separately using methods such as vacuum deposition with a shadow mask like a metal mask. Alternatively, they may be fabricated separately using photolithography. By using photolithography, it is possible to realize a display device with high resolution that is difficult to achieve when using a metal mask.

[0367] Furthermore, a protective layer 756 is provided on the conductive material 788, covering the display elements 61_R, 61_G, and 61_B. The protective layer 756 has the function of preventing impurities such as water from diffusing to each light-emitting element from above.

[0368] The protective layer 756 can be, for example, a single-layer structure or a multilayer structure including at least an inorganic insulating film. Examples of inorganic insulating films include oxide films or nitride films such as silicon oxide films, silicon oxide nitride films, silicon nitride films, silicon nitride films, aluminum oxide films, aluminum oxide nitride films, and hafnium oxide films. Alternatively, semiconductor materials such as indium gallium oxide and indium gallium zinc oxide may be used as the protective layer 756. The protective layer 756 may be formed using ALD, CVD, and sputtering methods. Although the example shows a configuration including an inorganic insulating film as the protective layer 756, it is not limited to this. For example, the protective layer 756 may be a multilayer structure of an inorganic insulating film and an organic insulating film.

[0369] Figure 22C shows a different example from the one described above.

[0370] Figure 22C shows a display element 61_W that emits white light. The display element 61_W has an EL layer 786W that emits white light between a conductor 772 and a conductor 788.

[0371] The EL layer 786W can be configured, for example, by stacking two or more light-emitting layers selected so that their respective emission colors are complementary. Alternatively, a stacked EL layer, a so-called tandem structure EL layer, can be used, in which a charge generation layer is sandwiched between the light-emitting layers. By using a tandem structure, a light-emitting element capable of high-brightness emission can be created.

[0372] Figure 22C shows three display elements 61_W arranged side by side. A colored layer 757R is provided on top of the left display element 61_W. The colored layer 757R functions as a bandpass filter that transmits red light. Similarly, a colored layer 757G that transmits green light is provided on top of the center display element 61_W, and a colored layer 757B that transmits blue light is provided on top of the right display element 61_W. As a result, the display device can display a color image.

[0373] Here, the EL layer 786W and the conductor 788 are separated between two adjacent display elements 61_W. This effectively prevents current from flowing through the EL layer 786W between two adjacent display elements 61_W, thus preventing unintended light emission. In particular, when a stacked EL element is used as the EL layer 786W, in which a charge generation layer is provided between two light-emitting layers, the effect of crosstalk becomes more pronounced as the resolution increases, i.e., the distance between adjacent pixels decreases, resulting in a decrease in contrast. Therefore, this configuration makes it possible to realize a display device that combines high resolution and high contrast.

[0374] It is preferable to separate the EL layer 786W and the conductor 788 by photolithography. This allows for a narrower spacing between light-emitting elements, enabling the realization of a display device with a higher aperture ratio compared to cases where a shadow mask such as a metal mask is used.

[0375] In the case of a bottom-emission type light-emitting element, a colored layer can be provided between the conductor 772 and the substrate 751.

[0376] Figure 22D shows a different example from the above. Specifically, Figure 22D shows a configuration in which the insulating layer 755 is not provided between the display elements 61_R, 61_G, and 61_B. This configuration allows for a display device with a high aperture ratio. In addition, the protective layer 756 covers the sides of the display elements 61_R, 61_G, and 61_B. This configuration suppresses impurities (typically water, etc.) that could enter from the sides of the display elements 61_R, 61_G, and 61_B. Furthermore, in the configuration shown in Figure 22D, the top surface shapes of the conductor 772, the EL layer 786R, and the conductor 788 are roughly the same. Such a structure can be formed all at once using a resist mask or the like after the conductor 772, the EL layer 786R, and the conductor 788 have been formed. This process, which involves processing the EL layer 786R and the conductor 788 using the conductor 788 as a mask, can also be called self-aligned patterning. Although the display element 61_R has been described here, the same configuration can be used for the display elements 61_G and 61_B.

[0377] Furthermore, in Figure 22D, a protective layer 758 is provided on top of the protective layer 756. For example, by forming the protective layer 756 using an apparatus capable of forming a highly covering film (typically an ALD apparatus, etc.) and forming the protective layer 758 using an apparatus capable of forming a film with lower covering properties than the protective layer 756 (typically a sputtering apparatus, etc.), a gap 759 can be provided between the protective layer 756 and the protective layer 758. In other words, the gap 759 is located between the display element 61_R and the display element 61_G, and between the display element 61_G and the display element 61_B.

[0378] The void 759 contains one or more of the following: air, nitrogen, oxygen, carbon dioxide, and Group 18 elements (typically helium, neon, argon, xenon, krypton, etc.). Furthermore, the void 759 may contain gases used during the deposition of the protective layer 758. For example, when the protective layer 758 is deposited by sputtering, the void 759 may contain one or more of the aforementioned Group 18 elements. If the void 759 contains gas, the gas can be identified by gas chromatography or other methods. Alternatively, when the protective layer 758 is deposited by sputtering, the protective layer 758 may also contain gases used during sputtering. In this case, elements such as argon may be detected when the protective layer 758 is analyzed by energy-dispersive X-ray spectroscopy (EDX analysis).

[0379] Furthermore, if the refractive index of the air gap 759 is lower than that of the protective layer 756, the light emitted from the display element 61_R, display element 61_G, or display element 61_B will be reflected at the interface between the protective layer 756 and the air gap 759. This suppresses the incidence of light emitted from the display element 61_R, display element 61_G, or display element 61_B on adjacent pixels. This suppresses the mixing of light of different colors, thereby improving the image quality of the display device.

[0380] In the configuration shown in Figure 22D, the region between display element 61_R and display element 61_G, or the region between display element 61_G and display element 61_B (hereinafter simply referred to as the distance between light-emitting elements) can be narrowed. Specifically, the distance between light-emitting elements can be 1 μm or less, preferably 500 nm or less, and more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the distance between the side surface of display element 61_R and the side surface of display element 61_G, or the distance between the side surface of display element 61_G and the side surface of display element 61_B, has a region of 1 μm or less, preferably a region of 0.5 μm (500 nm) or less, and more preferably a region of 100 nm or less.

[0381] Furthermore, for example, if the gap 759 contains air, the configuration shown in Figure 22D can be called an air isolation structure. By having an air isolation structure, it is possible to isolate the light-emitting elements while suppressing color mixing or crosstalk of light from each light-emitting element.

[0382] Figure 23A shows a different example from the one described above. Specifically, the configuration shown in Figure 23A differs from the configuration shown in Figure 22D in the configuration of the substrate 751. When the display elements 61_R, 61_G, and 61_B are processed, a portion of the top surface of the substrate 751 is shaved off, creating a recess. A protective layer 756 is formed in this recess. In other words, in a cross-sectional view, the lower surface of the protective layer 756 is located below the lower surface of the conductor 772 in a certain region. Having this region effectively suppresses impurities (typically water, etc.) that could enter the display elements 61_R, 61_G, and 61_B from below. The recess can be formed when impurities (also called residues) that may adhere to the sides of each light-emitting element during the processing of the display elements 61_R, 61_G, and 61_B are removed by wet etching or the like. After removing the above-mentioned residue, a highly reliable display device can be created by covering the sides of each light-emitting element with a protective layer 756.

[0383] Figure 23B also shows a different example from the above. Specifically, the configuration shown in Figure 23B includes an insulating layer 776 and a microlens array 777 in addition to the configuration shown in Figure 23A. The insulating layer 776 functions as an adhesive layer. When the refractive index of the insulating layer 776 is lower than that of the microlens array 777, the microlens array 777 can collect light emitted from the display elements 61_R, 61_G, and 61_B. This can improve the light extraction efficiency of the display device. This is particularly advantageous when a user views the display surface of the display device from the front, as it allows for the viewing of a bright image. Various types of curing adhesives can be used as the insulating layer 776, such as UV-curing adhesives, reaction-curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. Materials with low moisture permeability, such as epoxy resins, are particularly preferred. Two-component mixed resins may also be used. Adhesive sheets may also be used.

[0384] <Notes regarding the description in this specification, etc.> The above embodiments and a description of each component in those embodiments are provided below.

[0385] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Furthermore, if multiple configuration examples are shown within a single embodiment, these configuration examples can be appropriately combined.

[0386] Furthermore, the content described in one embodiment (even if only a part of it) can be applied to, combined with, or substituted for other content described in the same embodiment (even if only a part of it), and / or content described in one or more other embodiments (even if only a part of it).

[0387] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0388] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in that embodiment, and / or a diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0389] Furthermore, in this specification, block diagrams classify components by function and show them as independent blocks. However, in actual circuits, it is difficult to separate components by function, and there may be cases where multiple functions are involved in a single circuit, or where a single function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and can be appropriately rephrased depending on the situation.

[0390] Furthermore, in the drawings, the size, layer thickness, or area are shown at arbitrary sizes for the sake of explanation. Therefore, they are not necessarily limited to that scale. Also, the drawings are schematic for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0391] In this specification and other documents, when describing the connections of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the transistor's structure or operating conditions. The terms source and drain of a transistor can be appropriately rephrased as source (drain) terminal or source (drain) electrode, depending on the context.

[0392] Furthermore, in this specification, the terms "electrode" or "wiring" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0393] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is the potential difference from a reference potential; for example, if the reference potential is the ground voltage (earth voltage), then voltage can be replaced with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, it may change the potential applied to wiring, etc.

[0394] In this specification, terms such as "film" and "layer" may be interchanged depending on the context or situation. For example, the term "conductive layer" may be changed to "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer."

[0395] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows.

[0396] In this specification, channel length refers, for example, to the distance between the source and drain in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate overlap in a top view of a transistor, or in the region where the channel is formed.

[0397] In this specification, channel width refers, for example, to the length of the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or the region in which the channel is formed, where the source and drain face each other.

[0398] In this specification, "A and B are connected" includes not only those that are directly connected, but also those that are electrically connected. Here, "electrically connected" means that when there is an object between A and B that has some kind of electrical effect, it enables the exchange of electrical signals between A and B.

[0399] In this specification, devices fabricated using a metal mask or an FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as MM (Metal Mask) structured devices. Furthermore, in this specification, devices fabricated without using a metal mask or an FMM may be referred to as MML (Metal Maskless) structured devices.

[0400] In this specification, a structure in which different light-emitting layers are created or painted for each color of light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. Also, in this specification, a light-emitting device capable of emitting white light may be referred to as a white light-emitting device. A white light-emitting device can be combined with a colored layer (for example, a color filter) to realize a full-color display device.

[0401] Furthermore, light-emitting devices can be broadly classified into single-structure and tandem-structure devices. A single-structure device has one light-emitting unit between a pair of electrodes, and it is preferable that this light-emitting unit includes one or more light-emitting layers. To obtain white light emission, one should select light-emitting layers such that the light emitted from each of the two or more layers is complementary in color. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer complementary, a configuration that emits white light as a whole can be obtained. The same applies to light-emitting devices having three or more light-emitting layers.

[0402] A tandem device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, the device should be configured such that the light from the light-emitting layers of the multiple light-emitting units is combined to produce white light emission. The configuration for obtaining white light emission is the same as that for a single-structure device. In a tandem device, it is preferable to provide an intermediate layer, such as a charge-generating layer, between the multiple light-emitting units.

[0403] Furthermore, when comparing the aforementioned white light-emitting devices (single or tandem structure) with SBS structure light-emitting devices, SBS structure light-emitting devices can consume less power than white light-emitting devices. If you want to keep power consumption low, it is preferable to use SBS structure light-emitting devices. On the other hand, white light-emitting devices are preferable because their manufacturing process is simpler than that of SBS structure light-emitting devices, which can lead to lower manufacturing costs or higher manufacturing yields. [Explanation of Symbols]

[0404] 10_L: Display device, 10_R: Display device, 30: Drive circuit, 40: Function circuit, 51: Pixel circuit, 61: Display element, 100: Electronic device, 101: Motion detection unit, 102: Eye-gaze detection unit, 103: Calculation unit, 104: Communication unit, 105: Housing

Claims

1. It comprises a housing, a display device, a calculation unit, a gaze detection unit, and a motion detection unit. The display device comprises a display unit having a plurality of display elements and a plurality of pixel circuits, a plurality of drive circuits having the function of driving the plurality of pixel circuits in sections, and a function circuit. The motion detection unit has the function of detecting the movement of the housing, The gaze detection unit has a function to detect the point of focus corresponding to the user's gaze toward the display unit. The calculation unit has a function to detect the point of focus and then perform drawing processing according to the movement of the housing, and a function to divide the display unit into at least a first region and a second region according to the point of focus after performing the drawing processing. The first region has an area that overlaps with the point of focus, The second region has a region located around the first region, The functional circuit has the function of controlling the drive frequency of the drive circuit located in the section corresponding to the first region among the plurality of drive circuits so that it is higher than the drive frequency of the drive circuit located in the section corresponding to the second region. The multiple drive circuits and the functional circuits are arranged in the first layer of the display device. The plurality of pixel circuits are arranged in the second layer of the display device. The plurality of display elements are arranged in the third layer of the display device. The second layer is located above the first layer, The third layer is located above the second layer, The third layer has the connecting electrodes of the terminal portion arranged therein. electronic equipment.

2. In claim 1, The first layer has a first transistor having silicon in the channel formation region, The second layer has a second transistor having a metal oxide in the channel formation region. electronic equipment.

3. In claim 2, The metal oxide comprises In, element M (where M is Al, Ga, Y, or Sn), and Zn. electronic equipment.

4. In any one of claims 1 to 3, Each of the plurality of drive circuits has a gate driver circuit and a source driver circuit. electronic equipment.

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