A memory device that generates a reference voltage for each pin.

Abstract

The present invention provides a memory device that includes multiple reference voltage generators, each corresponding to a different data pin and generating a reference voltage for that corresponding data pin. [Solution] In the data drive unit of the memory device, each of the multiple reference voltage generators 121 includes a voltage distributor that distributes the power supply voltage to a plurality of distribution voltages Vout<127:0>, a control logic that receives a first code indicating internal reference voltage level information and a second code indicating offset voltage information DQ#_OFS<3:0> for the corresponding data pin, and generates a control code CODE0<6:0> based on the first code REF_CODE0<6:0> and the second code, and a reference voltage selector that includes a tree-structured transfer gate that selects one of the plurality of distribution voltages in response to the control code and outputs it as a reference voltage.

Description

[Technical Field]

[0001] Embodiments of this disclosure relate to a memory device that generates a reference voltage for each pin. [Background technology]

[0002] A memory device can receive data signals through multiple channels. The memory device includes multiple receive buffers, which can be used to determine the logic level of the received data signal. The receive buffers can determine whether the logic level of the received data signal is "1" or "0" based on a reference voltage.

[0003] An inaccurate reference voltage increases the error rate in determining the logical level of the data signal, degrading the overall system performance. Generally, as the data rate increases, the setup time and hold time required to latch the data signal against the reference voltage become shorter, thus requiring a more precise reference voltage. Therefore, a method has been proposed in which the reference voltage is set differently for each pin, taking into account the characteristics of the data signal and the channel through which the data signal is transmitted. [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] Embodiments of this disclosure can provide a memory device that generates a reference voltage for each pin.

[0005] The problems of the embodiments of this disclosure are not limited to those mentioned herein, and further problems not mentioned herein will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] Embodiments of the present disclosure can provide a memory device comprising a plurality of reference voltage generators, each corresponding to a plurality of data pins and generating a reference voltage for each corresponding data pin, each of the plurality of reference voltage generators comprising: a voltage distributor that distributes a power supply voltage to a plurality of distribution voltages; control logic that receives a first code indicating internal reference voltage level information and a second code indicating offset voltage information for a corresponding data pin and generates a control code based on the first and second codes; and a reference voltage selector including a tree-structured transfer gate that, in response to the control code, selects one of the plurality of distribution voltages and outputs it as a reference voltage.

[0007] Embodiments of the present disclosure can provide a memory device that includes a plurality of input / output circuit regions corresponding to a plurality of data pins, each of which includes a receive buffer region; and a reference voltage generator region that provides a reference voltage to the receive buffer region, wherein the reference voltage generator region includes a voltage distributor region that distributes a power supply voltage to a plurality of distribution voltages; a control logic region that receives a first code indicating internal reference voltage level information and a second code indicating offset voltage information for the corresponding data pin and generates a control code based on the first and second codes; and a reference voltage selector region that, in response to the control code, selects one of the plurality of distribution voltages and outputs it as the reference voltage. [Effects of the Invention]

[0008] According to embodiments of this disclosure, it is possible to provide a memory device that generates a reference voltage for each pin, which can shorten the settling time of the reference voltage.

[0009] According to embodiments of this disclosure, it is possible to provide a memory device that generates a pin-by-pin reference voltage that can improve area efficiency.

[0010] The effects of the embodiments of the present disclosure are not limited to the effects mentioned above, and further effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

Brief Description of Drawings

[0011] The content of the present disclosure will be more fully understood from the following detailed description and the accompanying drawings. The detailed description and the accompanying drawings are provided for illustrative purposes only and do not limit the content of the present disclosure.

[0012] [Figure 1] It is a block diagram showing a system including a memory device according to an embodiment of the present disclosure.

[0013] [Figure 2] It is a block diagram showing a data driver according to an embodiment of the present disclosure.

[0014] [Figure 3] It is a block diagram showing the first reference voltage generator of FIG. 2.

[0015] [Figure 4] It is an exemplary circuit diagram of the voltage distributor of FIG. 3.

[0016] [Figure 5] It is an exemplary circuit diagram of the control logic of FIG. 3.

[0017] [Figure 6] It is a configuration diagram of the reference voltage selector of FIG. 3.

[0018] F <0oo00105>It is a graph showing the reference voltage level change of the DQ0 pin by the offset enable signal, the first code, and the second code in a memory device according to an embodiment of the present disclosure.

[0019] [Figure 8]This figure schematically shows the arrangement of the receiving buffer and reference voltage generator according to the embodiment of the present disclosure.

[0020] [Figure 9] This figure schematically shows the first input / output circuit region of Figure 8. [Figure 10] This figure schematically shows the first input / output circuit region of Figure 8. [Figure 11] This figure schematically shows the first input / output circuit region of Figure 8. [Modes for carrying out the invention]

[0021] Hereinafter, some embodiments of this disclosure will be described in detail with reference to illustrative drawings. In assigning reference numerals to components in each drawing, the same reference numeral may be used for the same component whenever possible, even if it is shown in other drawings. In describing this disclosure, if it is determined that a specific description of a relevant known configuration or function would obscure the gist of this disclosure, such detailed description will be omitted. Where the terms “includes,” “has,” “consists of,” etc., used herein, other parts may be added unless “only” is used. When a component is expressed singularly, it may include multiple components unless otherwise explicitly stated.

[0022] Furthermore, in describing the components of this disclosure, terms such as 1, 2, A, B, (a), (b), etc., may be used. These terms are used solely to distinguish a component from other components, and do not limit the nature, order, sequence, or number of such components.

[0023] In descriptions of the positional relationships of components, when it is stated that two or more components are “linked,” “joined,” or “connected,” it should be understood that while two or more components can be directly “linked,” “joined,” or “connected,” it is also possible for two or more components to be further “interposed” with other components before being “linked,” “joined,” or “connected.” Here, the other components may be included in one or more of the two or more components that are “linked,” “joined,” or “connected” to each other.

[0024] In descriptions of temporal relationships concerning constituent elements, operating methods, or manufacturing methods, when temporal order or sequential relationships are described using phrases such as "after," "following," "next," or "before," unless "immediately" or "directly" is used, this can include cases that are not continuous.

[0025] On the other hand, if numerical values ​​or corresponding information (e.g., levels) relating to components are mentioned, even without further explicit mention, these numerical values ​​or corresponding information may be interpreted as including a range of errors that can occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0026] Various embodiments of this disclosure will be described in detail below with reference to the attached drawings.

[0027] Figure 1 is a block diagram showing a system including a memory device according to an embodiment of the present disclosure.

[0028] Referring to Figure 1, the system 10 includes a memory device 100 and a memory controller 200.

[0029] The memory device 100 can store data. The memory device 100 can operate in response to the control of the memory controller 200.

[0030] The memory device 100 can receive data signals from the memory controller 200. The memory controller 200 can output data signals to the memory device 100 or receive data signals from the memory device 100 or the host. The data signals include commands, addresses, and data.

[0031] The memory device 100 may include multiple memory cells. The memory device 100 includes a data drive unit 110 (hereinafter referred to as the "DQ drive unit") and multiple data pins (not shown, hereinafter referred to as "DQ pins"). Data signals from the memory controller 200 are input to the DQ pins of the memory device 100 via multiple channels. The DQ drive unit 110 generates a reference voltage for each DQ pin and can determine the received data signal using the reference voltage for each pin.

[0032] The reference voltage for each pin can be set to an appropriate voltage level, taking into account the characteristics of the data signal and the channel through which the data signal is transmitted. This allows the reference voltage to have different values ​​for each DQ pin.

[0033] Reference voltage-related information for each of the multiple DQ pins can be stored in code form in a separate memory circuit, such as a mode register. The DQ drive unit 110 can generate a reference voltage based on the reference voltage-related code. The reference voltage-related code can be determined during the training process of the memory device 100.

[0034] The memory device 100 can support termination modes by connecting termination resistors to the ends of the transmission lines. The ends of the transmission lines can be terminated at a constant voltage level by the termination resistors. The memory device 100 can support a first termination mode and a second termination mode. For example, the first termination mode may be LTT (Low Tap Termination) mode, and the second termination mode may be PI-LTT (Power Isolated LTT) mode. The reference voltage may have different voltage ranges depending on the termination mode. For example, the range of the reference voltage in LTT mode and the range of the reference voltage in PI-LTT may be different from each other.

[0035] Figure 2 is a block diagram showing a DQ drive unit according to one embodiment of the present disclosure.

[0036] For the sake of brevity, the DQ drive unit 110 will be described below as a receiver that reads input data, but it is not limited to this. The DQ drive unit 110 may include a transmitter for transmitting data to an external device.

[0037] Referring to Figure 2, the DQ drive unit 110 includes first to eighth receiving buffers 111 to 118, and first to eighth reference voltage generators 121 to 128, which correspond to the first to eighth receiving buffers 111 to 118, respectively.

[0038] The first to eighth receive buffers 111 to 118 can receive the first to eighth input data signals DIN0 to DIN7, respectively, via the first to eighth DQ pins DQ0 to DQ7. For example, the first receive buffer 111 can receive the first input data signal DIN0 via the first DQ pin DQ0, and the second receive buffer 112 can receive the second input data signal DIN1 via the second DQ pin DQ1. Similarly, the third to eighth receive buffers 113 to 118 can receive the third to eighth input data signals DIN2 to DIN7, respectively, via the third to eighth DQ pins DQ2 to DQ7.

[0039] Each of the first to eighth reference voltage generators 121 to 128 can receive an offset enable signal EN_OFS, a first code (VREF_CODE<6:0>), and a second code (DQ#_OFS<3:0>, where # is an integer between 0 and 7).

[0040] The offset enable signal EN_OFS and the first code VREF_CODE<6:0> may be provided in common to the first to eighth reference voltage generators 121 to 128. The second code DQ#_OFS<3:0> may be provided individually to each of the first to eighth reference voltage generators 121 to 128. For example, the first reference voltage generator 121 may be provided with DQ0_OFS<3:0> and the second reference voltage generator 122 may be provided with DQ1_OFS<3:0>. Similarly, the third to eighth reference voltage generators 123 to 128 may be provided with DQ2_OFS<3:0> to DQ7_OFS<3:0>, respectively.

[0041] The first to eighth reference voltage generators 121 to 128 can generate reference voltages VREF_DQ0 to VREF_DQ7 based on the first code VREF_CODE<6:0> and the second code DQ0_OFS<3:0> to DQ7_OFS<3:0>.

[0042] The first code, VREF_CODE<6:0>, indicates the level information of the internal reference voltage, and the second code, DQ#_OFS<3:0>, indicates the offset voltage information for adjusting the reference voltage currently used in the discrimination operation.

[0043] In the second code DQ#_OFS<3:0>, the most significant bit is DQ#_OFS <3> This represents + or -, and DQ#_OFS <3> The remaining bits, excluding the first bit, i.e., DQ#_OFS<2:0>, can represent an offset voltage value. That is, the second code DQ#_OFS<3:0> can represent a + offset voltage value or a - offset voltage value. For example, if the level of the internal reference voltage indicated by the first code VREF_CODE<6:0> is Vref Therefore, the second code DQ0_OFS<3:0> input to the first reference voltage generator 121 is +V offset In this case, the first reference voltage VREF_DQ0 output from the first reference voltage generator 121 is V ref +V offset It can have a voltage level of [value].

[0044] The reference voltages VREF_DQ0 to VREF_DQ7 generated by the first to eighth reference voltage generators 121 to 128 may be different from each other. Alternatively, the reference voltage generated by one of the first to eighth reference voltage generators 121 to 128 may be different from the reference voltage generated by the other reference voltage generator.

[0045] Each of the first to eighth receive buffers 111 to 118 receives a reference voltage from its corresponding reference voltage generator and, based on the received reference voltage, can determine the logic level of the data signal input via the corresponding DQ pin. For example, the first receive buffer 111 receives a first reference voltage VREF_DQ0 from the first reference voltage generator 121 and, based on the first reference voltage VREF_DQ0, can determine the logic level of the first input data signal DIN0 and generate the first data signal D0. The second receive buffer 112 receives a second reference voltage VREF_DQ1 from the second reference voltage generator 122 and, based on the second reference voltage VREF_DQ1, can determine the logic level of the second input data signal DIN1 and generate the second data signal D1. The descriptions of the first and second receive buffers 111 and 112 also apply to the third to eighth receive buffers 113 to 118.

[0046] In Figure 2, the memory device includes, but is not limited to, eight receive buffers and eight reference voltage generators. The number of receive buffers and voltage generators included in the memory device may vary depending on the number of DQ pins.

[0047] Figure 3 is a block diagram of the first reference voltage generator in Figure 2.

[0048] The description of the first reference voltage generator 121 described below is similarly applicable to the second to eighth reference voltage generators 122 to 128 in FIG. 2.

[0049] Referring to FIG. 3, the first reference voltage generator 121 includes a voltage divider 121A, control logic 121B, and a reference voltage selector 121C.

[0050] The voltage divider 121A can distribute the power supply voltage to generate a plurality of divided voltages V out <127:0>.

[0051] The reference voltage selector 121C receives a plurality of divided voltages V out <127:0> from the voltage divider 121A, receives the control code CODE0<6:0> and the inverted control code CODEB0<6:0> from the control logic 121B, and based on the control code CODE​​​​​​​​​​​​​​​​​​​​ Referring to Figure 4, the voltage distributor 121A responds to the inverting enable signal ENB_VREF by distributing multiple voltages V out It generates <127:0>. The voltage distributor 121A includes a switch 410, a first resistor R1, and a resistor ladder 420.

[0056] Switch 410 is connected between the power supply voltage terminal 430 and the first node N1 and can be turned on in response to an offset enable signal (EN_OFS in Figure 2). The power supply voltage terminal 430 may be a power supply voltage pin.

[0057] Switch 410 may consist of a PMOS transistor. The drain electrode of the PMOS transistor is connected to the power supply voltage terminal 430, the source electrode of the PMOS transistor is connected to the first node N1, and an inverting enable signal ENB_VREF may be input to the gate electrode of the PMOS transistor. Switch 410 can be turned on in response to a low-level inverting enable signal ENB_VREF and transmit the power supply voltage provided to the power supply voltage terminal 430 to the first node N1.

[0058] The level of the power supply voltage provided to the power supply voltage terminal 430 may vary depending on the termination mode. In the first termination mode, the power supply voltage may have a first level voltage value, and in the second termination mode, it may have a second level voltage value different from the first level. For example, the first termination mode is LTT mode, and the second termination mode is PI-LTT mode, where in LTT mode the power supply voltage is 1.2[V], and in PI-LTT mode the power supply voltage is 0.6[V].

[0059] The voltage distributor 121A distributes the power supply voltage, which has different levels depending on the termination mode, and distributes the voltage V out <127:0> can be generated. This allows the reference voltage to have different voltage ranges depending on the termination mode.

[0060] The first resistor R1 is connected between the first node N1 and the second node N2. The resistor ladder 420 includes a number of second resistors R2 connected in series between the second node N2 and the ground node VSS.

[0061] The voltage level of the second node N2 may be determined by the standard. The voltage level of the second node N2 is K (where K is a positive number less than 1) times the power supply voltage, and the value of K may be determined according to the standard. The first resistor R1 and the second resistor R2 may have different resistivity values. The resistivity of the first resistor R1 may be greater than that of the second resistor R2. Because the first resistor R1 has a greater resistivity than the second resistor R2, the area occupied by the first resistor R1 can be reduced compared to the case where the resistivity of the first resistor R1 is the same as or less than that of the second resistor R2.

[0062] The resistor ladder 420 distributes the potential difference between the second node N2 and the ground voltage terminal VSS using a voltage distribution method to generate multiple distributed voltages V out Generate <127:0>.

[0063] Figure 5 is an illustrative circuit diagram of the control logic shown in Figure 3.

[0064] Referring to Figure 5, the control logic 121B includes first to seventh XOR gates 51A to 51G, first to seventh subtractor / adder 52A to 52G, and first to seventh inverters 53A to 53G.

[0065] In each of the first to seventh subtractor / adder units 52A to 52G, IN1 and IN2 are input terminals, CI is the terminal to which the carry value is input, S is the output terminal, and CO is the terminal to which the carry value is output. The operation of each of the first to seventh subtractor / adder units 52A to 52G is as shown in Table 1 below. [Table 1]

[0066] The most significant bit of the second code is DQ0_OFS <3> The setting value of the first subtractor / adder 52A and the first inputs of the first to seventh XOR gates 51A to 51G are provided, and the remaining bits DQ0_OFS<2:0>, with the most significant bit removed in the second code, are provided as the second inputs of the first to third XOR gates 51A to 51C, respectively. A low-level voltage VSSI is provided as the second input of the fourth to seventh XOR gates 51D to 51G.

[0067] The most significant bit of the second code is DQ0_OFS <3> If it is "0", the control logic 121B performs an operation to add the remaining bits DQ0_OFS<2:0> of the second code, excluding the most significant bit, to the first code REF_CODE0<6:0>, thereby generating the control code CODE0<6:0>. The most significant bit DQ0_OFS of the second code <3> If the value is "1", the control logic 121B performs an operation to subtract the remaining bits DQ0_OFS<2:0> of the second code, which is obtained by removing the most significant bit from the first code REF_CODE<6:0>, and generates the control code CODE0<6:0>.

[0068] The inputs of inverters 53A to 53G (1st to 7th) are connected to the output terminals S of subtractor / adder units 52A to 52G (1st to 7th), respectively. The control code CODE0<6:0> output from the output terminals S of subtractor / adder units 52A to 52G (1st to 7th) is inverted to generate the inverted control code CODEB0<6:0>.

[0069] Figure 5 shows the distribution voltage V out This shows the case where there are 128 <127:0> units, and the number of inverters and subtractors / adders is 7 each, but the number of inverters and subtractors / adders can change depending on the number of distribution voltages. n In the case of n units, the number of inverters and the number of subtractors / adders can each be n.

[0070] Figure 6 is a diagram showing the configuration of the reference voltage selector shown in Figure 3.

[0071] Referring to Figure 6, the reference voltage selector 121C includes a plurality of transfer gates. The transfer gates may be layered into a plurality of layers L1 to L7. In one embodiment, the plurality of layers L1 to L7 include the first to seventh layers.

[0072] The input terminal of the transfer gate of layer 1 L1 receives the distributed voltage V from the voltage distributor 121A. out <127:0> are inputs respectively. The number of transfer gates in the first layer L1 is equal to the distribution voltage V out The number can be the same as <127:0>. out If there are 128 <127:0> pairs, then the number of transfer gates in the first layer L1 can be 128.

[0073] In each of the first to seventh layers L1 to L7, the transfer gates are of the binary tree type. In each of the first to seventh layers L1 to L7, the transfer gates are arranged in pairs and connected in common to one output terminal.

[0074] The output terminals of the K-th layer are connected to the input terminals of the transfer gates in the K+1-th layer. The number of transfer gates in the K+1-th layer may be half the number of transfer gates in the K-th layer. As shown in Figure 6, the number of transfer gates in the 1st layer L1, 2nd layer L2, 3rd layer L3, 4th layer L4, 5th layer L5, 6th layer L6, and 7th layer L7 are 128, 64, 32, 16, 8, 4, and 2, respectively.

[0075] A transfer gate can have a CMOS structure. That is, a transfer gate includes an NMOS transistor and a PMOS transistor connected in parallel between the input terminal and the output terminal, and can output the signal from the input terminal to the output terminal when both the NMOS transistor and the PMOS transistor are turned on.

[0076] Each of layers L1 to L7 receives one bit of a control code and its inverted bit. This single bit of the control code and its inverted bit can cause one of a pair of transfer gates in layer K to be turned on, while the other is turned off. For example, in layer L7, if a pair of transfer gates TG1 and TG2 are referred to as the first transfer gate TG1 and the second transfer gate TG2, then one of the two transfer gates can be turned on, while the other is turned off.

[0077] The gate electrode of the NMOS transistor NMOS1 of the first transfer gate TG1 and the gate electrode of the PMOS transistor PMOS2 of the second transfer gate TG2 are commonly connected to the first line W1, and the gate electrode of the PMOS transistor PMOS1 of the first transfer gate TG1 and the gate electrode of the NMOS transistor NMOS2 of the second transfer gate TG2 may be commonly connected to the second line W2. CODE0 <6> and CODEB0 <6> These signals are input to the first line W1 and the second line W2, respectively. As a result, either the first transfer gate TG1 or the second transfer gate TG2 is turned on and the other is turned off, which can result in the output of either the distribution voltage input to the first transfer gate TG1 or the distribution voltage input to the second transfer gate TG2. For example, if a "logic high level" is input to the first line W1 and a "logic low level" is input to the second line W2, the first transfer gate TG1 is turned on and the second transfer gate TG2 is turned off, resulting in the output of the distribution voltage input to the first transfer gate TG1. Conversely, if a "logic low level" is input to the first line W1 and a "logic high level" is input to the second line W2, the first transfer gate TG1 is turned off and the second transfer gate TG2 is turned on, resulting in the output of the distribution voltage input to the second transfer gate TG2.

[0078] The transfer gates included in layers L1 to L6 can operate in the same way as the transfer gate included in layer L7.

[0079] Figure 6 shows the case where there are 128 distribution voltages, and the reference voltage selector 121C contains 7 layers and has a 7-bit control code, however the number of layers in the reference voltage selector 121C can vary depending on the number of distribution voltages. n In the case of n units, the number of layers included in the reference voltage selector 121C is n, and the control code can be n bits.

[0080] Figure 7 is a graph showing the change in the reference voltage level of the DQ0 pin due to changes in the offset enable signal, the first code, and the second code in a memory device according to one embodiment of the present disclosure.

[0081] Referring to Figure 7, the DQ drive unit generates a reference voltage for each DQ pin when the offset enable signal EN_OFS is at a "high" level.

[0082] The offset enable signal EN_OFS is at a "high" level, and the most significant bit of the second code DQ0_OFS<3:0> is DQ0_OFS <3> If the value is at a "high" level, the first reference voltage generator of the DQ drive unit combines the internal reference voltage (0 offset) corresponding to the first code VREF_CODE<6:0> and the offset voltage corresponding to DQ0_OFS<2:0> to generate the reference voltage VREF_DQ0 for the DQ0 pin. For example, if the offset enable signal EN_OFS is at a "high" level, DQ0_OFS <3> If the value is at a "high" level and DQ0_OFS<2:0> is "4", the first reference voltage generator combines the internal reference voltage (0 offset) with the offset voltage corresponding to the "4" step to generate the reference voltage VREF_DQ0 for the DQ0 pin.

[0083] On the other hand, the offset enable signal EN_OFS is at a "high" level, and the most significant bit of the second code DQ0_OFS<3:0> is DQ0_OFS <3> If the offset enable signal EN_OFS is at a "low" level, the first reference voltage generator subtracts the offset voltage corresponding to DQ0_OFS<2:0> from the internal reference voltage (0 offset) to generate the reference voltage VREF_DQ0 for the DQ0 pin. For example, if the offset enable signal EN_OFS is at a "low" level, DQ0_OFS <3> When the signal is at a "low" level and DQ0_OFS<2:0> is "4", the first reference voltage generator subtracts the offset voltage corresponding to "4" steps from the internal reference voltage (0 offset) to generate the reference voltage VREF_DQ0 for the DQ0 pin. In Figure 7, when the offset enable signal EN_OFS transitions from a "low" level to a "high" level, DQ0_OFS<2:0> is "0", so the offset voltage is 0, and the reference voltage VREF_DQ0 for the DQ0 pin has the same value as the internal reference voltage (0 offset).

[0084] On the other hand, when the offset enable signal EN_OFS is at a "low" level, the DQ drive unit sets the reference voltage of all DQ pins to the internal reference voltage (0 offset). In Figure 7, when the offset enable signal EN_OFS transitions from a "high" level to a "low" level, the DQ0 reference voltage VREF_DQ0 transitions from OFS+2 to the internal reference voltage (0 offset), and the DQ0 reference voltage VREF_DQ0 is maintained at the internal reference voltage (0 offset) for the duration that the offset enable signal EN_OFS is at a "low" level.

[0085] The effects of the embodiments of this disclosure are as follows:

[0086] Unlike this disclosure, 2 n Two inputs each of the distributed voltages n Configure 2 transfer gates, n By turning on one of the transfer gates and turning off the other, 2 nOne possible method is to select one of the distributed voltages as the reference voltage. In this case, 2 n To control 2 transfer gates, n Because a bit control code is required, a large number of elements are needed to construct the circuit that generates the control code, and the circuit that generates the control code can be large in size. The reference voltage selector 121C according to this disclosure is 2 n Because only an n-bit control code is used to select one of the distributed voltages, the control logic that generates the control code can be configured in a small size using a small number of elements. This can improve area efficiency.

[0087] Figure 8 is a schematic diagram showing the arrangement of the receiving buffer and reference voltage generator according to an embodiment of the present disclosure.

[0088] Referring to Figure 8, the memory device includes first to eighth input / output circuit regions R-IO0 to R-IO7, each corresponding to the first to eighth DQ pins. Although not shown, the first to eighth DQ pins may be located in each of the first to eighth input / output circuit regions R-IO0 to R-IO7. Figure 8 includes eight input / output circuit regions, but this is illustrative, and the number of input / output circuit regions may vary depending on the number of DQ pins.

[0089] The first to eighth input / output circuit regions R-IO0 to R-IO7 may be arranged in a line along the first horizontal direction HD1.

[0090] Each of the first to eighth input / output circuit regions R-IO0 to R-IO7 includes one receive buffer and one reference voltage generator. In each of the first to eighth input / output circuit regions R-IO0 to R-IO7, the reference voltage output from the reference voltage generator is input to the receive buffer. Exemplarily, the first input / output circuit region R-IO0 is located in the first receive buffer 111 and the first reference voltage generator 121, and the first reference voltage VREF_DQ0 output from the first reference voltage generator 121 is input to the first receive buffer 111. The description of the first input / output circuit region R-IO0 also applies to the second to eighth input / output circuit regions R-IO1 to R-IO7.

[0091] Unlike in this disclosure, the reference voltage generator may be located in a separate area from the receive buffer. In such a case, the wiring that transmits the reference voltage output from the reference voltage generator to the receive buffer may be long, resulting in a longer time delay during the transmission of the reference voltage, which may cause the settling time of the reference voltage to exceed a previously set threshold and degrade the signal characteristics.

[0092] According to this disclosure, since the reference voltage generator and the receiving buffer to which the reference voltage output from the reference voltage generator is input are located in a single input / output circuit area, the wiring for transmitting the reference voltage can be configured to be short in length, reducing the time delay that occurs in the process of transmitting the reference voltage output from the reference voltage generator to the receiving buffer, and shortening the settling time of the reference voltage.

[0093] Figures 9 to 11 are illustrative diagrams showing the layout structure of the first input / output circuit region in Figure 8.

[0094] Referring to Figure 9, the first input / output circuit region R_IO0 includes the first region RA1 and the reference voltage generator regions R_121A, R_121B, and R_121C.

[0095] The first region RA1 includes a DQ pin region R-DQ0, a transmit buffer region R-Tx, and a receive buffer region R-Rx. DQ pins may be located in the DQ pin region R-DQ0, a transmit buffer in the transmit buffer region R-Tx, and a receive buffer in the receive buffer region R-Rx.

[0096] In one embodiment, the reference voltage generator regions R_121A, R-121B, and R-121C may be located outside the first region RA1. The reference voltage generator regions R_121A, R-121B, and R-121C may be located adjacent to the receive buffer region R-Rx and the transmit buffer region R-Tx and the second horizontal HD2.

[0097] The reference voltage generator regions R_121A, R-121B, and R-121C include the voltage distributor region R_121A, the control logic region R-121B, and the reference voltage selector region R-121C. The voltage distributor region R-121A, the control logic region R-121B, and the reference voltage selector region R-121C are respectively arranged in the voltage distributor region R-121A, the control logic region R-121B, and the reference voltage selector region R-121C.

[0098] The receive buffer region R-Rx is positioned closer to the reference voltage selector region R-121C than the DQ pin region R-DQ0. At least a portion of the reference voltage selector region R-121C may be superimposed on the receive buffer region R-Rx and the second horizontal HD2. The voltage distributor region R-121A and the control logic region R-121B may be positioned on either side of the reference voltage selector region R-121C in the first horizontal HD1, respectively.

[0099] In the first region RA1, a pull-up driver region R-PUD and a pull-down driver region R-PDD may be arranged on either side of the first horizontal HD1 of the DQ pin region R-DQ0. A pull-up driver is placed in the pull-up driver region R-PUD, and a pull-down driver is placed in the pull-down driver region R-PDD.

[0100] According to this disclosure, since the reference voltage selector area R-121C is adjacent to the receiving buffer area R-Rx, and at least a portion of the reference voltage selector area R-121C is superimposed on the receiving buffer area R-Rx and the second horizontal HD2, the wiring that transmits the reference voltage output from the reference voltage selector to the receiving buffer can be configured to have a short length connecting the reference voltage selector area R-121C and the receiving buffer area R-Rx, and to extend in the second horizontal HD2.

[0101] Referring to Figure 10, the reference voltage generator regions R_121A, R-121B, and R-121C may be positioned adjacent to the first region RA1 and the first horizontal HD1. As shown in Figure 10, the reference voltage generator regions R_121A, R-121B, and R-121C may be positioned to the left of the first region RA1. Although not shown, the reference voltage generator regions R_121A, R-121B, and R-121C may also be positioned to the right of the first region RA1.

[0102] At least a portion of the reference voltage selector region R-121C may be superimposed on the receive buffer region R-Rx and the first horizontal HD1. The voltage distributor region R-121A and the control logic region R-121B are located on either side of the reference voltage selector region R-121C in the second horizontal HD2, respectively.

[0103] Referring to Figure 11, the voltage distributor region R-121A and the reference voltage selector region R-121C may be located between the transmit buffer region R-Tx and the receive buffer region R-Rx.

[0104] The reference voltage selector region R-121C may be positioned closer to the receive buffer region R-Rx than the voltage distributor region R-121A. The reference voltage selector region R-121C may be positioned in the first horizontal direction HD1 between the voltage distributor region R-121A and the receive buffer region R-Rx, and the voltage distributor region R-121A may be positioned in the first horizontal direction HD1 between the reference voltage selector region R-121C and the transmit buffer region R-Tx.

[0105] The control logic region R-121B may be superimposed on the second horizontal HD2 with the reference voltage selector region R-121C. Exemplarily, the control logic region R-121B may be positioned adjacent to the voltage distributor region R-121A, the reference voltage selector region R-121C, and the receive buffer region R-Rx in the second horizontal HD2.

[0106] The above description is merely illustrative of the technical concept of this disclosure, and any person with ordinary skill in the art to which this disclosure belongs could make various modifications and variations without departing from the essential characteristics of this disclosure. Furthermore, the embodiments of this disclosure are for illustrative purposes only and not to limit the technical concept of this disclosure, and the scope of the technical concept of this disclosure is not limited by such embodiments.

Claims

1. Includes multiple reference voltage generators, each corresponding to a different data pin and generating a reference voltage for that corresponding data pin. Each of the aforementioned plurality of reference voltage generators is A voltage distributor that distributes the power supply voltage to multiple distribution voltages; Control logic that receives a first code indicating internal reference voltage level information and a second code indicating offset voltage information for the corresponding data pin, and generates a control code based on the first and second codes; and A memory device including a reference voltage selector, which includes a tree-structured transfer gate that selects one of the plurality of distribution voltages in response to the control code and outputs it as a reference voltage;

2. The transfer gate is grouped into multiple layers, The memory device according to claim 1, wherein in each of the plurality of layers, two transfer gates share one output terminal, and in response to the control code, one of the two transfer gates sharing the one output terminal is turned on and the other is turned off.

3. The number of the aforementioned multiple distribution voltages is 2 ｎ The memory device according to claim 1, wherein the control code is n bits.

4. In the first termination mode, a voltage of a first level is supplied to the voltage distributor as the power supply voltage. The memory device according to claim 1, wherein in the second termination mode, the voltage distributor is supplied with a second level voltage different from the first level as the power supply voltage.

5. The aforementioned voltage distributor is A switch connected between the power supply voltage terminal and the first node, which is turned on in response to an inverting enable signal; A first resistor connected between the first node and the second node; and A resistor ladder including a plurality of second resistors connected in series between the second node and the ground voltage terminal; The memory device according to claim 1, wherein the first resistor is of a different type from the plurality of second resistors.

6. The memory device according to claim 5, wherein the first resistor has a greater resistivity than the plurality of second resistors.

7. The memory device according to claim 1, wherein the control logic includes a plurality of adders that add or subtract the remaining bits of the second code, excluding the most significant bit, to the first code.

8. The first code is provided in common to the plurality of reference voltage generators, The memory device according to claim 1, wherein the second code provided to the first reference voltage generator among the plurality of reference voltage generators is different from the second reference voltage generator among the plurality of reference voltage generators.

9. It includes multiple input / output circuit areas corresponding to multiple data pins, Each of the aforementioned plurality of input / output circuit regions is Receive buffer area; and Includes a reference voltage generator area that provides a reference voltage to the receiving buffer area; The aforementioned reference voltage generator region is Voltage distributor region that distributes the power supply voltage to multiple distribution voltages; A control logic area that receives a first code indicating internal reference voltage level information and a second code indicating offset voltage information for the corresponding data pin, and generates a control code based on the first and second codes; and A memory device including a reference voltage selector area that selects one of a plurality of distribution voltages in response to the control code and outputs it as the reference voltage.

10. Each of the aforementioned plurality of input / output circuit regions is Data pin area; and The transmit buffer area further includes, The data pin area, the receive buffer area, and the transmit buffer area are included in the first area. The memory device according to claim 9, wherein the reference voltage generator region is located outside the first region.

11. The plurality of input / output circuit regions are arranged in a line along the first horizontal direction. The reference voltage generator region is arranged to be adjacent to the first region and the second region in the horizontal direction. The memory device according to claim 10, wherein the second horizontal direction is perpendicular to the first horizontal direction.

12. The memory device according to claim 11, wherein the receiving buffer area is located closer to the reference voltage generator area than the data pin area.

13. The memory device according to claim 11, wherein at least a portion of the reference voltage selector area is superimposed horizontally with the receiving buffer area.

14. The memory device according to claim 11, wherein the voltage distributor region and the control logic region are respectively arranged on both sides of the reference voltage selector region in the first horizontal direction.

15. The plurality of input / output circuit regions are arranged in a line along the first horizontal direction. The memory device according to claim 10, wherein the reference voltage generator region is arranged to be adjacent to the first region in the first horizontal direction.

16. The memory device according to claim 15, wherein at least a portion of the reference voltage selector area is superimposed horizontally with the receiving buffer area in the first direction.

17. The memory device according to claim 15, wherein the voltage distributor region and the control logic region are arranged on both sides of the reference voltage selector region in the first horizontal direction and a second horizontal direction perpendicular to it.

18. The plurality of input / output circuit regions are arranged in a line along the first horizontal direction. The memory device according to claim 10, wherein the voltage distributor region and the receiving buffer region are respectively arranged on both sides of the reference voltage selector region in the first horizontal direction.

19. The receiving buffer area and the transmitting buffer area are arranged along the first horizontal direction. The memory device according to claim 18, wherein the voltage distributor region and the reference voltage selector region are arranged between the receive buffer region and the transmit buffer region.

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