Quantum circuits for computational ground state shifts

Abstract

A method for configuring quantum circuits (300A-C) for computational basis state shifting is disclosed. The quantum circuits are configured with a first quantum register (312, f1), a second quantum register (314, f2), and a first ancillary register (316, a1). The first quantum register has four qubits (f10, f11, f12, f13), and the second quantum register (314, f2) has N-4 qubits (f20,...f2). N-5 ) The following are applied to the first quantum register, the second quantum register, and the first ancillary register (a1) in order: (i) a first step 320 including three CX gates (3201-3203) and a first X gate 3204; (ii) a first segment (324) including seven multi-control gates (3241-3247); (iii) a second segment 326 including a first set 3260 of CX gates, a second set 3262 of CX gates, and an array 3264 of gates disposed between the first and second sets; and (iv) a third segment 328 including two CX gates 3281 and 3282 and a second X gate 3284.

Description

[Technical Field]

[0001] The present disclosure (hereinafter referred to as the "Disclosure") relates to a method for configuring a quantum circuit for computational basis state shifts (state transitions). The Disclosure also relates to a quantum computer or quantum simulator configured to perform the method. The Disclosure further relates to a non-volatile computer-readable medium having stored thereon computer program instructions executable by at least one processor of a classical computer to control the quantum computer or quantum simulator to perform the method.

[0002] Quantum algorithms in which quantum operations scale logarithmically with the number of internal qubit states outperform corresponding classical algorithms that scale linearly or worse, achieving exponential speedups. The process of state shifting is a subroutine of several quantum algorithms. Shifting the computational basis state along various directions is a component of various quantum algorithms. In particular, in quantum walks, computational basis state shifting is used with the coin operator to define a quantum version of a random walk. Computational basis state shifting is responsible for propagating a walker in various directions along a geometric walking domain. In one-dimensional cases, the walker moves left and right along a line; in two-dimensional cases, the walker moves up and down, left and right. Quantum walks themselves are widely used in various applications of quantum computers, such as simulating random walks on quantum machines, solving simultaneous equations using Markov chains, simulating fluid dynamics problems based on the Madelung transform, developing efficient search quantum algorithms on graphs, and efficient matrix encoding. Therefore, optimizing quantum circuits for computational basis state shifting addresses specific needs.

[0003] Currently known quantum shifting methods have two possibilities: with and without the addition of (variable) ancilla registers. The ancilla-free configuration leads to an algorithm that scales linearly with the number of possible states. On the other hand, the introduction of a variable ancilla register provides a logarithmic dependence. These two configurations have complementary advantages and disadvantages. Implementing a shift step using the first configuration requires fewer qubits in the workspace, but the circuit is much deeper than the second configuration. On the other hand, the second configuration has a faster execution time and the number of gates required is a logarithmic function of the size of the state space. However, the number of ancilla qubits grows linearly with the number of control qubits, which quickly leads to a large workspace. To mitigate these drawbacks, the shifting algorithm needs to be redesigned and optimized. Abstract

[0004] The present disclosure seeks to provide improved methods for configuring quantum circuits for computational basis state shifting. The present disclosure also seeks to provide a quantum computer or quantum simulator configured to perform the aforementioned methods. The present disclosure further seeks to provide a non-volatile computer-readable medium storing computer program instructions executable by at least one processor of a classical computer to control a quantum computer or quantum simulator to perform the aforementioned methods. The present disclosure also seeks to provide solutions to existing problems with conventional quantum shifting procedures.

[0005] According to a first aspect, certain embodiments of the present disclosure provide a method for configuring a quantum circuit for computational basis state shifting. The method includes configuring a first quantum register (f1), a second quantum register (f2), and a first ancillary register (a1) for the quantum circuit, where the first quantum register (f1) comprises four qubits (f10, f11, f12, f13) and the second quantum register (f2) comprises N-4 qubits (f20,...f21). N-5 ) The method further comprises: (i) the first step, which includes three CX gates and the first X gate; (ii) the first segment containing seven multi-control gates; (iii) a second segment including a first set of CX gates, a second set of CX gates, and an array of gates disposed between the first set and the second set; (iv) a third segment containing two CX gates and a second X gate; This includes sequentially applying

[0006] According to a second aspect, an embodiment of the present disclosure provides a quantum computer or quantum simulator configured to execute the method according to the first aspect described above.

[0007] According to a third aspect, certain embodiments of the present disclosure seek to provide a non-volatile computer-readable medium storing computer program instructions executable by at least one processor of a classical computer to control a quantum computer or quantum simulator to perform the method according to the first aspect described above.

[0008] Embodiments of the present disclosure substantially eliminate or at least partially solve the aforementioned problems in the prior art and provide quantum circuits that are easily scalable.

[0009] Further aspects, advantages, features and objects of the present disclosure will become apparent from the accompanying drawings and detailed description of illustrative embodiments, taken in conjunction with the appended claims.

[0010] It will also be appreciated that features of the present disclosure can be combined in various combinations without departing from the scope defined by the appended claims. [Brief explanation of the drawings]

[0011] The foregoing summary, as well as the following detailed description of exemplary embodiments, will be better understood when read in conjunction with the accompanying drawings. For the purpose of illustrating the disclosure, exemplary configurations of the disclosure are shown in the drawings. However, the disclosure is not limited to the particular methods and apparatus disclosed therein. Also, the drawings are not to scale. Similar elements are designated by the same numerals wherever possible. Embodiments of the present disclosure will now be described, by way of example, with reference to the following drawings: [Figure 1A] FIG. 1 is a schematic diagram of a quantum computer. [Figure 1B] FIG. 1 is a schematic diagram of a quantum circuit of a quantum computer. [Figure 2A] Schematic of a six-qubit quantum circuit for computing basis state shifts. This circuit is not optimized. [Figure 2B] Schematic of a seven-qubit quantum circuit for computing ground state shifts. This circuit is not optimized. [Figure 2C] FIG. 2C is a schematic diagram of a variable ancillary resistor version of the unoptimized 7-qubit quantum circuit of FIG. 2B. [Figure 3] Figures 3A, 3B, and 3C are schematic diagrams illustrating quantum circuit setups for computational basis state shifting according to an embodiment of the present disclosure for 6, 7, and 8 qubits, respectively, while Figures 3D, 3E, and 3F are schematic diagrams of variable ancillary resistor versions of the quantum circuits of Figures 3A, 3B, and 3C, respectively, according to an embodiment of the present disclosure. [Figure 4A] 1 is a graph showing the number of CX gates (y-axis) as a function of qubits (x-axis) comparing an ancillary resistor-less configuration of an unoptimized quantum circuit with a fixed ancillary resistor configuration of a quantum circuit according to the present disclosure. [Figure 4B] 1 is a graph showing the number of CX gates (y-axis) as a function of state (x-axis) comparing an ancillary-free configuration of an unoptimized quantum circuit with a fixed ancillary register configuration of a quantum circuit according to the present disclosure. [Figure 4C]10 is a graph showing the number of IBM sets of basis gates CX, RZ, SX versus the number of qubits, comparing a variable ancillary register version of an ancillary-free configuration of an unoptimized quantum circuit with a variable ancillary register version of a quantum circuit according to the present disclosure. [Figure 4D] 1 is a graph showing the number of IBM sets of basis gates CX, RZ, SX versus the number of computational states for a variable ancillary register version of an ancillary-free configuration of a non-optimized quantum circuit compared to a variable ancillary register version of a quantum circuit according to the present disclosure. In the accompanying drawings, underlined numbers are used to represent the item at or adjacent to the number. Numbers without underlines are associated with items identified by lines extending from the number. When a number is not underlined and is accompanied by an arrow, the number is used to identify the item to which the arrow points. Detailed Description of the Embodiments

[0012] The following detailed description illustrates embodiments of the present disclosure and how they may be practiced. Although several forms for carrying out the present disclosure have been disclosed, those skilled in the art will recognize that other forms for carrying out the present disclosure are also possible.

[0013] FIG. 1A is a schematic diagram of a quantum computer 100. The quantum computer 100 includes N qubits, depicted as a first qubit 110a, a second qubit 110b, and an Nth qubit 110c. The quantum computer 100 also includes a first ancilla qubit 110d. Each of the qubits 110a, 110b, and 110c is in a superposition of a ground state |0> and an excited state |1>. The quantum computer 100 further includes a state preparation means 102 employed to initialize the quantum computer 100. The quantum computer 100 also optionally includes an implementation means 104 employed to configure gates for implementing a quantum algorithm. Each gate uses one or more of the N qubits. The quantum computer 100 further includes a measurement means 106 employed to measure the states of one or more of the N qubits after execution of the quantum algorithm.

[0014] 1B is a schematic diagram of a quantum circuit 100B. Quantum circuit 100B can be illustrated with a first quantum register 112, a second quantum register 114, and a first ancillary register 116. Also shown is a classical register 160. The term "classical register" refers to a line that provides an interface between a quantum computer and a classical computer.

[0015] The mapping of quantum registers onto quantum computer 100 of FIG. 1A is as follows: f10 corresponds to the first quantum bit 110a. f11 corresponds to the second qubit 110b, and so on. f2 n-5 corresponds to the Nth qubit 110c.

[0016] These N quantum bits are called working qubits. The above register naming is arbitrary. In this disclosure, the first quantum register 112 has four working qubits, and the second quantum register 114 has N-4 working qubits, where N is greater than 4. As an example, for N=6, the first quantum register 112 is composed of working qubits f10, f11, f12, and f13, and the second quantum register 114 is composed of working qubits f20 and f21.

[0017] Referring to FIG. 1B, quantum circuit 100B has an initialization phase 170 in which one or more qubits are set to an initial state, an implementation phase 172 in which the gates that make up the corresponding phase are set sequentially (i.e., set in a time-varying quantum system), and a measurement phase 174 that follows implementation phase 172.

[0018] Ground state shifting is required as a subroutine of various quantum algorithms. Examples of such quantum algorithms include, but are not limited to, quantum walks and efficient block encoding of matrices. In this regard, in some embodiments, a specific problem can be defined that can be executed or simulated on a quantum computer with N working qubits using a quantum algorithm that includes a state-shifting step. For example, this can be a mathematical description of a physical process of interest in the realm of quantum walks. Or, it can be a mathematical description of a physical process of interest in the realm of other procedures that include a propagation step (i.e., a state-shifting step) as an integral part. The specific problem is then posed, and the corresponding parameters are set according to the choice of quantum algorithm configuration and other requirements depending on the quantum algorithm being used. Here, the quantum algorithm configuration refers to the presence or absence of variable-size ancillary registers. Optionally, one of the available software development kits (SDKs) can be used to implement quantum circuits on a quantum computer (e.g., IBM Qiskit). The quantum computer can then be used to execute the quantum circuit.

[0019] The ground state shift is incremented by S + and decrement S - which map the binary encoded states |k> as follows: TIFF2026504256000002.tif839The superposition is induced by the control qubit c and follows the sequence: Resulting in the state shift as TIFF2026504256000003.tif829, where: TIFF2026504256000004.tif829 is a tensor product. In the quantum walk algorithm, the control qubit represents the outcome of a quantum coin flip.

[0020] This disclosure improves state-shifting performance by parallelizing the sequence of increment and decrement operators. This is done by decomposing the state into even and odd states. If the state is even, the increment is achieved by applying an invertor (represented by an X gate in the accompanying drawings) to the least significant qubit, and if the state is odd, the same inverter defines the decrement.

[0021] The state decomposition D requires an ancilla qubit. For states |k> even, the decomposition is TIFF2026504256000005.tif829, where ancilla qubits are marked with the subscript a. For states |k> odd, the decomposition is The ancilla qubits are given in TIFF2026504256000006.tif829. Similarly, ancilla qubits are marked with the subscript a.

[0022] After decomposition, the state is rearranged such that applying an inversion to the least significant qubit achieves an increment and a decrement in parallel. If we denote the rearrangement by R and the inversion by X, the improved state shift is given by the following sequence: TIFF2026504256000007.tif839

[0023] For comparison, a non-optimized quantum circuit (which represents the prior art) and a quantum circuit of the present disclosure are illustrated using several exemplary numbers of qubits. Figures 2A-2C represent a non-optimized quantum circuit, and Figures 3A-3F represent a quantum circuit of the present disclosure.

[0024] FIG. 2A is a schematic diagram of an unoptimized quantum circuit 200A for computational basis state shifting. Quantum circuit 200A has six qubits. This six-qubit unoptimized quantum circuit 200A is configured with a first quantum register 212 and a second quantum register 214. The total number of qubits, N, is six in this illustration. The number of classical registers 260 corresponds to the number of qubits. Further defining notation, the six-qubit unoptimized quantum circuit 200A includes a five-controlled gate 220a, a four-controlled gate 220b, a three-controlled gate 220c, a CX gate 220d, etc. The gates are implemented sequentially, i.e., from left to right, as shown in FIG. 2A (and all figures herein illustrating various quantum circuits).

[0025] As a further example of the notation used herein, five-control gate 220a in FIG. 2A uses all qubits in the first quantum register 212 as a first set of controls corresponding to the state |1>. This is shown as a solid dot in the figure. Five-control gate 220a also uses the last working qubit (f21) in the second quantum register 214 as a control corresponding to the state |0>. This is shown as a hollow dot. Five-control gate 220a uses the first working qubit (f20) in the second quantum register 214 as a target. Throughout this specification, phrases such as "using a qubit as a control" and "using a qubit as a target" mean that the value of the qubit "used as a control" is considered to determine whether a change is required in the value of the qubit "used as a target." The term "use" in phrases such as "using a qubit" should be understood to mean using the qubit for a particular purpose, i.e., as a control or as a target.

[0026] Similar to Figure 2A, Figure 2B is a schematic diagram of an unoptimized quantum circuit 200B for computational basis state shifting. Quantum circuit 200A has seven qubits. The total number of qubits, N, is 7 in this illustration.

[0027] The left-hand portion of each of quantum circuits 200A and 200B (i.e., up to the barrier line) applies a right shift, and the right-hand portion of each of quantum circuits 200A and 200B (i.e., after the barrier line) applies a left shift. In essence, quantum circuits 200A and 200B each add one bit (which corresponds to a right shift) and subtract one bit (which corresponds to a left shift) from the basis state. In this respect, quantum circuits 200A and 200B each perform operations completely analogous to classical methods: they perform addition and subtraction operations in exactly the same way as they are performed on a classical computer. In other words, quantum circuits 200A, 200B do not achieve quantum speedup.

[0028] In terms of scaling, each new qubit added to such a quantum circuit (i.e., 200A or 200B) introduces two new multi-control gates with N-1 controls (as evident from a comparison of FIGS. 2A and 2B). For scaling analysis on this unoptimized configuration, quantum circuits 200A and 200B can be decomposed using the IBM set of basis gates (I, SX, X, RZ, and CX), for example, using the IBM Qiskit transpiler. The transpiling process converts the general form of the algorithm (as shown in FIGS. 2A and 2B) into a device-specific set of operations executable on quantum hardware. In this regard, FIG. 2C is a schematic diagram of a variable ancillary register version 200C of the 7-qubit unoptimized quantum circuit 200B of FIG. 2B. The variable ancillary register version 200C is generated by applying the variable ancillary register (c_anc) decomposition to the unoptimized quantum circuit 200B.

[0029] The dependence of the number of CX gates (considered the most computationally expensive operation) on the number of qubits and computational states for the additional (variable) ancillary register version of the algorithm is shown by the solid lines in Figures 4A and 4B, respectively. An exponential dependence of the number of CX gates on the number of qubits and a clear linear dependence of the number of CX gates on the number of computational states is observed.

[0030] It will be understood that the unoptimized quantum circuits 200A and 200B relate to configurations without an ancillary register. To optimize the quantum circuit, at least one fixed ancillary register can be implemented, as shown in Figures 3A-3F. Furthermore, the number of working qubits depends on the dimensionality of the problem to be solved. When new qubits are introduced into the quantum circuit to increase the dimensionality of the problem to be solved, they are added to a second quantum register (f2). The first quantum register (f1) is fixed and consists of four qubits. Let N be the total number of working qubits in the quantum algorithm.

[0031] 3A, 3B, and 3C are schematic diagrams of quantum circuits 300A, 300B, and 300C setups for computational basis state shifting, with N=6, 7, and 8, respectively, according to one embodiment of the present disclosure. Quantum circuits 300A, 300B, and 300C can be employed for shifting (i.e., left shifts and right shifts). Shifts (transitions) can be one-dimensional or multidimensional. While state shifts are one-dimensional, it will be appreciated that they can be used to shift a single state or a group of states, depending on which group of qubits is used. In other words, a group of states can be shifted by applying the same algorithm (represented by quantum circuits 300A, 300B, and 300C described above) to different groups of qubits. Referring to FIG. 3A, quantum circuit 300A pertains to an example where the total number of working qubits is 6 (i.e., N=6). Referring to FIG. 3B, quantum circuit 300B pertains to another example where the total number of working qubits is 7 (i.e., N=7). Referring to FIG. 3C, quantum circuit 300C pertains to yet another example case in which the total number of working qubits is eight (ie, N=8).

[0032] Each of quantum circuits 300A, 300B, and 300C is configured with a first quantum register 312 (f1), a second quantum register 314 (f2), and a first ancillary register 316 (a1). The first quantum register 312 (f1) has four working qubits (f10, f11, f12, f13), and the second quantum register 314 (f2) has N-4 working qubits (f20, ...f2 N-5 The number of qubits in the first ancillary register 316 (a1) is fixed and equal to 1.

[0033] Each of the quantum circuits 300A, 300B, and 300C is used for the first quantum register 312 (f1), the second quantum register 314 (f2), and the first ancillary register 316 (a1). Here, each of the quantum circuits 300A, 300B, and 300C has, in order: (i) a first step 320 including three CX gates 3201, 3202, 3203 and a first X gate 3204; (ii) the first segment 324 including seven multi-control gates 3241 to 3247; (iii) a second segment 326 including a first set of CX gates 3260, a second set of CX gates 3262, and an array of gates 3264 disposed between the first and second sets; (iv) a third segment 328 including two CX gates 3281 and 3282 and a second X gate 3284;

[0034] As previously mentioned, the gates of quantum circuits 300A, 300B, and 300C are implemented sequentially, i.e., from left to right. Quantum circuits 300A, 300B, and 300C provide a technical advantage, achieved at least in part by adding a fixed ancillary register, first ancillary register 316(a1). A technical advantage of each quantum circuit 300A, 300B, and 300C is that as the number of working qubits increases, only the second segment 326 of these quantum circuits needs to be modified—that is, by adding additional gates to second set of CX gates 3262 and gate array 3264. Introducing additional qubits into a quantum circuit leaves the initial state 320, first segment 324, and third segment 328 unchanged. In particular, the number of controls in multi-control gates 3241-3247 of first segment 324 remains unchanged, as can be seen by comparing Figures 3A, 3B, and 3C. As a result, quantum circuits 300A, 300B, and 300C can be easily scaled up. Scaling quantum circuits 300A, 300B, and 300C is much cheaper than scaling unoptimized quantum circuits 200A and 200B, as can be seen using the graphs in Figures 4A-4D. It will be appreciated that if N is not greater than 5, second segment 326 can be omitted entirely.

[0035] Quantum circuits 300A, 300B, and 300C, as well as other quantum circuits scaled for more working qubits, can be employed for basis state shifting or propagation in quantum computers, as described herein below. These quantum circuits can be key parts of several different quantum algorithms and are optimized to provide significant quantum speedups compared to known quantum circuits (e.g., as shown in FIGS. 2A and 2B). Furthermore, according to embodiments of the present disclosure, these quantum circuits are shorter and more efficient than currently known quantum circuits, in both fixed ancillary register configurations (as shown in FIGS. 3A, 3B, and 3C) and variable ancillary register configurations (as shown in FIGS. 3D, 3E, and 3F). These quantum circuits can be used directly as subroutines for several different applications, such as quantum walks and efficient block encoding of matrices.

[0036] In some embodiments, the three CX gates 3201-3203 of the first step 320 are applied sequentially in the following order: The first CX gate 3201 in the first step, which uses the first working qubit (f10) in the first quantum register 312 (f1) as the control corresponding to the state |1>, and the ancillary qubit in the first ancillary register 316 (a1) as the target. The second CX gate 3202 in the first step. This is the last working qubit (f2) of the second quantum register 314 (f2) as the control corresponding to the state of |1>. N-5 ) and uses the ancillary qubit in the first ancillary register 316 (a1) as the target. The third CX gate 3203 in the first step, which uses the ancillary qubit in the first ancillary register 316 (a1) as the control corresponding to the state of |1> and the second working qubit (f11) in the first quantum register 312 (f1) as the target. Then, the first X gate 3204 in the first step is used for the first working qubit (f10) in the first quantum register 312 (f1).

[0037] In some embodiments, the seven multi-control gates 3241 to 3247 of the first segment 324 are used in the following order: first multi-control gate 3241, second multi-control gate 3242, third multi-control gate 3243, fourth multi-control gate 3244, fifth multi-control gate 3245, sixth multi-control gate 3246, and seventh multi-control gate 3247. However, The first multi-control gate 3241 and the fifth multi-control gate 3245 are connected to the last working qubit (f2) of the second quantum register 314 (f2) as the first control corresponding to the state |0>. N-5 ) and uses the ancillary quantum bit in the first ancillary quantum register 316 (a1) as the second control corresponding to the state |1>, and the second working quantum bit (f11) in the first quantum register 312 (f1) as the target. The second multi-control gate 3242 and the fourth multi-control gate 3244 control the last working qubit (f2) of the second quantum register 314 (f2) as a control corresponding to the state |1>. N-5 ) and the ancillary qubit in the first ancillary register 316 (a1), and uses the third working qubit (f12) in the first quantum register 312 (f1) as the target. The third multi-control gate 3243 uses the second working qubit (f11) of the first quantum register 312 (f1), the third working qubit (f12) of the first quantum register (f1), and the ancillary qubit of the first ancillary register 316 (a1) as controls corresponding to the |1> state, and uses the fourth working qubit (f13) of the first quantum register (f1) as a target. The sixth multi-control gate 3246 controls the second working qubit (f11) of the first quantum register 312 (f1) and the last working qubit (f2) of the second quantum register 314 (f2) as a control corresponding to the |0> state. N-5 ) and uses the ancillary quantum bit in the first ancillary quantum register 316 (a1) as the control corresponding to the state of |1>, and the third working quantum bit (f12) in the first quantum register (f1) as the target. The seventh multi-control gate 3247 controls the second working qubit (f11) of the first quantum register 312 (f1) and the last working qubit (f2) of the second quantum register 314 (f2) as a control corresponding to the |1> state. N-5 ) and the ancillary qubit in the first ancillary register 316 (a1), and uses the third working qubit (f12) in the first quantum register (f1) as the target.

[0038] In some embodiments, the first CX gate set 3260 of the second segment 326 has four CX gates that use the first working qubit (f10), the second working qubit (f11), the third working qubit (f12), and the fourth working qubit (f13) of the first quantum register 312 (f1) as their respective targets, in that order. Each of the four CX gates of the first CX gate set 3260 uses the last working qubit (f2) of the second quantum register 314 (f2) as a control corresponding to the |0> state. N-5 ) to use.

[0039] Further, in some embodiments, the second CX gate set 3262 of the second segment 326 has N-2 CX gates that use the first working qubit (f10), the second working qubit (f11), the third working qubit (f12), and so on up to the (N-2)th working qubit as their respective targets, in that order. Each of the N-2 CX gates of the second CX gate set 3262 uses the last working qubit (f2) of the second quantum register 314 (f2) as a control corresponding to the state |0>. N-5 ) is used. Here, the (N-2)th working qubit can be the working qubit in the first quantum register (f1) or the second quantum register (f2), depending on the value of N. As an example, when N=6, the second CX gate set 3262 has four CX gates, and the (N-2)th working qubit is the fourth working qubit in quantum circuit 300A, which is the fourth working qubit (f13) in the first quantum register (f1). This working qubit (f13) is used as the target for the last one of the four CX gates, as shown in FIG. 3A. When N>6, the (N-2)th working qubit is the working qubit (f2) in the second quantum register (f2). N-7 ) As an example, when N=7, the second set CX gates 3262 has five CX gates, and the (N-2)th working qubit is the first working qubit (f20) of the second quantum register (f2). This working qubit (f20) is used as the target of the last of the five CX gates, as shown in FIG. 3B. As another example, when N=8, the second CX gate set 3262 has six CX gates, and the (N-2)th working qubit is the second working qubit (f21) of the second quantum register (f2). The working qubit (f21) is used as the target of the last of the six CX gates, as shown in FIG. 3C.

[0040] Additionally, in some embodiments, an array of gates 3264 is placed after the first set of CX gates 3260 and before the second set of CX gates 3262. The number of gates in the array is a function of the total number of working qubits (N). It will be appreciated that the second set of CX gates 3262 and the array of gates 3264 depend on the value of N, facilitating scaling up of quantum circuits 300A, 300B, and 300C.

[0041] In some embodiments, the array of gates 3264 comprises: N-5 multi-control gates 3266, indexed 1 through N-5, arranged as an array of gates. The multi-control gate in this array, indexed "M", uses all of the working qubits in the first quantum register (f1) and the first M-1 working qubits in the second quantum register as controls corresponding to the |1> state, and uses the Mth working qubit in the second quantum register (f2) as a target. N-6 CX gates if N is greater than 6. Here, the N-5 multi-control gates and the N-6 CX gates are interleaved. The gate arrangement 3264 starts from the first multi-control gate among the N-5 multi-control gates. Each CX gate controls the last working qubit (f2) of the second quantum register (f2) as a control corresponding to the |0> state. N-5 ), and the Lth CX gate uses as a target the same working qubit that is used as a target by the Lth multi-control gate.

[0042] Here, the first one of the N-5 multi-control gates 3266 (i.e., the multi-control gate with index "1"; M=1) uses all working qubits (f10, f11, f12, f13) of the first quantum register 312 (f1) as controls corresponding to the state of |1>, and uses the first working qubit (f20) of the second quantum register 314 (f2) as a target. Therefore, the first one of the N-5 multi-control gates 3266 is a four-controlled gate, as shown in FIG. 3A.

[0043] Similarly, the second of the N-5 multi-control gates 3266 (i.e., the multi-control gate with index "2"; M=2) uses all working qubits (f10, f11, f12, f13) of the first quantum register 312 (f1) and the first working qubit (f20) of the second quantum register 314 (f2) as controls corresponding to the |1> state, and uses the second working qubit (f21) of the second quantum register 314 (f2) as a target. Thus, the second of the N-5 multi-control gates 3266 is a five-controlled gate, as shown in Figures 3B and 3C.

[0044] Similarly, the third of the N-5 multi-control gates 3266 (i.e., the multi-control gate with index "3"; M=3) uses all of the working qubits (f10, f11, f12, f13) of the first quantum register 312 (f1) and the first working qubit (f20) and the second working qubit (f21) of the second quantum register 314 (f2) as controls corresponding to the |1> state, and uses the third working qubit (f22) of the second quantum register 314 (f2) as a target. Thus, the third of the N-5 multi-control gates 3266 is a six-controlled gate, as shown in FIG. 3C .

[0045] Furthermore, as shown in Figures 3B and 3C, the N-5 multi-control gates and the N-6 CX gates are interleaved. The arrangement of gates starts from the first of the N-5 multi-control gates. Each CX gate is connected to the last working qubit (f2) of the second quantum register (f2). N-5 ) as a control corresponding to the |0> state, and the Lth CX gate uses as a target the same working qubit used as a target by the Lth multi-control gate. As an example, in Figures 3B and 3C, the first of the N-6 CX gates (i.e., the one with L=1) uses as a target the first working qubit (f20) of the second quantum register (f2), but the working qubit (f20) is also used as a target by the first of the N-5 multi-control gates 3266. As another example, in Figure 3C, the second of the N-6 CX gates (i.e., the one with L=2) uses as a target the second working qubit (f21) of the second quantum register (f2), but the working qubit (f21) is also used as a target by the second of the N-5 multi-control gates 3266.

[0046] It will be appreciated that the second segment 326 is a modular segment. As shown in Figures 3B and 3C, the addition of each new qubit to the quantum circuit introduces one multi-control gate and two CX gates, where the multi-control gate has N-2 controls, starting with the first working qubit (f10), and the two CX gates have the last working qubit as a control and the third-to-last working qubit (f2) as a target. n-7 ) This relationship holds for each new qubit added to the quantum circuit.

[0047] Furthermore, in some embodiments, the two CX gates 3281 and 3282 and the second X gate 3284 of the third segment 328 are used sequentially in the following order: The first CX gate 3281 of the third segment. This controls the last working qubit (f2) of the second quantum register 314 (f2) as a control corresponding to the state |1>. N-5 ) and uses the ancillary qubit in the first ancillary register 316 (a1) as the target. The second CX gate 3282 in the third segment, which uses the first working qubit (f10) in the first quantum register 312 (f1) as the control corresponding to the state |1>, and the ancillary qubit in the first ancillary register 316 (a1) as the target.

[0048] Here, the second X gate 3284 of the third segment is used for the ancillary qubit of the first ancillary register 316(a1).

[0049] For scaling analysis of these optimized ancillary configurations, quantum circuits 300A-300C can be decomposed using IBM's basis gate set (I, SX, X, RZ, CX), for example, using the IBM Qiskit transpiler. Transpiling converts the general form of a quantum algorithm (as shown in Figures 3A-3C) into a device-specific set of operations that can be executed on quantum hardware. The dependence of the number of CX gates (considered the most computationally expensive operation) on the number of qubits and computational state is shown by the dashed lines in Figures 4A and 4B, respectively. This comparison assumes that the qubits are fully connected (qubit connectivity is all-to-all), so no additional SWAP gates are required. For quantum circuits 300A-300C, the increase in the number of CX gates with respect to the number of qubits is very small compared to quantum circuits 200A-200B. Furthermore, the slope of the dashed line in Figure 4B is 1.49 (for the optimized quantum circuit), a significant decrease from 5.99 (for the unoptimized quantum circuit). This confirms that the optimized quantum circuits 300A-300C achieve a scaling in computational complexity that significantly exceeds classical computation. In other words, by exploiting the properties of quantum systems (i.e., interference and superposition), this new optimization algorithm provides scaling that is unattainable with classical machines (and thus, theoretically, provides computational quantum speedup).

[0050] At the cost of introducing one ancillar qubit, i.e., the ancillar qubit in the first ancillar register 316 (a1), quantum circuits 300A-300C perform significantly better than unoptimized quantum circuits 200A-200B. It will be appreciated that the number of qubits in the first ancillar register (a1) is independent of the expansion of the working register (i.e., the second quantum register 214 (f2)) and is fixed at one qubit.

[0051] 3D, 3E, and 3F are schematic diagrams of variable ancillary register versions 300D, 300E, and 300F of quantum circuits 300A, 300B, and 300C, respectively, according to embodiments of the present disclosure. Variable ancillary register versions 300D, 300E, and 300F are generated by applying decomposition using a variable ancillary register 350 (c_anc) with N-4 qubits. The third multi-control gate 3243 of the first segment 324 is decomposed into the first subcircuit 370, the sixth multi-control gate 3246 of the first segment 324 is decomposed into the second subcircuit 372, and the seventh multi-control gate 3247 of the first segment 324 is decomposed into the third subcircuit 374. In this regard, in some embodiments, the method further includes configuring a second ancillary register 318(a2) and a variable ancillary register 350(c_anc) having N-4 qubits for decomposition in the quantum circuit. The number of qubits in the second ancillary register 318(a2) is also fixed and equal to 1. Each multi-control gate (having two or more controls) is decomposed using a decomposition algorithm. Such decomposition algorithms are well known in the art.

[0052] Quantum circuits 300D, 300E, and 300F relate to variable ancillary register configurations. The main difference between the variable ancillary register configuration and the fixed ancillary register configuration is that by using a variable ancillary register as a temporary storage device, a multi-control gate with two or more controls is decomposed into a set of two-control gates (i.e., Toffoli gates).

[0053] A technical advantage of such a decomposition is that quantum circuits 300D, 300E, and 300F scale logarithmically as the number of working qubits increases, and is much cheaper than scaling unoptimized quantum circuit 200A. In other words, quantum circuits 300D, 300E, and 300F are logarithmically scalable with respect to the number of computational states.

[0054] In some embodiments, the first sub-circuit 370 has four two-controlled gates and a CX gate, which are used sequentially in the following order: first two-controlled gate, second two-controlled gate, CX gate, third two-controlled gate, and fourth two-controlled gate, where: The first two-control gate and the fourth two-control gate use the second working qubit (f11) and the third working qubit (f12) of the first quantum register 312 (f1) as controls corresponding to the state of |1>, and use the ancillary qubit of the second ancillary register 318 (a2) as targets. The second two-control gate and the third two-control gate use the ancillary quantum bit (a1) of the first ancillary register 316 and the ancillary quantum bit (a2) of the second ancillary register 318 as controls corresponding to the state |1>, and use the first quantum bit (c_anc0) of the variable ancillary register 350 (c_anc) as a target. The CX gate uses the first quantum bit (c_anc0) of the variable ancillary register 350 (c_anc) as the control corresponding to the |1> state, and the fourth quantum bit (f13) of the first quantum register 312 (f1) as the target.

[0055] In some embodiments, the second sub-circuit 372 and the third sub-circuit 374 each have four two-controlled gates and a CX gate, which are used sequentially in the following order: first two-controlled gate, second two-controlled gate, CX gate, third two-controlled gate, and fourth two-controlled gate, where: The first two control gates and the fourth two control gates are connected to the second working qubit (f11) of the first quantum register 312 (f1) and the last working qubit (f2 N-5 ) is used as a control corresponding to the state of |1>, and the ancillary qubit in the second ancillary register 318 (a2) is used as a target. The second two-control gate and the third two-control gate use the ancillary quantum bit (a1) of the first ancillary register 316 and the ancillary quantum bit (a2) of the second ancillary register 318 as controls corresponding to the state |1>, and use the first quantum bit (c_anc0) of the variable ancillary register 350 (c_anc) as a target. The CX gate uses the first qubit (c_anc0) of the variable ancillary register 350 (c_anc) as the control corresponding to the |1> state, and the third qubit (f12) of the first quantum register 312 (f1) as the target.

[0056] Additionally, the second sub-circuit 372 further comprises X gates that are applied before both controls of the first two control gates of the second sub-circuit 372 and after both controls of the fourth two control gates of the second sub-circuit 372. These X gates are incorporated into the second sub-circuit 372 because two of the three controls of the sixth multi-control gate 3246 of the first segment 324 (which is decomposed into the second sub-circuit 372) correspond to the |0> state before decomposition.

[0057] In some embodiments, the N-5 multi-control gates 3266 of the array of gates 3264 are decomposed into sub-circuits 376. As described above, the method further includes configuring the second ancillary register 318 (a2) and the variable ancillary register 350 (c_anc) having N-4 qubits for decomposition in the quantum circuit.

[0058] In some embodiments, sub-circuit 376 has 2N-6 two-control gates and N-5 CX gates. As shown in FIG. 3D , when N equals 6, sub-circuit 376 comprises, in order, a first of 2N-6 two-control gates, a second of 2N-6 two-control gates, a third of 2N-6 two-control gates, a first of N-5 CX gates, a fourth of 2N-6 two-control gates, a fifth of 2N-6 two-control gates, and a sixth of 2N-6 two-control gates, where: The first of the 2N-6 two-control gates and the sixth of the 2N-6 two-control gates use the first working qubit (f10) and the second working qubit (f11) of the first quantum register 312 (f1) as controls corresponding to the |1> state, and use the ancillary qubit of the second ancillary register 318 (a2) as a target. The second of the 2N-6 two-control gates and the fifth of the 2N-6 two-control gates use the third working qubit (f12) of the first quantum register 312 (f1) and the ancillary qubit (a2) of the second ancillary register 318 as controls corresponding to the |1> state, and use the first qubit (c_anc0) of the variable ancillary register 350 (c_anc) as a target. The third of the 2N-6 two-control gates and the fourth of the 2N-6 two-control gates use the fourth working qubit (f13) of the first quantum register 312 (f1) and the first qubit (c_anc0) of the variable ancillary register 350 (c_anc) as a control corresponding to the state of |1>, and use the second qubit (c_anc1) of the variable ancillary register 350 (c_anc) as a target. The first of the N-5 CX gates uses the second qubit (c_anc1) of variable ancillary register 350 (c_anc) as the control corresponding to the |1> state, and the first qubit (f20) of second quantum register 314 (f2) as the target.

[0059] In some embodiments, as shown in FIGS. 3E and 3F, when N is greater than 6, subcircuit 376 has a remainder of 2N-6 two-control gates and a remainder of N-5 CX gates, which are located between the first of the N-5 CX gates and the fourth of the 2N-6 two-control gates. Here, the N-5 CX gates are interleaved with sets of N-6 CX gates and sets of 2N-6 two-control gates, with the last of the N-5 CX gates following the last of the 2N-6 two-control gates. This is shown in FIGS. 3E and 3F for N=7 and 8, respectively. It will be appreciated that the aforementioned N-6 CX gates are original gates present in quantum circuits when N is greater than 6. For example, these N-6 CX gates were also present in quantum circuits 300B and 300C, as shown in FIGS. 3B and 3C, respectively.

[0060] As shown in Figures 3E and 3F, for each new qubit added to the (decomposed) quantum circuit, two additional Toffoli gates, two additional CX gates, and one additional X gate are introduced. This relationship holds for each new qubit added to the (decomposed) quantum circuit.

[0061] Furthermore, during decomposition, the controls of the first CX gate set 3260 and the second CX gate set 3262 are transformed to correspond to the |1> state, and X gates are applied to the controls before and after the first CX gate set 3260 and before and after the second CX gate set 3262. These X gates are incorporated into subcircuit 376 because the controls of the first CX gate set 3260 and the second CX gate set 3262 corresponded to the |0> state before decomposition.

[0062] Figure 4A is a graph showing the number of CX gates (y-axis) as a function of qubits (x-axis) comparing an ancillary-free configuration of a non-optimized quantum circuit with a fixed ancillary register configuration of a quantum circuit of the present disclosure, while Figure 4B is a graph showing the number of CX gates (y-axis) as a function of state (x-axis) comparing an ancillary-free configuration of a non-optimized quantum circuit with a fixed ancillary register configuration of a quantum circuit of the present disclosure.

[0063] To illustrate the advantages of embodiments of the present disclosure, in Figures 4A and 4B, the solid lines relate to an ancillary-free configuration of an unoptimized quantum circuit, and the dashed lines relate to a fixed ancillary register configuration. It can be seen that in the ancillary-free configuration, the number of CX gates grows exponentially with the number of qubits. The number of CX gates can be used as a metric for estimating the cost of a quantum circuit (in terms of implementation, reliability, etc.). It can be seen that in the fixed ancillary register configuration, the number of CX gates is significantly reduced. Figure 4B shows the number of CX gates required (y-axis) as a function of state. Again, it is clear that embodiments of the present disclosure offer surprisingly significant advantages.

[0064] Indeed, at the cost of introducing one ancillary qubit (a1), the fixed ancillary register configuration outperforms the ancillary-free configuration. Note that the added ancillary register (a) is independent of the expansion of the working register (i.e., the second quantum register (f2)) and is fixed at one qubit (i.e., does not depend on the variable ancillary register). The linear slope in Figure 4B decreases from 5.99 to 1.49, demonstrating that embodiments of the present disclosure enable linear scaling in terms of required operations at a significantly lower cost while outperforming classical computation. In other words, by utilizing the properties of quantum computing (i.e., interference, superposition, etc.), embodiments of the present disclosure enable scaling that is unattainable with classical machines.

[0065] Furthermore, a scaling analysis between the variable ancillary register versions of unoptimized quantum circuits 200A-200B (including variable ancillary register version 200C) and the variable ancillary register versions 300D-300F of quantum circuits 300A-300C is shown in FIG. 4C, which is performed in terms of the number of basis gates CX, RZ, and SX in the IBM set relative to the number of qubits. Also, a comparison of the two in terms of the number of basis gates CX, RZ, and SX in the IBM set relative to the number of computational states is shown in FIG. 4D. The solid line corresponds to the variable ancillary register version of the unoptimized quantum circuit configuration without an ancillary register, and the dashed line corresponds to the variable ancillary register configuration of quantum circuits 300D-300F (which are the variable ancillary register versions of quantum circuits 300A-300C, respectively).

[0066] As is evident from Figures 4A-4D, the optimized quantum circuit scales up significantly better across all basis gates and in both configurations (fixed and variable ancillary register configurations). It is also clear that the gate count is significantly reduced compared to the unoptimized quantum circuit. Comparing Figures 2C and 3D also reveals that the variable ancillary register version of optimized quantum circuit 300D requires one less qubit in the variable ancillary register compared to the variable ancillary register version of unoptimized quantum circuit 200C.

[0067] The present disclosure also relates to a quantum computer or quantum simulator configured to perform the above-described method of configuring a quantum circuit for computational basis state shifts as described above. Furthermore, the present disclosure relates to a non-volatile computer-readable medium storing computer program instructions executable by at least one processor of a classical computer to control a quantum computer or quantum simulator to perform the above-described method. The various embodiments and variations disclosed above with respect to the above-described method apply mutatis mutandis to the quantum computer or quantum simulator and the non-volatile computer-readable medium.

Claims

1. 1. A method of configuring a quantum circuit for computational basis state shifting, the method comprising: configuring a first quantum register, a second quantum register, and a first ancillary register for the quantum circuit, wherein the first quantum register has four qubits and the second quantum register has N-4 qubits; The method further comprises: (i) a first step containing three CX gates and the first X gate; (ii) the first segment containing seven multi-control gates; (iii) a second segment including a first set of CX gates, a second set of CX gates, and an array of gates disposed between the first set and the second set; (iv) a third segment containing two CX gates and a second X gate; The method of claim 1, wherein the first and second electrodes are connected to a first electrode.

2. The three CX gates in the first step are: a first CX gate in the first step, using a first working qubit in the first quantum register as a control corresponding to the state |1> and an ancillary qubit in the first ancillary register as a target; a second CX gate in the first step, using the last working qubit in the second quantum register as a control corresponding to the state |1> and the ancillary qubit in the first ancillary register as a target; a third CX gate in the first step, using the ancillary qubit in the first ancillary register as a control corresponding to the state of |1> and the second working qubit in the first quantum register as a target; a first X gate of the first step used for the first working qubit of the first quantum register; The method of claim 1, wherein the steps are applied in the order of:

3. the seven multiple control gates of the first segment are applied in the following order: first multiple control gate, second multiple control gate, third multiple control gate, fourth multiple control gate, fifth multiple control gate, sixth multiple control gate, seventh multiple control gate; the first multi-control gate and the fifth multi-control gate use the last working qubit of the second quantum register as a first control corresponding to a state of |0>, use the ancilla qubit of the first ancilla register as a second control corresponding to a state of |1>, and use the second working qubit of the first quantum register as a target; the second multi-control gate and the fourth multi-control gate use the last working qubit of the second quantum register and the ancillary qubit of the first ancillary register as controls corresponding to the state of |1>, and use the third working qubit of the first quantum register as a target; the third multi-control gate uses the second working qubit of the first quantum register, the third working qubit of the first quantum register, and the ancilla qubit of the first ancilla register as controls corresponding to the state of |1>, and uses the fourth working qubit of the first quantum register as a target; the sixth multi-control gate uses the second working qubit of the first quantum register and the last working qubit of the second quantum register as controls corresponding to a state of |0>, uses the ancilla qubit of the first ancilla register as controls corresponding to a state of |1>, and uses the third working qubit of the first quantum register as a target; the seventh multi-control gate uses the second working qubit of the first quantum register, the last working qubit of the second quantum register, and the ancilla qubit of the first ancilla register as controls corresponding to the state of |1>, and uses the third working qubit of the first quantum register as a target; The method according to claim 1 or 2.

4. the first CX gate set of the second segment has four CX gates that use the first working qubit, the second working qubit, the third working qubit, and the fourth working qubit of the first quantum register as respective targets, in that order; each of the four CX gates in the first CX gate set uses the last working qubit in the second quantum register as a control corresponding to a state of |0>; the second CX gate set of the second segment has N-2 CX gates that use the first working qubit, the second working qubit, the third working qubit, up to the N-2th working qubit, in that order, as their respective targets; each of the N-2 CX gates in the second CX gate set uses the last working qubit in the second quantum register as a control corresponding to a state of |0>; the array of gates is positioned after the first set of CX gates and before the second set of CX gates, the number of gates in the array of gates being a function of the total number of working qubits; 10. A method according to any preceding claim.

5. The gate arrangement is N-5 multi-control gates indexed from 1 to N-5; If N is greater than 6, then N-6 CX gates; Equipped with the N-5 multi-control gates are arranged as an array of gates, wherein the multi-control gate indexed "M" in the array uses all working qubits in the first quantum register and the first M-1 working qubits in the second quantum register as controls corresponding to the state of |1>, and uses the Mth working qubit in the second quantum register as a target; the N-5 multi-control gates and the N-6 CX gates are interleaved, the arrangement of the gates starting from a first multi-control gate among the N-5 multi-control gates, each CX gate using the last working qubit of the second quantum register as a control corresponding to a state of |0>, and an Lth CX gate using as a target the same working qubit used as a target by the Lth multi-control gate; The method of claim 4.

6. The two CX gates and the second X gate of the third segment are: a first CX gate in the third segment, using the last working qubit in the second quantum register as a control corresponding to the state of |1> and the ancillary qubit in the first ancillary register as a target; a second CX gate in the third segment, using a first working qubit in the first quantum register as a control corresponding to the state of |1> and an ancillary qubit in the first ancillary register as a target; and the second X gate of the third segment is used for the ancillary qubit of the first ancillary register.

7. 4. The method of claim 3, wherein the third multi-control gate of the first segment is decomposed into a first sub-circuit, the sixth multi-control gate of the first segment is decomposed into the second sub-circuit, and the seventh multi-control gate of the first segment is decomposed into a third sub-circuit, the method further comprising configuring the second ancillary register and a variable ancillary register having N-4 qubits for decomposition in the quantum circuit.

8. The first sub-circuit has four dual control gates and a CX gate, which are used sequentially in the following order: a first dual control gate, a second dual control gate, a CX gate, a third dual control gate, and a fourth dual control gate, with the proviso that: the first two control gates and the fourth two control gates use the second working qubit and the third working qubit of the first quantum register as controls corresponding to the state of |1> and use the ancillary qubit of the second ancillary register as a target; the second two control gates and the third two control gates use the ancilla qubit of the first ancilla register and the ancilla qubit of the second ancilla register as controls corresponding to the state of |1>, and use the first qubit of the variable ancilla register as a target; The CX gate uses the first qubit of the variable ancillary register as a control corresponding to the state |1> and the fourth qubit of the first quantum register as a target; The method of claim 7.

9. The second sub-circuit and the third sub-circuit each have four two control gates and a CX gate, which are used sequentially in the following order: first two control gate, second two control gate, CX gate, third two control gate, fourth two control gate, with the proviso that: the first two control gates and the fourth two control gates use the second working qubit of the first quantum register and the last working qubit of the second quantum register as controls corresponding to the state of |1>, and use the ancillary qubit of the second ancillary register as a target; the second two control gates and the third two control gates use the ancilla qubit of the first ancilla register and the ancilla qubit of the second ancilla register as controls corresponding to the state of |1>, and use the first qubit of the variable ancilla register as a target; the CX gate uses the first quantum bit of the variable ancillary register as a control corresponding to the state of |1> and the third quantum bit of the first quantum register as a target; the second sub-circuit includes an X gate applied before control of both of the first two control gates of the second sub-circuit and after control of both of the fourth two control gates of the second sub-circuit; 9. The method according to claim 7 or 8.

10. 6. The method of claim 5, wherein the N-5 multi-control gates of the array of gates are decomposed into sub-circuits, the method further comprising configuring the second ancillary register and a variable ancillary register having N-4 qubits for decomposition in the quantum circuit.

11. the sub-circuit having 2N-6 two-control gates and N-5 CX gates, where N equals 6, the sub-circuit comprising, in order, a first of the 2N-6 two-control gates, a second of the 2N-6 two-control gates, a third of the 2N-6 two-control gates, a first of the N-5 CX gates, a fourth of the 2N-6 two-control gates, a fifth of the 2N-6 two-control gates, and a sixth of the 2N-6 two-control gates, wherein the first of the 2N−6 two control gates and the sixth of the 2N−6 two control gates use the first working qubit and the second working qubit of the first quantum register as controls corresponding to the |1> state and use the ancillary qubit of the second ancillary register as a target; the second of the 2N−6 two-control gates and the fifth of the 2N−6 two-control gates use the third working qubit of the first quantum register and the ancillary qubit of the second ancillary register as a control corresponding to a state of |1> and the first qubit of the variable ancillary register as a target; the third one of the 2N-6 two-control gates and the fourth one of the 2N-6 two-control gates use the fourth working qubit of the first quantum register and the first qubit of a variable ancillary register as a control corresponding to the state of |1> and the second qubit of the variable ancillary register as a target; the first of the N-5 CX gates uses the second qubit of the variable ancillary register as a control corresponding to the |1> state and the first qubit of the second quantum register as a target; The method of claim 10.

12. 12. The method of claim 11, wherein, when N is greater than 6, the sub-circuit has the remainder of the 2N-6 two-control gates and the remainder of the N-5 CX gates, which are positioned between the first of the N-5 CX gates and the fourth of the 2N-6 two-control gates, the N-5 CX gates interleaved with sets of each of the 2N-6 CX gates and each of the 2N-6 two-control gates, and the last of the N-5 CX gates is followed by the last of the 2N-6 two-control gates.

13. 13. The method of claim 4, 5, 10, 11 or 12, wherein during decomposition, the controls of the first set of CX gates and the second set of CX gates are transformed to correspond to a |1> state, and X gates are applied to the controls before and after the first set of CX gates and before and after the second set of CX gates.

14. 14. A quantum computer or quantum simulator configured to carry out the method according to any one of claims 1 to 13.

15. A non-volatile computer-readable medium storing computer program instructions executable by at least one processor of a classical computer to control a quantum computer or quantum simulator to perform the method of any of claims 1 to 13.

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