Improved methods for fault detection using periodic signals.

Abstract

The device may include a processing circuit, a first pair of terminals electrically connected to the cable, and a second pair of terminals. The processing circuit may provide a periodic signal including a plurality of pulses to the first terminals. The duration of each pulse may be at least twice the travel time of the pulse along the length of the cable. The processing circuit may also detect a fault in the cable in response to a received signal at the second terminal in response to the periodic signal.

Description

[Technical Field]

[0001] (Priority Claim) This application claims the benefit of the filing date of Chinese Patent Application No. 202310177686.0, "IMPROVED METHODS OF FAULT DETECTION USING A PERIODIC SIGNAL," filed on February 17, 2023.

[0002] FIELD OF THE INVENTION FIELD Embodiments of the present disclosure generally relate to an apparatus and method for fault detection using periodic signals. [Background technology]

[0003] Cables, such as network cables, function as electrical transmission lines capable of transmitting power and / or information using electrical current. Damage to the cable's conductor or insulation can cause a cable fault. Two typical faults that occur in cables include open-circuit faults and short-circuit faults. An open-circuit fault occurs when a break in the cable's conductor prevents and / or attenuates the transmission of electrical signals through the cable. A short-circuit fault typically occurs when a failure in the cable's insulation causes two conductors of the cable to come into contact with each other. Both open-circuit faults and short-circuit faults can degrade cable performance or render the cable unusable. Because cables are widely used in modern infrastructure, cable faults can cause widespread problems for numerous industries. Furthermore, because cables are often laid underground or routed through complex structures, such as vehicles, fault identification and repair are costly and time-consuming. [Brief explanation of the drawings]

[0004] While the present disclosure concludes with claims that particularly point out and distinctly claim certain embodiments, the various features and advantages of embodiments within the scope of the present disclosure may be more readily ascertained from the following description when read in conjunction with the accompanying drawings. [Figure 1]FIG. 2 is a functional block diagram of a network segment according to one or more embodiments. [Figure 2] 1 illustrates a fault detection device according to one or more embodiments. [Figure 3] 1 is a flowchart illustrating a method for detecting faults in a cable, according to one or more embodiments. [Figure 4] 1 is a flowchart illustrating a method for detecting and locating open-circuit faults in a cable, in accordance with one or more embodiments. [Figure 5] 1 is a flowchart illustrating a method for detecting and locating short circuit faults in a cable, according to one or more embodiments. [Figure 6] 1 is a flowchart illustrating a method for detecting a fault in a cable at a connection point between the cable and a first terminal, according to one or more embodiments. [Figure 7] 1 is a flowchart illustrating a method for detecting faults in a cable at a distance substantially greater than zero meters from a connection point between the cable and a first terminal, according to one or more embodiments. [Figure 8] 1 is a flowchart illustrating a method for detecting faults in a cable using a clock signal, according to one or more embodiments. [Figure 9] 1 is a flowchart illustrating a method for detecting and locating open circuit faults in a cable using a clock signal, according to one or more embodiments. [Figure 10] 1 is a flowchart illustrating a method for detecting and locating short circuit faults in a cable using a clock signal, according to one or more embodiments. [Figure 11A] 1 illustrates a signal timing diagram according to one or more embodiments. [Figure 11B] 1 illustrates a signal timing diagram according to one or more embodiments. [Figure 11C] 1 illustrates a signal timing diagram according to one or more embodiments. [Figure 11D] 1 illustrates a signal timing diagram according to one or more embodiments. [Figure 12]1 is a block diagram of a fault detection system according to one or more embodiments. [Figure 13] FIG. 1 is a block diagram of circuitry that may be used, in one or more embodiments, to implement various functions, operations, acts, processes, and / or methods disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0005] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and which show illustrative examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other examples may be utilized, and changes in structure, materials, and processes may be made, as enabled herein, without departing from the scope of the present disclosure.

[0006] The figures presented herein are not meant to be actual illustrations of any particular method, system, device, or structure, but are merely idealized representations used to explain embodiments of the present disclosure. In some cases, similar structures or components in various figures may retain the same or similar numbering for the convenience of the reader. However, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0007] The following description may include examples to assist those skilled in the art in practicing the disclosed embodiments. The use of the terms "exemplary," "example," and "for example" means that the associated description is explanatory and that the scope of the present disclosure is intended to encompass examples and legal equivalents, but the use of such terms is not intended to limit the scope of the disclosed embodiments to the specified components, steps, features, functions, etc.

[0008] It will be readily understood that the components of the embodiments, as generally described and illustrated in the figures herein, could be arranged and designed in a wide variety of different configurations. Thus, the following description of various embodiments is not intended to limit the scope of the disclosure, but is merely representative of various embodiments. While various aspects of the embodiments may be presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0009] Furthermore, the specific implementations shown and described are merely examples and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form so as not to obscure the present disclosure in unnecessary detail. Conversely, the specific implementations shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Additionally, the block definitions and partitioning of logic among various blocks are illustrative of specific implementations. It will be readily apparent to one skilled in the art that the present disclosure can be implemented with numerous other partitioning solutions. For the most part, details regarding timing considerations and the like have been omitted; such details are not necessary to obtain a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0010] Those skilled in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. Some figures may show a signal as a single signal for clarity of presentation and explanation. Those skilled in the art will understand that a signal may represent a bus of signals, which may have various bit widths, and that the present disclosure may be implemented with any number of data signals, including a single data signal.

[0011] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, although the processor may alternatively be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer, and the general-purpose computer executes computing instructions (e.g., software code) associated with the embodiments of the present disclosure.

[0012] The embodiments may be described in terms of a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. While a flowchart may describe operational acts as a sequential process, many of these acts may be performed in a different order, in parallel, or substantially simultaneously. Additionally, the order of acts may be rearranged. A process may correspond to a method, a thread, a function, a procedure, a subroutine, a subprogram, other structure, or combinations thereof. Furthermore, the methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another.

[0013] Any reference to elements herein using designations such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitation is expressly stated. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, reference to a first element and a second element does not imply that only two elements may be used or that the first element must precede the second element in any manner. Additionally, unless otherwise specified, a set of elements may include one or more elements.

[0014] As used herein, the term "substantially" when referring to a given parameter, characteristic, or condition means and includes the extent to which one of ordinary skill in the art would understand that the given parameter, characteristic, or condition is met with slight variations, such as, for example, within acceptable manufacturing tolerances. As an example, depending on the particular parameter, characteristic, or condition that is substantially met, the parameter, characteristic, or condition may be at least 90% met, at least 95% met, or even at least 99% met.

[0015] As used herein, the term "echo," when used with respect to a signal, refers to a transmitted signal that is looped back directly into the receive path. The transmitted signal is understood to be a differential signal, transmitted on a pair of wires, referred to as the positive and negative wires, respectively; therefore, the receive and transmit wires may be the same, e.g., 10BASE-T1S as described in IEEE Std 802.3cg-2019, thereby defining a loopback. Thus, a short is a connection between the positive and negative wires.

[0016] As used herein, the phrase "maximum allowable length," when used with respect to a transmission line, such as a cable, refers to the maximum length of the transmission line allowed by the standard governing the transmission line. For example, a standard governing cable fault detection may require that a cable being tested by a fault detection system be no longer than the maximum allowable length. As a non-limiting example, the maximum allowable length may be 25 meters.

[0017] As used herein, the phrase "received signal," when used in reference to a signal used for cable fault detection, refers to a periodic signal provided on the cable, e.g., a signal that is the sum of an echo signal and one or more reflections of the periodic signal.

[0018] As used herein, the phrase "pulse amplitude" when used in reference to a pulse of a signal refers to the absolute value of the measured potential.

[0019]

[0003] Cables, such as network cables, function as electrical transmission lines capable of carrying power and / or information using electrical current. Damage to the cable's wiring or insulation can result in a cable fault. Two examples of faults that can occur in cables are open-circuit faults and short-circuit faults. An open-circuit fault typically occurs when there is a break in the cable's conductor or when there is a fault in the connection between the terminal and the cable. A short-circuit fault typically occurs when, by way of non-limiting example, two conductors of a cable come into contact with each other (either directly or indirectly through an intermediate conductor) due to a fault in the cable's insulation. Because cables are widely used in modern infrastructure, cable faults can cause widespread problems for numerous infrastructures and industries. Furthermore, cables are often laid underground or routed through complex objects, such as vehicles, making fault identification and repair costly and time-consuming. Therefore, it is desirable to quickly and accurately identify the type and location of a fault in order to efficiently locate, repair, or replace the faulty portion of the cable.

[0020] Cable fault detection may include locating faults in a cable. One method of cable fault detection involves the use of a time-domain reflectometer (TDR). A TDR operates by sending a single pulse of energy along a transmission line, such as a cable. The TDR measures the reflected pulse and the time it takes for the reflected pulse to return to estimate the length of the cable and determine the type and location of a fault in the cable based at least in part on the TDR measurement. The type and location of the fault may be determined using a lookup table that associates TDR measurements with the type and / or location of the fault in the cable. The association in the lookup table may be predetermined by testing a cable with a known fault and associating the type and location of the fault with the resulting TDR measurements.

[0021] However, this fault detection method has several problems that make it difficult to identify the type (e.g., short circuit or open circuit) and location of the fault. First, if a cable has multiple connections along its length, reflections from opens in the cable can become attenuated due to the multiple connections, making the reflections difficult to interpret. Second, if a cable has multiple connections, the overshoot that occurs on the first pulse edge can be difficult to distinguish from multiple reflections resulting from the connections, causing ambiguity in the received reflection. Third, the rules that TDR uses to detect faults depend on the location of the fault itself, which is complicated by the vast number of possible topologies. For example, if a fault is located near the end of the cable, pulse echoes can interfere with reflections from the fault. Interference from pulse echoes can degrade the accuracy of TDR measurements, resulting in unreliable TDR measurements or fault detection results.

[0022] According to the present disclosure, an apparatus is described that provides a periodic signal including pulses, each of the pulses having a duration greater than twice the travel time of the pulse along a length of a cable, and that detects faults in the cable in response to one or more reflections of the provided periodic signal.

[0023] In various examples, periodic signals may allow for reduced ambiguity compared to TDR pulses when analyzing attenuated reflections due to multiple connections, and may also reduce the effect of overshoot on the first pulse edge compared to TDR pulses, leading to a simpler and more accurate method for identifying and locating cable faults than via TDR.

[0024] 1 is a functional block diagram of a network segment 100 including a link layer device, MAC 106, and a physical layer (PHY) device, PHY 104, in accordance with one or more embodiments. By way of non-limiting example, network segment 100 may be a segment of a multi-drop network, a segment of a multi-drop subnetwork, a segment of a mixed-media network, or any combination or sub-combination thereof. By way of non-limiting example, network segment 100 may be, be part of, or include one or more of, without limitation, a microcontroller-based embedded system, a user-type computer, a computer server, a notebook computer, a tablet, a handheld device, a mobile device, a wireless earphone or headphone device, a wired earphone or headphone device, an appliance subsystem, a lighting subsystem, an audio subsystem, a building management system, a home monitoring system (e.g., without limitation, for security or utility use), an elevator system or subsystem, a public transportation control system (e.g., without limitation, for an overground train, subway, trolley, or bus), an automobile system or automobile subsystem, or an industrial control system.

[0025] PHY 104 may interface with MAC 106. As a non-limiting example, PHY 104 and / or MAC 106 may be chip packages that include memory and / or logic configured to perform all or a portion of the embodiments described herein. As a non-limiting example, PHY 104 and MAC 106 may each be implemented as separate chips or circuits (e.g., integrated circuits) within a single chip package (e.g., a system-in-a-package (SIP)).

[0026] PHY 104 also interfaces with shared transmission medium 102, i.e., the physical medium that is the communication path for nodes (including nodes that include instances of PHY 104 and MAC 106) that are part of network segment 100 or of the network of which network segment 100 is a part. As a non-limiting example, shared transmission medium 102 may be a single twisted pair such as used in single-pair Ethernet, such as 10BASE-T1S, a network technology specified by IEEE 802.3cg™.

[0027] FIG. 2 illustrates a fault detection system 200 according to one or more embodiments. The fault detection system may include a fault detection device 202 and a cable (e.g., a network cable) 204. The fault detection device 202 may include a processing circuit 210 electrically connected to the cable 204 via a first pair of terminals 206 and a second pair of terminals 208. While the first terminal 206 and the second terminal 208 are depicted as different terminals in FIG. 2 , this is merely to more easily distinguish between the periodic signal 212 and the received signal 214 in the discussion; the first terminal 206 and the second terminal 208 may be the same or different terminals without departing from the scope. In some embodiments, the first terminal 206 and the second terminal 208 may be in the form of input / output terminals, such that the fault detection system 200 may include any number of input / output terminals. For example, the fault detection system 200 may include one input / output terminal for each conductor included in the cable 204. As a specific, non-limiting example, the first terminal 206 can provide a periodic signal (e.g., periodic signal 212) to a first conductor of the cable, and the second terminal 208 can provide a complementary periodic signal (e.g., a signal having a waveform that mirrors the periodic signal) to a second conductor of the cable. In some embodiments, the processing circuit 210 provides the periodic signal 212 as a differential signal to the cable 204 via the first terminal 206 and receives a received signal 214 from the cable 204 via the second terminal 208. The processing circuit 210 can receive one or more reflections of the periodic signal 212 provided to the cable 204 in the received signal 214, as well as an echo signal of the periodic signal 212 (e.g., via the second terminal 208). In a non-limiting example, the one or more reflections can be a result of the provided periodic signal 212 encountering a fault 216 in the cable 204. In one or more examples, the fault 216 can be an open circuit in the cable 204. In another example, the fault 216 may be a short circuit in the cable 204 .

[0028] Processing circuit 210 may receive a received signal 214, which is the provided periodic signal 212, i.e., the echo signal, plus one or more reflections of the periodic signal 212. In one or more examples, processing circuit 210 may be a signal generator that provides a clock signal to cable 204 (e.g., via first terminal 206) as periodic signal 212 and also receives one or more reflections from the clock signal as received signal 214, which may be the resulting sum of periodic signal 212 and one or more reflections of periodic signal 212. Processing circuit 210 may detect faults in cable 204 in response to received signal 214 received at second terminal 208.

[0029] Cable 204 may be of a maximum allowable length l as shown in FIG. 2, which may be, by way of non-limiting example, substantially 25 meters. The actual length of cable 204 may be less than or equal to the maximum allowable length l (l). In other examples, maximum allowable length l may be any length specified by the standards governing fault detection system 200. Furthermore, cable 204 may be a network cable, such as shared transmission medium 102 of a wired local area network as shown in FIG. 1.

[0030] In one or more examples, the fault detection device 202 may be implemented in a processing circuit, such as a microcontroller. In one or more examples, the fault detection device 202 may be implemented in a physical layer device, such as PHY 104 of FIG. 1. In some such examples, the second terminal 208 and the first terminal 206 may include integrated circuit device connections, terminals, or pins.

[0031] FIG. 3 is a flowchart illustrating a method 300 for detecting a fault in a cable according to one or more embodiments. In one or more examples, method 300 may be performed by a device or system, such as fault detection apparatus 202 (see FIG. 2). In operation 302, method 300 provides a periodic signal (e.g., periodic signal 212 of FIG. 2) including positive-going and negative-going pulses to a first pair of terminals (e.g., first terminal 206 of FIG. 2) that may be electrically connected to a cable (e.g., cable 204 of FIG. 2). The duration of each pulse of the periodic signal is at least twice the travel time of the pulse along the maximum allowable length of the cable (e.g., 25 meters). In operation 304, method 300 detects a fault in the cable (e.g., fault 216 of FIG. 2) in response to a received signal (e.g., received signal 214 of FIG. 2) at a second pair of terminals (e.g., second terminal 208 of FIG. 2) in response to the periodic signal. As previously mentioned, the "received signal" includes the periodic signal and one or more reflections generated in response to the periodic signal, and the first terminal may be the same as the second terminal.

[0032] FIG. 4 is a flowchart illustrating a method 400 for detecting an open circuit in a cable according to one or more embodiments. In operation 402, the method 400 provides a periodic signal including pulses (e.g., periodic signal 212 of FIG. 2 ) to a first terminal (e.g., first terminal 206 of FIG. 2 ), which may be electrically connected to a cable (e.g., cable 204 of FIG. 2 ), wherein the duration of each pulse of the periodic signal is at least twice the travel time of the pulse along the maximum allowable length of the cable. In one or more examples, the maximum allowable length of the cable is 25 meters. In one or more examples, the cable is a shared transmission medium (e.g., shared transmission medium 102 of FIG. 1 ). In operation 404, the method 400 detects the amplitude of a pulse in a received signal (e.g., received signal 214 of FIG. 2 ) following a leading edge of one of the pulses of the periodic signal. In one or more examples, the received signal is the periodic signal plus one or more reflections of the periodic signal.

[0033] Following operation 404, method 400 may proceed to operation 406. In operation 406, method 400 determines whether the amplitude detected in operation 404 is high for substantially the entire duration of the pulse of the periodic signal passing through the cable. As used herein, a "high amplitude" or "high amplitude pulse" is a detected amplitude or pulse having an amplitude higher than a high threshold, where the high threshold is higher than the amplitude of the pulse of the periodic signal (i.e., the echo signal). As used herein, the term "cable" refers to the maximum allowable length of the cable, as the actual length of the cable may be unknown. If a high amplitude is detected for substantially the entire duration of the pulse of the periodic signal, the method proceeds to operation 410, where method 400 detects an open circuit in the cable. If no, the method proceeds to operation 408.

[0034] At operation 408, method 400 determines whether the amplitude detected at operation 404 is a low amplitude followed by a high amplitude pulse within the duration of a pulse of the periodic signal. As used herein, a "low amplitude" or "low amplitude pulse" is a detected amplitude or pulse having an amplitude below a low threshold, which may be substantially zero. If a low amplitude pulse is detected followed by a high amplitude pulse, method 400 proceeds to operation 410, where method 400 detects an open circuit in the cable. If no, the method proceeds to operation 414, where method 400 determines that an open circuit fault is not detected in the cable.

[0035] In one example, the high threshold is greater than the amplitude of the pulses of the periodic signal and the low threshold is substantially zero. In another example, multiple tests on multiple sample cables with predetermined faults are performed to determine appropriate thresholds.

[0036] At operation 410, method 400 detects an open circuit in the cable if it proceeded through either operation 406 or operation 408. Method 400 may then proceed to operation 412. At operation 412, method 400 detects a location of the detected open circuit in the cable in response to a time period beginning with the leading edge of the periodic signal during which a low-amplitude pulse is detected in the received signal within the duration of a pulse of the periodic signal. For example, at operation 412, the location of the detected open circuit may be located at a point along the cable that is a distance from the connection point between the cable and the first terminal along the length of the cable, where the distance may be calculated based on a time period beginning with the leading edge of the pulse during which a low-amplitude pulse is detected in the received signal. In a non-limiting example, if method 400 proceeds through operation 406 during which a high-amplitude pulse is detected in the received signal for substantially the entire duration of the pulse of the periodic signal following the leading edge of the pulse, operation 412 may locate the fault as being substantially zero meters away from the connection point between the cable and the first terminal. Stated another way, in operation 412, method 400 locates the fault based on the period during which a low amplitude pulse is detected within the duration of a pulse of the periodic signal, which, as a non-limiting example, will be zero when proceeding through operation 406. In another non-limiting example, if method 400 proceeds through operation 408 in which a low amplitude pulse is detected in the received signal within the duration of a pulse of the periodic signal following a leading edge, followed by a high amplitude pulse in the received signal, operation 412 may locate the fault as being along the length of the cable at a distance away from the connection point between the first terminal and the cable, the distance being calculated based on the amount of time within the duration of the pulse of the periodic signal that a low amplitude pulse is detected in the received signal.

[0037] FIG. 5 is a flowchart illustrating a method 500 for detecting a short circuit in a cable (e.g., cable 204) according to one or more examples. In operation 502, method 500 provides a periodic signal (e.g., periodic signal 212 of FIG. 2) including pulses to a first terminal (e.g., first terminal 206 of FIG. 2), which may be electrically connected to a cable, wherein the duration of each pulse is at least twice the travel time of the pulse along the maximum allowable length of the cable. In one or more examples, the maximum allowable length of the cable is 25 meters. In one or more examples, the cable is a shared transmission medium (e.g., shared transmission medium 102 of FIG. 1). In operation 504, method 500 detects the amplitude of a received signal (e.g., received signal 214 of FIG. 2) following a leading edge of one of the pulses of the periodic signal (i.e., the echo signal). In one or more examples, the received signal is the periodic signal plus one or more reflections of the periodic signal.

[0038] Following operation 504, method 500 may proceed to operation 506. In operation 506, method 500 checks whether the amplitude detected in operation 504 is a high amplitude followed by a low amplitude within the duration of a pulse of the periodic signal. If yes, method 500 proceeds to operation 510. If no, method 500 proceeds to operation 508.

[0039] At operation 508, method 500 checks whether the amplitude detected at operation 504 is low for substantially the entire duration of the pulse of the periodic signal. If no, method 500 proceeds to operation 514, where no short circuit fault is detected in the cable. If yes, method 500 proceeds to operation 510.

[0040] At operation 510, method 500 detects a short circuit in the cable via either operation 506 or operation 508. At operation 512, method 500 detects a location of the detected short circuit in the cable in response to a time period beginning with the leading edge of the periodic signal during which a high-amplitude pulse is detected in the received signal. In a non-limiting example, if method 500 proceeds through operation 506 and a low-amplitude pulse is detected in the received signal for substantially the entire duration of the pulse of the periodic signal, operation 512 may locate the fault as being substantially zero meters away from the point of connection between the cable and the first terminal. Stated another way, at operation 512, method 500 locates the fault based on the time period during which a high-amplitude pulse is detected within the duration of the pulse of the periodic signal, which, as a non-limiting example, would be zero if proceeding through operation 506. As another non-limiting example, if method 500 proceeds to operation 508 in which a high amplitude pulse is detected in the received signal following the leading edge of one of the pulses of the periodic signal, followed by a low amplitude pulse in the received signal within the duration of the pulse of the periodic signal, operation 512 may locate the fault as being more than zero meters away from the point of connection between the cable and the first terminal in response to the amount of time the high amplitude pulse is detected in the received signal.

[0041] FIG. 6 is a flowchart illustrating a method 600 for detecting a fault (e.g., fault 216 in FIG. 2 ) in a cable (e.g., cable 204 in FIG. 2 ) at a connection point between a first terminal (e.g., first terminal 206 in FIG. 2 ) and the cable electrically connected to the first terminal. In operation 602, method 600 provides a periodic signal including pulses to the first terminal, each pulse having a duration at least twice the travel time of the pulse along the maximum allowable length of the cable. In one or more examples, the maximum allowable length of the cable is 25 meters. In one or more examples, the cable is a shared transmission medium (e.g., shared transmission medium 102 in FIG. 1 ). In operation 604, method 600 detects the amplitude of a pulse in a received signal following a leading edge of one of the pulses in the periodic signal. In one or more examples, the received signal is the periodic signal plus one or more reflections of the periodic signal.

[0042] Next, following operation 604, method 600 may proceed to operation 606. At operation 606, method 600 checks whether the amplitude detected at operation 604 is high for substantially the entire duration of the pulse of the periodic signal. If yes, method 600 proceeds to operation 610. If no, method 600 proceeds to operation 608. At operation 608, method 600 checks whether the amplitude detected at operation 604 is low for substantially the entire duration of the pulse of the periodic signal. If no, method 600 proceeds to operation 612, where no fault is detected at the connection point between the first terminal and the cable. If yes, method 600 proceeds to operation 610. At operation 610, having moved through either operation 606 or 608, method 600 detects a fault in the cable at the connection point between the first terminal and the cable.

[0043] FIG. 7 is a flowchart illustrating a method 700 for detecting a fault (e.g., fault 216 in FIG. 2 ) in a cable (e.g., cable 204 in FIG. 2 ) substantially greater than zero meters from a connection point between a first terminal (e.g., first terminal 206 in FIG. 2 ) and a cable electrically connected to the first terminal. In operation 702, method 700 provides a periodic signal (e.g., periodic signal 212 in FIG. 2 ) including pulses to the first terminal, wherein the duration of each pulse is at least twice the travel time of the pulse along the maximum allowable length of the cable. In one or more examples, the maximum allowable length of the cable is 25 meters. In one or more examples, the cable is a shared transmission medium (e.g., shared transmission medium 102 in FIG. 1 ). In operation 704, method 700 detects the amplitude of a received signal (e.g., received signal 214 in FIG. 2 ) following a leading edge of one of the pulses of the periodic signal. In one or more examples, the received signal is the periodic signal plus one or more reflections of the periodic signal.

[0044] Following operation 704, method 700 may proceed to operation 706. In operation 706, method 700 checks whether the amplitude detected in operation 704 is a high amplitude followed by a low amplitude within the duration of a pulse of the periodic signal. If yes, method 700 proceeds to operation 710. If no, method 700 proceeds to operation 708.

[0045] At operation 708, method 700 checks whether the amplitude detected at operation 704 is a high amplitude followed by a low amplitude within the duration of a pulse of the periodic signal. If no, method 700 proceeds to operation 712, where no fault is detected at a distance greater than substantially zero meters from the connection point between the cable and the first terminal. If yes, method 700 proceeds to operation 710. At operation 710, method 700, having moved through either operation 706 or 708, detects a fault in the cable at a distance greater than substantially zero meters from the connection point between the cable and the first terminal.

[0046] 8 is a flowchart illustrating a method 800 for detecting a fault (e.g., fault 216 of FIG. 2) in a cable (e.g., cable 204 of FIG. 2) in accordance with one or more embodiments. At operation 802, method 800 provides a clock signal to a cable (e.g., cable 204 of FIG. 2), wherein the duration of a single clock cycle of the clock signal is at least four times the travel time of a pulse of the clock signal along a maximum length of the cable. At operation 804, method 800 detects the fault in the cable in response to a received signal, the received signal being received from the cable in response to the clock signal.

[0047] FIG. 9 is a flowchart illustrating a method 900 for detecting an open circuit in a cable (e.g., cable 204 of FIG. 2 ), according to one or more examples. In operation 902, method 900 provides a clock signal to the cable, wherein the duration of a single clock cycle is at least four times the travel time of a pulse of the clock signal along the maximum allowable length of the cable. In one or more examples, the clock signal may be a low-frequency clock signal. In one or more examples, the maximum allowable length of the cable is 25 meters. In one or more examples, the cable is a shared transmission medium (e.g., shared transmission medium 102 of FIG. 1 ). In operation 904, method 900 detects the amplitude of a received signal following a leading edge of a pulse of the clock signal. Each pulse of the clock signal may correspond to a first logic level of the clock signal. In one or more examples, the received signal is the clock signal plus one or more reflections of the clock signal.

[0048] Next, following operation 904, method 900 may proceed to operation 906. In operation 906, method 900 checks whether the amplitude detected in operation 904 is high amplitude (i.e., amplitude above a high threshold that is higher than the amplitude of the pulse of the clock signal) for substantially the entire duration of the pulse of the clock signal. If yes, method 900 proceeds to operation 910. If no, method 900 proceeds to operation 908. In operation 908, method 900 checks whether the amplitude detected in operation 904 is low amplitude (i.e., amplitude below a low threshold, which may be substantially zero) in the received signal and is followed by a high amplitude pulse and within the duration of the pulse of the clock signal that follows the leading edge of the clock signal. If no, the method proceeds to operation 914, where no open circuit fault is detected in the cable. If yes, method 900 proceeds to operation 910.

[0049] At operation 910, method 900 detects an open circuit in the cable via either operation 906 or operation 908. At operation 912, method 900 detects a location of the detected open circuit in the cable in response to a time period beginning with the leading edge of a pulse of the clock signal during which a low-amplitude pulse is detected in the received signal. For example, at operation 910, the location of the detected open circuit may be located at a point in the cable that is a distance from the connection point between the cable and the first terminal, and the distance may be calculated based on the time period beginning with the leading edge of the pulse of the clock signal during which a low-amplitude pulse is detected in the received signal. In a non-limiting example, if method 900 proceeds to operation 906 and a high-amplitude pulse is detected in the received signal for substantially the entire duration of the pulse of the clock signal, operation 912 may locate the fault as being substantially zero meters away from the connection point between the cable and the first terminal. Stated another way, at operation 912, method 900 locates the fault based on the time period during which a low-amplitude pulse is detected within the duration of the pulse of the clock signal, which is zero when proceeding through operation 906. As another non-limiting example, if method 900 proceeds to operation 908 and there is a low amplitude pulse detected in the received signal within the duration of a pulse of the clock signal, followed by a high amplitude pulse in the received signal within the duration of the pulse of the clock signal, operation 912 may locate the fault as being more than zero meters away from the point of connection between the cable and the first terminal based on the period during which the low amplitude pulse is detected within the duration of the pulse of the clock signal.

[0050] FIG. 10 is a flowchart illustrating a method 1000 for detecting an open circuit in a cable (e.g., cable 204 of FIG. 2) in response to one or more reflections of a clock signal, according to one or more examples. In operation 1002, method 1000 provides a clock signal to the cable, wherein the duration of a single clock cycle is at least four times the travel time of a pulse of the clock signal along the maximum allowable length of the cable. In one or more examples, the clock signal may be a low-frequency clock signal. In one or more examples, the maximum allowable length of the cable is 25 meters. In one or more examples, the cable is a shared transmission medium (e.g., shared transmission medium 102 of FIG. 1). In operation 1004, method 1000 detects the amplitude of a received signal following a leading edge of a pulse of the clock signal. In one or more examples, the received signal is the clock signal plus one or more reflections of the clock signal.

[0051] Next, following operation 1004, method 1000 may proceed to operation 1006. In operation 1006, method 1000 checks whether the amplitude detected in operation 1004 is a high amplitude followed by a low amplitude within the duration of a pulse of the clock signal. If yes, method 1000 proceeds to operation 1010. If no, method 1000 continues to operation 1008. In operation 1008, method 1000 detects a high amplitude pulse in the received signal within the duration of a pulse of the clock signal, followed by a low amplitude pulse in the received signal within the duration of the pulse of the clock signal. If yes, method 1000 proceeds to operation 1010. If no, method 1000 continues to operation 1014, and no short circuit fault is detected in the cable.

[0052] At operation 1010, method 1000 detects a short circuit in the cable via either operation 1006 or operation 1008. At operation 1012, method 1000 detects a location of the detected short circuit in the cable in response to a time period beginning with a leading edge of a pulse of the clock signal during which a high amplitude pulse is detected in the received signal. For example, at operation 1010, the location of the detected short circuit may be located at a point in the cable that is a distance from the connection point between the cable and the first terminal, and the distance may be calculated based on a time period beginning with a leading edge of a pulse of the clock signal during which a high amplitude pulse is detected in the received signal. In a non-limiting example, if method 1000 proceeds to operation 1006 and a low amplitude pulse is detected in the received signal for substantially the entire duration of the pulse of the clock signal, operation 1012 may locate the fault as being substantially zero meters away from the connection point between the cable and the first terminal. Stated another way, in operation 1012, method 1000 locates the fault based on the time period during which a high amplitude pulse is detected within the duration of a pulse of the clock signal, which is zero when proceeding through operation 1006. In another example, if method 1000 proceeds to operation 1008 and a high amplitude pulse is detected in the received signal within the duration of a pulse of the clock signal, followed by a low amplitude pulse is detected in the received signal within the duration of a pulse of the periodic signal, operation 1012 may locate the fault to a location greater than zero meters from the point of connection between the cable and the first terminal, the location being determined based on the time the high amplitude pulse was detected within the duration of the pulse of the clock signal.

[0053] 11A is an example of a signal timing diagram 1100a showing signals from the fault detection system 200 of FIG. 2 where an open-circuit fault is located substantially zero meters from the connection point between the cable and the first terminal. The signal timing diagram 1100a shows a periodic signal 1102, one or more reflections 1114a of the periodic signal 1102, and a received signal 1112a.

[0054] In one or more examples, the received signal 1112a is the sum of the periodic signal 1102 (i.e., the echo signal) and one or more reflections 1114a. Furthermore, the signal timing diagram 1100a also includes a period 1104 representing the round trip time, which is the duration of the maximum amount of time it may take for a pulse of the periodic signal to travel back across the cable, i.e., the period during which a processing circuit (e.g., processing circuit 210 of FIG. 2 ) may detect the amplitude of the received signal 1112a beginning with a leading edge 1106 of the periodic signal 1102. In one or more examples, the period 1104 represents twice the travel time of a pulse of the periodic signal 1102 along the maximum length of the cable. In one or more examples, the leading edge 1106 may be either a rising edge or a falling edge of the periodic signal 1102. In one or more examples, the periodic signal 1102 may be in the form of a clock signal.

[0055] 11A, the periodic signal 1102 may have a duty cycle of substantially 50%. Further, in one or more examples, the pulses of the received signal 1112a may be in the form of high-amplitude pulses 1108, the amplitude of which is greater than a high threshold, which in turn is greater than the amplitude of the corresponding pulses of the periodic signal 1102.

[0056] 11A, the sum of the periodic signal 1102 and one or more reflections 1114a creates a signal pattern of a received signal 1112a that is detected during a period 1104 following a leading edge 1106 of the periodic signal 1102. For example, signal timing diagram 1100a includes multiple signal diagrams: one for the periodic signal 1102, one for one or more reflections 1114a, and the resulting received signal 1112a.

[0057] In one or more examples, a processing circuit (e.g., processing circuit 210) may detect both the type of fault (e.g., open or short) and the location of the fault along the cable to which the periodic signal is provided in response to a signal pattern exhibited by a received signal (e.g., received signal 1112a) within time period 1104. For example, in the example depicted in signal timing diagram 1100a, an open circuit at a distance of substantially zero meters may be detected if a high-amplitude pulse 1108 is detected within time period 1104 and for substantially the entirety of time period 1104, and this high-amplitude pulse represents periodic signal 1102 plus reflections from an open connection at zero meters as represented by one or more reflections 1114a, and therefore coincides with periodic signal 1102.

[0058] 11B is an example of a signal timing diagram 1100b showing signals from the fault detection system 200 of FIG. 2 where an open circuit is located substantially greater than zero meters from the connection point between the cable and the first terminal. The signal timing diagram 1100b shows a periodic signal 1102, one or more reflections 1114b of the periodic signal 1102, and a received signal 1112b.

[0059] Received signal 1112b and one or more reflections 1114b may be identical to received signal 1112a and one or more reflections 1114a, respectively, shown in FIG. 11A , except for the different signal patterns detected within time period 1104. As shown in the example depicted in signal timing diagram 1100b, an open circuit at a distance substantially greater than zero meters from the connection point between the cable and the first terminal may be detected if, within time period 1104, a low-amplitude pulse 1110 is detected followed by a high-amplitude pulse 1108. The one or more reflections 1114b at the rising edge of periodic signal 1102 represent a previous negative-going portion of periodic signal 1102 that was reflected back by the open connection. Thus, at the rising edge of periodic signal 1102, the one or more reflections 1114b reduce the amplitude of received signal 1112b. Because the pulse width is greater than the maximum round trip time, at least a portion of one or more reflections 1114b coincides with the positive portion of the periodic signal 1102 when the rising edge of the periodic signal 1102 is received as part of the received signal 1112b after a delay due to the round trip time from an open connection, as indicated by the high amplitude pulse 1108.

[0060] 11C is an example of a signal timing diagram 1100c showing signals from the fault detection system 200 of FIG. 2 where the short circuit is located substantially zero meters from the connection point between the cable and the first terminal. The signal timing diagram 1100c shows a periodic signal 1102, one or more reflections 1114c of the periodic signal 1102, and a received signal 1112c.

[0061] Received signal 1112c and one or more reflections 1114c may be identical to received signal 1112a and one or more reflections 1114a, respectively, shown in FIG. 11A, except for a different signal pattern, including a different signal pattern, detected within time period 1104. As shown in the example depicted in signal timing diagram 1100c, a short located substantially zero meters from the connection point between the cable and the first terminal may be detected if a low amplitude pulse 1110 is detected within time period 1104, where the short provides an inverted signal substantially aligned in time with periodic signal 1102 (because the positive and negative wires are shorted as one or more reflections 1114c).

[0062] 11D is an example of a signal timing diagram 1100d illustrating signals from the fault detection system 200 of FIG. 2 when an open circuit is located substantially greater than zero meters from the connection point between the cable and the first terminal. The signal timing diagram 1100d shows a periodic signal 1102, one or more reflections 1114d of the periodic signal 1102, and a received signal 1112d.

[0063] Received signal 1112d and one or more reflections 1114d may be identical to received signal 1112a and one or more reflections 1114a, respectively, shown in FIG. 11A, except for the different signal patterns detected within time period 1104. As shown in the sample depicted in signal timing diagram 1100d, an open circuit located substantially greater than zero meters from the connection point between the cable and the first terminal may be detected if, within time period 1104, a high-amplitude pulse 1108 is detected followed by a low-amplitude pulse 1110. One or more reflections 1114d at the rising edge of periodic signal 1102 represent the previous negative-going portion of periodic signal 1102 reflected back by the short connection and inverted. Thus, at the rising edge of periodic signal 1102, one or more reflections 1114d increase the amplitude of received signal 1112d. Because the pulse width is greater than the maximum round trip time, at least a portion of one or more reflections 1114d, or the positive going portion of the inverted periodic signal 1102, coincides with the positive going portion of the periodic signal 1102, as indicated by the falling edge of the high amplitude pulse 1108.

[0064] 12 is a block diagram of a fault detection system 1200 according to one or more embodiments. The fault detection system 1200 may include a signal generator 1202, a cable 1206, a periodic signal PCS (physical coding sublayer) 1216, a received signal PCS 1220, a medium dependent interface (MDI) 1218, a multiplexer (MUX) 1222, a processing circuit 1210, and a fault detector 1204.

[0065] In one or more examples, signal generator 1202 may provide a periodic signal 1214 to cable 1206 via MUX 1222 and MDI 1218. In one or more examples, signal generator 1202 may be in the form of a clock signal generator that may provide a clock signal to cable 1206 via MUX 1222 and MDI 1218. In one or more examples, fault detector 1204 may receive a received signal 1212, which in one or more examples is a sum of periodic signal 1214 and one or more reflections of periodic signal 1214. In one or more examples, signal generator 1202 may also provide a leading edge indicator 1208 to fault detector 1204, and fault detector 1204 may receive leading edge indicator 1208 from signal generator 1202. In one or more examples, the fault detector 1204 may detect a leading edge of the periodic signal 1214 in response to the received signal 1212, and the leading edge indicator 1208 may not be provided or may be generated by the fault detector 1204. In one or more examples, the leading edge indicator 1208 may be an indication of a rising edge or a falling edge of the periodic signal 1214.

[0066] In one or more examples, the fault detector 1204 may determine the type and location of the fault based at least in part on the received signal 1212 and the leading edge indicator 1208. For example, the fault detector 1204 may begin detecting the amplitude of the received signal 1212, with the detection starting at the leading edge of the periodic signal 1214 according to the leading edge indicator 1208. The fault detector 1204 can then detect the type and location of the fault based on the detected amplitude of the received signal 1212. In one or more examples, the fault detector 1204 may then provide the detected type and location of the fault to the processing circuit 1210. It will be understood that the signal generator 1202, the fault detector 1204, and the processing circuit 1210, in one or more examples, can be a single processor for performing the aforementioned functions.

[0067] The periodic signal PCS 1216 and the received signal PCS 1220 may provide data encoding, decoding, scrambling, descrambling, or perform alignment marker insertion and removal, as well as lane block synchronization and deskew. The periodic signal PCS 1216 may also provide T1S traffic to a MUX 1222. The MUX 1222 may take multiple input connections and select which of the input connections to pass to its output. For example, the MUX 1222 may select whether the T1S traffic provided by the periodic signal PCS 1216 or the periodic signal 1214 provided by the signal generator 1202 is passed to the MDI 1218. The MDI 1218 may be an interface between a physical layer implementation (e.g., the T1S traffic or the periodic signal 1214) and a physical transmission medium (e.g., the cable 1206).

[0068] Those skilled in the art will appreciate that the functional elements (e.g., functions, operations, actions, processes, and / or methods) of the embodiments disclosed herein may be implemented in any suitable hardware, software, firmware, or combination thereof. Figure 13 illustrates a non-limiting example implementation of the functional elements disclosed herein. In one or more embodiments, some or all of the functional elements disclosed herein may be performed by hardware specifically configured to perform the functional elements.

[0069] 13 is a block diagram of a circuit 1300 that, in one or more embodiments, may be used to implement various functions, operations, acts, processes, and / or methods disclosed herein. The circuit 1300 includes one or more processors 1302 (sometimes referred to herein as “processors 1302”) operably coupled to one or more data storage devices (sometimes referred to herein as “storage devices 1304”). The storage devices 1304 include machine-executable code 1306 stored thereon, and the processors 1302 include logic circuitry 1308. The machine-executable code 1306 includes information describing functional elements that may be implemented (e.g., executed) by the logic circuitry 1308. The logic circuitry 1308 is adapted to implement (e.g., execute) the functional elements described by the machine-executable code 1306. The circuitry 1300, when executing the functional elements described by the machine-executable code 1306, should be considered as dedicated hardware configured to execute the functional elements disclosed herein. In one or more embodiments, processor 1302 may execute the functional elements described by machine-executable code 1306 sequentially, simultaneously (e.g., on one or more different hardware platforms), or in one or more parallel processing streams.

[0070] When implemented by the logic 1308 of the processor 1302, the machine-executable code 1306 causes the processor 1302 to perform the operations of embodiments disclosed herein. For example, the machine-executable code 1306 may cause the processor 1302 to perform at least a portion of, or all of, method 300 of Figure 3, method 400 of Figure 4, method 500 of Figure 5, method 600 of Figure 6, method 700 of Figure 7, method 800 of Figure 8, method 900 of Figure 9, and / or method 1000 of Figure 10. As another example, the machine-executable code 1306 may cause the processor 1302 to perform at least a portion of, or all of, the operations discussed with respect to the apparatus of Figure 2. As a specific, non-limiting example, the machine-executable code 1306 may adapt the processor 1302 to provide a periodic signal including pulses to a first terminal, the pulses each having a duration greater than two times the travel time of the pulse along a length of the cable, and detect a fault in the cable in response to one or more reflections of the periodic signal received at a second terminal. As another specific, non-limiting example, the machine-executable code 1306 may adapt the processor 1302 to provide a clock signal to a cable, the duration of a single clock cycle of the clock signal being greater than four times the travel time of the clock along a length of the cable, and detect a fault in the cable in response to one or more reflections of the clock signal.

[0071] The processor 1302 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. Although a general-purpose computer including a processor is considered a special-purpose computer, the general-purpose computer executes functional elements corresponding to machine-executable code 1306 (e.g., software code, firmware code, hardware descriptions) associated with embodiments of the present disclosure. It should be noted that the general-purpose processor (sometimes referred to herein as a host processor or simply host) may be a microprocessor, but the processor 1302 may alternatively include any conventional processor, controller, microcontroller, or state machine. The processor 1302 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0072] In one or more embodiments, the memory device 1304 includes a volatile data storage device (e.g., random-access memory (RAM)), a non-volatile data storage device (e.g., flash memory, a hard disk drive, a solid-state drive, an erasable programmable read-only memory (EPROM), etc.). In one or more embodiments, the processor 1302 and the memory device 1304 may be implemented in a single device (e.g., a semiconductor device product, a system on chip (SOC), etc.). In one or more embodiments, the processor 1302 and the memory device 1304 may be implemented in separate devices.

[0073] In one or more embodiments, machine-executable code 1306 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored by storage device 1304, accessed directly by processor 1302, and executed by processor 1302 using at least logic circuitry 1308. Also, as a non-limiting example, the computer-readable instructions may be stored in storage device 1304, transferred for execution to a memory device (not shown), and executed by processor 1302 using at least logic circuitry 1308. Thus, in one or more embodiments, logic circuitry 1308 includes electrically configurable logic circuitry 1308.

[0074] In one or more embodiments, machine-executable code 1306 may describe hardware (e.g., circuits) to be implemented in logic circuitry 1308 to perform the functional elements. This hardware may be described at any of a variety of levels of abstraction, from low-level transistor layouts to high-level description languages. At high levels of abstraction, a hardware description language (HDL) such as the IEEE standard hardware description language (HDL) may be used. As non-limiting examples, VERILOG™, SYSTEMVERILOG™, or very large scale integration (VLSI) hardware description language (VHDL™) may be used.

[0075] The HDL description may be converted into a description at any of a number of other levels of abstraction, as desired. As a non-limiting example, the high-level description may be converted into a logic-level description, such as a register-transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting example, micro-operations performed by hardware logic circuits (e.g., without limitation, gates, flip-flops, registers) of logic circuit 1308 may be described in RTL and then converted by a synthesis tool into a GL description, which may be converted by a place-and-route tool into a layout-level description that corresponds to the physical layout of an integrated circuit of a programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination thereof. Thus, in one or more embodiments, machine-executable code 1306 may include HDL, RTL, a GL description, a mask-level description, other hardware descriptions, or any combination thereof.

[0076] In embodiments in which machine-executable code 1306 includes a hardware description (at any level of abstraction), a system (not shown, but including storage 1304) may implement the hardware description described by machine-executable code 1306. As a non-limiting example, processor 1302 may include a programmable logic device (e.g., an FPGA or PLC), and logic circuitry 1308 may be electronically controlled to implement circuitry in logic circuitry 1308 that corresponds to the hardware description. Also, as a non-limiting example, logic circuitry 1308 may include hardwired logic manufactured by a manufacturing system (not shown, but including storage 1304) according to the hardware description in machine-executable code 1306.

[0077] Regardless of whether the machine-executable code 1306 includes computer-readable instructions or a hardware description, the logic circuitry 1308, when implementing the functional elements of the machine-executable code 1306, is adapted to perform the functional elements described by the machine-executable code 1306. Note that the hardware description may not directly describe the functional elements, but rather the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description can perform.

[0078] Conclusion As used in this disclosure, the term "module" or "component" may refer to a module or component and / or a specific hardware implementation that performs the actions of a software object or routine that may be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing device, etc.) of a computing system. In one or more embodiments, different components, modules, engines, and services described in this disclosure may be implemented as objects or processes (e.g., as separate threads) that execute on a computing system. While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations, or a combination of software and specific hardware implementations, are also possible and contemplated.

[0079] As used in this disclosure, the term "combination," referring to multiple elements, can include a combination of all elements or any of various different subcombinations of elements. For example, the phrase "A, B, C, D, or combinations thereof" can refer to A, B, C, or D; each combination of A, B, C, and D; and any subcombination of A, B, C, or D, such as any one of A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0080] The terms used in this disclosure, and particularly in the appended claims (e.g., the body of the appended claims), are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," the term "includes" should be interpreted as "includes, but is not limited to," etc.).

[0081] Additionally, if a specific number of introduced claim recitations is intended, such intent will be expressly recited in the claim; absent such recitation, no such intent exists. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed as limiting any particular claim including such introduced claim recitations to embodiments including only one such recitation (e.g., "a" and / or "an" should be construed to mean "at least one" or "one or more"), even if the same claim includes the introductory phrase "one or more" or "at least one" and an indefinite article such as "a" or "an"). The same is true for the use of definite articles used to introduce claim recitations.

[0082] Additionally, even when a specific number of introduced claim recitations are explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the explicit recitation of "two recitations" without other modifiers means at least two recitations or more than two recitations). Furthermore, when conventions similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." are used, such constructions are generally intended to include A only, B only, C only, A and B together, A and C together, B and C together, or A, B, and C together, etc.

[0083] Furthermore, any disjunction or phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B."

[0084] While the present disclosure has been described herein with reference to certain illustrated embodiments, those skilled in the art will recognize and understand that the disclosure is not so limited. Rather, numerous additions, deletions, and modifications may be made to the illustrated and described embodiments without departing from the scope of the present disclosure as claimed below, along with their legal equivalents. In addition, features of one embodiment can be combined with features of another embodiment and still fall within the scope of the present disclosure.

Claims

1. 1. An apparatus comprising: A processing circuit, providing a periodic signal to the first pair of terminals, the periodic signal including a plurality of pulses, the duration of each of the plurality of pulses being at least twice the travel time of the pulse along a predetermined allowable length of cable; and processing circuitry for detecting faults in the cable in response to a received signal at a second pair of terminals in response to the periodic signal.

2. The device of claim 1 , wherein the cable is a network cable.

3. The device of claim 2 , wherein the network cable is a shared transmission medium of a wired local area network.

4. The processing circuitry one high amplitude pulse in the received signal for substantially the entire duration that one pulse of the periodic signal passes through the maximum allowable length of the cable, the high amplitude pulse having an amplitude higher than the amplitude of an echo pulse in response to the periodic signal; or 2. The apparatus of claim 1, wherein the apparatus detects an open circuit in the cable and detects the fault in the cable in response to a low amplitude pulse in the received signal following the leading edge of one of the pulses of the periodic signal that precedes a high amplitude pulse in the received signal within the entire duration that the one pulse of the periodic signal passes through a maximum allowable length of the cable following the leading edge.

5. The processing circuitry a single low amplitude pulse in the received signal that lasts for substantially the entire duration that a single pulse of the periodic signal passes through the maximum allowable length of the cable; or 2. The apparatus of claim 1, wherein the apparatus detects a short circuit in the cable and detects a fault in the cable in response to one high amplitude pulse in the received signal following the leading edge of the periodic signal that precedes a low amplitude pulse in the received signal within the entire duration that the pulse of the periodic signal following the leading edge passes through the maximum allowable length of the cable, the high amplitude pulse having an amplitude higher than the amplitude of an echo pulse in response to the periodic signal.

6. The apparatus of claim 1 , wherein the processing circuitry detects the location of the fault in response to the received signal.

7. The processing circuitry one high amplitude pulse in the received signal for substantially the entire duration that a pulse of the periodic signal passes through the maximum allowable length of the cable, the high amplitude pulse having an amplitude higher than the amplitude of an echo pulse in response to the periodic signal; or 2. The apparatus of claim 1, wherein the apparatus detects a fault in the cable at a connection point between the first pair of terminals and the cable in response to a leading edge of the pulse of the periodic signal followed by a single low amplitude pulse in the received signal for substantially the entire duration that the pulse of the periodic signal passes through a maximum allowable length of the cable.

8. the processing circuitry one low amplitude pulse in the received signal following the leading edge of a pulse of the periodic signal that follows the leading edge and precedes a high amplitude pulse in the received signal within the entire duration that the pulse of the periodic signal passes through the maximum allowable length of the cable; or 2. The apparatus of claim 1, wherein the apparatus detects a fault in the cable at a distance substantially greater than zero meters from a connection point between the cable and the first pair of terminals in response to one high-amplitude pulse in the received signal following the leading edge of the pulse of the periodic signal that precedes a low-amplitude pulse in the received signal within the entire duration that the pulse of the periodic signal following the leading edge passes through the maximum allowable length of the cable, the high-amplitude pulse having an amplitude higher than an amplitude of an echo pulse responsive to the periodic signal.

9. The processing circuitry a period of time beginning with the leading edge of the pulse of the periodic signal, during which one low amplitude pulse is detected in the received signal; or 9. The apparatus of claim 8, wherein the apparatus detects the location of the fault in the cable in response to a time period beginning with the leading edge of the pulse of the periodic signal, during which the high amplitude pulse is detected in the received signal.

10. 2. The apparatus of claim 1, wherein the periodic signal has a duty cycle of substantially 50%.

11. 1. A method for cable fault detection, comprising: providing a periodic signal to a cable, the periodic signal comprising a plurality of pulses, each pulse having a duration at least twice the travel time of the pulse along a maximum allowable length of the cable; detecting a fault in the cable in response to a received signal, the received signal responsive to the periodic signal.

12. detecting one high amplitude pulse in the received signal for substantially the entire duration that the periodic signal passes through the maximum allowable length of the cable, the high amplitude pulse having an amplitude higher than the amplitude of an echo pulse responsive to the periodic signal; or 12. The method of claim 11, comprising detecting a fault in the cable in response to detecting a low amplitude pulse in one or more reflections following a leading edge of the pulse of the periodic signal, and thereafter detecting a high amplitude pulse in the received signal following the leading edge within the duration for the one pulse of the periodic signal to pass through a maximum allowable length of the cable.

13. detecting a low amplitude pulse in one or more reflections following a leading edge of a pulse of the periodic signal in the one or more reflections; or 12. The method of claim 11, comprising detecting a short circuit in the cable in response to detecting one high amplitude pulse in the received signal following the leading edge of the periodic signal that precedes a low amplitude pulse in the received signal within the entire duration that the pulse of the periodic signal follows the leading edge and passes through a maximum allowable length of the cable, the high amplitude pulse having an amplitude higher than an amplitude of an echo pulse in response to the periodic signal.

14. The method of claim 11 further comprising detecting the location of the fault in response to one or more reflections.

15. 12. The method of claim 11, wherein the plurality of pulses corresponds to a first logic level of a clock signal.

16. 16. The method of claim 15, wherein the duty cycle of the clock signal is substantially 50%.

17. 1. An apparatus comprising: a signal generator for providing a clock signal to a cable, the duration of a single clock cycle of said clock signal being greater than four times the transit time of a pulse of said clock signal along a maximum allowable length of said cable; a processing circuit for detecting faults in the cable in response to a received signal, the received signal being received from the cable in response to the clock signal.

18. The processing circuitry a single high amplitude pulse in the received signal that lasts for substantially the entire duration that the clock signal passes through the maximum allowable length of the cable; or 18. The apparatus of claim 17, wherein the apparatus detects an open circuit in the cable in response to a low amplitude pulse following the leading edge of the clock signal in the received signal that precedes a high amplitude pulse in one or more reflections within the entire duration that the one pulse of the clock signal passes through a maximum allowable length of the cable, the high amplitude pulse having an amplitude higher than the amplitude of an echo pulse in response to the clock signal.

19. The processing circuitry a single low amplitude pulse in the received signal that lasts for substantially the entire duration that the clock signal passes through the maximum allowable length of the cable; or 20. The apparatus of claim 18, wherein the apparatus detects a short circuit in the cable in response to a high-amplitude pulse in the received signal following a leading edge of a pulse of the clock signal that precedes the low-amplitude pulse in the received signal within the entire duration that the pulse passes through the maximum allowable length of the cable, the high-amplitude pulse having an amplitude higher than an amplitude of an echo pulse in response to the clock signal.

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