Software-defined compute unit resource allocation mode

Abstract

The program code (400) executing on the processing system (100) includes one or more instructions for identifying workloads (344) each including a plurality of waves and for identifying resource allocations (348) for the plurality of waves of the workgroup. In response to receiving the instructions identifying the workloads and resource allocations for the plurality of waves of the workgroup, the processor (114) assigns a first set of processing resources to a computing unit (224) of the processor based on the resource allocations for the plurality of waves. The computing unit then performs operations for the workgroup using the assigned set of processing resources.

Description

[Background technology]

[0001] To execute instructions for an application, a processing system includes a processor having compute units configured to execute waves of operations of the application. To execute these waves, each compute unit also includes processing resources, such as vector registers and scratch memory that store data used in the execution of the wave. To simultaneously launch multiple waves on a compute unit, the processor's fixed-function hardware allocates a portion of the available processing resources to each wave launched on the compute unit. However, such fixed-function hardware only considers limited conditions when allocating available processing resources to waves, causing the fixed-function hardware to allocate more resources to a wave than necessary. Such over-allocation reduces the number of waves that can be simultaneously launched on a compute unit, reducing the efficiency and processing speed of the processing system.

[0002] The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings, in which: The use of the same reference numbers in different drawings indicates similar or identical items. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram of a processing system that implements software-defined compute unit resource allocation, according to some embodiments. [Figure 2] FIG. 1 is a block diagram of an exemplary processor core configured for software-defined compute unit resource allocation, according to some embodiments. [Figure 3] FIG. 1 is a flow diagram of an exemplary process for software-defined allocation of compute unit resources, according to some embodiments. [Figure 4]FIG. 1 is a block diagram of exemplary program code for software-defined compute unit resource allocation, according to some embodiments. [Figure 5] FIG. 1 is a flow diagram of an exemplary method for software-defined compute unit resource allocation, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0004] An application (e.g., a shader program, a ray tracing program) executing on a processing system generates program code that indicates multiple work items (e.g., functions, operations) to be executed for the application. In an embodiment, the processing system is configured to group such work items into one or more workgroups, each workgroup including a respective number of waves (e.g., subgroups of work items) to be executed. To execute these waves for the workgroups, the processing system includes an accelerated processing unit (APU) having one or more compute units, each of which includes wave slots (e.g., portions of compute units) configured to execute a respective wave of the workgroup (e.g., execute one or more operations of the workgroup's waves). Each compute unit further includes or is otherwise connected to compute unit resources (e.g., vector registers, local data shares, scratch memory) configured to store data used in executing operations for the wave. To facilitate simultaneous execution of multiple waves on the compute units, fixed-function hardware of the processing system assigns portions of the compute unit resources to each wave (e.g., to wave slots of the compute units assigned to the wave). However, due to the nature of fixed-function hardware, only limited conditions are considered when allocating compute unit resources to waves. As a result, compute unit resources may not be allocated to waves efficiently or effectively. For example, under some conditions, the fixed-function hardware may allocate more compute unit resources to a wave than are necessary or available for executing the wave, limiting the number of compute unit resources allocated to other waves and limiting the number of waves that can be simultaneously executed by a compute unit.

[0005] To this end, the systems and techniques described herein are directed to software-defined compute unit resource allocation. To facilitate such software-defined compute unit resource allocation, an application (e.g., a shader program, a ray tracing program) generates program code indicating multiple work items (e.g., functions, operations) grouped into one or more workgroups, each having one or more waves (e.g., subgroups of work items). Additionally, the application generates program code indicating resource allocation and synchronization data for the waves. Such resource allocation includes data indicating one or more respective compute unit resources to allocate to each wave of the workgroup. For example, the resource allocation includes data indicating one or more respective compute unit resources (e.g., number of registers, amount of memory) to allocate to each wave, one or more compute unit resources (e.g., number of registers, amount of memory) to share between two or more waves (e.g., allocate to two or more waves), or both. Furthermore, such synchronization data indicates, for example, one or more workgroup barriers (e.g., thread barriers) for a wave of a workgroup, two or more waves of a workgroup executing simultaneously, two or more waves of two or more workgroups executing simultaneously, or any combination thereof. A workgroup barrier (eg, a thread barrier) pauses one or more threads of a wave until each thread of the wave executes a predetermined operation, function, or both indicated by the barrier.

[0006] In response to receiving program code (e.g., as commands, instructions, or both) including workgroups, resource allocations, and synchronization data, the processor allocates compute unit resources to waves of the workgroups (e.g., wave slots of compute units executing waves) based on the received program code. For example, the processor allocates compute unit resources to waves such that one or more conditions indicated in the resource allocations, the synchronization data, or both are satisfied. In this manner, the allocation of compute unit resources to waves is defined by program code rather than by fixed-function hardware of the processing system. By defining compute unit resource allocations by program code, additional conditions are considered when allocating compute unit resources, increasing the number of resources available for allocation to waves and increasing the number of simultaneous waves that can be launched on a compute unit. Additionally, because compute unit resource allocations are defined by program code, the processor can dynamically allocate available resources each time a workgroup is assigned (e.g., the processor can allocate resources each time a workgroup is assigned). This improves the processing speed and efficiency of the processing system. Furthermore, to allocate such resources, the processor is configured to modify one or more hardware registers of the processor based on the received program code (e.g., based on resource allocation and synchronization data indicated in the program code). As an example, the processor updates a hardware register (e.g., a base register) that stores the base addresses of one or more compute unit resources to allocate the compute unit resources to waves. In this manner, the processor allocates compute unit resources to waves using the physical addresses of the compute unit resources (e.g., based on the base addresses), limiting the need to invoke a renaming table, for example, and improving the processing speed and efficiency of the processing system.

[0007] 1 is a block diagram of a processing system 100 that implements software-defined compute unit resource allocation, according to some embodiments. The processing system 100 includes or has access to a memory 106 or other storage component implemented using a non-transitory computer-readable medium, such as, for example, dynamic random-access memory (DRAM). However, in embodiments, the memory 106 is implemented using other types of memory, including static random-access memory (SRAM), non-volatile RAM, etc. According to embodiments, the memory 106 includes external memory, for example, implemented externally to a processing unit implemented in the processing system 100. The processing system 100 also includes a bus 112 that facilitates communication between entities executed on the processing system 100, such as the memory 106. Some embodiments of the processing system 100 include other buses, bridges, switches, routers, etc., which are not shown in FIG. 1 for clarity.

[0008] The techniques described herein, in different embodiments, are employed in an accelerated processing unit (APU) 114. The APU 114 may include, for example, any of a variety of parallel processors, vector processors, coprocessors, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), non-scalar processors, highly parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, other multithreaded processing units, scalar processors, serial processors, or any combination thereof. The APU 114 renders images according to one or more applications 110 (e.g., shader programs) for presentation on the display 120. For example, the APU 114 renders objects (e.g., groups of primitives) according to one or more shader programs to generate pixel values ​​that are provided to the display 120, and the display 120 uses the pixel values ​​to display images representing the rendered objects. To render objects, the APU 114 may implement multiple processor cores 116-1 through 116-N that simultaneously or in parallel execute instructions from one or more applications 110. For example, the APU 114 may use multiple processor cores 116 to execute instructions from a shader program, a ray tracing program, a graphics pipeline, or both, to render one or more objects. While the exemplary embodiment shown in FIG. 1 presents three processor cores (116-1, 116-2, 116-N) representing N cores, the number of processor cores 116 implemented within the APU 114 is a matter of design choice. As such, in other embodiments, the APU 114 may include any number of processor cores 116. Some embodiments of the APU 114 are used for general-purpose computing.The APU 114 executes instructions, such as program code 108 (e.g., shader code, ray tracing code), for one or more applications 110 (e.g., shader programs, ray tracing programs) stored in the memory 106, and the APU 114 stores information, such as results of the executed instructions, in the memory 106.

[0009] In an embodiment, instructions appearing in program code 108 (e.g., shader code, ray tracing code) from one or more applications 110 (e.g., shader programs, ray tracing programs) define one or more work items (e.g., functions) that each identify, for example, one or more operations to be performed, the size of one or more work groups (e.g., groups of work items), or both. Additionally, in an embodiment, processing system 100 groups such work items into one or more work groups based, for example, on predetermined values, the types of operations identified in the work items, the architecture of APU 114, the availability of compute unit resources, or any combination thereof. To execute a work group (e.g., a group of work items), one or more processor cores 116 of APU 114 operate as one or more compute units each configured to launch one or more wavefronts (e.g., waves) to execute the work group. To this end, each compute unit includes one or more single instruction and data (SIMD) units, each including multiple lanes configured to perform the same operation on different data sets, e.g., as indicated in one or more instructions received from application 110. As an example, each SIMD unit includes multiple arithmetic logic units (ALUs), each performing the same operation on multiple data sets. In an embodiment, one or more SIMD units of a compute unit include vector SIMD units (e.g., SIMD units including one or more vector ALUs), scalar SIMD units (e.g., SIMD units including one or more scalar ALUs), or both. According to an embodiment, each compute unit is configured to launch one or more waves simultaneously. For example, one or more lanes of each SIMD unit of a compute unit are configured to perform operations for one or more waves simultaneously. Each portion (e.g., lane) of a SIMD unit configured to perform operations for a wave is also referred to herein as, for example, a wave slot.In this manner, a compute unit has several wave slots (e.g., portions of a SIMD unit) each configured to execute one or more waves simultaneously (e.g., perform operations for one or more waves).

[0010] Additionally, to support SIMD units, each processor core 116 includes or is otherwise coupled to one or more respective sets of compute unit resources 122. For example, each compute unit of processor core 116 includes or is otherwise coupled to a respective set of compute unit resources 122. These compute unit resources 122 are configured to store (e.g., in workgroups based on instructions from application 110) values, register files, operands, instructions, variables, result data (e.g., data resulting from the execution of one or more operations), flags, or any combination thereof necessary to execute one or more operations indicated in one or more instructions from application 110, assist in executing one or more operations, or be useful for executing one or more operations. Additionally, such compute unit resources 122 may include, for example, one or more registers (e.g., vector registers, scalar registers), a local data share, scratch memory, or any combination thereof. According to an embodiment, one or more compute unit resources 122 are included in each compute unit, one or more compute unit resources 122 are shared between two or more compute units, or both. While the exemplary embodiment shown in Figure 1 presents processing system 100 with three sets of compute unit resources (122-1, 122-2, 122-N) for three respective processor cores 116, in other embodiments, processing system 100 may have any number of sets of compute unit resources 122 for one or more respective processor cores 116.

[0011] In an embodiment, processing system 100 is configured to allocate one or more portions of one or more compute unit resources 122 (e.g., registers, local data shares, scratch memory) to one or more waves of a workgroup (e.g., portions of SIMD units of one or more compute units that perform operations for the wave). To this end, in an embodiment, APU 114 includes a command processor (not shown for clarity) that includes hardware-based circuitry, software-based circuitry, or both configured to issue respective workgroups (e.g., as commands, instructions, or both) to one or more compute units of one or more processor cores 116. In response to workgroups being issued to one or more compute units, fixed-function hardware of the APU 114 (e.g., software-based circuitry, hardware-based circuitry, or both configured to implement graphics pipeline stages, tessellation stages, rasterization stages, or any combination thereof) allocates one or more portions of one or more compute unit resources 122 to waves of workgroups being launched on the compute unit (e.g., to lanes of a SIMD unit that perform operations for the waves) based on the types of operations identified in the workload, the availability of compute unit resources 122, the priority associated with the workload, or any combination thereof. For example, the fixed-function hardware of the APU 114 programs (e.g., via a serial peripheral interface (SPI)) a base register with a base address to allocate one or more physical registers (e.g., vector registers, scalar registers) of the set of compute unit resources 122 to one or more waves being launched on the compute unit. In response to receiving an instruction to launch a wave, the compute unit of the processor core 116 determines the physical registers (e.g., vector registers, scalar registers) of the set of compute unit resources 122 assigned to the launched wave based on the base address in the base register.However, using the fixed-function hardware of the APU 114 to allocate compute unit resources 122 to waves limits the flexibility in allocating compute unit resources 122 to different waves, SIMD units, or both. For example, operations for some applications (e.g., shader programs) require fewer compute unit resources 122 than are allocated by the fixed-function hardware of the APU 114. As another example, the number of compute unit resources 122 required to execute operations for some applications changes as operations (e.g., workgroups) are executed. Therefore, the fixed-function hardware of the APU 114 allocates more compute unit resources 122 to waves, SIMD units, or both than are needed or available to execute those operations. In this way, the processing system 100 limits the number of compute unit resources 122 available for allocation, which reduces the number of simultaneous waves that the compute units launch and reduces the processing efficiency of the processing system 100.

[0012] To help increase the number of concurrent waves on a compute unit and increase processing efficiency of the processing system 100, the processing system 100 is configured to allocate one or more portions of one or more compute unit resources 122 (e.g., a set of registers, a local data share, scratch memory) to one or more waves based on program code 108 (e.g., shader code, ray tracing code) from one or more applications 110 (e.g., shader programs, ray tracing programs). For example, in an embodiment, the program code 108 includes data identifying a workgroup including multiple waves and data identifying resource allocations for one or more waves of the workgroup. Such resource allocations for a wave may include, for example, data identifying one or more registers allocated to each wave, an amount of local data share (e.g., in kilobytes) allocated to each wave, one or more barriers for each wave, one or more other waves synchronized with each wave (e.g., one or more waves executing concurrently with each wave), or any combination thereof. Such barriers include one or more thread barriers (e.g., thread synchronization points) for each wave, e.g., a thread barrier suspends one or more threads of a wave until each thread of the wave executes a predetermined operation, function, or both indicated by the barrier. Based on receiving data (e.g., as commands, instructions, or both) indicating the workgroups, resource allocations, synchronization data, or any combination thereof of program code 108, APU 114 allocates at least a portion of the set of compute unit resources 122 to one or more waves indicated in program code 108 based on the resource allocations indicated in program code 108. For example, in response to receiving data indicating the workgroups, resource allocations, and synchronization data of program code 108, APU 114 edits one or more hardware registers of APU 114 based on the one or more resource allocations indicated in program code 108.In some embodiments, data identifying the workgroups, resource allocations, or synchronization data of program code 108 is provided to APU 114 via commands or instructions (e.g., instructions identifying the workgroups and resource allocations). For example, in some embodiments, APU 114 receives instructions identifying the workgroups, resource allocations, and synchronization data and allocates at least a portion of a set of compute unit resources 122 to one or more waves of the workgroups based on the instructions.

[0013] Allocating compute unit resources 122 to waves in this manner allows for increased flexibility in resource allocation. For example, only the amount of compute unit resources 122 needed to execute one or more operations of the wave is allocated to the wave. Additionally, the APU 114 can dynamically allocate compute unit resources 122 as workgroups are assigned to or received by the APU 114. That is, the APU 114 is configured to dynamically allocate respective compute unit resources 122 to each workgroup received by the APU 114, such that, for example, a first workgroup received by the APU 114 is assigned a first set of compute unit resources 122 having a first number of compute unit resources, and a second workgroup received by the APU 114 is assigned a second set of compute unit resources 122 having a second number of compute unit resources different from the first number of compute unit resources 122. Furthermore, allocating compute unit resources 122 in this manner allows the APU 114 to allocate compute unit resources 122 while a workgroup, wave, or both is being processed (e.g., operations for the workgroup or wave are being executed). For example, while executing a workgroup, the APU 114 receives one or more instructions identifying a second set of compute unit resources 122 to allocate to the workgroup. As such, the APU 114 can modify the allocation of compute unit resources 122 as the number of compute unit resources 122 needed to execute the workgroup, wave, or both changes while the workgroup is being executed. In this manner, the processing efficiency of the processing system 100 increases as the number of excess processing resources allocated to a wave decreases, allowing additional concurrent waves to be launched on the compute units.Additionally, for example, by specifying which waves to launch simultaneously, processing system 100 can further increase the efficiency of allocation of compute unit resources 122 by grouping such waves based on the availability of compute unit resources 122 (e.g., grouping waves to maximize the number of simultaneous waves launched by a compute unit). Further, in an embodiment, program code 108 includes data indicating that two or more waves should be allocated the same processing resource (e.g., vector registers, scalar registers, LDS) of the set of compute unit resources 122. That is, program code 108 includes data indicating that one or more compute unit resources 122 should be shared across two or more waves. Thus, sharing compute unit resources 122 between two or more waves increases the amount of compute unit resources 122 available to the workgroup as a whole, increasing the number of simultaneous waves launched by the compute units and improving the processing efficiency of processing system 100.

[0014] Processing system 100 also includes a central processing unit (CPU) 102 connected to a bus 112 and thus communicating with an APU 114 and memory 106 via bus 112. CPU 102 implements multiple processor cores 104-1 through 104-N that execute instructions simultaneously or in parallel. In an embodiment, one or more of processor cores 104 each operate as one or more computational units (e.g., SIMD units) that perform the same operation on different data sets. While the exemplary embodiment shown in FIG. 1 presents three processor cores (104-1, 104-2, 104-M) representing M cores, the number of processor cores 104 implemented within CPU 102 is a matter of design choice. As such, in other embodiments, CPU 102 may include any number of processor cores 104. In some embodiments, CPU 102 and APU 114 have an equal number of processor cores 104, 116, while in other embodiments, CPU 102 and APU 114 have a different number of processor cores 104, 116. Processor cores 104 execute instructions, such as program code 108, stored in memory 106, and CPU 102 stores information, such as results of executed instructions, in memory 106. CPU 102 can also initiate graphics operations by issuing draw calls to APU 114. In embodiments, CPU 102 implements multiple processor cores (not shown in FIG. 1 for clarity) that independently execute instructions simultaneously or in parallel.

[0015] Input / output (I / O) engine 118 includes hardware and software that handles input or output operations associated with display 120 and other elements of processing system 100, such as a keyboard, mouse, printer, external disk, etc. I / O engine 118 is coupled to bus 112 such that I / O engine 118 communicates with memory 106, GPU 114, or CPU 102.

[0016] 2, an exemplary processor core 200 configured for software-defined compute unit resource allocation is presented. In an embodiment, processor core 200, similar to or the same as processor core 116, includes two compute units 224 configured to execute one or more workgroups (e.g., groups of work items) indicated in program code 108 from application 110 (e.g., shader programs, ray tracing programs). While the exemplary embodiment of FIG. 2 presents processor core 200 with two compute units (224-1, 224-2), in other embodiments, processor core 200 may have any number of compute units 224. To execute the workgroups indicated in program code 108, each compute unit 224 is configured to launch one or more waves (e.g., wavefronts) to perform one or more functions, operations, or both indicated in the workgroup (e.g., indicated in program code 108). To this end, each compute unit 224 includes one or more SIMD units 226 (e.g., vector SIMD units) each configured to execute one or more operations for one or more functions identified in a workgroup within one or more waves. That is, at least some of the SIMD units 226 are configured to launch waves using one or more lanes of the SIMD units 226 to execute one or more operations for one or more functions identified in a workgroup. While the exemplary embodiment of FIG. 2 presents compute unit 224-1 with three SIMD units (226-1, 226-2, 226-N) representing N SIMD units and compute unit 224-2 with three SIMD units (226-3, 226-4, 226-M) representing M SIMD units, in other embodiments, each compute unit 224 may include any number of SIMD units 226.

[0017] To assist the SIMD units 226 in executing one or more operations for a workgroup, each compute unit 224 includes or is otherwise connected to an instruction cache 230. For example, in an embodiment, each compute unit 224-1, 224-2 includes a respective instruction cache 230, while in other embodiments, one or more instruction caches 230 are connected to (e.g., shared by) each compute unit 224-1, 224-2. The instruction cache 230 includes, for example, memory (e.g., SRAM) configured to store one or more instructions that assist in executing or are useful for executing one or more operations necessary to execute one or more operations of a workgroup (e.g., one or more operations for a wave of a workgroup). In an embodiment, the instruction cache 230 is shared by each wave (e.g., a lane of a SIMD unit that executes operations for a wave) launched by one or more compute units. For example, the instruction cache 230 is shared by waves launched on compute units 224-1, 224-2. Similarly, each compute unit 224 includes or is otherwise connected to a data cache 232. For example, in embodiments, each compute unit 224-1, 224-2 includes a respective data cache 232, while in other embodiments, one or more data caches 232 are connected to each compute unit 224-1, 224-2 (e.g., shared by the compute units 224). The data cache 232 includes, for example, memory (e.g., SRAM) configured to store data (e.g., cache lines) that assist in executing one or more operations or that are useful for executing one or more operations necessary to execute one or more operations of a workgroup (e.g., one or more operations for a wave of a workgroup). In embodiments, the instruction cache 230 is shared by each wave (e.g., a lane of a SIMD unit that executes operations for a wave) launched by one or more compute units.

[0018] Additionally, to assist SIMD unit 226 in executing one or more operations for a workgroup, processor core 200 includes, or is otherwise connected to, a set of compute unit resources similar to or the same as set of compute unit resources 122 configured to store, for example, values, register files, operands, instructions, variables, result data (e.g., data resulting from the execution of one or more operations), flags, or any combination thereof necessary to execute one or more operations indicated in a workgroup received by processor core 200, assist in executing one or more operations, or be useful for executing one or more operations. Such processing resources include, for example, registers 228, local data share 234, or both. For example, each compute unit 224 includes or is otherwise connected to a set of registers 228 configured to store values, operands, resulting data (e.g., data resulting from the execution of one or more operations, a register file, or any combination thereof) necessary to execute one or more operations for the workgroup, that aid in executing one or more operations, or that are useful for executing one or more operations. In an embodiment, the set of registers 228 includes, for example, one or more vector registers 240 configured to store data (e.g., operands, values) necessary to execute one or more operations by vector SIMD unit 226, that aid in executing one or more operations, or that are useful for executing one or more operations. Such vector registers 240 are shared, for example, by one or more lanes of SIMD unit 226 that execute operations for one or more waves of the workgroup.According to an embodiment, one or more vector registers 240 are assigned to one or more lanes of a SIMD unit 226 that perform operations for the same wave, one or more vector registers are assigned to one or more lanes of a SIMD unit 226 that perform operations for more than one wave (e.g., one or more vector registers are assigned such that they are shared by lanes of a SIMD unit 226 that perform operations for more than one wave), or both. The set of registers 228, in an embodiment, additionally or alternatively includes one or more scalar registers 242 configured to store data (e.g., operands, values) that aid in performing one or more operations or that are useful for performing one or more operations, e.g., necessary for performing one or more operations by a scalar SIMD unit 226. While the exemplary embodiment presented in FIG. 2 provides a first computation unit 224-1 having one set of registers 228-1 (e.g., including vector registers 240-1 and scalar registers 242-1) and a second computation unit having one set of registers 228-2 (e.g., including vector registers 240-2 and scalar registers 242-2), in other embodiments, each computation unit 224 may have any number of sets of registers 228, each including any number of vector registers 240, scalar registers 242, or both.

[0019] Additionally, each compute unit 224 includes or is otherwise connected to a local data share 234. The local data share 234 includes memory (e.g., SRAM) shared across each SIMD unit 226 across one or more compute units. That is, the local data share 234 is shared across each wave executing on one or more compute units 224. For example, in the exemplary embodiment shown in FIG. 2 , the local data share 234 is shared across each SIMD unit 226 of compute units 224-1 and 224-2, such that the local data share 234 is shared across waves launched on compute units 224-1 and 224-2. In an embodiment, the local data share 234 is configured to store results (e.g., data resulting from the execution of one or more operations by one or more SIMD units 226), operands, a register file, or any combination thereof that is necessary for, assists in, or is useful for, executing one or more operations by one or more SIMD units 226. As an example, local data share 234 is used as scratch memory for storing results necessary for, assisting in, or useful for executing one or more operations by one or more SIMD units 226. Additionally, because local data share 234 is shared across each SIMD unit 226 and one or more compute units (e.g., shared across waves executing on one or more compute units 224), local data share 234 allows data to be shared across SIMD units 226 of one or more compute units 224 (e.g., across waves executing on compute units 224). For example, results determined from execution of operations for a first wave by one or more lanes of SIMD unit 226 are stored in local data share 234.Such results are then made available to one or more operations of one or more other waves executing on, for example, one or more other lanes of the same or different SIMD units 226. According to an embodiment, processing system 100 is configured to allocate at least a portion of local data share 234 to one or more waves of a workgroup executing on one or more compute units 224. For example, processing system 100 defines one or more respective portions (e.g., in kilobytes) of local data share 234 that are visible to one or more waves of a workgroup executing on one or more compute units 224 (e.g., visible to one or more lanes of one or more SIMD units 226 configured to execute one or more waves of the workgroup).

[0020] 3 , an exemplary operation 300 for software-defined allocation of compute unit resources is presented. In an embodiment, the exemplary operation 300 includes a processing system 100 executing an application 310 similar to or the same as application 110. The application 310 may include, for example, a shader program, a ray tracing program, a machine learning program, or any combination thereof, executing on the processing system 100. In an embodiment, the application 310 includes generating program code similar to or the same as program code 108, the program code including one or more instructions executed by APU 114. For example, the program code includes one or more work items (e.g., functions) executed by APU 114. According to an embodiment, the application 310 is configured to group one or more work items of the program code into one or more workgroups 344 based, for example, on available compute unit resources of APU 114, the type of function, operation, or both indicated in the work item, the priority of the work item, or any combination thereof. For example, application 310 may be configured to group work items based on available compute unit resources of APU 114, such that one or more resulting workgroups 344 include a predetermined number of waves, a number of waves based on a maximum number of wave slots currently available on one or more compute units, a number of waves based on a maximum number of wave slots associated with one or more compute units, or any combination thereof. Furthermore, application 310 may be configured to define synchronization data for the workgroups 344 within the program code. Such synchronization data may include, for example, one or more waves of a workgroup, one or more respective thread barriers (e.g., thread synchronization points) for the workgroup, the workgroup grouping, or both. Such workgroup groupings may include, for example, data indicating one or more waves of one or more workgroups 344 that are to execute concurrently.For example, the workgroup grouping may include data indicating that a first wave of a first workgroup 344 should be executed concurrently with a second wave of the first workgroup 344, a second workgroup 344, or both.

[0021] In an embodiment, application 310 is further configured to determine one or more respective parameters 346 for workgroups 344 within the program code. Such parameters 346 may include, for example, one or more values, instructions, operands, register files, results (e.g., data resulting from the execution of one or more operations), or any combination thereof necessary for the execution of workgroup 344 (e.g., work items of workgroup 344), assisting in the execution of workgroup 344, or useful for the execution of workgroup 344. Additionally, application 310 is configured to define one or more respective resource allocations 348 for one or more workgroups 344 within the program code. Such resource allocations 348 may include, for example, data that allocates one or more portions of one or more allocatable resources (e.g., vector registers 240, scalar registers 242, local data share 234) to one or more waves of workgroup 344. As one example, such resource allocations 348 may include data indicating the respective number of vector registers 240 and the respective amounts of data in local data share 234 that are allocated to waves of workgroup 344. In an embodiment, resource allocation 348 includes data indicating that one or more allocated resources are to be shared between two or more waves of workgroup 344 (e.g., shared between two or more wave slots of a compute unit). For example, resource allocation 348 includes data indicating that two vector registers 240 are to be allocated to a first wave of workgroup 344 and that the same two vector registers 240 are also to be allocated (e.g., shared) to a second wave of workgroup 344.

[0022] According to an embodiment, one or more workgroups 344, parameters 346, resource allocations 348, or any combination thereof, in the program code of application 310 are stored in local work queue 350. For example, data indicative of one or more workgroups 344, parameters 346, resource allocations 348, or any combination thereof, is stored in local work queue 350 as one or more commands, instructions, or both. Local work queue 350 may, for example, include one or more hardware queues, software queues, or both, communicatively coupled to one or more computing units of APU 114. In an embodiment, local work queue 350 is configured to store workgroups 344, parameters 346, resource allocations 348, or any combination thereof, as one or more work packets 352. These work packets 352 may include, for example, data (e.g., commands, instructions) identifying a workgroup 344, one or more parameters 346 associated with the workgroup 344 (e.g., necessary for, assist in, or useful for the execution of the workgroup 344), one or more resource allocations 348 associated with the workgroup 344 (e.g., defining resources allocated to waves of the workgroup 344), or any combination thereof. For example, a work packet 352 may include a workgroup 344 including instructions identifying one or more waves to be launched, parameters 346 (e.g., values, instructions, operands, register files, results) required to execute the waves, and resource allocations 348 defining the number of vector registers 240 allocated to each wave and the number of vector registers 240 shared between two or more waves. According to an embodiment, the compute units 224 of the APU 114 are configured to request one or more work packets 352 from a local work queue 350.For example, the compute unit 224 may be configured to request (e.g., obtain) a work packet 352 from the local work queue 350 in response to the compute unit 224 having one or more free wave slots (e.g., the wave slot is not performing operations for the wave), the compute unit 224 not currently being assigned to a workgroup 344, the compute unit 224 completing a wave, the compute unit 224 completing a workgroup 344 (e.g., completing a previous workgroup), or any combination thereof.

[0023] To this end, compute unit 224 includes a resource allocation module 354 that includes hardware-based circuitry, software-based circuitry, or both configured to receive (e.g., retrieve) work packets 352 from local work queue 350. In response to receiving work packets 352, resource allocation module 354 is configured to allocate one or more waves of workgroup 344 indicated in work packet 352 to one or more respective wave slots of compute unit 224. For example, resource allocation module 354 is configured to allocate waves of workgroup 344 to respective wave slots based on allocatable resources shared among the waves, wave synchronization data (e.g., data indicating two or more waves to be launched simultaneously), data shared between two or more waves (e.g., results, operands), or any combination thereof. As another example, resource allocation module 354 is configured to allocate waves of workgroup 344 to respective wave slots based on one or more instructions associated with workgroup 344 indicating allocable resources shared among the waves, synchronization data for the waves (e.g., data indicating two or more waves to be launched simultaneously), data shared among two or more waves (e.g., results, operands), or any combination thereof. Additionally, resource allocation module 354 is further configured to allocate portions of one or more allocable resources associated with compute unit 224 (e.g., vector registers 240, scalar registers 242, local data share 234) to each wave slot of compute unit 224 (e.g., portions of SIMD unit 226). For example, based on respective resource allocations 348 for each wave of workgroup 344 indicated in work packet 352, resource allocation module 354 is configured to allocate portions of the allocable resources.To allocate such allocable resources, resource allocation module 354 is configured to determine one or more addresses 356, values ​​360, or both, used to update hardware registers 362 of APU 114. Such hardware registers 362 include, for example, hardware-based circuitry configured to define base addresses of one or more allocable resources (e.g., vector registers 240, scalar registers 242, local data shares 234) such that the allocable resources are allocated to one or more waves (e.g., wave slots of one or more compute units 224) of workgroup 344. According to an embodiment, resource allocation module 354 determines one or more addresses 356, values ​​360, or both, necessary to update hardware registers 362 such that the allocable resources of compute units 224 are allocated to one or more waves (e.g., wave slots of one or more compute units 224) of workgroup 344 based on respective resource allocations 348 for each wave of workgroup 344 indicated in work packet 352. As an example, the resource allocation module 354 determines one or more base addresses and values ​​needed to allocate vector registers 240 and portions of the local data shares 234 of the compute units 224 to one or more waves of the workgroup 344 (e.g., one or more wave slots of one or more compute units 224) based on the respective resource allocations 348 for each wave of the workgroup 344 indicated in the work packet 352.

[0024] After updating the hardware registers 362 to assign allocable resources to one or more wave slots of the compute unit 224, the compute unit 224 is configured to launch one or more waves of the workgroup 344 indicated in the work packet 352, such that one or more SIMDs perform operations 358 for the waves. In an embodiment, the compute unit 224 (e.g., the SIMD unit 226) is configured to execute waves based on the synchronization data indicated in the work packet 352. For example, the compute unit 224 is configured to launch two or more waves simultaneously based on the synchronization data indicated in the work packet 352. As another example, the compute unit 224 is configured to pause, resume, or both, execution of one or more waves based on one or more barriers (e.g., thread barriers) indicated in the synchronization data of the work packet. According to an embodiment, the resource allocation module 354 is further configured to allocate the allocable resources to one or more wave slots of the workgroup while the compute unit is executing the workgroup. As an example, while a workgroup is being executed by the computing unit using a first set of allocatable resources, the resource allocation module 354 is configured to allocate a second set of allocatable resources that differs from the first set of allocatable resources based on one or more received instructions that identify the workgroup (e.g., one or more instructions in a work packet 352 associated with the workgroup).

[0025] 4, exemplary program code 400 for software-defined compute unit resource allocation is presented. In an embodiment, program code 400 is generated by an application similar to or the same as application 110, 310, where the application includes, for example, a shader program, a ray tracing program, a machine learning program, or any combination thereof. Program code 400 includes data indicative of, for example, workgroups 344, parameters 346, resource allocation 348, and synchronization data 468. Workgroup 344, e.g., one or more work items grouped together based on available allocatable resources of APU 114, the type of function, operation, or both indicated in the work item, the priority of the work item, or any combination thereof, and parameters 346, include one or more respective values, instructions, operands, register files, results (e.g., data resulting from the execution of one or more operations), or any combination thereof, that are necessary for, assist in, or are useful for the execution of workgroup 344 (e.g., work items of workgroup 344).

[0026] For each workgroup in workgroups 344, program code 400 includes a respective resource allocation 348. Such resource allocation 348 includes, for example, a vector register allocation 462, a scalar register allocation 464, and a local data share allocation 466. Vector register allocation 462 includes data indicating, for example, a respective number of vector registers 240 to allocate to each wave of workgroup 344, a respective number of vector registers 240 to share between two or more waves of workgroup 344, or both. As an example, vector register allocation 462 includes data indicating a first number of vector registers 240 to allocate to a first wave of workgroup 344, a second number of vector registers 240 to allocate to a second wave of workgroup 344, and the number of vector registers 240 shared between the first wave and the second wave. Similarly, scalar register allocation 464 includes data indicating, for example, the respective number of scalar registers 242 to allocate to each wave of workgroup 344, the respective number of scalar registers 242 to share between two or more waves of workgroup 344, or both. In an embodiment, resource allocation 348 includes local data share allocation 466. Local data share allocation 466 includes data indicating, for example, the respective amount of local data share 234 to allocate (e.g., make visible) to each wave of workgroup 344, the respective amount of local data share 234 to share between two or more waves of workgroup 344, or both. As an example, local data share allocation 466 includes data indicating a first amount (e.g., in KB) of local data share 234 to allocate (e.g., make visible) to a first wave of workgroup 344, a second amount of local data share 234 to allocate to a second wave of workgroup 344, and the amount of local data share 234 shared between the first wave and the second wave.

[0027] According to an embodiment, the program code 400 further includes synchronization data 468, including, for example, a workgroup barrier 470, a workgroup grouping 472, or both. The workgroup barrier 470 includes data defining one or more respective thread barriers (e.g., thread synchronization points) for one or more waves of the workgroup 344. Such thread barriers include, for example, data identifying one or more operations, functions, or both of the wave. Based on the identified operation, function, or both, one or more threads of the wave (e.g., lanes of the SIMD unit 226) pause after completing the identified operation or function and resume operation when each thread of the wave has executed the identified operation or function. In this manner, the threads of the wave are synchronized based on the thread barrier. The workgroup grouping 472 includes, for example, data indicating two or more workgroups 344 executing simultaneously, two or more waves of the workgroup 344 executing simultaneously, two or more waves or two or more workgroups 344 executing simultaneously, or any combination thereof. Based on such workgroup groupings 472, one or more computing units 224 are configured to launch waves such that the workgroups 344, waves, or both identified in the workgroup groupings 472 are executed simultaneously.

[0028] 5, an exemplary method 500 for performing software-defined processing resource allocation is presented. At step 505 of method 500, an APU similar to or the same as APU 114 receives program code (e.g., shader code, ray tracing code) similar to or the same as program code 108 from one or more applications (e.g., shader programs, ray tracing programs) similar to or the same as application 110. Such program code may include, for example, data identifying one or more workgroups (e.g., groups of work items) similar to or the same as workgroup 344 to be executed by the APU, and one or more resource allocations similar to or the same as resource allocation 348 for executing workgroup 344. For example, the program code may include data identifying a workgroup having a first number of waves and a resource allocation indicating the number of vector registers (e.g., vector register 240) to allocate to each wave of the workgroup, the number of vector registers to share between two or more waves of the workgroup, or both. In an embodiment, the APU receives program code, data identifying one or more workgroups, resource allocations, or both as one or more commands, instructions, or both (e.g., instructions identifying one or more workgroups, resource allocations, or both). In step 510, the APU stores the workgroups and resources (e.g., instructions identifying the workgroups and resources) in a local work queue similar to or the same as local work queue 350. In an embodiment, the local work queue is configured to store the workgroups and associated resource allocations (e.g., resource allocations for waves of workgroups) as work packets similar to or the same as work packet 352. In step 515, the APU requests (e.g., obtains) one or more work packets identifying the workgroups and one or more resource allocations from the local work queue.For example, in response to one or more compute units of an APU completing execution of one or more workloads (e.g., completing a previous workgroup), completing one or more waves of one or more workloads, having one or more available (e.g., empty) wave slots, or any combination thereof, the APU requests (e.g., obtains) one or more work packets from a local work queue.

[0029] In step 520, the APU allocates resources to wave slots (e.g., lanes of one or more SIMD units) of one or more compute units similar to or the same as compute unit 224 based on the received work packet (e.g., one or more instructions of the work packet). For example, the APU allocates resources to wave slots of one or more compute units based on the resource allocations identified in the work packet (e.g., identified in one or more instructions). As another example, based on the resource allocations identified in a second instruction of the work packet, the APU allocates resources to one or more wave slots of the compute unit while the compute unit is processing one or more workgroups (e.g., executing operations for one or more workgroups). To allocate such resources, the APU is configured to edit one or more hardware registers similar to or the same as hardware register 362 of the APU. For example, the APU determines one or more addresses (e.g., address 356, base address), values ​​(e.g., value 360), or both necessary to allocate resources to wave slots of one or more compute units based on the resource allocations identified in the work packet. After determining the one or more addresses, values, or both, the APU updates one or more addresses in hardware registers based on the determined addresses to allocate resources to wave slots of the compute units. In step 525, in response to updating the hardware registers, the APU executes the workgroups identified in the work packet by launching one or more waves of the workgroups on one or more compute units.

[0030] As disclosed herein, in some embodiments, a method includes, in response to receiving instructions from an application identifying a workgroup including a plurality of waves and identifying a resource allocation for the plurality of waves, assigning a set of processing resources to a compute unit based on the resource allocation for the plurality of waves, and executing the workgroup using the set of processing resources assigned to the compute unit. In one aspect, the method includes storing, in a local work queue, the instructions identifying the workgroup and the resource allocation for the plurality of waves. In another aspect, the method includes, in response to the compute unit having executed a previous workgroup, requesting data including the instructions identifying the workgroup and the resource allocation for the plurality of waves from the local work queue. In yet another aspect, the method includes, while the workgroup is being executed, assigning a second set of processing resources to the workgroup based on a second instruction identifying the workgroup. In yet another aspect, assigning the set of processing resources to the compute unit includes assigning the same processing resource to two or more wave slots of the compute unit based on the resource allocation for the plurality of waves.

[0031] In one aspect, a method includes executing multiple waves of a workgroup based on synchronization data received from an application. In another aspect, the synchronization data identifies a thread barrier for any wave of the multiple waves. In yet another aspect, the synchronization data identifies two or more waves of the multiple waves to be executed simultaneously. In yet another aspect, the resource allocations for the multiple waves identify a respective number of vector registers for each of the multiple waves. In another aspect, the method includes modifying hardware registers based on the resource allocations for the multiple waves.

[0032] In some embodiments, a processing system includes a memory and a processor coupled to the memory and configured to receive instructions from an application to identify a workgroup including a plurality of waves and identify a resource allocation for the plurality of waves, the processor including a plurality of computing units, at least one computing unit of the plurality of computing units including a resource allocation module configured to assign a set of processing resources to the at least one computing unit based on the resource allocation for the plurality of waves, and a plurality of wave slots configured to execute the workgroup using the set of processing resources assigned to the computing unit. In one aspect, the processing system includes a local work queue configured to store instructions identifying the workgroup and the resource allocation for the plurality of waves. In another aspect, the at least one computing unit is configured to request data including instructions identifying the workgroup and the resource allocation for the plurality of waves from the local work queue in response to the at least one computing unit executing a previous workgroup. In yet another aspect, the resource allocation module is configured to assign a second set of processing resources to one or more wave slots based on second instructions identifying the workgroup while executing the workgroup.

[0033] In one aspect, the resource allocation module is configured to allocate the same processing resource to two or more wave slots of the plurality of wave slots based on the resource allocation for the plurality of waves. In another aspect, the processor is configured to receive data from the application identifying respective thread barriers for one or more waves of the plurality of waves. In yet another aspect, the processor further includes hardware registers, and the resource allocation module is configured to allocate the set of processing resources by modifying the hardware registers based on the resource allocation for the plurality of waves. In yet another aspect, the resource allocation for the plurality of waves identifies a respective amount of local data share for each of the plurality of waves.

[0034] In some embodiments, a processor includes one or more processing cores configured to, in response to receiving from an application synchronization data for the plurality of waves and instructions identifying resource allocations for the plurality of waves, allocate a set of processing resources to a compute unit based on the resource allocations for the plurality of waves, and execute the plurality of waves using the set of processing resources allocated to the compute unit based on the synchronization data. In one aspect, the synchronization data identifies a thread barrier for any wave of the plurality of waves. In another aspect, the synchronization data identifies two or more waves of the plurality of waves to be executed simultaneously. In yet another aspect, the one or more processor cores are configured to allocate a second set of processing resources to the compute unit based on a second instruction while executing the plurality of waves.

[0035] In some embodiments, the above-described apparatus and techniques are implemented in a system including one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the processing system configured for software-defined resource allocation described above with reference to FIGS. 1-5. Electronic design automation (EDA) and computer-aided design (CAD) software tools can be used in the design and manufacture of these IC devices. These design tools are typically represented as one or more software programs. The one or more software programs include code executable by a computer system for operating the computer system to operate on code representing the circuits of one or more IC devices to perform at least a portion of a process for designing or adapting a manufacturing system for manufacturing the circuits. This code may include instructions, data, or a combination of instructions and data. The software instructions representing the design or manufacturing tools are typically stored in a computer-readable storage medium accessible to the computing system. Similarly, code representing one or more stages of the design or manufacture of the IC devices is stored in and accessed from the same or a different computer-readable storage medium.

[0036] A computer-readable storage medium includes any non-transitory storage medium or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tape, magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical systems (MEMS)-based storage media. The computer-readable storage medium (e.g., system RAM or ROM) may be internal to the computing system, the computer-readable storage medium (e.g., a magnetic hard drive) may be permanently attached to the computing system, the computer-readable storage medium (e.g., an optical disk or Universal Serial Bus (USB)-based flash memory) may be removably attached to the computing system, or the computer-readable storage medium (e.g., network-accessible storage (NAS)) may be coupled to the computer system via a wired or wireless network.

[0037] In some embodiments, certain aspects of the techniques described above are implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied in a non-transitory computer-readable storage medium. The software may include instructions and specific data that, when executed by one or more processors, operate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device such as flash memory, a cache, a random access memory (RAM), or other non-volatile memory device(s). The executable instructions stored on the non-transitory computer-readable storage medium may be implemented as source code, assembly language code, object code, or other form of instructions that can be interpreted or otherwise executed by one or more processors.

[0038] In addition to the above, it should be noted that not all activities or elements described in the summary description are required, that some of the particular activities or devices may not be required, that one or more additional activities may be performed, and that one or more additional elements may be included. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will recognize that various modifications and variations can be made without departing from the scope of the invention as set forth in the claims. Accordingly, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention.

[0039] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and features from which any benefit, advantage, or solution may arise or be manifested are not construed as critical, essential, or essential features of any or all claims. Moreover, the specific embodiments described above are illustrative only, since the disclosed invention may be modified and practiced in different, but similar manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as described in the appended claims. It is therefore apparent that the specific embodiments described above may be altered or modified, and that all such variations are considered within the scope of the disclosed invention. Accordingly, the protection sought herein is set forth in the appended claims.

Claims

1. 1. A method comprising: In response to receiving instructions from an application identifying a workgroup including a plurality of waves and identifying resource allocations for the plurality of waves, assigning a set of processing resources to a compute unit based on the resource allocations for the plurality of waves; executing the workgroup using the set of processing resources assigned to the compute unit; method.

2. storing, in a local work queue, the instructions identifying the workgroup and resource allocations for the plurality of waves; 10. The method of claim 1.

3. requesting data from the local work queue, in response to the computing unit having executed a previous workgroup, the data including the instructions identifying the workgroup and resource allocations for the plurality of waves. The method of claim 2.

4. allocating a second set of processing resources to the workgroup based on second instructions identifying the workgroup while the workgroup is executing.

10. The method of claim 1.

5. Allocating the set of processing resources to the computing units comprises: allocating the same processing resource to two or more wave slots of the computing unit based on the resource allocations for the plurality of waves.

10. The method of claim 1.

6. executing the plurality of waves of the workgroup based on synchronization data received from an application; 10. The method of claim 1.

7. the synchronization data identifies a thread barrier for any one of the plurality of waves; The method of claim 6.

8. the synchronization data identifies two or more waves of the plurality of waves to be executed simultaneously; The method of claim 6.

9. the resource allocation for the plurality of waves identifies the number of vector registers for each of the plurality of waves; 10. The method of claim 1.

10. modifying a hardware register based on the resource allocation for the plurality of waves; The method of any one of claims 1 to 9.

11. 1. A processing system comprising: Memory and a processor coupled to the memory and configured to receive instructions from an application to identify a workgroup including a plurality of waves and to identify a source allocation for the plurality of waves; The processor: A plurality of computing units are provided, At least one of the plurality of computing units a resource allocation module configured to allocate a set of processing resources to the at least one computing unit based on resource allocations for the plurality of waves; a plurality of wave slots configured to execute the workgroups using the set of processing resources assigned to the compute units; Processing system.

12. a local work queue configured to store the instructions identifying the workgroup and resource allocations for the plurality of waves; The processing system of claim 11.

13. The at least one computing unit: configured to request, in response to at least one computing unit having executed a previous workgroup, data from the local work queue, the data including the instructions identifying the workgroup and resource allocations for the plurality of waves. The processing system of claim 12.

14. The resource allocation module: and configuring, while executing the workgroup, to allocate a second set of processing resources to one or more wave slots based on second instructions identifying the workgroup. The processing system of claim 11.

15. The resource allocation module: and assigning the same processing resource to two or more of the plurality of wave slots based on the resource allocation for the plurality of waves. The processing system of claim 11.

16. The processor: configured to receive, from the application, data identifying a thread barrier for each of one or more waves of the plurality of waves; The processing system of claim 11.

17. the processor comprises hardware registers; The resource allocation module: configured to allocate the set of processing resources by modifying the hardware registers based on resource allocations for the plurality of waves. The processing system of claim 11.

18. the resource allocation for the plurality of waves identifies an amount of local data share for each of the plurality of waves; The processing system of claim 11.

19. 1. A processor, comprising: one or more processing cores; the one or more processing cores In response to receiving synchronization data for a plurality of waves and instructions identifying resource allocations for the plurality of waves from an application, allocating a set of processing resources to a computing unit based on the resource allocations for the plurality of waves; executing the plurality of waves based on the synchronization data using the set of processing resources allocated to the computing unit; configured to: Processor.

20. the synchronization data identifies a thread barrier for any one of the plurality of waves; 20. The processor of claim 19.

21. the synchronization data identifies two or more waves of the plurality of waves to be executed simultaneously; 20. The processor of claim 19.

22. the one or more processing cores and configuring, while executing the plurality of waves, to allocate a second set of processing resources to the computing unit based on a second instruction. A processor according to any one of claims 19 to 21.

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