Power saving in network devices

Abstract

The controller determines the period during which the media access control (MAC) layer circuit outputs data corresponding to an idle symbol, which is output by the MAC layer circuit for transmission over the communication link. In response to the stage of determining the period, at least a portion of the PHY circuitry transitions to a low-power mode during that period, and the PHY circuitry outputs a signal corresponding to an idle symbol, which is for transmission over the communication link.

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 462,884, filed on April 28, 2023, entitled "Low Power FEC Mode for Ethernet Ports", the disclosure of which is hereby incorporated by reference in its entirety.

[0002] The present disclosure generally relates to communication networks, and more specifically to power - saving techniques for network devices operating in communication networks.

Background Art

[0003] The techniques described in this section are searchable techniques but are not necessarily techniques that have been previously conceived or searched. Therefore, unless otherwise indicated, none of the techniques described in this section should be considered as corresponding to the prior art merely because they are included in this section.

[0004] Facilities such as data centers, server farms, etc. typically have a communication network with multiple communication links. Data center networks are currently expanding at an exponential rate, and thus the number of communication links within the data center is also increasing rapidly. Along with the increase in the number of communication links in such facilities, the total amount of power consumed by network devices in such facilities becomes substantial.

[0005] In addition, to improve data throughput, operators often update and / or replace network devices (or their components) to increase link speed, but increasing the link speed also increases power consumption. For example, when the link speed increases by a factor of 4, typically the power consumption corresponding to that link will increase from 2 to 3 times.

[0006] For example, increased power consumption in facilities such as data centers and server farms leads to increased operating expenses (OpEx) and capital expenditures (CapEx) associated with such facilities. For instance, increased energy demand in such facilities necessitates operators to increase their power expenditures. This increased energy demand also necessitates CapEx for more complex power supply and cooling solutions.

[0007] Furthermore, since the density and / or overall size of facilities are constrained by power consumption, the aforementioned increase in power consumption is limiting the expansion of facilities such as data centers and server farms.

[0008] Therefore, it is advantageous to reduce the amount of power consumed by individual network devices in such facilities. [Overview of the Initiative]

[0009] In one embodiment, the network device includes: a medium access control (MAC) layer circuit configured to i) perform MAC layer operations defined by a communication protocol, ii) output MAC layer data for transmission over a network link, and iii) output an idle symbol when no packet data is output by the MAC layer circuit; a controller configured to generate an indicator that the MAC layer circuit has output an idle symbol for a period of time; and a physical layer (PHY) circuit communicatively coupled to the network link, configured to i) receive MAC layer data and an idle symbol from the MAC layer circuit, and ii) output a signal corresponding to the MAC layer data and the idle symbol, wherein the PHY circuit is further configured to: when the MAC layer circuit has output an idle symbol during the period, i) put a portion of the circuit of the PHY circuit into a low-power mode during the period, and ii) control the PHY circuit to output a signal corresponding to the idle symbol during the period.

[0010] In another embodiment, a method for saving power in a communication network comprises: a step in a controller of determining a period of time during which a medium access control (MAC) layer circuit outputs data corresponding to an idle symbol, the data being output by the MAC layer circuit for transmission over a communication link; and, in response to the step of determining the period, placing at least a portion of the PHY circuitry into a low-power mode during the period; and the PHY circuitry outputting a signal corresponding to the idle symbol, the signal being for transmission over the communication link. [Brief explanation of the drawing]

[0011] [Figure 1] This is a simplified diagram of an exemplary network device used in a communication network according to one embodiment.

[0012] [Figure 2] This is a simplified diagram of another exemplary network device used in a communication network, according to another embodiment.

[0013] [Figure 3] This is a simplified diagram of an exemplary communication system, including the communication device shown in Figure 2, according to one embodiment.

[0014] [Figure 4] Figures 1 and 2 are simplified diagrams of the components of the network device according to one embodiment, showing the data flow associated with the data to be transmitted via the communication medium. [Figure 5] Figure 5A shows an exemplary FEC data unit 400 containing packet data and an exemplary FEC data unit 404 having an idle symbol, configured to be output by the FEC circuit 148 according to one embodiment. Figure 5B shows another exemplary FEC data unit 454, configured to be output by the FEC circuit 148 according to one embodiment.

[0015] [Figure 6] Figures 1 and 2 are simplified diagrams of the network device components according to another embodiment, showing the data flow associated with data received via the communication medium.

[0016] [Figure 7] This is a flowchart illustrating an exemplary method for saving power in a communication network according to one embodiment.

[0017] [Figure 8] This is a flowchart of another exemplary method for saving power in a communication network, according to another embodiment. [Modes for carrying out the invention]

[0018] In the following description, several specific details are given for illustrative purposes to provide a thorough understanding of the subject matter of the present invention. However, it will become clear that the subject matter of the present invention can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the subject matter of the present invention.

[0019] Methods, techniques, and mechanisms for more optimally reducing power consumption in network devices, such as switches, routers, and endpoint devices, are disclosed. By reducing the power consumed by multiple network devices, the power consumption of facilities such as data centers and server farms can be significantly reduced.

[0020] In data center communication networks, for example, more than 50% of power is typically consumed by Ethernet® links, and in large data centers, there can be tens of thousands of Ethernet® links. When an Ethernet® link is not transmitting packets (i.e., the Ethernet® link is idle), the Ethernet® port corresponding to that Ethernet® link consumes power to maintain synchronization (i.e., keep the Ethernet® link "up"), and as a result, when packet transmission resumes, packets can be transmitted with low latency without having to go through a long process to bring the Ethernet® link back "up". For example, a first Ethernet® port transmits an idle symbol to a second Ethernet® port via the Ethernet® link, and the second Ethernet® port processes the idle symbol to maintain synchronization with the first Ethernet® port. The first and / or second Ethernet® ports can also use the transmission of idle symbols to train signal processing components, such as filters and echo cancellers. The amount of power consumed by an Ethernet® port when an Ethernet® link is idle is typically a large portion (e.g., 80%) of the power consumed when the Ethernet® link is active, i.e., when the Ethernet® link is transmitting packets.

[0021] Most of the power consumed while an Ethernet (registered trademark) link is in an idle state is essentially unnecessary. For example, a physical layer (PHY) circuit such as a forward error correction (FEC) encoding circuit processes dummy data unnecessarily, and / or the dummy data is transferred unnecessarily between PHY components. However, such PHY circuits / components typically do not recognize the content of the data processed / transferred by the PHY circuits / components. For example, the PHY circuits / components do not recognize when the PHY circuits / components are processing / transferring dummy data. In various embodiments described below, the controller determines when an idle symbol is being output by a media access control (MAC) layer circuit for transmission over a communication link, and notifies the PHY circuits / components when the MAC layer circuit is outputting an idle symbol. When the MAC layer circuit is outputting an idle symbol, the PHY circuits / components place at least a portion of the circuit in a low-power state to suppress power. As an exemplary example, when the MAC layer circuit is outputting an idle symbol, the circuit associated with generating FEC parity information is placed in a low-power state.

[0022] FIG. 1 is a simplified diagram of an exemplary network device 100 used in a communication network according to one embodiment. In some embodiments, the network device 100 is included within a communication network such as a data center, server farm, etc. In other embodiments, the network device 100 is included within another suitable communication network.

[0023] Network device 100 includes a switch 104 coupled to a PHY module 108 via an internal communication link 112. The PHY module 108 is coupled to an external network link comprising a suitable communication medium, such as a copper cable, optical fiber, etc. The network device 100 receives and transmits packets via the PHY module 108. In one embodiment, the network device 100 includes one or more other PHY modules (not shown) similar to the PHY module 108 coupled to one or more other external network links (not shown). In an embodiment where the network device 100 includes one or more other PHY modules (not shown), the switch 104 is coupled to the one or more other PHY modules via one or more respective other internal communication links (not shown) such as communication link 112.

[0024] Switch 104 includes a packet processor 120 configured to process at least the header of the packets received via the network link to determine through which network link the packets are to be transmitted. The switch 140 further includes or is coupled to a packet memory (not shown) configured to store the packets while they are being processed by the packet processor 120.

[0025] Switch 104 also includes a switch port 124 coupled to the packet processor 120. The switch port 124 is also coupled to the PHY module 108 via the internal communication link 112. The switch 104 also includes a plurality of other switch ports (not shown) such as the switch port 124, each of which is coupled to a respective other PHY module (not shown). The packet processor 120 analyzes the header of the packets received via the switch port to determine through which switch port the packets are to be forwarded.

[0026] In one embodiment, the switch port 124 includes a MAC circuit 132 configured to perform MAC layer protocol operations on packets that will be received and transmitted via the internal communication link 112. The switch port 124 also includes a PHY module 136 coupled to the MAC circuit 132 and the internal communication link 112.

[0027] In one embodiment, the PHY module 136 is configured to perform PHY layer protocol operations on packets that are received and transmitted over a network link. In one embodiment, the PHY module 136 includes a PCS circuit 144 configured to perform physical coding sublayer (PCS) protocol operations on packets that are received and transmitted over a network link. For example, according to one embodiment, the PCS circuit 144 includes an encoding circuit that encodes a bit block (e.g., 80 bits) received from the MAC circuit 132 to generate an encoded bit block (e.g., 81 bits) to be transmitted over the network link; and a decoding circuit that decodes the encoded bit block (e.g., 81 bits) received over the network link to generate a decoded bit block (e.g., 80 bits) for forwarding to the MAC circuit 132.

[0028] The PHY module 136 also includes a forward error correction (FEC) circuit 148 coupled to the PCS circuit 144. The FEC circuit 148 includes an FEC encoder for encoding data to be transmitted over a network link according to an FEC code, and an FEC decoder for decoding the data received over the network link according to the FEC code. In one embodiment, the FEC encoder includes a circuit for generating parity information. In one embodiment, the FEC circuit receives an encoded bit block from the PCS circuit 144 and generates FEC encoded data from the encoded bit block for transmission over the network link; and provides the PCS circuit 144 with FEC decoded data (corresponding to the data received over the network link).

[0029] The PHY module 136 also includes a serializer-deserializer (SERDES) 152 coupled to an FEC circuit 148 and an internal communication link 112. In one embodiment, the SERDES 152 is configured to transmit and receive packets to and from the PHY module 108 via the internal communication link 112. In one embodiment, the communication link 112 comprises a serial communication link having multiple lanes, and the SERDES 152 is configured to transmit and receive via these multiple lanes. The SERDES 152 is configured to receive packet data in parallel format via the FEC circuit 148 and convert the parallel format data into serial data, which is then forwarded to the PHY module 108 via the serial communication link 112. Similarly, the SERDES 152 is configured to receive serial packet data from the PHY module 108 via the serial communication link 112 and convert the serial packet data into parallel format packet data, which is then forwarded to the FEC circuit 148.

[0030] The PHY module 108 includes a SERDES 160, which is similar to a SERDES 152. In one embodiment, the SERDES 160 is configured to send and receive packets to and from a switch port 124 via an internal communication link 112. In one embodiment, where the communication link 112 is a serial communication link having multiple lanes, the SERDES 160 is configured to send and receive via these multiple lanes. The SERDES 160 is configured to receive packet data in parallel format from another component of the PHY module 108, convert this parallel data into serial data, which is then forwarded to the switch port 124 via the serial communication link 112. Similarly, the SERDES 160 is configured to receive serial packet data from the switch port 124 via the serial communication link 112, convert this serial packet data into parallel packet data, which is then forwarded to other components of the PHY module 108.

[0031] The PHY module 108 also includes a digital signal processor (DSP) circuit 164 configured to perform DSP functions, such as equalization, filtering, etc. In one embodiment, the DSP circuit 164 includes a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC).

[0032] The PHY module 108 also includes a transceiver 168 configured to transmit and receive signals over a communication medium. For example, the transceiver 168 is coupled to a DSP circuit 164 and is configured to receive a baseband signal (or intermediate frequency (IF) signal) output by the DSP circuit 164 and to generate a modulated signal for transmission over the communication medium based on the baseband (or IF) signal output by the DSP circuit 164. In another example, the transceiver 168 is configured to receive a modulated signal over the communication medium and to generate a baseband (or IF) signal for processing by the DSP circuit 164 based on the modulated signal received over the communication medium. In one embodiment, the transceiver 168 includes a modulation circuit and a demodulation circuit. In embodiments in which the communication medium includes a metallic medium (e.g., twisted pair cable, coaxial cable, etc.) or a wireless medium, the modulation circuit and demodulation circuit are configured to modulate and demodulate an electrical signal and / or a radio frequency (RF) signal, respectively. In embodiments where the communication medium includes an optical medium (e.g., optical fiber cable, free space, etc.), the modulation circuit and demodulation circuit are configured to modulate and demodulate the optical signal, respectively.

[0033] The MAC circuit 132 includes or is coupled to a power saving controller 172. The power saving controller 172 is configured to determine when the MAC circuit 132 is outputting or preparing to output idle symbols for forwarding to the PHY module 136. For example, the power saving controller 172 is configured to determine the period during which the MAC circuit 132 is outputting idle symbols for forwarding to the PHY module 136. In one embodiment, if the MAC circuit 132 has outputted idle symbols for forwarding to the PHY module 136 and, for example, has not received packet data for forwarding to the PHY module 108, and / or if one or more buffer memories (not shown) of the MAC circuit 132 are empty, such one or more buffer memories are for storing packet data received by the MAC circuit 132 for forwarding to the PHY module 136.

[0034] The power saving controller 172 is also configured to determine when the MAC circuit 132 is receiving idle symbols from the PHY module 136. For example, the power saving controller 172 is configured to determine the period during which the MAC circuit 132 is receiving idle symbols from the PHY module 108. In one embodiment, the MAC circuit 132 receives idle symbols from the PHY module 136, for example, when a link partner is sending idle symbols because the link partner does not have packet data to send and / or is not ready to send packet data.

[0035] In one embodiment, in response to determining that the MAC circuit 132 is outputting or preparing to output an idle symbol for transfer to the PHY module 136, the power saving controller 172 places a subset of the MAC circuit 132 into a low-power state, where this subset does not need to operate when the MAC circuit 132 is outputting and / or preparing to output an idle symbol for transfer to the PHY module 136.

[0036] In one embodiment, in response to the MAC circuit 132 determining that it has received an idle symbol from the PHY module 136, the power saving controller 172 places a subset of the MAC circuit 132 into a low-power state, where this subset of the circuit does not need to operate when the MAC circuit 132 is receiving an idle symbol from the PHY module 136.

[0037] The power saving controller 172 is also configured to generate a signal indicating when the MAC circuit 132 is outputting an idle symbol for transfer to the PHY module 136, in response to determining when the MAC circuit 132 is outputting or preparing to output an idle symbol for transfer to the PHY module 136. In one embodiment, the signal is contained within the data path between the MAC circuit 132 and the PHY module 136, i.e., the signal is an "in-band" signal. In another embodiment, the signal is outside the data path between the MAC circuit 132 and the PHY module 136, i.e., the signal is an "out-of-band" signal.

[0038] The components of PHY module 108 and / or PHY module 136 include their respective power saving controllers 180. In some embodiments, power saving controller 172 directly provides signals to two or more power saving controllers 180. In other embodiments, power saving controller 172 directly provides a signal to a first power saving controller 180, e.g., power saving controller 180-1, which then provides the signal to a second power saving controller 180, or generates a new signal and provides the new signal to the second power saving controller 180. According to one embodiment, the new signal indicates that a component including the first power saving controller 180 is outputting an idle symbol. In various embodiments, the transfer of the signal (indicating that an idle symbol is being output) from one power saving controller 180 to another is performed in-band or out-of-band. In some embodiments, one or more components use out-of-band signaling, and one or more other components use in-band signaling.

[0039] Each power saving controller 180 is configured to put at least some of the circuits of the components including the power saving controller 180 into a power saving mode in response to a signal indicating that an idle symbol is being output. For example, according to one embodiment, the PCS circuit 144 includes an encoder, and the power saving controller 180-1 puts the encoder into a power saving mode while the PCS circuit 144 is receiving an idle symbol as indicated by a signal. As another example, according to one embodiment, the FEC circuit 148 includes a parity information generator, and the power saving controller 180-2 puts the parity information generator into a power saving mode while the FEC circuit 148 is receiving an idle symbol as indicated by a signal.

[0040] As an example of in-band transmission of a signal indicating that a component is outputting an idle symbol, the component marks the data unit containing the idle symbol to indicate to the power saving controller 180 of a downstream component that the data unit contains an idle symbol. For example, a component of the PHY module 136, such as the FEC circuit 148 or another component, marks the data unit to indicate to one or more downstream components (e.g., the PHY module 108 and / or another network device coupled to a communication medium) that the data unit contains an idle symbol. In such an embodiment, one or more downstream components detect the marked data unit, and in response, the power saving controller 180 of one or more downstream components puts at least some of the circuits of that one or more components into power saving mode.

[0041] In some embodiments, each of at least a portion of the power saving controller 180 is also configured to detect when a component including the power saving controller 180 is receiving an idle symbol received via a communication medium; and in response to the detection that a component including the power saving controller 180 is receiving an idle symbol, at least a portion of the circuitry of that component is placed into a power saving mode. For example, according to one embodiment, the PCS circuit 144 includes a decoder, and the power saving controller 180-1 places the decoder into a power saving mode while the PCS circuit 144 is receiving an idle symbol. In another example, according to one embodiment, the FEC circuit 148 includes an FEC decoder circuit, and the power saving controller 180-2 places the FEC decoder circuit into a power saving mode while the FEC circuit 148 is receiving an idle symbol.

[0042] In some embodiments, one or more components of PHY module 108 and / or PHY module 136 detect marked data units received via a communication medium, and in response, a power saving controller 180 of the one or more components puts at least some of the circuits of the one or more components into the power saving mode described above. In such embodiments, a communication device that transmits data units via a communication medium is configured to mark packets containing such idle data units.

[0043] Figure 2 is a simplified diagram of another exemplary network device 200 used in a communication network according to one embodiment. In some embodiments, the network device 200 is included in a communication network such as a data center or server farm. In other embodiments, the network device 200 is included in another preferred communication network.

[0044] Network device 200 is similar to network device 100 in Figure 1, and for the sake of brevity, elements with the same numbering will not be described in detail again. Network device 200 includes a retimer and / or gearbox circuit 204 coupled between switch port 124 and PHY module 108. The retimer and / or gearbox circuit 204 (which may be referred to herein as “retimer / gearbox 204”) is employed to communicatively couple PHY module 108 to switch port 124. In particular, the retimer / gearbox 204 is coupled to switch port 124 via communication link 112, and the retimer / gearbox 204 is coupled to PHY module 108 via internal communication link 208.

[0045] The retimer circuit is useful when the PHY processor 108 is located at a relatively long distance from the switch port 124. The retimer circuit is configured to receive a signal, extract data from the signal, regenerate the signal using the extracted data, and then retransmit the regenerated signal.

[0046] A gearbox circuit is useful for interfacing a first communication link consisting of a first set of lanes, each operating at a first data rate, and a second communication link consisting of a second set of lanes, separate from the first set of lanes, each operating at a second data rate different from the first data rate. The gearbox circuit is configured to receive a first signal via the first set of lanes (each operating at a first data rate), extract data from the first signal, generate a second signal using the extracted data, configure the second signal for transmission via the second set of lanes, and then transmit the second signal via the second set of lanes (each operating at a second data rate).

[0047] The retimer / gearbox 204 includes a first SERDES 208, a DSP circuit 216, and a second SERDES 220. Each of the first SERDES 208, the DSP circuit 216, and the second SERDES 220 includes its respective power saving controller 232. In some embodiments, one or more power saving controllers 232 receive signals generated by power saving controller 172 directly from power saving controller 172. In other embodiments, one or more power saving controllers 232 receive signals indicating that an idle symbol has been received from another power saving controller 232, one of the power saving controllers 180, etc. In various embodiments, the transfer of signals (indicating that an idle symbol has been output) from one power saving controller 232 (or from power saving controller 180) to another power saving controller 232 may occur in-band or out-of-band.

[0048] Each power saving controller 232 is configured to put at least some of the circuits of the components including the power saving controller 232 into a power saving mode in response to a signal indicating that an idle symbol is being output. For example, according to one embodiment, the power saving controller 232-2 puts at least some of the DSP circuits into a low-power mode while the DSP circuit 216 is receiving an idle symbol as indicated by the signal.

[0049] In some embodiments, each of at least a portion of the power saving controller 232 is also configured to detect when a component including the power saving controller 232 is receiving an idle symbol received via a communication medium; and in response to the detection that a component including the power saving controller 232 is receiving an idle symbol, at least a portion of the circuitry of that component is placed into a power saving mode.

[0050] According to some embodiments, a signal indicating that a component is outputting an idle symbol also indicates the duration for which the component is outputting the idle symbol. In some embodiments, a signal indicating that a component is outputting an idle symbol includes an indication of the duration for which the component is outputting the idle symbol. In one embodiment, a signal indicating that a component is outputting an idle symbol is set to a first value when it is outputting data and / or control information, and to a second value when it is outputting an idle symbol. In another embodiment, the duration indication includes i) an indication of the start time of the period, and ii) an indication of the end time of the period. In another embodiment, the duration indication includes i) an indication of the start time of the period, and ii) an indication of the duration of the period. In another embodiment, the duration indication includes an indication of the start time of the period, where the duration of the period is a predetermined fixed duration known by the power saving controller 180 / 232.

[0051] In some embodiments, the MAC circuit 132 is configured to output data to the PHY module 136 in fixed-length data units (referred to herein as MAC data units) corresponding to the FEC codewords generated by the FEC circuit 148, that is, each MAC data unit is contained within its respective FEC codeword.

[0052] Figure 3 is a simplified diagram of an exemplary communication system 250 according to one embodiment, which includes the communication device 200 of Figure 2 (referred to as the "first communication device 200" in Figure 3). The communication system 250 includes a second communication device 258 which is communicatively coupled to the first communication device 200 via a preferred communication medium 262.

[0053] According to one embodiment, the PHY module 136 includes a marker circuit 270 configured to mark a data unit containing an idle symbol (i.e., the data unit does not contain packet data) so that it is identified as containing an idle symbol. For example, the marker circuit 270 sets at least a portion of the data unit to a predetermined value to indicate that the data unit contains an idle symbol.

[0054] The retimer / gearbox 204 includes a marking detection circuit 274 configured to detect marked data units (i.e., data units marked to indicate that the data unit contains an idle symbol) among the data units received from the PHY module 136. For example, in an embodiment in which a marker circuit 270 sets at least a portion of a data unit to a predetermined value to indicate that the data unit contains an idle symbol, the marking detection circuit 274 is configured to detect the predetermined value in the data unit received from the PHY module 136. In response to the marking detection circuit 274 detecting a marked data unit, the power saving controller 180 of the retimer / gearbox 204 puts the circuit of the retimer / gearbox 204 into power saving mode when the circuit of the retimer / gearbox 204 is receiving information that is not packet data.

[0055] Similarly, the PHY module 108 includes a marking detection circuit 278 that is identical or similar to the marking detection circuit 274. In response to the marking detection circuit 278 detecting a marked data unit from the retimer / gearbox 204, the power saving controller 180 of the PHY module 108 puts the circuit of the PHY module 108 into power saving mode when the circuit of the PHY module 108 is receiving information that is not packet data.

[0056] The first communication device 200 transmits a packet containing packet data and a packet 282 that includes an idle symbol and is marked (for example, by a marker circuit 270) to indicate that packet 282 contains an idle symbol.

[0057] The second communication device 258 includes a marking detection circuit 286 (e.g., identical or similar to the marking detection circuit 274) configured to detect marked packets (i.e., packets marked to indicate that the packet contains an idle symbol) among the packets received from the first communication device 200. In response to the marking detection circuit 286 detecting marked packets from the first communication device 200, the power saving controller of the second communication device 258 (identical or similar to the power saving controller 180 described above; not shown) puts the circuit of the second communication device 258 into power saving mode when the circuit of the second communication device 258 is receiving information that is not packet data.

[0058] In an embodiment in which the second communication device 258 includes a marker circuit (e.g., identical or similar to marker circuit 270; not shown) that marks packets containing idle symbols (i.e., packets that do not contain packet data) transmitted by the second communication device 258, the marking detection circuit 278 of the PHY module 108 detects marked packets received from the second communication device 258. In response to the marking detection circuit 278 detecting marked packets from the second communication device 258, the power saving controller 180 of the PHY module 108 puts the circuit of the PHY module 108 into power saving mode when the circuit of the PHY module 108 is receiving information that is not packet data.

[0059] Similarly, in an embodiment in which the second communication device 258 includes a marker circuit (e.g., identical or similar to marker circuit 270) that marks packets containing idle symbols (i.e., packets that do not contain packet data) transmitted by the second communication device 258, the marking detection circuit 274 detects marked data units from data units received from the PHY module 108 that correspond to marked packets. In response to the marking detection circuit 274 detecting marked data units from the PHY module 108, the power saving controller 180 of the retimer / gearbox 204 puts the circuit of the retimer / gearbox 204 into power saving mode when the circuit of the retimer / gearbox 204 is receiving information that is not packet data.

[0060] Similarly, in an embodiment in which the second communication device 258 includes a marker circuit (e.g., identical or similar to marker circuit 270) that marks packets containing idle symbols (i.e., packets that do not contain packet data) transmitted by the second communication device 258, the marking detection circuit of the PHY module 136 (not shown in Figure 3) detects marked data units from the data units received from the retimer / gearbox 204 that correspond to the marked packets. In response to the marking detection circuit detecting marked data units from the retimer / gearbox 204, the power saving controller 180 of the PHY module 136 puts the circuit of the PHY module 136 into power saving mode when the circuit of the PHY module 136 is receiving information that is not packet data.

[0061] In other embodiments, the retimer / gearbox 204 is omitted.

[0062] Figure 4 is a simplified diagram of the MAC circuit 132 and PHY module 136 components of network device 100 (Figure 1) and network device 200 (Figure 2) according to one embodiment, showing the data flow associated with data transmitted via the communication medium.

[0063] The power saving controller 172 determines when the MAC circuit 132 is not processing packet data. When the MAC circuit 132 is processing packet data, the MAC circuit 132 outputs a MAC data unit containing packet data. On the other hand, in response to the determination that the MAC circuit 132 is not processing packet data, the power saving controller 172 controls the MAC circuit 132 to output a MAC data unit containing idle symbols or other suitable content. In addition, the power saving controller 172 generates a signal indicating when the MAC circuit 132 is outputting information that is not packet data, such as idle symbols or other suitable content. In one embodiment, the signal generated by the power saving controller 172 indicates, according to one embodiment, that the MAC data unit output by the MAC circuit 132 does not contain packet data.

[0064] The power saving controller 180-1 of the PCS circuit 144 receives signals generated by the power saving controller 172. In response to signals from the power saving controller 172, the power saving controller 180-1 puts the circuit of the PCS circuit 144 into power saving mode when the PCS circuit 144 is receiving information that is not packet data, as indicated by the signals from the power saving controller 172. For example, according to one embodiment, if signals from the power saving controller 172 indicate that MAC data units from MAC circuit 132 do not contain packet data, the power saving controller 180-1 puts the circuit of the PCS circuit 144 into power saving mode while the PCS circuit 144 is receiving MAC data units that do not contain packet data.

[0065] The PCS circuit 144 includes an encoder 304 configured to encode an FEC data unit to generate encoded data as a PCS data unit when the power saving controller 172 indicates that the MAC circuit 132 is outputting a MAC data unit having packet data. For example, according to one embodiment, the encoder 304 encodes a plurality of 80-bit subblocks within the MAC data unit to generate an 81-bit encoded subblock. In another embodiment, the encoder 304 encodes subblocks of a suitable length other than 80 bits to generate an encoded subblock of a suitable length other than 82 bits.

[0066] In one embodiment, the power saving controller 180-1 places the encoder 304 into power saving mode while the PCS circuit 144 receives MAC units that do not contain packet data. In one embodiment, the power saving controller 180-1 controls the PCS circuit 144 to generate PCS data units that contain information that is not packet data, such as idle symbols or other suitable content. In one embodiment, each PCS data unit that does not contain packet data instead contains information set to a predetermined value.

[0067] The power saving controller 180-2 of the FEC circuit 148 receives a signal generated by the power saving controller 172. In response to the signal from the power saving controller 172, the power saving controller 180-2 puts the circuit of the FEC circuit 148 into power saving mode when the FEC circuit 148 is receiving information that is not packet data, as indicated by the signal from the power saving controller 172. For example, according to one embodiment, if the signal from the power saving controller 172 indicates that a PCS data unit from the PCS circuit 144 does not contain packet data, the power saving controller 180-2 puts the circuit of the FEC circuit 148 into power saving mode while the FEC circuit 148 is receiving the PCS data unit.

[0068] The FEC circuit 148 includes a parity information calculator 308 configured to generate parity information for an FEC codeword when the power saving controller 172 indicates that the PCS circuit 144 is outputting a PCS data unit containing packet data. The FEC circuit 148 outputs an FEC data unit. If the FEC data unit contains packet data, the FEC data unit contains an FEC codeword. If the FEC data unit does not contain packet data, the FEC data unit contains information that is not packet data, such as an idle symbol or other suitable content.

[0069] In one embodiment, the power saving controller 180-2 puts the parity information calculator 308 into power saving mode while the FEC circuit 148 is receiving PCS data units that do not contain packet data. In one embodiment, the power saving controller 180-2 controls the FEC circuit 148 to generate parity information having a predetermined value for FEC codewords that do not contain packet data.

[0070] In one embodiment, the FEC circuit 148 also includes a marker circuit 312 configured to mark FEC data units that do not contain packet data so that the FEC data units are identified as not containing packet data. For example, the marker circuit 312 sets at least a portion of the FEC data unit to a predetermined value to indicate that the FEC data unit does not contain packet data. In one embodiment, at least a portion of the FEC data unit lies within a location in the FEC data unit corresponding to the location of the payload in the FEC codeword, i.e., outside another location in the FEC data unit corresponding to the location of the parity information in the FEC codeword. In another embodiment, at least a portion of the FEC data unit lies within a location in the FEC data unit corresponding to the location of the parity information in the FEC codeword. In another embodiment, the marker circuit 312 sets at least a portion of the FEC data unit to a predetermined value to indicate that the FEC data unit does not contain packet data. In one embodiment, the power saving controller 180-2 controls the marker circuit 312 to mark FEC data units that do not contain packet data.

[0071] In some embodiments, the marker circuit 312 corresponds to the marker circuit 270 in Figure 3.

[0072] Figure 5A shows an exemplary FEC data unit 400 containing packet data and an exemplary FEC data unit 404 having an idle symbol, configured to be output by an FEC circuit 148 according to one embodiment. The FEC data unit 400 has an FEC codeword including a payload portion 416 and a parity portion 420. According to one embodiment, the payload portion 416 corresponds to a PCS data unit received from a PCS circuit 144. According to one embodiment, a parity calculator 308 is configured to calculate parity information contained in the parity portion 420, which is calculated using a PCS data unit received from a PCS circuit 144.

[0073] The FEC data unit 404 has a length equal to the length of the FEC data unit 400. According to one embodiment, the FEC data unit 404 includes a portion 428 that is set to a predetermined value to indicate that the FEC data unit 404 does not contain packet data, i.e., that the FEC data unit 404 is not an FEC codeword 400. The portion 428 is included in the section of the FEC data unit 404 corresponding to the payload 416 of the FEC data unit 400. In Figure 5A, the portion 428 is shown as corresponding to a subset of the section of the FEC data unit 400 corresponding to the payload 416, but in other embodiments, the portion 428 extends to the entire section of the FEC data unit 400 corresponding to the payload 416.

[0074] Figure 5B shows another exemplary FEC data unit 454 configured to be output by the FEC circuit 148 according to one embodiment. The FEC data unit 454 has a length equal to the length of the FEC codeword 400. According to one embodiment, the FEC data unit 454 includes a portion 458 that is set to a predetermined value to indicate that the FEC data unit 454 does not contain packet data, i.e., that the FEC data unit 454 is not the FEC codeword 400. The portion 458 is included in a section of the FEC data unit 404 corresponding to the parity portion 420 of the FEC data unit 400. In Figure 5B, the portion 458 is shown as corresponding to a subset of the section corresponding to the parity portion 420 of the FEC data unit 400, but in other embodiments, the portion 458 extends to the entire section corresponding to the parity portion 458 of the FEC data unit 400.

[0075] In some embodiments, the signal from the power saving controller 172 includes an indication of the end time for a set of multiple FEC data units that do not contain packet data. In these embodiments, the marker circuit 312 includes an indication of the end time for each of the one or more FEC data units that contain an idle symbol. According to various embodiments, the indication of the end time includes the number of subsequent FEC data units that do not contain packet data, a time value corresponding to the end time, a time value specifying the duration of the period during which the FEC circuit outputs FEC data units that do not contain packet data, and so on.

[0076] As will be further discussed below, the marking of FEC data units as described above allows a receiver of FEC data units (e.g., one or more of the SERDES152, the retimer / gearbox 204, the PHY module 108, the second communication device 258, etc.) to distinguish between FEC data units with idle symbols and FEC data units with packet data for the purpose of saving power.

[0077] The power saving controller 180-3 of SERDES152 receives signals generated by the power saving controller 172. In response to signals from the power saving controller 172, the power saving controller 180-3 puts the circuitry of SERDES152 into power saving mode when SERDES152 is receiving information that is not packet data, as indicated by the signals from the power saving controller 172. For example, according to one embodiment, if signals from the power saving controller 172 indicate that SERDES152 is receiving an FEC data unit that does not contain packet data, the power saving controller 180-3 puts the circuitry of SERDES152 into power saving mode while SERDES152 is receiving the FEC data unit.

[0078] In another embodiment, SERDES152 includes a marking detection circuit (not shown) identical or similar to the marking detection circuit 274 in Figure 3, wherein the marking detection circuit detects FEC data units that are marked to indicate that the FEC data unit does not contain packet data. In some such embodiments, in response to the marking detection circuit detecting a marked FEC data unit, the power saving controller 180-3 puts the circuit of SERDES152 into power saving mode when SERDES152 is receiving information that is not packet data, as indicated by the marked FEC data unit. In some such embodiments, the power saving controller 180-3 does not receive signals generated by the power saving controller 172.

[0079] SERDES152 includes a plurality of serial output signal generators 324 corresponding to each lane of the internal communication link 112. In one embodiment, the power saving controller 180-3 puts a subset of the serial output signal generators 324 (e.g., serial output signal generators 324-1, 324-2, and 324-3) into power saving mode while SERDES152 is receiving FEC data units that do not contain packet data.

[0080] In some embodiments, SERDES152 includes a DSP circuit (not shown), and the power saving controller 180-3 additionally or alternatively puts the DSP circuit into power saving mode when SERDES152 receives information that is not packet data, as indicated by signals from the power saving controller 172 and / or the marking detection circuit.

[0081] In some embodiments, one or two of the power saving controllers 180 are omitted. For example, SERDES 152 does not include power saving controller 180-3 and does not put the circuit into power saving mode when SERDES 152 is receiving an FEC data unit that does not contain packet data.

[0082] Referring again to Figure 1, one or both of SERDES160 and DSP164 include a marking detection circuit (not shown) identical or similar to the marking detection circuit 274 in Figure 3, where the marking detection circuit detects FEC data units that are marked to indicate that the FEC data units do not contain packet data. In some such embodiments, in response to the marking detection circuit detecting a marked FEC data unit, the power saving controller 180-4 / 180-5 puts the circuitry of SERDES160 and / or DSP164 into power saving mode when SERDES160 and / or DSP164 are receiving information that is not packet data, as indicated by the marked FEC data unit. In some such embodiments, the power saving controller 180-4 / 180-5 does not receive signals generated by the power saving controller 172.

[0083] Referring again to Figure 2, one or more of SERDES212, DSP216, and SERDES220 include a marking detection circuit (not shown) identical or similar to the marking detection circuit 274 in Figure 3, where the marking detection circuit detects FEC data units that are marked to indicate that the FEC data units do not contain packet data. In some such embodiments, in response to the marking detection circuit detecting a marked FEC data unit, the power saving controllers 232-1 / 232-2 / 232-3 put the circuits of SERDES212, DSP216, and / or SERDES220 into power saving mode when SERDES212, DSP216, and / or SERDES220 are receiving information that is not packet data, as indicated by the marked FEC data unit. In some such embodiments, the power saving controllers 232-1 / 232-2 / 232-3 do not receive signals generated by the power saving controller 172.

[0084] Referring again to Figure 4, the marking circuit 312 is configured to mark FEC data units by including a pattern in a portion of the FEC data unit corresponding to the payload of the FEC codeword. In some embodiments, the pattern is designed so that when the communication device 100 / 200 transmits a packet corresponding to the FEC data unit over the communication medium, the packet has a suitable number of symbol transitions and is DC balanced. In some embodiments, the pattern includes a repeating subpattern designed so that when the communication device 100 / 200 transmits a packet corresponding to the FEC data unit over the communication medium, the packet has a suitable number of symbol transitions and is DC balanced. In some embodiments, the pattern is identical to or similar to an alignment marker. In one embodiment, the pattern is an inverted alignment marker. In one embodiment using non-return to zero (NRZ) SERDES, the pattern corresponds to alternating 1s and 0s. In one embodiment using a 4-level pulse amplitude modulation (PAM4) SERDES having levels 0, 1, 2, and 3, the pattern corresponds to a repeating pattern of 0, 1, 2, and 3. In other embodiments (including other embodiments using NRZ or PAM4 SERDES), other suitable patterns are used.

[0085] Figure 6 is a simplified diagram of the components of the MAC circuit 132 and PHY module 136 of network devices 100 (Figure 1) and 200 (Figure 2) according to one embodiment, showing a data flow 500 associated with data received via a communication medium. In the embodiment of Figure 6, the MAC circuit 132 and PHY module 136 receive data from a link partner via a communication medium, and the link partner can mark packets to indicate that a packet does not contain packet data and / or to distinguish such packets from packets that contain packet data. For example, in some embodiments, the link partner includes a marking circuit that is identical or similar to the marker circuit 312 in Figure 4. In another embodiment, the MAC circuit 132 and PHY module 136 receive data from another module in the network device, such as PHY module 108 (Figures 1 and 2), retimer / gearbox 204 (Figure 2), etc., and the module can mark the FEC data unit to indicate that it does not contain packet data and / or to distinguish an FEC data unit from an FEC data unit that has an FEC codeword. For example, in some embodiments, the other module includes a marking circuit that is identical or similar to the marker circuit 312 in Figure 4.

[0086] SERDES152 receives FEC data units via multiple lanes of the internal communication link 112, and these FEC data units correspond to packets received from link partners via the communication medium. SERDES152 includes multiple parallel output signal generators 504, each corresponding to a lane. Each parallel output signal generator 504 generates its own parallel output based on its respective serial input received via its respective lane. SERDES152 is configured to combine the outputs of the parallel output signal generators 504 to produce a combined output.

[0087] The FEC circuit 148 is configured to receive FEC data units output by SERDES 152. The FEC circuit 148 includes a marking detection circuit 512 configured to detect FEC data units that do not contain packet data, and the FEC data units are marked, for example, by a link partner or another component in the network device, to indicate that the FEC data units do not contain packet data and / or to distinguish them from FEC data units that have an FEC codeword. In response to the marking detection circuit 512 detecting an FEC data unit that does not contain packet data, the power saving controller 180-2 puts the circuit of the FEC circuit 148 into power saving mode. For example, according to one embodiment, if the marking detection circuit 512 detects a marked FEC data unit, the power saving controller 180-2 puts the circuit of the FEC circuit 148 into power saving mode while the FEC circuit 148 is receiving the marked FEC data unit.

[0088] The FEC circuit 148 includes an FEC decoder circuit 516 configured to decode FEC codewords according to FEC. In one embodiment, the power saving controller 180-2 places at least a portion of the FEC decoder circuit 516 into a low-power mode, so that the FEC decoder circuit 516 does not perform FEC decoding of marked FEC data units. For example, in one embodiment, the power saving controller 180-2 controls the FEC circuit 148 to output only PCS data units containing a section of an FEC data unit, without performing FEC decoding, the section corresponding to the payload of the FEC codeword and having the length of the payload of the FEC codeword. In another example, in one embodiment, the power saving controller 180-2 controls the FEC circuit 148 to output PCS data units having a predetermined value, the predetermined value having the length corresponding to the payload of the FEC codeword, without performing FEC decoding.

[0089] Furthermore, in response to the marking detection circuit 512 detecting an FEC data unit that does not contain packet data, the power saving controller 180-2 generates a signal to indicate that the information output by the FEC circuit is a PCS data unit that does not contain packet data, and / or to distinguish such PCS data unit from a PCS data unit that contains packet data. The signal indicating that the PCS data unit does not contain packet data corresponds to a signal indicating the period during which the FEC circuit 148 is outputting information that is not packet data. For example, the FEC data unit and / or PCS data unit has a predetermined fixed length known in other components of the PHY module 136 and / or MAC circuit 132, and / or the start time of the FEC data unit and / or PCS data unit is known in other components of the PHY module 136 and / or MAC circuit 132, and therefore the indication that the FEC circuit is outputting a PCS data unit that does not contain packet data also indicates the period during which the FEC circuit 148 is outputting information that is not packet data.

[0090] In some embodiments, where an FEC data unit indicates a period of non-packet data that is greater than one FEC data unit, the power saving controller 180-2 generates a signal indicating a period during which the FEC circuit 148 is outputting information that does not contain packet data.

[0091] The power saving controller 180-1 receives a signal output by the power saving controller 180-2 and, in response, places some of the circuits of the PCS 144 into power saving mode during the period indicated by the signal from the power saving controller 180-2. For example, if the PCS 144 includes a decoder circuit 520, the power saving controller 180-1 places the decoder circuit 520 into power saving mode during the period indicated by the signal from the power saving controller 180-2.

[0092] The power saving controller 172 receives a signal output by the power saving controller 180-2 and, in response, puts a portion of the MAC circuit 132 into power saving mode during the period indicated by the signal from the power saving controller 180-2.

[0093] In some embodiments, the power saving controller 180-3 also receives a signal output by the power saving controller 180-2 and, in response, places some of the circuits of the SERDES 152 into power saving mode during the period indicated by the signal from the power saving controller 180-2. For example, according to one embodiment, the power saving controller 180-3 places a subset of the parallel output generators 504 (e.g., parallel output generators 504-1, 504-2, and 504-3) into power saving mode during that period. According to another embodiment, as another example, the SERDES 152 includes a DSP circuit (not shown), and the power saving controller 180-3 additionally or alternatively places the DSP circuit into power saving mode during that period.

[0094] In one embodiment, the marking detection circuit 512 is configured to compare N bits from an M-bit pattern, where M is the length of a preferred pattern and N is a preferred positive integer smaller than M. Generally, N is selected according to a trade-off between false positives and false negatives. For example, as N decreases, the probability of a false positive increases because the probability of the packet data matching N bits increases. In addition, as N increases, the probability of the pattern not being detected due to bit errors increases.

[0095] Figure 7 is a flowchart of an exemplary method 600 for saving power in a communication network according to one embodiment. In various embodiments, method 600 is implemented by the communication device 100, communication device 200, and / or circuit 300 shown in Figures 1 to 4, and method 600 is described with reference to Figures 1 to 4 for illustrative purposes. In other embodiments, method 600 is implemented by other preferred network devices different from the communication devices / circuits shown in Figures 1 to 4.

[0096] In block 604, the controller (e.g., power saving controller 172) determines the period during which the MAC layer circuit (e.g., MAC layer circuit 132) outputs data corresponding to an idle symbol, which is then output by the MAC layer circuit for transmission over the network link. In some embodiments, the period corresponds to the MAC data unit described above. In some embodiments, the period corresponds to multiple MAC data units. In other embodiments, the period does not need to correspond to a boundary between MAC data units.

[0097] In block 608, in response to determining a period, at least some PHY circuits are placed in low-power mode during that period. For example, in one embodiment, the circuits of PHY module 136 are placed in low-power mode during that period. For example, in one embodiment, the circuits of PCS circuit 144 (e.g., encoder 304) are placed in low-power mode during that period. As another example, in another embodiment, the circuits of FEC circuit 148 (e.g., parity calculator 308) are additionally or alternatively placed in low-power mode during that period. As yet another example, in another embodiment, the circuits of SERDES 152 (e.g., a subset of serial output generator 324) are additionally or alternatively placed in low-power mode during that period.

[0098] In block 612, in response to the determination of a period, the PHY circuit outputs a signal corresponding to an idle symbol, which is for transmission over the communication link. For example, in one embodiment, during the period, the PHY circuit 136 outputs a signal corresponding to non-packet data output by the MAC circuit 132. In another embodiment, during the period, the PCS circuit 144 outputs a PCS data unit corresponding to the non-packet data output by the MAC circuit 132. In yet another embodiment, during the period, the FEC circuit 148 outputs an FEC data unit corresponding to the non-packet data output by the MAC circuit 132.

[0099] As another example, according to another embodiment, during the period, the PHY circuit 108 outputs a signal corresponding to the non-packet data output by the MAC circuit 132. As another example, according to another embodiment, during the period, the SERDES 160 outputs a signal corresponding to the non-packet data output by the MAC circuit 132. As another example, according to another embodiment, during the period, the DSP circuit 164 outputs a signal corresponding to the non-packet data output by the MAC circuit 132.

[0100] In one embodiment, method 500 further comprises marking a signal output by a PHY circuit to include an indication of a period, so that a receiver of the signal can determine the period. For example, in one embodiment, an FEC circuit marks an FEC data unit containing non-packet data.

[0101] Figure 8 is a flowchart of another exemplary method 700 for saving power in a communication network, according to a different embodiment. In various embodiments, method 700 is implemented by the communication device 100, communication device 200, and / or circuit 300 of Figures 1-4, and method 700 is described with reference to Figures 1-4 for illustrative purposes. In other embodiments, method 700 is implemented by a different preferred network device than the communication device / circuit of Figures 1-4.

[0102] In block 704, the PHY circuit receives a signal via a communication link. For example, according to one embodiment, PHY circuit 136 receives a signal. In another example, according to another embodiment, PHY circuit 108 receives a signal.

[0103] In block 708, the PHY circuit determines that the signal contains an indicator of the period corresponding to an idle symbol. For example, the PHY circuit includes marking detection circuits (e.g., marking detection circuits 274, 278, 286, and 512) configured to detect markings in the signal that indicate the period corresponding to an idle symbol. For example, the signal is composed of packets, FEC data units, etc., and the marking detection circuits are configured to detect packets and / or FEC data units that are marked to indicate that the packet / FEC data unit contains non-packet data, and / or to distinguish between such packet / FEC data units and packet / FEC data units that contain packet data.

[0104] In block 712, in response to the determination that the signal includes an indicator, at least some PHY circuits are placed in low-power mode during the period. For example, in one embodiment, the circuits of PHY module 136 are placed in low-power mode during the period. For example, in one embodiment, the circuits of PCS circuit 144 (e.g., encoder 304) are placed in low-power mode during the period. As another example, in another embodiment, the circuits of FEC circuit 148 (e.g., parity calculator 308) are additionally or alternatively placed in low-power mode during the period. As yet another example, in another embodiment, the circuits of SERDES 152 (e.g., a subset of serial output generator 324) are additionally or alternatively placed in low-power mode during the period.

[0105] In some embodiments and / or scenarios, the circuitry of the PHY module 108 is additionally or alternatively placed into a low-power mode during the period. For example, the circuitry of the DSP 164 is placed into a low-power mode during the period. As another example, the circuitry of the SERDES 152 (e.g., a subset of the serial output generator 324) is additionally or alternatively placed into a low-power mode during the period.

[0106] As another example, according to some embodiments and / or scenarios, the circuit of the retimer / gearbox 204 is placed in a low-power mode during that period.

[0107] In block 716, during the relevant period, the PHY circuit outputs data corresponding to the idle symbol. For example, according to one embodiment, during the relevant period, the PHY circuit 136 outputs non-packet data to the MAC circuit 132. As another example, according to one embodiment, during the relevant period, the FEC circuit 148 outputs PCS data units corresponding to the idle symbol. As yet another example, according to one embodiment, during the relevant period, the SERDES 152 outputs data corresponding to the idle symbol.

[0108] As another example, according to one embodiment, during the period, the PHY circuit 108 outputs data corresponding to the idle symbol to the internal communication link 112. As yet another example, according to another embodiment, during the period, the DSP circuit 164 outputs data corresponding to the idle symbol.

[0109] Embodiment 1: A network device comprising: a media access control (MAC) layer circuit configured to i) perform MAC layer operations defined by a communication protocol, ii) output MAC layer data for transmission over a network link, and iii) output an idle symbol when no packet data is output by the MAC layer circuit; a controller configured to generate an indicator that the MAC layer circuit has output an idle symbol for a period of time; and a physical layer (PHY) circuit communicatively coupled to the network link, configured to i) receive MAC layer data and an idle symbol from the MAC layer circuit, and ii) output a signal corresponding to the MAC layer data and the idle symbol, wherein the PHY circuit is further configured to, when the MAC layer circuit has output an idle symbol during the period, i) put a portion of the circuit of the PHY circuit into a low-power mode during the period, and ii) control the PHY circuit to output a signal corresponding to the idle symbol during the period.

[0110] Embodiment 2: The network device according to Embodiment 1, wherein the PHY circuit further includes a forward error correction (FEC) encoder configured to, when an idle symbol is output by the MAC layer circuit during the period, i) put a portion of the circuit of the FEC encoder into the low-power mode during the period, and ii) output one or more data units corresponding to the idle symbol.

[0111] Embodiment 3: The network device according to Embodiment 2, wherein the FEC encoder includes a parity information calculation circuit; and the FEC encoder is configured to place the parity information calculation circuit into the low-power mode during the period.

[0112] Embodiment 4: The network device according to either Embodiment 1 or 2, wherein the PHY circuit further includes a serializer / deserializer (SERDES), the SERDES configured to i) put some of the circuits of the SERDES into a low-power mode during the period, and ii) generate one or more serial signals corresponding to the idle symbol, in relation to the MAC layer circuit outputting an idle symbol during the period.

[0113] Embodiment 5: The network device according to Embodiment 4, wherein the SERDES includes a plurality of serial output generators coupled to each lane of the communication link; and the SERDES is configured to place a subset of the serial output generators into the low-power mode during the period when the MAC layer circuit outputs idle symbols during the period.

[0114] Embodiment 6: The network device according to any one of Embodiments 1 to 5, wherein the PHY circuit includes an FEC encoder circuit configured to generate forward error correction (FEC) data units for transmission over the network link; and the PHY circuit is configured to mark the one or more FEC data units to indicate that the one or more FEC data units corresponding to the period contain non-packet data.

[0115] Embodiment 7: The network device according to Embodiment 6, wherein the FEC encoder circuit includes a marking circuit configured to mark each section of the one or more FEC data units corresponding to the location of the payload in the FEC codeword.

[0116] Embodiment 8: The network device according to Embodiment 6, wherein the FEC encoder circuit includes a marking circuit configured to mark each of the one or more sections of the one or more FEC data units corresponding to the position of the parity portion in the FEC codeword.

[0117] Embodiment 9: A network device according to any one of Embodiments 1 to 8, wherein the controller is included in the MAC circuit.

[0118] Embodiment 10: The network device according to any one of Embodiments 1 to 9, wherein the PHY circuit is a first PHY circuit configured to output a first signal corresponding to the MAC layer data and idle symbols; the network device further comprises a second PHY circuit coupled to the first PHY circuit via a communication link; the second PHY circuit communicatively couples the first PHY circuit to the network link; and the second PHY circuit is configured to: i) put a portion of the circuit of the second PHY circuit into a low-power mode during the period when the MAC layer circuit is outputting idle symbols during the period; and ii) control the second PHY circuit to output a signal corresponding to the idle symbols during the period.

[0119] Embodiment 11: A method for saving power in a communication network, comprising the steps of: determining a period of time during which a media access control (MAC) layer circuit outputs data corresponding to an idle symbol, the data being output by the MAC layer circuit for transmission over a communication link; and, in response to the step of determining the period, placing at least a portion of the circuitry of the PHY circuitry into a low-power mode during the period; and the PHY circuitry outputting a signal corresponding to the idle symbol, the signal being for transmission over the communication link.

[0120] Embodiment 12: The step of placing at least a portion of the PHY circuit into the low-power mode during the period is: the step of placing a subset of the circuit of a forward error correction (FEC) encoder circuit into the low-power mode during the period, the FEC encoder circuit being coupled to the MAC layer circuit; wherein the method further comprises: the step of the FEC encoder circuit outputting one or more FEC data units containing data corresponding to the idle symbol, the method according to Embodiment 11.

[0121] Embodiment 13: The method according to Embodiment 12, wherein the step of placing a subset of the FEC encoder circuit into the low-power mode during the period is: the step of placing the parity information generation circuit into the low-power mode during the period.

[0122] Embodiment 14: The step of placing at least a portion of the circuits of the PHY circuit into the low-power mode during the period comprises: placing a subset of the circuits of a serializer / deserializer (SERDES) into the low-power mode during the period, the SERDES being coupled to the MAC layer circuit, wherein the method further comprises: the SERDES outputting one or more serial signals containing data corresponding to the idle symbol, according to any one of Embodiments 11 to 13.

[0123] Embodiment 15: The method according to Embodiment 14, wherein the SERDES includes a plurality of serial output generators coupled to each lane of the communication link; and includes the steps of placing a subset of the circuits of the SERDES into the low-power mode during the period, and placing a subset of the serial signal generators into the low-power mode.

[0124] Embodiment 16: The method according to any one of Embodiments 11 to 15, wherein the step of placing at least a portion of the PHY circuit into the low-power mode during the period is: the step of placing the digital signal processing circuit into the low-power mode during the period.

[0125] Embodiment 17: The method according to any one of Embodiments 11 to 16, wherein the PHY circuit includes an FEC encoder circuit that generates forward error correction (FEC) data units for transmission over the communication link; the method, in response to a step of determining the period, further comprises a step of the PHY circuit marking the one or more FEC data units to indicate that one or more FEC data units corresponding to the period contain non-packet data.

[0126] Embodiment 18: The step of marking one or more FEC data units is: The PHY circuit marks each section of the one or more FEC data units that corresponds to the location of the payload within the FEC codeword. The method according to embodiment 17, wherein the method is characterized by having the following features.

[0127] Embodiment 19: The method according to Embodiment 17, wherein the step of marking the one or more FEC data units is: the step of the PHY circuit marking each of the one or more sections of the one or more FEC data units that correspond to the location of the payload portion in the FEC codeword.

[0128] Some of the various blocks, operations, and techniques described above can be implemented using hardware, a processor that executes firmware instructions, a processor that executes software instructions, or any suitable combination thereof. When implemented using a processor that executes software or firmware instructions, the software or firmware instructions can be stored in any suitable computer-readable memory. When executed by one or more processors, the software or firmware instructions may include machine-readable instructions that cause one or more processors to perform the various operations described above.

[0129] When implemented in hardware, the hardware may include one or more of the following: individual components, integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), etc.

[0130] Although the present invention is described with reference to specific examples, these are merely illustrative and not intended to limit the invention, and modifications, additions, and / or deletions may be made to the disclosed embodiments without departing from the scope of the invention. (Other possible items) (Item 1) A media access control (MAC) layer circuit configured to i) perform MAC layer operations defined by a communication protocol, ii) output MAC layer data for transmission over a network link, and iii) output an idle symbol when no packet data is being output by the MAC layer circuit; A controller configured to generate an indicator that an idle symbol has been output by the MAC layer circuit for a certain period of time; and A physical layer (PHY) circuit communicatively coupled to the network link, wherein the PHY circuit is configured to: i) receive MAC layer data and idle symbols from the MAC layer circuit, and ii) output signals corresponding to the MAC layer data and idle symbols, where the PHY circuit is: When the MAC layer circuit outputs an idle symbol during the aforementioned period, i) put a portion of the PHY circuit into a low-power mode during the aforementioned period, and ii) control the PHY circuit to output a signal corresponding to the idle symbol during the aforementioned period. It is further structured in the following way: A network device equipped with the following features. (Item 2) The aforementioned PHY circuit is: A forward error correction (FEC) encoder configured such that, when an idle symbol is output by the MAC layer circuit during the period, i) a portion of the circuitry of the FEC encoder is placed in the low-power mode during the period, and ii) one or more data units corresponding to the idle symbol are output. The network devices listed in item 1, including, furthermore. (Item 3) The FEC encoder includes a parity information calculation circuit; The FEC encoder is configured to put the parity information calculation circuit into the low-power mode during the period. The network device described in item 2. (Item 4) The network device according to any one of items 1 to 3, wherein the PHY circuit further includes a serializer / deserializer (SERDES), the SERDES configured to i) put some of the circuits of the SERDES into a low-power mode during the period, and ii) generate one or more serial signals corresponding to the idle symbol, in connection with the MAC layer circuit outputting an idle symbol during the period. (Item 5) The SERDES includes multiple serial output generators coupled to each lane of the communication link; The SERDES is configured to place a subset of the serial output generators into the low-power mode during the period when idle symbols are output by the MAC layer circuit during that period. The network device described in item 4. (Item 6) The PHY circuit includes an FEC encoder circuit configured to generate forward error correction (FEC) data units for transmission over the network link; The PHY circuit is configured to mark one or more FEC data units to indicate that one or more FEC data units corresponding to the period include non-packet data. A network device listed in any one of items 1 through 5. (Item 7) The FEC encoder circuit includes a marking circuit configured to mark each section of the one or more FEC data units corresponding to the payload position within the FEC codeword. The network device described in item 6. (Item 8) The FEC encoder circuit includes a marking circuit configured to mark each section of the one or more FEC data units corresponding to the position of the parity portion within the FEC codeword. The network device described in item 6. (Item 9) The controller is included in the MAC layer circuit. A network device listed in any one of items 1 through 8. (Item 10) The PHY circuit is a first PHY circuit configured to output a first signal corresponding to the MAC layer data and idle symbols; The network device further comprises a second PHY circuit coupled to the first PHY circuit via a communication link; The second PHY circuit connects the first PHY circuit to the network link in a communicative manner; The second PHY circuit is configured to: i) put a portion of the circuit of the second PHY circuit into a low-power mode during the period when the MAC layer circuit outputs an idle symbol during the period, and ii) control the second PHY circuit to output a signal corresponding to the idle symbol during the period. A network device listed in any one of items 1 through 9. (Item 11) In the controller, the step of determining the period of time during which the media access control (MAC) layer circuit outputs data corresponding to an idle symbol, the data being output by the MAC layer circuit for transmission over a communication link; and In response to the step of determining the aforementioned period, The steps include: placing at least a portion of the PHY circuit into a low-power mode during the aforementioned period, and The PHY circuit outputs a signal corresponding to the idle symbol, the signal being for transmission via the communication link. A method for saving power in a communication network, comprising the features described above. (Item 12) The step of placing at least a portion of the PHY circuit into the low-power mode during the aforementioned period is: During the aforementioned period, a subset of the circuitry of the forward error correction (FEC) encoder circuit is placed into the low-power mode, wherein the FEC encoder circuit is coupled to the MAC layer circuit; The method has, where the method is: The FEC encoder circuit outputs one or more FEC data units, including data corresponding to the idle symbol. The method described in item 11, further comprising: (Item 13) The step of placing a subset of the FEC encoder circuit into the low-power mode during the aforementioned period is: Steps to place the parity information generation circuit into the low-power mode during the aforementioned period. The method described in item 12, including the method described in item 12. (Item 14) The step of placing at least a portion of the PHY circuit into the low-power mode during the aforementioned period is: During the aforementioned period, a subset of the serializer / deserializer (SERDES) circuitry is placed into the low-power mode, wherein the SERDES are coupled to the MAC layer circuitry; The method has, where the method is: The SERDES process outputs one or more serial signals containing data corresponding to the idle symbol. The method described in any one of items 11 to 13, further comprising: (Item 15) The SERDES includes multiple serial output generators coupled to each lane of the communication link; The step of placing a subset of the circuits of the SERDES into the low-power mode during the aforementioned period includes the step of placing a subset of the serial signal generators into the low-power mode. The method described in item 14. (Item 16) The step of placing at least a portion of the PHY circuit into the low-power mode during the aforementioned period is: Steps to place the digital signal processing circuit into the low-power mode during the aforementioned period. The method described in any one of items 11 to 15, wherein the method is provided. (Item 17) The PHY circuit includes an FEC encoder circuit that generates forward error correction (FEC) data units for transmission over the communication link; The method described above responds to the step of determining the period: The PHY circuit marks one or more FEC data units to indicate that one or more FEC data units corresponding to the period include non-packet data. The method described in any one of items 11 to 16, further comprising: (Item 18) The step of marking one or more FEC data units is: The PHY circuit marks each section of the one or more FEC data units that corresponds to the location of the payload within the FEC codeword. The method described in item 17, which has the following characteristics. (Item 19) The step of marking one or more FEC data units is: The PHY circuit marks each section of the one or more FEC data units that corresponds to the location of the payload portion within the FEC codeword. The method described in item 17, which has the following characteristics.

Claims

1. A media access control (MAC) layer circuit configured to: i) perform MAC layer operations defined by a communication protocol; ii) output MAC layer data for transmission over a network link; and iii) output an idle symbol when no packet data is being output by the MAC layer circuit; A controller configured to generate an indicator that an idle symbol has been output by the MAC layer circuit for a certain period of time; and A physical layer (PHY) circuit communicatively coupled to the network link, wherein the PHY circuit is configured to: i) receive MAC layer data and idle symbols from the MAC layer circuit, and ii) output signals corresponding to the MAC layer data and idle symbols, where the PHY circuit is: When the MAC layer circuit outputs an idle symbol during the aforementioned period, i) put a portion of the PHY circuit into low-power mode during the aforementioned period, and ii) control the PHY circuit to output a signal corresponding to the idle symbol during the aforementioned period. It is further structured in the following way: A network device equipped with the following features.

2. The aforementioned PHY circuit is: A forward error correction (FEC) encoder is configured such that, when an idle symbol is output by the MAC layer circuit during the period, i) a portion of the circuitry of the FEC encoder is placed in the low-power mode during the period, and ii) one or more data units corresponding to the idle symbol are output. The network device according to claim 1, further comprising:

3. The FEC encoder includes a parity information calculation circuit; The FEC encoder is configured to put the parity information calculation circuit into the low-power mode during the period. The network device according to claim 2.

4. The network device according to claim 1, wherein the PHY circuit further includes a serializer / deserializer (SERDES), the SERDES configured to, in connection with the MAC layer circuit outputting an idle symbol during the period, i) put a portion of the SERDES circuit into a low-power mode during the period, and ii) generate one or more serial signals corresponding to the idle symbol.

5. The SERDES includes a plurality of serial output generators coupled to each lane of the communication link; The SERDES is configured to place a subset of the serial output generators into the low-power mode during the period when idle symbols are output by the MAC layer circuit during that period. The network device according to claim 4.

6. The PHY circuit includes an FEC encoder circuit configured to generate forward error correction (FEC) data units for transmission over the network link; The PHY circuit is configured to mark one or more FEC data units to indicate that one or more FEC data units corresponding to the period include non-packet data. The network device according to claim 1.

7. The FEC encoder circuit includes a marking circuit configured to mark each section of the one or more FEC data units corresponding to the payload position within the FEC codeword. The network device according to claim 6.

8. The FEC encoder circuit includes a marking circuit configured to mark each section of the one or more FEC data units corresponding to the position of the parity portion within the FEC codeword. The network device according to claim 6.

9. The controller is included in the MAC layer circuit. The network device according to claim 1.

10. The PHY circuit is a first PHY circuit configured to output a first signal corresponding to the MAC layer data and idle symbols; The network device further comprises a second PHY circuit coupled to the first PHY circuit via a communication link; The second PHY circuit connects the first PHY circuit to the network link in a communicative manner; The second PHY circuit is configured to: i) put a portion of the circuit of the second PHY circuit into a low-power mode during the period when the MAC layer circuit outputs an idle symbol during the period, and ii) control the second PHY circuit to output a signal corresponding to the idle symbol during the period. A network device according to any one of claims 1 to 9.

11. In the controller, the step of determining the period of time during which the media access control (MAC) layer circuit outputs data corresponding to an idle symbol, the data being output by the MAC layer circuit for transmission over a communication link; and In response to the step of determining the aforementioned period, The steps include: placing at least a portion of the PHY circuit into low-power mode during the aforementioned period, and The PHY circuit outputs a signal corresponding to the idle symbol, and this signal is for transmission via the communication link. A method for saving power in a communication network, comprising the features described above.

12. The step of placing at least a portion of the PHY circuit into the low-power mode during the aforementioned period is: During the aforementioned period, a subset of the circuitry of the forward error correction (FEC) encoder circuit is placed into the low-power mode, wherein the FEC encoder circuit is coupled to the MAC layer circuit; The method has, where the method is: The FEC encoder circuit outputs one or more FEC data units, including data corresponding to the idle symbol. The method according to claim 11, further comprising:

13. The step of placing a subset of the FEC encoder circuit into the low-power mode during the aforementioned period is: Steps to place the parity information generation circuit into the low-power mode during the aforementioned period. The method according to claim 12, including the method described in claim 12.

14. The step of placing at least a portion of the PHY circuit into the low-power mode during the aforementioned period is: During the aforementioned period, a subset of the serializer / deserializer (SERDES) circuitry is placed into the low-power mode, wherein the SERDES is coupled to the MAC layer circuitry; The method has, where the method is: The SERDES outputs one or more serial signals containing data corresponding to the idle symbol. The method according to claim 11, further comprising:

15. The SERDES includes a plurality of serial output generators coupled to each lane of the communication link; The step of placing a subset of the circuits of the SERDES into the low-power mode during the aforementioned period includes the step of placing a subset of the serial signal generators into the low-power mode. The method according to claim 14.

16. The step of placing at least a portion of the PHY circuit into the low-power mode during the aforementioned period is: Steps to place the digital signal processing circuit into the low-power mode during the aforementioned period. The method according to claim 11, comprising:

17. The PHY circuit includes an FEC encoder circuit that generates forward error correction (FEC) data units for transmission over the communication link; The method described above, in response to the step of determining the period: The PHY circuit marks one or more FEC data units to indicate that one or more FEC data units corresponding to the period include non-packet data. The method according to any one of claims 11 to 16, further comprising:

18. The step of marking one or more FEC data units is: The PHY circuit marks each section of the one or more FEC data units corresponding to the payload location within the FEC codeword. The method according to claim 17, having the following characteristics.

19. The step of marking one or more FEC data units is: The PHY circuit marks each section of the one or more FEC data units that corresponds to the location of the payload portion within the FEC codeword. The method according to claim 17, having the following characteristics.

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