Display board and method for manufacturing the same, display device

Abstract

Embodiments of this disclosure provide a display substrate, a method for manufacturing the same, and a display device. The display substrate comprises a plurality of repeating units, each repeating unit comprising a display area and a light-transmitting area, each display area comprising a plurality of subpixels, each subpixel comprising a pixel driving circuit, each pixel driving circuit comprising a first transistor, a second transistor, a third transistor, and a memory capacitor, the first electrode of the first transistor being connected to a data signal line, the second electrode of the first transistor being connected to the gate electrode of the second transistor and the first terminal of the memory capacitor, respectively, the first electrode of the second transistor being connected to a first power line, the second electrode of the second transistor being connected to the second electrode of the third transistor and the second terminal of the memory capacitor, respectively, the first electrode of the third transistor being connected to a compensation signal line, and in at least one subpixel, the gate electrode of the first transistor and the gate electrode of the third transistor being connected to the same scan signal line.

Description

Technical Field

[0001] This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on April 26, 2023, with an application number of 202310466298.4 and an invention title of "Display Substrate, Manufacturing Method Thereof, and Display Device", and its content should be understood to be incorporated into this application by reference.

[0002] This disclosure relates to the field of display technology, but is not limited thereto, and particularly relates to a display substrate, a manufacturing method thereof, and a display device.

Background Art

[0003] An organic light-emitting diode (abbreviated as OLED) is an active light-emitting display device, having advantages such as self-luminous, ultra-thin, wide viewing angle, high brightness, high contrast, low power consumption, extremely fast response speed, lightweight and thin, deformable, and flexible displayable, and is becoming a next-generation display technology with great development potential. Among them, an active matrix drive (AM) type OLED is a current drive device, using independent transistors (thin film transistors, TFTs) to control each sub-pixel, and each sub-pixel can drive light emission continuously and independently.

[0004] With the development of display technology, OLED technology is increasingly applied to transparent displays. Transparent display is an important and personalized display field in display technology, which refers to displaying an image in a transparent state, where the viewer can not only see the video in the display device, but also see the scene behind the display device, and can realize virtual reality (VR), augmented reality (AR), and 3D display functions. In a transparent display device adopting OLED technology, usually, each sub-pixel is partitioned into a display area and a light-transmitting area, and a pixel drive circuit and a light-emitting element are provided in the display area to realize image display, and the light-transmitting area realizes light transmission. [Overview of the Initiative]

[0005] The following is a brief overview of the topics described in detail in this disclosure. This overview is not intended to limit the scope of protection of the claims.

[0006] Embodiments of the present disclosure provide a display substrate comprising a plurality of regularly arranged repeating units, each repeating unit comprising a display area and a light-transmitting area located on at least one side of the display area, wherein the display area is configured to display an image, the light-transmitting area is configured to transmit light rays, the display area comprises a plurality of subpixels forming at least two pixel rows and two pixel columns, each subpixel comprises a pixel driving circuit, the pixel driving circuit comprises a first transistor, a second transistor, a third transistor and a memory capacitor, the first electrode of the first transistor is connected to a data signal line, the second electrode of the first transistor is connected to the gate electrode of the second transistor and the first end of the memory capacitor, respectively, the first electrode of the second transistor is connected to a first power line, the second electrode of the second transistor is connected to the second electrode of the third transistor and the second end of the memory capacitor, respectively, the first electrode of the third transistor is connected to a compensation signal line, and in the pixel driving circuit of at least one subpixel, the gate electrode of the first transistor and the gate electrode of the third transistor are connected to the same scan signal line.

[0007] In an exemplary embodiment, in a plurality of pixel driving circuits for at least one pixel row, the gate electrodes of a plurality of first transistors and the gate electrodes of a plurality of third transistors are connected to the same scan signal line.

[0008] In an exemplary embodiment, in a plurality of pixel driving circuits of at least one repeating unit, the gate electrodes of a plurality of first transistors and the gate electrodes of a plurality of third transistors are connected to the same scan signal line.

[0009] In an exemplary embodiment, in at least one repeating unit, the scan signal line extends from the display area to the light-transmitting area, and the scan signal line comprises a single-line segment and a double-line segment, the single-line segment being located in the light-transmitting area, the double-line segment being located in the display area, and each of the double-line segments being connected to a pixel drive circuit for a plurality of subpixels in the repeating unit.

[0010] In an exemplary embodiment, the dual-line segment comprises a first subline and a second subline extending along the pixel row direction, the first and second sublines being arranged along the pixel column direction, the first subline being connected to the pixel drive circuits of multiple subpixels in one pixel row, and the second subline being connected to the pixel drive circuits of multiple subpixels in another adjacent pixel row.

[0011] In an exemplary embodiment, the double-wire segment further comprises a first connecting wire and a second connecting wire, the first connecting wire being connected to one end of the first sub-wire and the second sub-wire, respectively, and the second connecting wire being connected to the other end of the first sub-wire and the second sub-wire, and the first connecting wire, the first sub-wire, the second connecting wire, and the second sub-wire together form a ring structure.

[0012] In an exemplary embodiment, the single-line segment is located in the direction of extension of the first sub-line or the second sub-line.

[0013] In the exemplary embodiment, the first connection line is connected to a single-line segment located in the light-transmitting region on one side of the pixel row direction of the display area, and the second connection line is connected to a single-line segment located in the light-transmitting region on the other side of the pixel row direction of the display area.

[0014] In an exemplary embodiment, in at least one repeating unit, the single-wire segment and the double-wire segment are connected to each other in an integrated structure.

[0015] In an exemplary embodiment, the orthographic projections of the first power line, the data signal line, and the compensation signal line on the plane of the display board and the orthographic projection of the annular structure on the plane of the display board overlap at least partially.

[0016] In an exemplary embodiment, in at least one repeating unit, the active layers of the third transistors of two subpixels in adjacent pixel rows are a single, interconnected structure, and the orthogonal projection of the active layer of the third transistors on the plane of the display substrate and the orthogonal projection of the annular structure on the plane of the display substrate overlap at least partially.

[0017] In an exemplary embodiment, in at least one repeating unit, a plurality of subpixels are mirror-symmetric with respect to the scan signal line.

[0018] In an exemplary embodiment, the first end of the memory capacitor comprises a first plate and a third plate, and the second end of the memory capacitor comprises a second plate, the orthographic projection of the second plate on the plane of the display substrate and the orthographic projection of the first plate on the plane of the display substrate overlap at least partially, the first plate and the second plate form a first capacitor, the orthographic projection of the second plate on the plane of the display substrate and the orthographic projection of the third plate on the plane of the display substrate overlap at least partially, the third plate and the second plate form a second capacitor, the first plate is connected to the third plate, the second electrode of the first transistor and the gate electrode of the second transistor, respectively, the second plate is connected to the second electrode of the second transistor and the second electrode of the third transistor, respectively, and the first capacitor and the second capacitor constitute a memory capacitor in a parallel connection structure.

[0019] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display area comprises a drive circuit layer installed on a base and a light-emitting structure layer installed on the side of the drive circuit layer away from the base, the drive circuit layer comprises at least a first conductive layer, a second conductive layer, and a third conductive layer installed sequentially along the direction away from the base, the first electrode plate installed on the first conductive layer, the second electrode plate installed on the second conductive layer, the third electrode plate installed on the third conductive layer, the third electrode plate connected to the first electrode plate via vias, and at least one repeating unit further comprises an electrode plate connecting electrode, the electrode plate connecting electrode installed in the light-transmitting area, and the electrode plate connecting electrode connected to the first electrode plate.

[0020] In an exemplary embodiment, in at least one repeating unit, the plate connecting electrode and the first plate are connected to each other in an integrated structure.

[0021] In an exemplary embodiment, the light-emitting structure layer comprises at least a fourth conductive layer located away from the base of the third conductive layer, the fourth conductive layer comprising at least a first anode and an anode connecting electrode, the first anode being located in a plurality of subpixels of the display area, the anode connecting electrode being located in the light-transmitting area, the anode connecting electrode being connected to the plate connecting electrode via an anode via, the anode via being located in the light-transmitting area, and in at least one subpixel, the first anode comprising a separately located first sub-anode and a second sub-anode, the first end of the anode connecting electrode being connected to the first sub-anode, and the second end of the anode connecting electrode being connected to the second sub-anode.

[0022] In an exemplary embodiment, the third conductive layer further comprises a second power line and a first auxiliary electrode, wherein the second power line is installed in the display area, the first auxiliary electrode is installed in the light-transmitting area, and the first auxiliary electrode is connected to the second power line.

[0023] In an exemplary embodiment, in at least one repeating unit, the first auxiliary electrode and the second power line are connected to each other in an integrated structure.

[0024] In an exemplary embodiment, the orthographic projection of the second power line on the plane of the display board and the orthographic projection of the annular structure of the scanning signal line on the plane of the display board overlap at least partially.

[0025] Embodiments of the present disclosure further provide a display device comprising the aforementioned display substrate.

[0026] Embodiments of the present disclosure further provide a method for manufacturing a display substrate, the display substrate comprising a plurality of regularly arranged repeating units, the repeating unit comprising a display area and a light-transmitting area located on at least one side of the display area, the display area being configured to display an image, the light-transmitting area being configured to transmit light rays, the display area comprising a plurality of subpixels forming at least two pixel rows and two pixel columns, the subpixels comprising a pixel driving circuit, and the manufacturing method is as follows: A pixel driving circuit is formed in the subpixel, and the pixel driving circuit comprises a first transistor, a second transistor, a third transistor, and a memory capacitor, wherein the first electrode of the first transistor is connected to a data signal line, the second electrode of the first transistor is connected to the gate electrode of the second transistor and the first terminal of the memory capacitor, respectively, the first electrode of the second transistor is connected to a first power line, the second electrode of the second transistor is connected to the second electrode of the third transistor and the second terminal of the memory capacitor, respectively, the first electrode of the third transistor is connected to a compensation signal line, and the gate electrode of the first transistor and the gate electrode of the third transistor are connected to the same scan signal line.

[0027] Naturally, when carrying out any of the products or methods of the present invention, it is not necessarily required to achieve all of the above advantages simultaneously. Other features and advantages of the present invention are described in the following examples of the specification and are partially revealed therefrom or understood by carrying out the invention. The objectives and other advantages of the examples of this disclosure can be realized and obtained by the structures specifically shown in the specification, claims and drawings.

[0028] After reading and understanding the accompanying drawings and the detailed description, other aspects can be understood.

Brief Description of the Drawings

[0029] The drawings are for better understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, but are not for limiting the technical solutions of the present disclosure.

[0030] [Figure 1] It is a structural schematic diagram of a display device. [Figure 2] It is a planar structural schematic diagram of a display substrate. [Figure 3] It is a layout schematic diagram of sub-pixels in a display substrate according to an exemplary embodiment of the present disclosure. [Figure 4] It is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure. [Figure 5] It is an equivalent circuit diagram of a pixel driving circuit in a display unit according to an exemplary embodiment of the present disclosure. [Figure 6] It is a structural schematic diagram of a scanning signal line according to an exemplary embodiment of the present disclosure. [Figure 7] It is a schematic diagram after the formation of the first conductive layer pattern in an embodiment of the present disclosure. [Figure 8A] It is a schematic diagram after the formation of the semiconductor layer pattern in an embodiment of the present disclosure. [Figure 8B] It is a schematic diagram after the formation of the semiconductor layer pattern in an embodiment of the present disclosure. [Figure 9A] It is a schematic diagram after the formation of the second conductive layer pattern in an embodiment of the present disclosure. [Figure 9B] It is a schematic diagram after the formation of the second conductive layer pattern in an embodiment of the present disclosure. [Figure 10] It is a schematic diagram after the formation of the third insulating layer pattern in an embodiment of the present disclosure. [Figure 11A] It is a schematic diagram after the formation of the third conductive layer pattern in an embodiment of the present disclosure. [Figure 11B] This is a schematic diagram of the embodiment of the present disclosure after the third conductive layer pattern has been formed. [Figure 12] This is a schematic diagram of the embodiment of the present disclosure after the fourth insulating layer and the first flat layer pattern have been formed. [Figure 13A] This is a schematic diagram of the embodiment of the present disclosure after the fourth conductive layer pattern has been formed. [Figure 13B] This is a schematic diagram of the embodiment of the present disclosure after the fourth conductive layer pattern has been formed. [Figure 14A] This is a schematic diagram of the embodiment of the present disclosure after the fifth conductive layer pattern has been formed. [Figure 14B] This is a schematic diagram of the embodiment of the present disclosure after the fifth conductive layer pattern has been formed. [Figure 15] This is a schematic diagram of the embodiment of the present disclosure after the pixel definition layer pattern has been formed. [Figure 16] This is a schematic diagram illustrating the repair of a short-circuit defect in a display board according to an exemplary embodiment of the present disclosure. [Modes for carrying out the invention]

[0031] To clarify the purpose, technical proposals, and merits of this disclosure, embodiments of this disclosure will be described in detail below with reference to the drawings. However, embodiments may be carried out in multiple different forms. The methods and content may be transformed into various forms without deviating from the spirit and scope of this disclosure, so as can be easily understood by those skilled in the art. Accordingly, this disclosure should not be construed as being limited only to the descriptions of the embodiments below. The embodiments and features in this disclosure can be combined in any way, as long as they do not conflict.

[0032] The proportions in the drawings in this disclosure may, but are not limited to, be used as reference in actual processes. For example, the ratio of channel width to length, the thickness and spacing of each film layer, and the width and spacing of each signal line may be adjusted according to actual requirements. The number of pixels on the display substrate and the number of subpixels in each pixel are also not limited to the quantities shown in the drawings, and the drawings described in this disclosure are schematic diagrams of the structure, and one method of this disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0033] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion regarding the constituent elements and do not limit them in terms of quantity.

[0034] In this specification, for convenience, descriptions indicating directional or positional relationships, such as "center," "top," "bottom," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to describe the positional relationships of components with reference to the drawings. However, this is merely for the sake of simplicity in describing this specification and does not express or imply that the indicated devices or elements necessarily have a specific orientation or are configured and operated in a specific orientation, and should therefore not be considered a limitation of this disclosure. The positional relationships of components may be appropriately modified depending on the direction in which each component is described. Accordingly, the terminology used in this specification is not limited and can be appropriately substituted as appropriate in the context.

[0035] In this specification, unless otherwise explicitly stated or limited, the terms “attachment” and “connection” should be understood in a broad sense. For example, this could mean being permanently connected, or detachably connected, or integrally connected; it could be a mechanical connection or an electrical connection; it could be a direct connection, an indirect connection via an intermediate member, or internal communication between two elements. Those skilled in the art will be able to understand the specific meaning of these terms in this disclosure from the specific context.

[0036] In this specification, a transistor refers to an element having at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. However, in this specification, the channel region refers to the region through which current primarily flows.

[0037] In this specification, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. When transistors with opposite polarity are used, or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" may be swapped. Therefore, in this specification, the "source electrode" and the "drain electrode" can be swapped with each other, and the "source terminal" and the "drain terminal" can be swapped with each other.

[0038] In this specification, "electrically connected" includes cases where components are connected via an element having an electrical function. The "element having an electrical function" is not particularly limited and only needs to be capable of transmitting and receiving electrical signals between the connected components. Examples of "elements having an electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and various other elements having different functions.

[0039] In this specification, "parallel" refers to a state in which the angle between two straight lines is -10° or more and 10° or less, and therefore also includes a state in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" refers to a state in which the angle between two straight lines is 80° or more and 100° or less, and therefore also includes a state in which the angle is 85° or more and 95° or less.

[0040] In this specification, "film" and "layer" can be interchanged. For example, "conductive layer" may be changed to "conductive film." Similarly, "insulating film" may be changed to "insulating layer."

[0041] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined, and may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have small deformations due to tolerances, as well as chamfers, arcs, and other deformations.

[0042] In this disclosure, "approximately" means that the limits are not strictly defined and that numerical values ​​within the error range of the process and measurement are permitted.

[0043] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the OLED display device may include a timing controller, a data driver, a scanning driver, and a pixel array. The timing controller is connected to the data driver and the scanning driver, respectively. The data driver is connected to a plurality of data signal lines (D1 to Dn), respectively. The scanning driver is connected to a plurality of scanning signal lines (S1 to Sm), respectively. The pixel array may include a plurality of sub-pixels Pxij, each sub-pixel Pxij being connected to a corresponding data signal line and a corresponding scanning signal line, where i and j are natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a display unit. The circuit unit may include at least a pixel driving circuit, each pixel driving circuit being connected to a scanning signal line and a data signal line. The display unit may include at least a light-emitting element, the light-emitting element being connected to the pixel driving circuit of the circuit unit. The sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scanning signal line and the j-th data signal line. In exemplary embodiments, the timing controller may provide the data driver with grayscale values ​​and control signals suitable for the data driver's specifications, and may also provide the scan driver with a clock signal, a scan start signal, etc., suitable for the scan driver's specifications. The data driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines 531, D2, D3, ..., and Dn. For example, the data driver may use the clock signal to sample the grayscale values ​​and then apply data voltages corresponding to the grayscale values ​​to data signal lines 531 to Dn, with n being a natural number. The scan driver may receive a clock signal, a scan start signal, etc., from the timing controller to generate scan signals to be provided to scan signal lines S1, S2, S3, ..., and Sm. For example, the scan driver may sequentially provide scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register, and the scan signal may be generated by sequentially transmitting a scan start signal, provided in the form of an on-level pulse, to the next stage circuit under the control of a clock signal, and m may be a natural number.In an exemplary embodiment, the pixel array may be mounted on a display substrate.

[0044] Figure 2 is a schematic diagram of the planar structure of a display board. As shown in Figure 2, in an exemplary embodiment, the display board may comprise a plurality of regularly arranged repeating units 100, and at least one repeating unit 100 may comprise a display area 110 and a light-transmitting area 120. The display area 110 may comprise a plurality of subpixels, and at least one subpixel may comprise a circuit unit and a light-emitting unit, the circuit unit may comprise at least a pixel driving circuit, and the light-emitting unit may comprise at least a light-emitting element, the light-emitting element of the light-emitting unit is connected to the pixel driving circuit of the corresponding circuit unit, and the display area 110 is configured to display an image. The light-transmitting area 120 may be located on at least one side of the display area 110 in the repeating unit 100, and the light-transmitting area 120 is configured to transmit light rays, thereby enabling the repeating unit 100 to display an image in a transparent state, i.e., transparent display. In an exemplary embodiment, the repeating unit is the basic unit constituting the display board, and the display board is formed by repeatedly and continuously installing them along at least one direction, that is, the display board is made up of a plurality of repeating units joined together.

[0045] Currently, existing transparent display devices have drawbacks such as low resolution and low transparency. Furthermore, transparent display devices employing OLED technology, especially large-sized transparent display devices, have high yield requirements at the pixel level and signal line defects, requiring repair of any resulting signal line defects. As revealed in research by the inventors of this application, existing repair processes can only repair signal lines at some locations, making it impossible to repair all signal lines, resulting in a low repair success rate and a decrease in the yield rate of good products.

[0046] An exemplary embodiment of the present disclosure provides a display substrate comprising a plurality of regularly arranged repeating units, each repeating unit comprising a display area and a light-transmitting area located on at least one side of the display area, wherein the display area is configured to display an image, the light-transmitting area is configured to transmit light rays, the display area comprises a plurality of subpixels forming at least two pixel rows and two pixel columns, the subpixels comprising a pixel driving circuit, the pixel driving circuit comprising a first transistor, a second transistor, a third transistor and a memory capacitor, wherein the first electrode of the first transistor is connected to a data signal line, the second electrode of the first transistor is connected to the gate electrode of the second transistor and the first end of the memory capacitor, respectively, the first electrode of the second transistor is connected to a first power line, the second electrode of the second transistor is connected to the second electrode of the third transistor and the second end of the memory capacitor, respectively, the first electrode of the third transistor is connected to a compensation signal line, and in the pixel driving circuit of at least one subpixel, the gate electrode of the first transistor and the gate electrode of the third transistor are connected to the same scan signal line.

[0047] In an exemplary embodiment, in a plurality of pixel driving circuits for at least one pixel row, the gate electrodes of a plurality of first transistors and the gate electrodes of a plurality of third transistors are connected to the same scan signal line.

[0048] In an exemplary embodiment, in a plurality of pixel driving circuits of at least one repeating unit, the gate electrodes of a plurality of first transistors and the gate electrodes of a plurality of third transistors are connected to the same scan signal line.

[0049] In an exemplary embodiment, in at least one repeating unit, the scan signal line extends from the display area to the light-transmitting area, and the scan signal line comprises a single-line segment and a double-line segment, the single-line segment being located in the light-transmitting area, the double-line segment being located in the display area, and each of the double-line segments being connected to a pixel drive circuit for a plurality of subpixels in the repeating unit.

[0050] In an exemplary embodiment, in at least one repeating unit, a plurality of subpixels are mirror-symmetric with respect to the scan signal line.

[0051] The display substrate according to this disclosure will be described below with reference to several exemplary embodiments.

[0052] In exemplary embodiments, the display substrate may comprise a plurality of regularly arranged repeating units in a direction parallel to the display substrate, and at least one repeating unit may comprise a display area 110 and a light-transmitting area 120, the display area 110 being configured to realize image display, and the light-transmitting area 120 being configured to realize light transmission, thereby realizing transparent display. In a direction perpendicular to the display substrate, the display substrate may comprise at least a drive circuit layer installed on the base and a light-emitting structure layer installed on the side of the drive circuit layer away from the base, and in at least one repeating unit, the drive circuit layer of the display area 110 may comprise a plurality of circuit units, the light-emitting structure layer of the display area 110 may comprise a plurality of light-emitting units, the circuit units may comprise at least a pixel drive circuit, the light-emitting units may comprise at least a light-emitting element, and the light-emitting element is connected to the pixel drive circuit of the corresponding circuit unit.

[0053] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to a pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to a light-emitting element. In exemplary embodiments, the orthographic projection position on the base of the light-emitting unit may correspond to the orthographic projection position on the base of the circuit unit, or the orthographic projection position on the base of the light-emitting unit may not correspond to the orthographic projection position on the base of the circuit unit.

[0054] In exemplary embodiments of this disclosure, the orthographic projection position of the circuit unit on its base corresponds one-to-one with the orthographic projection position of the light-emitting unit on its base, the circuit unit and the light-emitting unit constitute a subpixel, and therefore in the following description, the circuit unit and the light-emitting unit are collectively referred to as a subpixel.

[0055] Figure 3 is a schematic diagram of the arrangement of subpixels in a display substrate according to an exemplary embodiment of the present disclosure, showing the structure of a repeating unit. As shown in Figure 3, the repeating unit may comprise a display area 110 and a light-transmitting area 120, and the display area 110 may be located on one side of the light-transmitting area 120 in a first direction X. In the exemplary embodiment, the display area 110 may comprise four subpixels, namely a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4, which are arranged in a square configuration, effectively increasing the aperture ratio and the light-transmitting area.

[0056] In an exemplary embodiment, the second subpixel P2 may be located on one side of the first subpixel P1 in the first direction X, the third subpixel P3 may be located on one side of the first subpixel P1 in the second direction Y, the fourth subpixel P4 may be located on one side of the third subpixel P3 in the first direction X, a plurality of subpixels sequentially located along the first direction X may be called a pixel row, a plurality of subpixels sequentially located along the second direction Y may be called a pixel column, and the first direction X intersects with the second direction Y.

[0057] In exemplary embodiments, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, the third subpixel P3 may be a white subpixel (W) emitting white light, and the fourth subpixel P4 may be a green subpixel (G) emitting green light. In some possible embodiments, the RGBW arrangement can be adjusted according to actual needs and is not specifically limited herein.

[0058] In exemplary embodiments, each subpixel may comprise a circuit unit and a light-emitting unit located on the side away from the base of the circuit unit, the circuit unit may comprise at least a pixel driving circuit, and the light-emitting unit may comprise at least a light-emitting element, the light-emitting element of the light-emitting unit being connected to the pixel driving circuit of the corresponding circuit unit.

[0059] Figure 4 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure, showing the structure of a pixel driving circuit in a repeating unit. As shown in Figure 4, the repeating unit may include a display area 110 and a light-transmitting area 120, and the display area 110 may include a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4 arranged in a square manner, and at least one subpixel may include a pixel driving circuit and a light-emitting element.

[0060] In an exemplary embodiment, at least one repeating unit may include one scan signal line 31, one first power line 51, one second power line 52, four data signal lines 53, and one compensation signal line 54. In an exemplary embodiment, the scan signal line 31 may be located in the display area 110 and the light-transmitting area 120, and the first power line 51, the second power line 52, the data signal line 53, and the compensation signal line 54 may be located in the display area 110.

[0061] In an exemplary embodiment, at least one pixel driving circuit comprises at least a first transistor T1 as a data writing transistor, a second transistor T2 as a driving transistor, a third transistor T3 as a sensing transistor, and a storage capacitor C.

[0062] In the exemplary embodiment, in at least one subpixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 31.

[0063] In the exemplary embodiment, in at least one pixel row, the gate electrodes of two first transistors T1 and the gate electrodes of two third transistors T3 are connected to the same scan signal line 31.

[0064] In an exemplary embodiment, in at least one repeating unit, the gate electrodes of four first transistors T1 and the gate electrodes of four third transistors T3 are connected to the same scan signal line 31.

[0065] In exemplary embodiments, the shape of the scan signal line 31 may be a linear shape in which the main body portion extends along a first direction X, the scan signal line 31 may be located in the middle region of the repeating unit in a second direction Y, and the multiple subpixels in the repeating unit may be mirror-symmetric with respect to the scan signal line 31.

[0066] In exemplary embodiments, the shapes of the first power line 51, the second power line 52, the data signal line 53, and the compensation signal line 54 may be linear in shape with the main body portion extending along the second direction Y, and one first power line 51, two data signal lines 53, one compensation signal line 54, two data signal lines 53, and one second power line 52 may be installed sequentially along the first direction X. In at least one repeating unit, the first power line 51 may be located on one side of the display area 110 in the first direction X, the second power line 52 may be located on the other side of the display area 110 in the first direction X, the compensation signal line 54 may be located between the first power line 51 and the second power line 52, two of the four data signal lines 53 may be located between the first power line 51 and the compensation signal line 54, and the other two of the four data signal lines 53 may be located between the second power line 52 and the compensation signal line 54.

[0067] In the exemplary embodiment, the positions of the first power line 51 and the second power line 52 may be basically mirror-symmetric with respect to the compensation signal line 54, and the two data signal lines 53 located on one side of the first direction X opposite to the compensation signal line 54 may be basically mirror-symmetric with respect to the compensation signal line 54.

[0068] In an exemplary embodiment, one scan signal line 31 can define two adjacent pixel rows, where one side of the scan signal line 31 in the opposite direction of the second direction Y is the first pixel row, and the other side of the scan signal line 31 in the second direction Y is the second pixel row. The first power line 51, the compensation signal line 54, and the second power line 52 can define two pixel rows, where the first power line 51 and the compensation signal line 54 can define the first pixel row, and the second power line 52 and the compensation signal line 54 can define the second pixel row. Thus, four subpixels are defined by the scan signal line 31, the first power line 51, the second power line 52, and the compensation signal line 54.

[0069] In an exemplary embodiment, a subpixel located in the first pixel row and first pixel column (upper left side of the display unit) may be referred to as the first subpixel P1, a subpixel located in the first pixel row and second pixel column (upper right side of the display unit) may be referred to as the second subpixel P2, a subpixel located in the second pixel row and first pixel column (lower left side of the display unit) may be referred to as the third subpixel P3, and a subpixel located in the second pixel row and second pixel column (lower right side of the display unit) may be referred to as the fourth subpixel P4.

[0070] In an exemplary embodiment, the pixel driving circuit structure in the first pixel row and the pixel driving circuit structure in the second pixel row may be basically mirror-symmetric with respect to the compensation signal line 54. That is, the pixel driving circuit structure of the first sub-pixel P1 and the pixel driving circuit structure of the second sub-pixel P2 may be basically mirror-symmetric with respect to the compensation signal line 54, and the pixel driving circuit structure of the third sub-pixel P3 and the pixel driving circuit structure of the fourth sub-pixel P4 may be basically mirror-symmetric with respect to the compensation signal line 54.

[0071] Figure 5 is an equivalent circuit diagram of a pixel driving circuit in a display unit according to an exemplary embodiment of the present disclosure. As shown in Figure 5, at least one display unit may have four pixel driving circuits, the four pixel driving circuits may be arranged in a square configuration, and the pixel driving circuits may have a 3T1C structure.

[0072] In an exemplary embodiment, at least one pixel driving circuit may comprise three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and one memory capacitor C, and the pixel driving circuit is connected to the scan signal line 31, the first power line 51, the data signal line 53, and the compensation signal line 54, respectively.

[0073] In an exemplary embodiment, the pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first terminal of the memory capacitor C, respectively, while the second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second terminal of the memory capacitor C, respectively.

[0074] In an exemplary embodiment, the first end of the memory capacitor C is connected to the first node N1, the second end of the memory capacitor C is connected to the second node N2, and the memory capacitor C is used to store the potential of the gate electrode of the second transistor T2.

[0075] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the scan signal line 31, the first electrode of the first transistor T1 is connected to the data signal line 53, and the second electrode of the first transistor T1 is connected to the first node N1. When a conduction signal is applied to the scan signal line 31, the first transistor T1 inputs the data signal from the data signal line 53 to the gate electrode of the second transistor T2.

[0076] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the first node N1, the first electrode of the second transistor T2 is connected to the first power line 51, and the second electrode of the second transistor T2 is connected to the second node N2. The second transistor T2 generates a corresponding current at its second electrode under the control of the data signal received by its gate electrode.

[0077] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the scan signal line 31, the first electrode of the third transistor T3 is connected to the compensation signal line 54, and the second electrode of the third transistor T3 is connected to the second node N2. When a conduction signal is applied to the scan signal line 31, the third transistor T3 extracts the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing, thereby compensating for the threshold voltage Vth.

[0078] In the exemplary embodiment, in the pixel driving circuit for at least one subpixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 31.

[0079] In the exemplary embodiment, in two pixel driving circuits for at least one pixel row, the gate electrodes of two first transistors T1 and the gate electrodes of two third transistors T3 are connected to the same scan signal line 31.

[0080] In an exemplary embodiment, in four pixel driving circuits of at least one repeating unit, the gate electrodes of four first transistors T1 and the gate electrodes of four third transistors T3 are connected to the same scan signal line 31.

[0081] In exemplary embodiments, the light-emitting element EL may be an OLED in which a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) are stacked, or it may be a QLED in which a first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode) are stacked. The first electrode of the light-emitting element EL is connected to the second node N2, and the second electrode of the light-emitting element EL is connected to the second power line 52, and the light-emitting element EL emits light of a corresponding brightness in response to the current of the second electrode of the second transistor T2.

[0082] In an exemplary embodiment, the signal on the first power line 51 is a continuously supplied high-level signal, and the signal on the second power line 52 is a continuously supplied low-level signal.

[0083] In exemplary embodiments, the first to third transistors T1 to T3 may be P-type transistors or N-type transistors. By employing the same type of transistors in the pixel driving circuit, the process flow can be simplified, the difficulty of the display panel process can be reduced, and the product yield can be increased. In some possible implementations, the first to third transistors T1 to T3 may include both P-type and N-type transistors.

[0084] In exemplary embodiments, the first to third transistors T1 to T3 may be low-temperature polysilicon thin-film transistors, oxide thin-film transistors, or a combination of low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (abbreviated as LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor. Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. By integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors onto a single display substrate, i.e., an LTPS+Oxide (abbreviated as LTPO) display substrate, the advantages of both can be utilized, enabling low-frequency driving, reducing power consumption, and improving display properties.

[0085] As shown in Figures 4 and 5, in exemplary embodiments, the shape of the scanning signal line 31 may be a linear shape in which the main body portion extends along the first direction X, and the scanning signal line 31 may be installed in the display area 110 and the light-transmitting area 120. In the first direction X, the scanning signal line 31 may extend from the display area 110 to the light-transmitting area 120, or the scanning signal line 31 may extend from the light-transmitting area 120 to the display area 110. In the second direction Y, the scanning signal line 31 is located in the central region of the repeating unit in the second direction Y, between the first subpixel P1 and the third subpixel P3, and may also be located between the second subpixel P2 and the fourth subpixel P4. With respect to the scanning signal line 31, the multiple subpixels in the repeating unit are mirror-symmetric with respect to the scanning signal line 31; that is, the first subpixel P1 and the third subpixel P3 may be basically mirror-symmetric with respect to the scanning signal line 31, and the second subpixel P2 and the fourth subpixel P4 may be basically mirror-symmetric with respect to the scanning signal line 31.

[0086] Figure 6 is a schematic diagram of the structure of a scanning signal line according to an exemplary embodiment of the present disclosure. As shown in Figure 6, in the exemplary embodiment, the scanning signal line 31 may comprise a double-line segment 31-1 with a double-line structure and a single-line segment 31-2 with a single-line structure, the double-line segment 31-1 may be located in the display area 110 and the single-line segment 31-2 may be located in the light-transmitting area 120, that is, two signal lines are installed in the display area 110, and these two signal lines are each connected to the pixel driving circuits of a plurality of subpixels in the repeating unit, while only one signal line is installed in the light-transmitting area 120.

[0087] In an exemplary embodiment, the dual-line segment 31-1 of the display area 110 may include a first sub-line 31a and a second sub-line 31b extending along a first direction X (pixel row direction), the first sub-line 31a and the second sub-line 31b being arranged along a second direction Y (pixel column direction), and the second sub-line 31b being located on one side of the first sub-line 31a in the second direction Y. The first sub-line 31a may be connected to the pixel drive circuits of two sub-pixels in a first pixel row, and the second sub-line 31b may be connected to the pixel drive circuits of two sub-pixels in a second pixel row, thereby realizing the connection between the dual-line segment 31-1 and multiple pixel drive circuits in a repeating unit.

[0088] In an exemplary embodiment, the first sub-wire 31a is connected to the gate electrodes of the first transistor T1 and the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2, respectively, and the second sub-wire 31b is connected to the gate electrodes of the first transistor T1 and the third transistor T3 in the third sub-pixel P3 and the fourth sub-pixel P4, respectively, so that the dual-wire segment 31-1 can control the conduction or disconnection of the multiple first transistors T1 and third transistors T3 in the repeating unit.

[0089] In an exemplary embodiment, the double-line segment 31-1 of the display area 110 may further include a first connecting line 31c and a second connecting line 31d, the first connecting line 31 may be connected to the ends of the first sub-line 31a and the second sub-line 31b in the opposite direction of the first direction X, and the second connecting line 31d may be connected to the ends of the first sub-line 31a and the second sub-line 31b in the first direction X, thereby connecting the first connecting line 31c, the first sub-line 31a, the second connecting line 31d, and the second sub-line 31b in sequence to form a ring structure.

[0090] In an exemplary embodiment, the single-line segment 31-2 may be located in the extension direction of the first sub-line 31a or the second sub-line 31b, the first connecting line 31c may be connected to the single-line segment 31-2 of the light-transmitting region 120 in the opposite direction to the first direction X of the display region 110, and the second connecting line 31d may be connected to the single-line segment 31-2 of the light-transmitting region 120 in the first direction X of the display region 110, and the double-line segment 31-1 and the single-line segment 31-2 constitute a continuous scanning signal line 31.

[0091] In an exemplary embodiment, in at least one repeating unit, the double-line segment 31-1 of the display area 110 and the single-line segment 31-2 of the light-transmitting area 120 may be an integrated structure connected to each other.

[0092] In an exemplary embodiment, in at least one subpixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 31, the first electrode of the first transistor T1 is connected to the data signal line 53, the second electrode of the first transistor T1 is connected to the gate electrode of the second transistor and the first terminal of the memory capacitor C, respectively, the second electrode of the second transistor T2 is connected to the first power line 51, the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3 and the second terminal of the memory capacitor C, respectively, and the first electrode of the third transistor T3 is connected to the compensation signal line 54.

[0093] In exemplary embodiments, at least one repeating unit may further include a compensation connection line 13, the compensation connection line 13 may be in the shape of a strip extending along a first direction X, may be located between a first pixel row and a second pixel row, and the extension length of the compensation connection line 13 in the first pixel row and the extension length in the second pixel row may be substantially the same, and the compensation connection line 13 in the first pixel row and the compensation connection line 13 in the second pixel row may be basically mirror-symmetric with respect to the compensation signal line 54.

[0094] In an exemplary embodiment, at the point where the compensation connection line 13 and the compensation signal line 54 overlap, the compensation signal line 54 is connected to the compensation connection line 13 via a via. The end of the compensation connection line 13 located in the first pixel row is connected to the first electrode of the third transistor T3 in the first pixel row, and the end of the compensation connection line 13 located in the second pixel row is connected to the first electrode of the third transistor T3 in the second pixel row, thereby realizing a 1-to-4 connection structure for the compensation connection line, and enabling the compensation signal to be written to each of the four pixel drive circuits in the display unit using a single compensation signal line.

[0095] In exemplary embodiments, at least one repeating unit may further comprise at least one first power supply auxiliary line 35 such that the orthographic projection of the base of the first power supply auxiliary line 35 at least partially overlaps with the orthographic projection of the base of the first power supply line 51, and the first power supply line 51 is connected to the first power supply auxiliary line 35 via vias, thereby forming a double-layer first power supply wiring structure.

[0096] In exemplary embodiments, at least one repeating unit may further comprise at least one second power supply auxiliary line 36 such that the orthographic projection of the base of the second power supply auxiliary line 36 at least partially overlaps with the orthographic projection of the base of the second power supply line 52, and the second power supply line 52 is connected to the second power supply auxiliary line 36 via vias, forming a double-layer second power supply wiring structure.

[0097] In an exemplary embodiment, the first end of the memory capacitor C may comprise a first plate and a third plate, and the second end of the memory capacitor C may comprise a second plate. The orthographic projection of the second plate on its base at least partially overlaps with the orthographic projection of the first plate on its base, and the first and second plates together form a first capacitor. The orthographic projection of the second plate on its base at least partially overlaps with the orthographic projection of the third plate on its base, and the third and second plates together form a second capacitor. The first and third plates are connected, and the first and second capacitors constitute a memory capacitor in a parallel connection structure.

[0098] In exemplary embodiments, in a direction perpendicular to the base, the display area 110 may comprise a drive circuit layer installed on the base and a light-emitting structure installed on the side of the drive circuit layer away from the base. The drive circuit layer may comprise at least a first conductive layer, a second conductive layer, and a third conductive layer sequentially installed along the direction away from the base, with a first electrode plate installed on the first conductive layer, a second electrode plate installed on the second conductive layer, and a third electrode plate installed on the third conductive layer, with the third electrode plate connected to the first electrode plate via vias. The light-emitting structure layer may comprise at least a fourth conductive layer installed on the side of the third conductive layer away from the base, a fifth conductive layer installed on the side of the fourth conductive layer away from the base, and a cathode layer installed on the side of the fifth conductive layer away from the base, with the fourth conductive layer comprising at least a first anode installed on a plurality of subpixels of the display area 110, and the fifth conductive layer comprising at least a second anode installed on a plurality of subpixels of the display area 110.

[0099] In an exemplary embodiment, in at least one repeating unit, the light-transmitting region 120 may further include at least one auxiliary cathode 80, which is connected to a second power line 52. The auxiliary cathode 80 is configured to provide a low-level signal to the cathode and at the same time reduce diffraction effects in the light-transmitting region.

[0100] The following is an illustrative explanation through the manufacturing process of a display substrate. The “patterning process” as referred to in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metallic materials, inorganic materials, or transparent conductive materials, and processes such as coating, mask exposure, and development for organic materials. For deposition, one or more of sputtering, vapor deposition, and chemical vapor deposition may be employed; for coating, one or more of spray coating, spin coating, and inkjet printing may be employed; and for etching, one or more of dry etching and wet etching may be employed; the embodiments of this disclosure are not limited. A “thin film” refers to a thin film of a single layer produced on a base material by deposition, coating, or other processes. If the “thin film” does not require a patterning process throughout the entire manufacturing process, the “thin film” may further be referred to as a “layer.” If the “thin film” requires a patterning process throughout the entire manufacturing process, it is referred to as a “thin film” before the patterning process and as a “layer” after the patterning process. A “layer” after the patterning process contains at least one “pattern.” As used in this disclosure, “A and B are placed in the same layer” means that A and B are formed simultaneously by the same patterning process, and the “thickness” of the film layer is the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” or “the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B is within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A and the boundary of the orthographic projection of B overlap.

[0101] In an exemplary embodiment, taking four subpixels (first subpixel P1, second subpixel P2, third subpixel P3, and fourth subpixel P4) of one repeating unit as an example, the manufacturing process of the display substrate according to the exemplary embodiment of the present disclosure may include the following operations:

[0102] (1) Form a first conductive layer pattern. In an exemplary embodiment, as shown in Figure 7, forming a first conductive layer pattern includes depositing a first conductive thin film on a base and patterning the first conductive thin film by a patterning process to form a first conductive layer pattern on the base. In an exemplary embodiment, the first conductive layer may be referred to as a light-shielding layer (SHL).

[0103] In an exemplary embodiment, the first conductive layer of each subpixel on the display substrate may include at least a first electrode plate 11 and an electrode plate connecting electrode 12.

[0104] In the exemplary embodiment, the shape of the first electrode plate 11 may be rectangular, the corners of the rectangular shape may be chamfered, the first electrode plate 11 may be one of the electrodes of a memory capacitor, and the first electrode plate 11 is configured to form a first capacitor with a second electrode plate that is formed subsequently.

[0105] In an exemplary embodiment, the first electrode plate 11 is further configured to shield the second transistor from light, thereby reducing the light intensity irradiated onto the second transistor, reducing the leakage current of the second transistor, and thereby reducing the effect of light irradiation on the characteristics of the second transistor.

[0106] In an exemplary embodiment, the shape of the electrode plate connecting electrode 12 may be a strip with a main body portion extending along a first direction X, the first end of the electrode plate connecting electrode 12 is connected to the first electrode plate 11, the second end of the electrode plate connecting electrode 12 extends toward an adjacent light-transmitting region 120 in a direction away from the first electrode plate 11, and the electrode plate connecting electrode 12 is connected to a subsequently formed sixth connecting electrode, and is connected to the anode connecting electrode via the sixth connecting electrode.

[0107] In an exemplary embodiment, the second end of the plate connection electrode 12 may form a rectangular anode connection block 12-1, so that the entire plate connection electrode 12 is "T" shaped, and the anode connection block 12-1 is located in the light-transmitting region 120. The connection block 12-1 is configured to accommodate a subsequently formed 11th via, so that a subsequently formed 6th connection electrode is connected to the plate connection electrode 12 via the via.

[0108] In exemplary embodiments, the electrode plate connecting electrode 12 in the first subpixel P1 may be located on one side of the first electrode plate 11 in the subpixel in the direction opposite to the first direction X, and the first electrode plate 11 and the electrode plate connecting electrode 12 in the first subpixel P1 may be an integrated structure connected to each other. The electrode plate connecting electrode 12 in the second subpixel P2 may be located on one side of the first electrode plate 11 in the subpixel in the direction opposite to the first direction X, and the first electrode plate 11 and the electrode plate connecting electrode 12 in the second subpixel P2 may be an integrated structure connected to each other. The electrode plate connecting electrode 12 in the third subpixel P3 may be located on one side of the first electrode plate 11 in the subpixel in the direction opposite to the first direction X, and the first electrode plate 11 and the electrode plate connecting electrode 12 in the third subpixel P3 may be an integrated structure connected to each other. The electrode plate connecting electrode 12 in the fourth subpixel P4 may be located on one side of the first electrode plate 11 in the first direction X of the subpixel, and the first electrode plate 11 and the electrode plate connecting electrode 12 in the fourth subpixel P4 may be an integrated structure connected to each other.

[0109] In exemplary embodiments, the first conductive layer in at least one repeating unit may further comprise a compensation connection line 13. The shape of the compensation connection line 13 may be a strip with its main body extending along a first direction X, and in the first direction X, the compensation connection line 13 may span a first pixel row and a second pixel row, and in the second direction Y, the compensation connection line 13 may be placed between a first pixel row and a second pixel row, and the compensation connection line 13 is configured to be connected on the one hand to a subsequently formed compensation signal line, realizing a 1:4 connection structure of compensation signal lines in one repeating unit, and on the other hand to a first region of the third active layer in each subpixel via subsequently formed connection electrodes, thereby enabling the compensation signal line to provide a compensation signal to the third transistor in each subpixel.

[0110] In exemplary embodiments, the first conductive layer pattern in the first subpixel P1 and the first conductive layer pattern in the third subpixel P3 may be basically mirror-symmetric with respect to a horizontal reference line, and the first conductive layer pattern in the second subpixel P2 and the first conductive layer pattern in the fourth subpixel P4 may be basically mirror-symmetric with respect to a horizontal reference line. The first conductive layer pattern in the first subpixel P1 and the first conductive layer pattern in the second subpixel P2 may be basically mirror-symmetric with respect to a vertical reference line, and the first conductive layer pattern in the third subpixel P3 and the first conductive layer pattern in the fourth subpixel P4 may be basically mirror-symmetric with respect to a vertical reference line. The horizontal reference line may be a straight line extending along a first direction X and bisecting the display area 110 in a second direction Y, and the vertical reference line may be a straight line extending along a second direction Y and bisecting the display area 110 in a first direction X.

[0111] After this patterning process, the first electrode plate 11, the electrode plate connecting electrode 12, and the compensation connecting line 13 are formed in the display area 110, and there is no corresponding film layer in the light-transmitting area 120.

[0112] (2) Forming a semiconductor layer pattern. In exemplary embodiments, as shown in Figures 8A and 8B, forming a semiconductor layer pattern may include sequentially depositing a first insulating thin film and a semiconductor thin film on a base on which the aforementioned pattern has been formed, and then patterning the semiconductor thin film by a patterning process to form a first insulating layer covering the first conductive layer and a semiconductor layer placed on the first insulating layer. Figure 8B is a schematic diagram of the semiconductor layer in Figure 8A.

[0113] In an exemplary embodiment, the semiconductor layer of each subpixel on the display substrate may comprise at least a first active layer 21, a second active layer 22, and a third active layer 23, where the first active layer 21 is the active layer of the first transistor T1, the second active layer 22 is the active layer of the second transistor T2, and the third active layer 23 is the active layer of the third transistor T3.

[0114] In exemplary embodiments, the first active layer 21 and the third active layer 23 of the first subpixel P1 and the second subpixel P2 may be installed on one side of the first electrode plate 11 of the subpixel in the second direction Y, and the second active layer 22 may be installed in the edge region of the first electrode plate 11 of the subpixel away from the first active layer 21 and the third active layer 23, such that the orthographic projection of the base of the second active layer 22 lies within the range of the orthographic projection of the base of the first electrode plate 11 of the subpixel, thereby allowing the first electrode plate 11 as a shielding layer to shield the channel region of the second transistor T2, avoiding the influence of light rays on the channel and ensuring the electrical performance of the second transistor T2. The third active layer 23 of the first subpixel P1 may be installed on one side of the first active layer 21 of the subpixel in the first direction X, and the third active layer 23 of the second subpixel P2 may be installed on one side of the first active layer 21 of the subpixel in the opposite direction X.

[0115] In exemplary embodiments, for the third subpixel P3 and the fourth subpixel P4, the first active layer 21 and the third active layer 23 may be installed on one side of the first electrode plate 11 of the subpixel opposite to the second direction Y, and the second active layer 22 may be installed in the edge region of the first electrode plate 11 of the subpixel away from the first active layer 21 and the third active layer 23, such that the orthographic projection of the base of the second active layer 22 lies within the range of the orthographic projection of the base of the first electrode plate 11 of the subpixel, thereby allowing the first electrode plate 11 as a shielding layer to shield the channel region of the second transistor T2, avoiding the influence of light rays on the channel and ensuring the electrical performance of the second transistor T2. The third active layer 23 of the third subpixel P3 may be installed on one side of the first active layer 21 of the subpixel opposite to the first direction X, and the third active layer 23 of the fourth subpixel P4 may be installed on one side of the first active layer 21 of the subpixel in the first direction X.

[0116] In exemplary embodiments, the third active layer 23 of the first subpixel P1 and the third active layer 23 of the third subpixel P3 may be a connected integrated structure, and the third active layer 23 of the second subpixel P2 and the third active layer 23 of the fourth subpixel P4 may be a connected integrated structure, that is, the third active layers 23 of two subpixels in adjacent pixel rows are a connected integrated structure. In this disclosure, by providing a shared source electrode for the second transistor of two adjacent subpixels in one pixel row, not only is space saved, but via connections are reduced and the manufacturing process is simplified.

[0117] In exemplary embodiments, the first active layer 21 and the third active layer 23 may be "I" shaped, the second active layer 22 may be rectangular, the corners of the rectangular shape may be chamfered, and the sides of the rectangular shape may be grooved.

[0118] In an exemplary embodiment, the active layer of each transistor may comprise a first region, a second region, and a channel region located between the first and second regions.

[0119] In exemplary embodiments, the orthographic projection of the base of the first active layer 21 does not overlap with the orthographic projection of the base of the first electrode plate 11, and the orthographic projection of the base of the third active layer 23 does not overlap with the orthographic projection of the base of the first electrode plate 11. In this disclosure, by positioning the first active layer 21 and the first electrode plate 11 so that there are no overlapping regions, and the third active layer 23 and the first electrode plate 11, it is advantageous to design the channel width ratio of the first and third transistors according to relevant needs.

[0120] In exemplary embodiments, the first active layer 21 and the third active layer 23 in the first subpixel P1 and the first active layer 21 and the third active layer 23 in the third subpixel P3 may be basically mirror-symmetric with respect to a vertical reference line, and the first active layer 21 and the third active layer 23 in the second subpixel P2 and the first active layer 21 and the third active layer 23 in the fourth subpixel P4 may be basically mirror-symmetric with respect to a vertical reference line.

[0121] In an exemplary embodiment, the semiconductor layer may be made of a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, and the like. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0122] In an exemplary embodiment, after the patterning process described above, the semiconductor layer pattern is formed in the display region 110, and the film layer in the light-transmitting region 120 comprises a first insulating layer.

[0123] (3) Forming a second conductive layer pattern. In exemplary embodiments, as shown in Figures 9A and 9B, forming a second conductive layer pattern may include sequentially depositing a second insulating thin film and a second conductive thin film on a base on which the aforementioned pattern has been formed, and then patterning the second conductive thin film by a patterning process to form a second insulating layer covering the semiconductor layer and a second conductive layer pattern placed on the second insulating layer. Figure 9B is a schematic diagram of the second conductive layer in Figure 9A.

[0124] In exemplary embodiments, the second conductive layer in at least one repeating unit may comprise at least one scanning signal line 31. The shape of the scanning signal line 31 may be a linear shape extending along a first direction X, or it may be located in the middle of the repeating unit in the second direction Y, i.e., between the first subpixels P1 and P2 and the third subpixels P3 and P4. The region where the scanning signal line 31 overlaps with the plurality of first active layers may serve as the gate electrode of the plurality of first transistors T1, and the region where the scanning signal line 31 overlaps with the plurality of third active layers may serve as the gate electrode of the plurality of third transistors T3.

[0125] In an exemplary embodiment, the scanning signal line 31 may comprise a double-line segment 31-1 and a single-line segment 31-2, the double-line segment 31-1 may be located in the display area 110, and the single-line segment 31-2 may be located in the light-transmitting area 120, that is, two signal lines are installed in the display area 110, while only one signal line is installed in the light-transmitting area 120.

[0126] In an exemplary embodiment, the dual-line segment 31-1 of the display area 110 may include a first sub-line 31a and a second sub-line 31b extending along a first direction X, the first sub-line 31a and the second sub-line 31b being arranged along a second direction Y, and the second sub-line 31b being located on one side of the first sub-line 31a in the second direction Y. The first sub-line 31a may be connected to the pixel drive circuits of two sub-pixels in a first pixel row, and the second sub-line 31b may be connected to the pixel drive circuits of two sub-pixels in a second pixel row, thereby realizing the connection between the dual-line segment 31-1 and multiple pixel drive circuits in a repeating unit.

[0127] In an exemplary embodiment, the orthographic projection of the first sub-line 31a on the base at least partially overlaps with the orthographic projections of the first active layer 21 and the third active layer 23 on the base in the first sub-pixel P1 and the second sub-pixel P2, respectively, and the overlapping region becomes the gate electrode of the first transistor T1 and the third transistor T3, respectively. That is, the first sub-line 31a is simultaneously connected to the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2. The orthographic projection of the second subline 31b at the base at least partially overlaps with the orthographic projections of the first active layer 21 and the third active layer 23 at the base of the third subpixel P3 and the fourth subpixel P4, respectively, and the overlapping region becomes the gate electrode of the first transistor T1 and the third transistor T3, respectively. That is, the second subline 31b is simultaneously connected to the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 at the third subpixel P3 and the fourth subpixel P4, respectively, so that the dual-line segment 31-1 transmitting the same scanning signal simultaneously controls the conduction or disconnection of all first transistors T1 and all third transistors T3 at the four subpixels of the repeating unit.

[0128] In an exemplary embodiment, the double-line segment 31-1 of the display area 110 may further include a first connecting line 31c and a second connecting line 31d, the first connecting line 31 may be connected to the ends of the first sub-line 31a and the second sub-line 31b in the opposite direction of the first direction X, and the second connecting line 31d may be connected to the ends of the first sub-line 31a and the second sub-line 31b in the first direction X, thereby connecting the first connecting line 31c, the first sub-line 31a, the second connecting line 31d, and the second sub-line 31b in sequence to form a ring structure. In an exemplary embodiment, the ring may be a rectangular ring or a polygonal ring.

[0129] In an exemplary embodiment, the single-line segment 31-2 may be located in the extension direction of the first sub-line 31a or the second sub-line 31b, the first connecting line 31c may be connected to the single-line segment 31-2 of the light-transmitting region 120 in the opposite direction to the first direction X of the display region 110, and the second connecting line 31d may be connected to the single-line segment 31-2 of the light-transmitting region 120 in the first direction X of the display region 110, and the double-line segment 31-1 and the single-line segment 31-2 constitute a continuous scan signal line 31. Therefore, the double-line segment 31-1 of the display region 110 and the single-line segment 31-2 of the light-transmitting region 120 constitute a continuous scan signal line 31.

[0130] In an exemplary embodiment, for a plurality of repeating units sequentially installed in a first direction X, the twin-wire segment 31-1 and the single-wire segment 31-2 in each repeating unit may be an integrated structure connected to each other, and the plurality of twin-wire segments 31-1 and the plurality of single-wire segments 31-2 in the plurality of repeating units may also be an integrated structure connected to each other.

[0131] In an exemplary embodiment, in at least one repeating unit, the orthogonal projection on the base of the integrated third active layer in two subpixels of adjacent pixel rows and the orthogonal projection on the base of the annular structure of the scan signal line 31 overlap at least partially.

[0132] In an exemplary embodiment, in at least one repeating unit, the orthographic projection at the base of the compensating connection line 13 may be located within the range of the orthographic projection at the base of the region enclosed by the annular structure of the scanning signal line 31.

[0133] In an exemplary embodiment, the second conductive layer of each subpixel on the display substrate may include at least a second electrode plate 32, a second gate electrode 33, and a power supply connection electrode 34.

[0134] In exemplary embodiments, the shape of the second electrode plate 32 may be rectangular, the corners of the rectangular plate may be chamfered, the second electrode plate 32 may be positioned close to the scanning signal line 31 of the subpixel, the orthographic projection of the base of the second electrode plate 32 at least partially overlaps with the orthographic projection of the base of the first electrode plate 11, the second electrode plate 32 may also serve as an intermediate electrode plate of a memory capacitor, and the first electrode plate 11 and the second electrode plate 32 form a first capacitor.

[0135] In an exemplary embodiment, an opening may be provided on the side of the second electrode plate 32 away from the third active layer, and the opening is configured to accommodate a subsequently formed seventh via, thereby connecting the subsequently formed third electrode plate to the first electrode plate 11 via the via.

[0136] In an exemplary embodiment, the second gate electrode 33 may be a strip extending along a second direction Y, and may be located on the side of the second electrode plate 32 of the subpixel away from the scan signal line 31, the first end of the second gate electrode 33 is connected to the second electrode plate 32 of the subpixel, the second end of the second gate electrode 33 extends away from the scan signal line 31, and the orthographic projection of the second gate electrode 33 on the base at least partially overlaps with the orthographic projection of the second active layer 22 on the base, and the second gate electrode 33 serves as the gate electrode of the second transistor T2.

[0137] In an exemplary embodiment, the second electrode plate 32 and the second gate electrode 33 may be an integrated structure connected to each other.

[0138] In exemplary embodiments, the power supply connection electrode 34 may be rectangular in shape and may be located on the side of the second gate electrode 33 of the subpixel away from the scan signal line 31, and the power supply connection electrode 34 is configured to be connected to the first electrode of the second transistor T2 via a second connection electrode formed subsequently.

[0139] In exemplary embodiments, the second conductive layer in at least one repeating unit may further include a first power supply auxiliary line 35, a second power supply auxiliary line 36, a power supply connection line 37, and an electrode connection line 38.

[0140] In exemplary embodiments, the first power supply auxiliary line 35 may be in the shape of a strip extending along the second direction Y, and may be installed on the first sub-pixel P1 and the third sub-pixel P3, respectively, and may be located on one side of the second electrode plate 32 in the direction opposite to the first direction X, and the first power supply auxiliary line 35 is configured to be connected to the subsequently formed first power supply line to form a double-layer wiring structure with the first power supply line. In exemplary embodiments, there may be a plurality of first power supply auxiliary lines 35, and the plurality of first power supply auxiliary lines 35 may be installed at intervals along the second direction Y.

[0141] In exemplary embodiments, the second power supply auxiliary line 36 may be in the shape of a strip extending along the second direction Y, and may be installed on the second sub-pixel P2 and the fourth sub-pixel P4, respectively, and located on one side of the second electrode plate 32 in the first direction X, and the second power supply auxiliary line 36 is configured to be connected to the second power supply line that is formed subsequently to form a double-layer wiring structure with the second power supply line. In exemplary embodiments, there may be a plurality of second power supply auxiliary lines 36, and the plurality of second power supply auxiliary lines 36 may be installed at intervals along the second direction Y.

[0142] In an exemplary embodiment, the power connection line 37 may be in the shape of a strip extending along a first direction X, and may be installed on the first subpixel P1 and the third subpixel P3, respectively, and may be located on the side away from the scanning signal line 31 of the second gate electrode 33 of the subpixel. The first end of the power connection line 37 is connected to the first power auxiliary line 35, and the second end of the power connection line 37 extends along the first direction X and is then connected to the power connection electrodes 34 in the first subpixel P1 and the third subpixel P3, respectively, thereby enabling the transmission of the first power signal to the power connection electrodes 34 in the first subpixel P1 and the third subpixel P3.

[0143] In an exemplary embodiment, the electrode connection line 38 may be in the shape of a strip extending along a first direction X, and may be located between power connection electrodes 34 of adjacent subpixels in the first direction X. Both terminals of the electrode connection line 38 in the first pixel row are connected to the power connection electrodes 34 of the first subpixel P1 and the second subpixel P2, respectively, and both terminals of the electrode connection line 38 in the second pixel row are connected to the power connection electrodes 34 of the third subpixel P3 and the fourth subpixel P4, respectively, thereby enabling the transmission of the first power signal to the power connection electrodes 34 of the second subpixel P2 and the fourth subpixel P4.

[0144] In an exemplary embodiment, the power supply connection line 37 and the electrode connection line 38 are configured to realize a one-to-four connection structure for the first power supply line in one repeating unit.

[0145] In exemplary embodiments, the two power supply connection electrodes 34, at least one first power supply auxiliary line 35, one power supply connection line 37, and one electrode connection line 38 in one pixel row may be an integrated structure connected to one another.

[0146] In exemplary embodiments, a strip-shaped opening (through-hole) extending along the first direction X may be provided in the middle of the electrode connection line 38, thereby forming an annular structure for the electrode connection line 38. This reduces the overlap area between the electrode connection line 38 and the subsequently formed data signal line and compensation signal line, reduces parasitic capacitance between the first power line and the data signal line, reduces parasitic capacitance between the first power line and the compensation signal line, and improves the display effect.

[0147] In exemplary embodiments, the patterns of the second electrode plate 32, the second gate electrode 33, and the power connection electrode 34 in the second conductive layer may be basically mirror-symmetric with respect to a vertical reference line between the patterns in the first subpixel P1 and the patterns in the second subpixel P2, and the patterns in the third subpixel P3 and the patterns in the fourth subpixel P4 may be basically mirror-symmetric with respect to a vertical reference line.

[0148] In exemplary embodiments, the second conductive layer pattern in the first subpixel P1 and the second conductive layer pattern in the third subpixel P3 may be basically mirror-symmetric with respect to a horizontal reference line, and the second conductive layer pattern in the second subpixel P2 and the second conductive layer pattern in the fourth subpixel P4 may be basically mirror-symmetric with respect to a horizontal reference line.

[0149] In exemplary embodiments, the double-line segment 31-1 in the second conductive layer may have a double-line segment pattern that is basically mirror-symmetric with respect to a horizontal reference line and also mirror-symmetric with respect to a vertical reference line.

[0150] In an exemplary embodiment, the present process can pattern the second conductive thin film and the second insulating thin film simultaneously, thereby resulting in the second insulating layer pattern and the second conductive layer pattern being identical.

[0151] In an exemplary embodiment, after forming a first conductive layer pattern, the semiconductor layer can be made conductive by using the first conductive layer as a shield. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor T1 to the third transistor T3, while the semiconductor layer in the region not shielded by the first conductive layer is made conductive.

[0152] In an exemplary embodiment, the scanning signal line 31 is formed in the display area 110 and the light-transmitting area 120, and the second electrode plate 32, second gate electrode 33, power supply connection electrode 34, first power supply auxiliary line 35, second power supply auxiliary line 36, power supply connection line 37, and electrode connection line 38 are formed in the display area 110, so that after the patterning process, the film layer of the light-transmitting area 120 comprises a first insulating layer and a second insulating layer, and the single-line segment of the scanning signal line is placed in the second insulating layer.

[0153] (4) Forming a third insulating layer pattern. In an exemplary embodiment, as shown in Figure 10, forming a third insulating layer pattern involves depositing a third insulating thin film on the base on which the aforementioned pattern is formed, patterning the third insulating thin film by a patterning process to form a third insulating layer pattern that covers the second conductive layer pattern, and providing a plurality of vias in the third insulating layer.

[0154] In an exemplary embodiment, the multiple vias of each subpixel on the display substrate include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, and an eleventh via V11.

[0155] In an exemplary embodiment, the orthographic projection of the first via V1 at its base lies within the range of the orthographic projection of the first region of the first active layer, the third and second insulating layers within the first via V1 are etched to expose the surface of the first region of the first active layer, and the first via V1 is configured such that a subsequently formed data signal line is connected to the first region of the first active layer through the via.

[0156] In an exemplary embodiment, the orthographic projection at the base of the first via V1 may be located within the range of the orthographic projection at the base of the region enclosed by the annular structure of the scan signal line 31.

[0157] In an exemplary embodiment, the orthographic projection of the base of the second via V2 lies within the range of the orthographic projection of the base of the second region of the first active layer, the third and second insulating layers within the second via V2 are etched to expose the surface of the second region of the first active layer, and the second via V2 is configured such that a subsequently formed first connecting electrode is connected to the second region of the first active layer via the via.

[0158] In an exemplary embodiment, the orthographic projection of the base of the third via V3 lies within the range of the orthographic projection of the base of the first region of the second active layer, the third and second insulating layers within the third via V3 are etched to expose the surface of the first region of the second active layer, and the third via V3 is configured such that a subsequently formed second connecting electrode is connected to the first region of the second active layer via the via. In an exemplary embodiment, there may be multiple third vias V3, thereby improving the reliability of the connection.

[0159] In an exemplary embodiment, the orthographic projection of the base of the fourth via V4 lies within the orthographic projection of the base of the second region of the second active layer, the third and second insulating layers within the fourth via V4 are etched to expose the surface of the second region of the second active layer, and the fourth via V4 is configured such that a subsequently formed third connecting electrode is connected to the second region of the second active layer via the via. In an exemplary embodiment, there may be multiple fourth vias V4, thereby improving the reliability of the connection.

[0160] In an exemplary embodiment, the orthographic projection of the base of the fifth via V5 lies within the range of the orthographic projection of the base of the first region of the third active layer, the third and second insulating layers within the fifth via V5 are etched to expose the surface of the first region of the third active layer, and the fifth via V5 is configured such that a subsequently formed fourth connecting electrode is connected to the first region of the third active layer via the via.

[0161] In an exemplary embodiment, the orthographic projection at the base of the fifth via V5 may be located within the range of the orthographic projection at the base of the region enclosed by the annular structure of the scan signal line 31.

[0162] In an exemplary embodiment, the orthographic projection of the sixth via V6 at its base lies within the range of the orthographic projection of the second region of the third active layer at its base, the third and second insulating layers within the sixth via V6 are etched to expose the surface of the second region of the third active layer, and the sixth via V6 is configured such that a subsequently formed fifth connecting electrode is connected to the second region of the third active layer via the via.

[0163] In an exemplary embodiment, the orthographic projection of the seventh via V7 at its base lies within the range of the orthographic projection of the first electrode plate 11 at its base, the third insulating layer, the second insulating layer, and the first insulating layer within the seventh via V7 are etched to expose the surface of the first electrode plate 11, and the seventh via V7 is configured such that a subsequently formed third electrode plate is connected to the first electrode plate 11 via the via.

[0164] In an exemplary embodiment, the orthographic projection of the eighth via V8 on its base lies within the range of the orthographic projection of the second electrode plate 32 on its base, the third insulating layer within the eighth via V8 is etched to expose the surface of the second electrode plate 32, and the eighth via V8 is configured such that a subsequently formed first connecting electrode is connected to the second electrode plate 32 via the via.

[0165] In an exemplary embodiment, the orthographic projection of the ninth via V9 at its base lies within the range of the orthographic projection of the end of the compensating connection line 13 near the third active layer, the third insulating layer, the second insulating layer, and the first insulating layer within the ninth via V9 are etched to expose the surface of the compensating connection line 13, and the ninth via V9 is configured such that a subsequently formed fourth connection electrode is connected to the compensating connection line 13 through the via.

[0166] In an exemplary embodiment, the orthographic projection at the base of via 9 V9 may be located within the range of the orthographic projection at the base of the region enclosed by the annular structure of the scan signal line 31.

[0167] In an exemplary embodiment, the orthographic projection of the base of the tenth via V10 lies within the orthographic projection of the base of the power supply connection electrode 34, the third insulating layer within the tenth via V10 is etched to expose the surface of the power supply connection electrode 34, and the tenth via V10 is configured such that a subsequently formed second connection electrode is connected to the power supply connection electrode 34 via the via.

[0168] In an exemplary embodiment, the orthographic projection of the 11th via V11 on its base lies within the orthographic projection of the connection block 12-1 on the base of the plate connection electrode 12, and the third, second, and first insulating layers within the 11th via V11 are etched to expose the surface of the connection block 12-1, and the 11th via V11 is configured such that a subsequently formed sixth connection electrode is connected to the connection block 12-1 via the via.

[0169] In an exemplary embodiment, at least one repeating unit may further comprise a 12th via V12, a 13th via V13, and a 14th via V14.

[0170] In an exemplary embodiment, the 12th via V12 may be installed between the first subpixel P1 and the third subpixel P3, the orthographic projection of the 12th via V12 at its base lies within the orthographic projection of the first power supply auxiliary line 35 at its base, the third insulating layer within the 12th via V12 is etched to expose the surface of the first power supply auxiliary line 35, and the 12th via V12 is configured such that a subsequently formed first power supply line is connected to the first power supply auxiliary line 35 through the via. In an exemplary embodiment, there may be multiple 12th vias V12, and the multiple 12th vias V12 may be installed sequentially along the second direction Y, thereby improving the reliability of the connection.

[0171] In an exemplary embodiment, the 13th via V13 may be installed on the second subpixel P2 and the fourth subpixel P4, the orthographic projection of the base of the 13th via V13 is within the range of the orthographic projection of the base of the second power supply auxiliary line 36, the third insulating layer in the 13th via V13 is etched to expose the surface of the second power supply auxiliary line 36, and the 13th via V13 is configured such that a subsequently formed second power supply line is connected to the second power supply auxiliary line 36 through the via. In an exemplary embodiment, there may be multiple 13th vias V13, and multiple 13th vias V13 may be installed sequentially along a first direction X to form a via group, and multiple via groups may be installed sequentially along a second direction Y, thereby improving the reliability of the connection.

[0172] In an exemplary embodiment, the orthographic projection of the base of the 14th via V14 lies within the range of the orthographic projection of the middle portion of the base of the compensation connection line 13, the third insulating layer, the second insulating layer, and the first insulating layer within the 14th via V14 are etched to expose the surface of the compensation connection line 13, and the 14th via V14 is configured such that a subsequently formed compensation signal line is connected to the compensation connection line 13 through the via.

[0173] In an exemplary embodiment, the orthographic projection at the base of the 14th via V14 may be located within the range of the orthographic projection at the base of the region enclosed by the annular structure of the scan signal line 31.

[0174] In an exemplary embodiment, the patterning process may employ a half-tone mask process.

[0175] Following this patterning process, the film layer of the light-transmitting region 120 comprises a first insulating layer, a second insulating layer, and a third insulating layer.

[0176] (5) Forming a third conductive layer pattern. In exemplary embodiments, as shown in Figures 11A and 11B, forming a third conductive layer pattern may include depositing a third conductive thin film on a base on which the aforementioned pattern is formed, and then patterning the third conductive thin film by a patterning process to form a third conductive layer pattern on the third insulating layer, with Figure 11B being a schematic diagram of the third conductive layer in Figure 1A.

[0177] In an exemplary embodiment, the third conductive layer of each repeating unit on the display board may include at least one first power line 51, one second power line 52, four data signal lines 53, one compensation signal line 54, two auxiliary electrode lines 55, and two first auxiliary electrodes 56.

[0178] In exemplary embodiments, the shapes of the first power line 51, the second power line 52, the data signal line 53, and the compensation signal line 54 may be straight lines extending along the second direction Y of the main body, the first power line 51 may be located on one side of the first direction X of the display area 110, the second power line 52 may be located on the other side of the first direction X of the display area 110, the compensation signal line 54 may be located between the first power line 51 and the second power line 52, two of the four data signal lines 53 may be located between the first power line 51 and the compensation signal line 54, and the other two of the four data signal lines 53 may be located between the second power line 52 and the compensation signal line 54.

[0179] In exemplary embodiments, the first power line 51 may be located on one side of the display area 110 opposite to the first direction X, and the second power line 52 may be located on one side of the display area 110 in the first direction X. The first power line 51 and the compensation signal line 54 can define a first pixel row, and two data signal lines 53 are installed in the first pixel row. The second power line 52 and the compensation signal line 54 can define a second pixel row, and two data signal lines 53 are installed in the second pixel row.

[0180] In exemplary embodiments, the present disclosure provides that the first power line 51 and the second power line 52 are located on both sides of the display area 110, and in one repeating unit, the first power line 51 and the second power line 52 are separated by two pixel driving circuits, and in two repeating units adjacent in a first direction X, the first power line 51 and the second power line 52 are separated by one light-transmitting area 120, thereby ensuring a large distance between them, effectively preventing short-circuit failures due to overlap, and minimizing the risk of the screen burning out due to the large current caused by the short-circuit failure.

[0181] In exemplary embodiments, the positions of the first power line 51 and the second power line 52 may be basically mirror-symmetric with respect to the compensation signal line 54, and the two data signal lines 53 in the first pixel row and the two data signal lines 53 in the second pixel row may be basically mirror-symmetric with respect to the compensation signal line 54.

[0182] In an exemplary embodiment, the first power line 51 may be connected to a plurality of first auxiliary power lines 35 via a plurality of 12 vias V12, and the first power line 51 and the first auxiliary power lines 35 form a double-layer wiring structure, thereby ensuring the reliability of power signal transmission, effectively reducing the resistance of the first power line, effectively reducing the voltage drop of the first power signal, and enhancing the display effect.

[0183] In an exemplary embodiment, the second power line 52 may be connected to a plurality of second auxiliary power lines 36 via a plurality of 13 vias V13, and the second power line 52 and the second auxiliary power lines 36 form a double-layer wiring structure, thereby ensuring the reliability of power signal transmission, effectively reducing the resistance of the second power line, effectively reducing the voltage drop of the second power signal, and enhancing the display effect.

[0184] In an exemplary embodiment, each data signal line 53 may be connected to a first region of the first active layer in one subpixel via a first via V1, thereby enabling the data signal line 53 to write a data signal to the first electrode of the first transistor T1.

[0185] In exemplary embodiments, the four data signal lines 53 may include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line. The first data signal line may be located on one side of the first power line 51 in the first direction X and may be connected via a first via V1 to a first region of the first active layer in the first subpixel P1. The second data signal line may be located on one side of the compensation signal line 54 in the opposite direction X and may be connected via a first via V1 to a first region of the first active layer in the third subpixel P3. The third data signal line may be located on one side of the compensation signal line 54 in the first direction X and may be connected via a first via V1 to a first region of the first active layer in the fourth subpixel P4. The fourth data signal line may be located on one side of the second power line 52 in the opposite direction X and may be connected via a first via V1 to a first region of the first active layer in the second subpixel P2.

[0186] In an exemplary embodiment, the compensation signal line 54 may be connected to the compensation connection line 13 via a 14th via V14, thereby allowing the compensation signal line 54 to provide a compensation signal to the pixel drive circuit in each subpixel via the compensation connection line 13, so that four pixel drive circuits in one display area 110 can share one compensation connection line 13, i.e., the compensation connection line in one repeating unit has a 1:4 connection structure. By designing the compensation signal line in a 1:4 connection structure, the display board of the present disclosure saves the number of signal lines, reduces the occupied space, has a simple structure, a rational layout, makes full use of layout space, increases space utilization, and is advantageous for increasing resolution and transparency.

[0187] In an exemplary embodiment, a compensation signal line 54 is placed between a first pixel row and a second pixel row, the compensation signal line 54 is connected to a third transistor T3 in the first and second pixel rows via a compensation connection line 13, and the third transistor T3 in the first pixel row and the third transistor T3 in the second pixel row are placed symmetrically with respect to the compensation signal line 54. This symmetrical structure ensures that the RC delay in which the compensation signal is written to the third transistor T3 is essentially the same, thereby ensuring display uniformity.

[0188] In an exemplary embodiment, two auxiliary electrode wires 55 and two first auxiliary electrodes 56 may be installed in the light-transmitting region 120 of the repeating unit. The shape of the auxiliary electrode wire 55 may be a strip extending along a first direction X, with a first end of the auxiliary electrode wire 55 connected to a second power line 52, and a second end of the auxiliary electrode wire 55 extending away from the second power line 52 before being connected to the auxiliary electrode 55. The shape of the first auxiliary electrode 56 may be rectangular, and the first auxiliary electrode 56 is configured to connect to a second auxiliary electrode formed subsequently. Since the first auxiliary electrode 56 is connected to the second power line 52 via the auxiliary electrode wire 55, and the second auxiliary electrode is configured to connect to a cathode formed subsequently, a connection between the second power line 52 and the cathode is achieved.

[0189] In an exemplary embodiment, the two auxiliary electrode wires 55 and the two first auxiliary electrodes 56 may be installed in the light-transmitting region 120 on one side of the first direction X of the second subpixel P2 and the fourth subpixel P4.

[0190] In exemplary embodiments, the lengths of the two auxiliary electrode wires 55 extending in the first direction X may be the same or different, and the areas of the two first auxiliary electrodes 56 may be the same or different.

[0191] In an exemplary embodiment, the second power line 52, the two auxiliary electrode lines 55, and the two first auxiliary electrodes 56 may be an integrated structure connected to one another.

[0192] In exemplary embodiments, considering the problem of voltage drop (IR drop) present in large-size transparent displays, the embodiments of this disclosure provide a second power line that transmits a low-voltage signal in each repeating unit, the second power line connected to the cathode in a subsequently formed light-emitting structure layer via an auxiliary electrode, thereby effectively reducing the voltage drop of the second power signal and effectively solving the problem of voltage drop present in large-size transparent displays, and ensuring display uniformity.

[0193] In an exemplary embodiment, the third conductive layer of each subpixel on the display substrate may include at least a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, and a third electrode plate 47.

[0194] In an exemplary embodiment, the shape of the first connecting electrode 41 may be a strip with its main body extending along the second direction Y, the first end of the first connecting electrode 41 is connected to the second region of the first active layer via the second via V2, and the second end of the first connecting electrode 41 is connected to the second electrode plate 32 via the eighth via V8, so that the second electrode of the first transistor T1 of each subpixel and the second electrode plate 32 have the same potential.

[0195] In an exemplary embodiment, the shape of the second connecting electrode 42 may be a strip with its main body extending along the second direction Y, the first end of the second connecting electrode 42 is connected to a first region of the second active layer via a third via V3, and the second end of the second connecting electrode 42 is connected to a power supply connecting electrode 34 via a tenth via V10. The power supply connecting electrode 34 is connected to a first power supply auxiliary line 35 via a power supply connection line 37, and the first power supply auxiliary line 35 is connected to a first power supply line via a via, so that the first power supply line is connected to a first region of the second active layer, and the first power supply line can write a first power supply signal to the first electrode of the second transistor T2 of each subpixel.

[0196] In an exemplary embodiment, the shape of the third connecting electrode 43 may be a strip with its main body extending along the second direction Y, the first end of the third connecting electrode 43 is connected to the third electrode plate 47, and the second end of the third connecting electrode 43 is connected to the second region of the second active layer via the fourth via V4, so that the second electrode of the second transistor T2 of each subpixel and the third electrode plate 47 have the same potential.

[0197] In an exemplary embodiment, the shape of the fourth connecting electrode 44 may be a strip with its main body extending along a first direction X, the first end of the fourth connecting electrode 44 is connected to a first region of the third active layer via a fifth via V5, and the second end of the fourth connecting electrode 44 is connected to the compensation connecting line 13 via a ninth via V9. Since the compensation connecting line 13 is connected to the compensation signal line via a via, the compensation signal line is connected to the first region of the third active layer, and the compensation signal line can write the compensation signal to the first electrode of the third transistor T3 of each subpixel.

[0198] In an exemplary embodiment, the shape of the fifth connecting electrode 45 may be a strip with its main body extending along the second direction Y, the first end of the fifth connecting electrode 45 is connected to the third electrode plate 47, and the second end of the fifth connecting electrode 45 is connected to the second region of the third active layer via the sixth via V6, thereby giving the second electrode of the third transistor T3 of each subpixel and the third electrode plate 47 the same potential.

[0199] In an exemplary embodiment, the shape of the sixth connecting electrode 46 may be rectangular, and the orthographic projection of the sixth connecting electrode 46 on its base at least partially overlaps with the orthographic projection of the plate connecting electrode on its base at the connection block 12-1, the sixth connecting electrode 46 is connected to the connection block 12-1 via the eleventh via V11, and the sixth connecting electrode 46 is configured to be connected to a subsequently formed anode connecting electrode.

[0200] In exemplary embodiments, the shape of the third electrode plate 47 may be rectangular, the corners of the rectangular plate may be chamfered, the third electrode plate 47 may be positioned close to the scan signal line 31 of the subpixel, and the third electrode plate 47 is connected to the first electrode plate 11 via the seventh via V7. The orthographic projection of the base of the third electrode plate 47 at least partially overlaps with the orthographic projection of the base of the second electrode plate 32, the third electrode plate 47 may also serve as the upper electrode plate of a memory capacitor, and the second electrode plate 32 and the third electrode plate 47 form a second capacitor.

[0201] In an exemplary embodiment, the third connecting electrode 43, the fifth connecting electrode 45, and the third electrode plate 47 may be an integrated structure connected to each other.

[0202] In an exemplary embodiment, the first connecting electrode 41 is connected to the second electrode plate 32, and the second electrode plate 32 is connected to the second gate electrode 33. As a result, the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first end of the memory capacitor (including the second electrode plate 32) have the same potential, and the first connecting electrode 41 may also serve as the first node N1 of the pixel driving circuit.

[0203] In an exemplary embodiment, the third connecting electrode 43 is connected to the second region of the second active layer, the fifth connecting electrode 45 is connected to the second region of the third active layer, the third connecting electrode 43 and the fifth connecting electrode 45 are connected to the third electrode plate 47, and the first electrode plate 11 and the third electrode plate 47 are connected. As a result, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second end of the memory capacitor (including the first electrode plate 11 and the third electrode plate 47) have the same potential due to the third connecting electrode 43 and the fifth connecting electrode 45, and the third connecting electrode 43 and the fifth connecting electrode 45 may also be the second node N2 in the pixel driving circuit.

[0204] In an exemplary embodiment, the second plate 32 has the potential of the first node N1, and the first plate 11 and the third plate 47 have the potential of the second node N2. Therefore, the second node N2 having the potential of the first node N1 and the first plate 11 having the potential of the second node N2 constitute the first capacitor of the pixel driving circuit, the second node N2 having the potential of the first node N1 and the third plate 47 having the potential of the second node N2 constitute the second capacitor of the pixel driving circuit, and the first and second capacitors are connected in parallel. In this disclosure, the first and second capacitors are formed in a parallel structure using the first conductive layer, the second conductive layer and the third conductive layer, and the first and second capacitors in a parallel structure constitute the memory capacitor of the complete pixel driving circuit. On the one hand, the capacitance value of the memory capacitor can be effectively increased, and on the other hand, the plate area can be reduced while maintaining the capacitance value of the memory capacitor, thereby effectively reducing the occupied area.

[0205] In an exemplary embodiment, the first power auxiliary line 35 is connected to two power connection electrodes 34 in one pixel row via the power connection line 37 and the electrode connection line 38, and the first power line 51 is connected to the first power auxiliary line 35. Thus, four pixel driving circuits in one display area 110 can share one first power line 51, meaning that the first power line in one repeating unit has a 1:4 connection structure, which reduces the space occupied by the display area, increases the area ratio of the light-transmitting area, and improves resolution and transparency.

[0206] In an exemplary embodiment, in at least one repeating unit, the orthographic projections at the base of the first power line 51, the second power line 52, the data signal line 53, and the compensation signal line 54 at least partially overlap with the orthographic projection at the base of the annular structure of the scan signal line 31.

[0207] Following this patterning process, the film layer of the light-transmitting region 120 comprises a first insulating layer, a second insulating layer, and a third insulating layer.

[0208] (6) Forming the fourth insulating layer and the first flat layer pattern. In an exemplary embodiment, as shown in Figure 12, forming the fourth insulating layer and the first flat layer pattern includes depositing the fourth insulating thin film on the base on which the aforementioned pattern is formed, then applying the first flat thin film, patterning the fourth insulating thin film and the first flat thin film by a patterning process to form a fourth insulating layer covering the third conductive layer and a first flat layer pattern placed on the fourth insulating layer, and providing a plurality of vias in the fourth insulating layer and the first flat layer.

[0209] In an exemplary embodiment, the first flat layer is installed only in the display area 110, and the first flat layer located in the light-transmitting area 120 is completely removed, including the area where the plate connecting electrode 12 and the first auxiliary electrode 56 are located.

[0210] In an exemplary embodiment, at least one repeating unit may comprise four 21st vias V21 and two 22nd vias V22.

[0211] In an exemplary embodiment, the orthographic projection of each 21st via V21 at its base lies within the orthographic projection of the 6th connecting electrode 46 at its base, the 4th insulating layer within the 21st via V21 is etched to expose the surface of the 6th connecting electrode 46, and the 21st via V21 is configured such that a subsequently formed anode connecting electrode is connected to the 6th connecting electrode 46 via the via.

[0212] In an exemplary embodiment, the orthographic projection of each 22 via V22 at its base lies within the range of the orthographic projection of the first auxiliary electrode 56 at its base, the fourth insulating layer within the 22 via V22 is etched to expose the surface of the first auxiliary electrode 56, and the 22 via V22 is configured such that a subsequently formed second auxiliary electrode is connected to the first auxiliary electrode 56 via the via.

[0213] In an exemplary embodiment, the patterning process may employ a half-tone mask process.

[0214] Following this patterning process, the film layer of the light-transmitting region 120 comprises a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer.

[0215] (7) Forming a fourth conductive layer pattern. In exemplary embodiments, as shown in Figures 13A and 13B, forming a fourth conductive layer pattern may include depositing a fourth conductive thin film on a base on which the aforementioned pattern has been formed, and then patterning the fourth conductive thin film by a patterning process to form a fourth conductive layer pattern, where Figure 13B is a schematic diagram of the fourth conductive layer in Figure 3A.

[0216] In an exemplary embodiment, the fourth conductive layer of each subpixel on the display substrate may include at least a first anode 61 and an anode connecting electrode 62.

[0217] In exemplary embodiments, the first anode 61 in at least one subpixel may comprise a separately installed first sub-anode 61-1 and a second sub-anode 61-2, the first sub-anode 61-1 and the second sub-anode 61-2 may be rectangular in shape, located in the display area 110 and installed in the first flat layer, and the first sub-anode 61-1 and the second sub-anode 61-2 may be installed sequentially along the second direction Y.

[0218] In an exemplary embodiment, the anode connection electrode 62 may be "C" shaped, located in the light-transmitting region 120 and installed in the fourth insulating layer, the first end of the anode connection electrode 62 is connected to the first sub-anode 61-1, the second end of the anode connection electrode 62 is connected to the second sub-anode 61-2, and the region between the first and second ends is connected to the sixth connection electrode 46 via the 21st via V21. In an exemplary embodiment, the anode connection electrode 62 enables interconnection between the first sub-anode 61-1 and the second sub-anode 61-2, the sixth connection electrode 46 is connected to the plate connection electrode 12, and the plate connection electrode 12 is connected to the first plate 11, so the anode connection electrode 62 enables connection between the first anode 61 and the first plate 11 of the memory capacitor.

[0219] In an exemplary embodiment, if a bright spot defect occurs on the display substrate, the anode connection electrode 62 can be cut by laser cutting, so that one of the first sub-anode 61-1 and the second sub-anode 61-2 is connected to the first electrode plate 11 and the other is left floating, thereby repairing the bright spot defect.

[0220] In exemplary embodiments, the 21st via V21 may also be referred to as an anode via, and the orthographic projection on the base of the anode via does not overlap with the orthographic projection on the bases of the first sub-anode 61-1 and the second sub-anode 61-2. This not only increases the success rate of repairing bright spot defects and avoids the impact of repairs on the pixel driving circuit, but also ensures the flatness of the anode, improves the light emission quality of the light-emitting element, and enhances the display effect.

[0221] In an exemplary embodiment, the four first anodes 61 are arranged in a square, with the upper left first anode 61 connected to the pixel driving circuit of the first sub-pixel P1, the upper right first anode 61 connected to the pixel driving circuit of the second sub-pixel P2, the lower left first anode 61 connected to the pixel driving circuit of the third sub-pixel P3, and the lower right first anode 61 connected to the pixel driving circuit of the fourth sub-pixel P4. In several possible implementations, the arrangement of the anodes can be adjusted according to the actual needs, and this disclosure is not specifically limited thereto.

[0222] In exemplary embodiments, the first sub-anode 61-1, the second sub-anode 61-2, and the anode connecting electrode 62 of each sub-pixel may be an integrated structure connected to one another.

[0223] In exemplary embodiments, the fourth conductive layer of at least one repeating unit may further comprise a second auxiliary electrode 63. The shape of the second auxiliary electrode 63 may be rectangular, and the orthographic projection of the second auxiliary electrode 63 on its base may at least partially overlap the orthographic projection of the first auxiliary electrode 56 on its base, and the second auxiliary electrode 63 may be connected to the first auxiliary electrode 56 via a 22 via V22, and the second auxiliary electrode 63 may be configured to be connected to a subsequently formed third auxiliary electrode.

[0224] In exemplary embodiments, the material of the fourth conductive layer may be a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0225] After this patterning process, there is no change in the film layer of the translucent region 120.

[0226] (8) Forming a fifth conductive layer pattern. In exemplary embodiments, as shown in Figures 14A and 14B, forming a fifth conductive layer pattern may include depositing a fifth conductive thin film on a base on which the aforementioned pattern has been formed, and then patterning the fifth conductive thin film by a patterning process to form a fifth conductive layer pattern, where Figure 14B is a schematic diagram of the fifth conductive layer in Figure 4A.

[0227] In an exemplary embodiment, the fifth conductive layer of each subpixel on the display substrate may include at least a second anode 72.

[0228] In exemplary embodiments, the second anode 72 may include separately installed third sub-anodes 72-1 and fourth sub-anodes 72-2, the third sub-anodes 72-1 and fourth sub-anodes 72-2 may be rectangular in shape, located in the display area 110, and installed on the first sub-anode 61-1 and second sub-anodes 61-2, respectively, the third sub-anodes 72-1 and fourth sub-anodes 72-2 may be installed sequentially along a second direction Y, the orthographic projection of the third sub-anode 72-1 on its base at least partially overlaps with the orthographic projection of the first sub-anode 61-1 on its base, the third sub-anode 72-1 is connected to the first sub-anode 61-1, the orthographic projection of the fourth sub-anode 72-2 on its base at least partially overlaps with the orthographic projection on its base, and the fourth sub-anode 72-2 is connected to the second sub-anode 61-2.

[0229] In exemplary embodiments, the fifth conductive layer of at least one repeating unit may further comprise a third auxiliary electrode 73. The shape of the third auxiliary electrode 73 may be rectangular, and the second auxiliary electrode 63 may be mounted on the second auxiliary electrode 63, such that the orthographic projection of the second auxiliary electrode 63 on its base at least partially overlaps with the orthographic projection of the second auxiliary electrode 63 on its base, the second auxiliary electrode 63 is connected to the second auxiliary electrode 63, and the third auxiliary electrode 73 is connected to a subsequently formed cathode.

[0230] In exemplary embodiments, the third auxiliary electrode 73 may employ a separation column (RIB) structure, and the cross-sectional shape of the third auxiliary electrode 73 may be an inverted trapezoid. This allows the subsequently formed organic light-emitting layer to be cut off at the side edge of the third auxiliary electrode 73, forming an isolated organic light-emitting block. This effectively avoids interference of the organic light-emitting block with the emitted light, improves the quality of the emitted light, and is advantageous for improving display attributes.

[0231] In an exemplary embodiment, the stacked first auxiliary electrode 56, the second auxiliary electrode 63, and the third auxiliary electrode 73 constitute an auxiliary cathode.

[0232] In exemplary embodiments, the material for the fifth conductive layer may be a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0233] After this patterning process, there is no change in the film layer of the translucent region 120.

[0234] (9) Form a pixel definition layer. In an exemplary embodiment, as shown in Figure 15, forming a pixel definition layer pattern may include applying a pixel definition thin film to a base on which the aforementioned pattern has been formed, and then patterning the pixel definition thin film by a patterning process to form a pixel definition layer.

[0235] In an exemplary embodiment, a first pixel aperture K1 and a second pixel aperture K2 are provided in the pixel definition layer of each subpixel on the display substrate. The pixel definition thin film in the first pixel aperture K1 is removed to expose a portion of the surface of the third sub-anode 72-1 on the second anode 72, and the pixel definition thin film in the second pixel aperture K2 is removed to expose a portion of the surface of the fourth sub-anode 72-2 on the second anode 72.

[0236] In an exemplary embodiment, the orthographic projection of the base of the first pixel aperture K1 lies within the range of the orthographic projection of the base of the third sub-anode 72-1, and the orthographic projection of the base of the second pixel aperture K2 lies within the range of the orthographic projection of the base of the fourth sub-anode 72-2.

[0237] In exemplary embodiments, the shapes of the first pixel aperture K1 and the second pixel aperture K2 may be similar to the shape of the sub-anode in a plane parallel to the base, and the cross-sectional shapes of the first pixel aperture K1 and the second pixel aperture K2 may be rectangular or trapezoidal in a plane perpendicular to the base.

[0238] In an exemplary embodiment, an auxiliary electrode aperture K3 is opened in the pixel definition layer of at least one repeating unit, the pixel definition thin film within the auxiliary electrode aperture K3 is removed to expose a portion of the surface of a third auxiliary electrode 73, and the orthogonal projection of the base of the auxiliary electrode aperture K3 lies within the orthogonal projection of the base of the third auxiliary electrode 73.

[0239] In exemplary embodiments, the shape of the auxiliary electrode opening K3 may be similar to the shape of the third auxiliary electrode 73 in a plane parallel to the base, and the cross-sectional shape of the auxiliary electrode opening K3 may be rectangular, trapezoidal, or the like in a plane perpendicular to the base.

[0240] In the exemplary embodiment, the pixel definition layer of the light-transmitting region 120 is essentially removed to form a light-transmitting aperture T, a groove is provided on the side of the light-transmitting aperture T closer to the display region 110, and the pixel definition block placed in the groove can shield the anode connection electrode 62.

[0241] In exemplary embodiments, the pixel definition layer may be made of polyimide, acrylic, or polyethylene terephthalate, etc.

[0242] (10) Forming the organic light-emitting layer and cathode pattern. In an exemplary embodiment, forming the organic light-emitting layer and cathode pattern includes first forming an organic light-emitting layer pattern in the display area 110, the organic light-emitting layer being connected to a third sub-anode 72-1 and a fourth sub-anode 72-2 via a first pixel aperture K1 and a second pixel aperture K2, respectively; then forming a cathode, in the display area 110 the cathode being connected to the organic light-emitting layer, and in the light-transmitting area 120 the cathode being connected to a third auxiliary electrode 73 via an auxiliary electrode aperture K3. The connection between the cathode and the second power line is achieved because the third auxiliary electrode 73 is connected to a second power line.

[0243] In exemplary embodiments, the organic light-emitting layer may comprise an emissive layer (EML) and one or more layers selected from a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In exemplary embodiments, the organic light-emitting layer may be formed by deposition using a fine metal mask (FMM) or an open mask, or by employing an inkjet process.

[0244] In exemplary embodiments, the manufacturing process for the display substrate may further include forming a package layer pattern. Forming the package layer pattern may include first depositing a first inorganic thin film using an open mask to form a first package layer, then inkjet printing an organic material onto the first package layer using an inkjet printing process, curing it to form a film, and then depositing a second inorganic thin film using an open mask to form a third package layer, so that the package layers consist of the first package layer, the second package layer and the third package layer. The first and third package layers may employ one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), carbon silicon nitride (SiCN), and silicon nitride (SiON), and may be single layers, multilayer layers, or composite layers. The second package layer may employ a resin material to form an inorganic / organic / inorganic laminated structure, and the organic material layer may be placed between two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer.

[0245] In an exemplary embodiment, the manufacturing process of the display substrate further includes forming a color film layer and a black matrix, the black matrix having a plurality of opening regions exhibiting a matrix arrangement, and the color film layer filling the opening regions.

[0246] This completes the manufacturing of the display board according to the exemplary embodiment of the present disclosure.

[0247] In exemplary embodiments, the base may be a flexible base or a rigid base. The rigid base may be one or more types of glass and quartz, but is not limited thereto, and the flexible base may be one or more types of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers, but is not limited thereto. In exemplary embodiments, the flexible base may include a laminated first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials for the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials for the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx) to improve the hydroxyl resistance of the base. The semiconductor layer can be amorphous silicon (a-si).

[0248] In exemplary embodiments, the first conductive layer, the second conductive layer, and the third conductive layer may be made of a metallic material, for example, one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, for example, aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multilayer composite structure, for example, Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon nitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first flat layer may be made of an organic material, for example, a resin.

[0249] Figure 16 is a schematic diagram of the repair of a short-circuit defect in a display board according to an exemplary embodiment of the present disclosure. As shown in Figure 16, when a short point 200 occurs between the scanning connection line 31 and another signal line (e.g., data signal line 53), the first sub-lines on both sides of the short point 200 are cut by laser cutting, forming two cutoff points 300 on each side of the short point 200, thereby isolating the short point 200. Since the scanning connection line 31 in the display area is a double-wire segment 31-1 with a double-wire structure and has a double-channel function, the cutoff points 300 do not affect the pixel driving circuit, ensuring that the scanning signal line drives all pixel driving circuits in the repeating area. Furthermore, repairs can be performed on short points 200 at all locations, enabling the repair of all signal short-circuit defects, avoiding product discard, and effectively increasing the product yield rate.

[0250] As can be seen from the structure and manufacturing flow of the display board described above, the display board according to this disclosure employs a 3T1C pixel driving circuit with one scan signal line, and one scan signal line is connected to the first and third transistors in the pixel driving circuit. By reducing the number of scan signal lines, the structure of the pixel driving circuit can be simplified and the area occupied by the pixel driving circuit can be reduced, which is advantageous not only for achieving high resolution display but also for effectively increasing the light-transmitting area of ​​the light-transmitting region and improving the spatial occupancy rate of the light-transmitting region, which is advantageous for achieving high transparency display. Furthermore, since one repeating unit is driven by only one scan signal line, the number of corresponding gate drive circuits (GOA) and clock signal lines (CLK) can be doubled, which is advantageous for effectively reducing the area occupied by the gate drive circuits and clock signal lines, enabling a narrow bezel and enhancing the product's competitiveness.

[0251] In exemplary embodiments of this disclosure, by installing a single-line structure in the light-transmitting region and a double-line structure in the display region, it is possible to ensure that the scanning signal lines drive all pixel drive circuits in the repeating region, as well as to realize a double-channel function, allowing repair to be performed on signal lines at all positions, enabling the repair of all signal short-circuit defects and effectively increasing the yield rate of the product.

[0252] In exemplary embodiments of this disclosure, a first capacitor and a second capacitor are formed using a three-layer metal layout sandwich structure with a first conductive layer, a second conductive layer, and a third conductive layer. The first and second capacitors, connected in parallel, constitute a memory capacitor. On the one hand, the capacitance value of the memory capacitor can be effectively increased, while on the other hand, the plate area can be reduced while maintaining the capacitance value of the memory capacitor, thereby effectively reducing the occupied area of ​​the pixel driving circuit, which is advantageous for realizing high-resolution displays.

[0253] In exemplary embodiments of this disclosure, by installing a 1:4 connection structure for the first power lines and a 1:4 connection structure for the compensation signal lines, the number of signal lines is reduced, the occupied space is decreased, the structure is simple, the layout is rational, the layout space is fully utilized, the space utilization rate is increased, and it is advantageous for increasing resolution.

[0254] In exemplary embodiments of this disclosure, by arranging the anode connection electrodes to be connected to a first sub-anode and a second sub-anode, respectively, the success rate of repairing bright spot defects can be increased, the impact of repair on the pixel driving circuit can be avoided, and other defects can be prevented, resulting in a high success rate of repair, ensuring anode flatness, improving the light emission quality of the light-emitting element, and enhancing the display effect.

[0255] In exemplary embodiments of this disclosure, by installing a second power line and an auxiliary electrode, the second power line is connected to the cathode via the auxiliary electrode, thereby effectively reducing the voltage drop of the second power supply and ensuring display uniformity.

[0256] In exemplary embodiments of this disclosure, the anode connecting electrode and auxiliary electrode are placed in a light-transmitting region, and the shape of the light-transmitting region is changed to an irregular shape. When light rays pass through the irregularly shaped light-transmitting region, the positions and directions in which diffraction fringes are generated differ. As a result, the diffraction fringes caused by the light rays do not diffuse in one direction but diffuse in multiple directions. This significantly weakens the diffraction effect, avoids blurring of objects behind the screen, and enhances the transparent display effect.

[0257] The manufacturing processes described in the exemplary embodiments of this disclosure are well compatible with existing manufacturing processes, are easy to implement, are easy to carry out, have high production efficiency, low manufacturing costs, and high yield rates.

[0258] The structures and manufacturing processes described above in this disclosure are illustrative only, and in the exemplary embodiments, the corresponding structures may be modified or patterning processes may be added or removed depending on actual needs, and this disclosure is not limited thereto.

[0259] In exemplary embodiments, the display substrate of the present disclosure can be applied to display devices having pixel driving circuits, such as OLEDs, quantum dot displays (QLEDs), light-emitting diode displays (Micro LEDs or Mini LEDs), or quantum dot light-emitting diode displays (QDLEDs), and the present disclosure is not limited thereto.

[0260] This disclosure further provides a method for manufacturing a display substrate for manufacturing a display substrate according to the above embodiment. In an exemplary embodiment, the display substrate comprises a plurality of regularly arranged repeating units, each repeating unit comprising a display area and a light-transmitting area located on at least one side of the display area, the display area being configured to display an image, the light-transmitting area being configured to transmit light rays, the display area comprising a plurality of subpixels forming at least two pixel rows and two pixel columns, the subpixels comprising a pixel driving circuit, and the manufacturing method is as follows: A pixel driving circuit is formed in the subpixel, and the pixel driving circuit comprises a first transistor, a second transistor, a third transistor, and a memory capacitor, wherein the first electrode of the first transistor is connected to a data signal line, the second electrode of the first transistor is connected to the gate electrode of the second transistor and the first terminal of the memory capacitor, respectively, the first electrode of the second transistor is connected to a first power line, the second electrode of the second transistor is connected to the second electrode of the third transistor and the second terminal of the memory capacitor, respectively, the first electrode of the third transistor is connected to a compensation signal line, and the gate electrode of the first transistor and the gate electrode of the third transistor are connected to the same scan signal line.

[0261] This disclosure further provides a display device comprising the aforementioned display board. The display device may be any product or component having a display function, such as a mobile phone, tablet PC, television, display, notebook computer, digital photo frame, navigator, etc., and the embodiments of the present invention are not limited thereto.

[0262] While the embodiments disclosed herein are as described above, the descriptions are merely examples adopted to facilitate understanding of this disclosure and are not intended to limit it. Those skilled in the art may modify and change the form and details of the implementation without deviating from the spirit and scope disclosed herein, but the scope of patent protection of the present invention should be limited to that set forth in the claims. [Explanation of symbols]

[0263] 11 - 1st plate 12 - Plate connecting electrodes 13 - Compensation connection line 21 - 1st active layer 22-Second active layer 23-Third active layer 31 - Scanning signal line 31-1 - Double-line segment 31-2 - Single-track segment 32-Second plate 33 - Second Termination 34 - Power connection electrode 35 - 1st power supply auxiliary line 36 - 2nd power supply auxiliary line 37 - Power connection cable 38 - Electrode connection wire 41 - First connecting electrode 42 - Second connecting electrode 43 - Third connecting electrode 44 - Fourth connecting electrode 45 - Fifth connecting electrode 46 - Sixth connecting electrode 47-Third plate 51 - 1st power line 52—Second power line 53 - Data signal line 54 - Compensation signal line 55 - Auxiliary electrode wire 52 - 1st auxiliary electrode 61 - 1st anode 61-1-1st sub-anode 61-2 - Second Sub-Anode 62 - Anode connection electrode 72-Second anode 72-1 - Third Sub-anode 72-1 - Fourth Sub-Anode 73-Third auxiliary electrode 80 - Repeat Unit 100 - Repeating Unit 110—Display area 120 - Translucent area 200 - Short points 300 - Cutoff Point

Claims

1. A display board comprising a plurality of regularly arranged repeating units, each repeating unit comprising a display area and a light-transmitting area located on at least one side of the display area, the display area being configured to display an image, the light-transmitting area being configured to transmit light rays, the display area comprising a plurality of subpixels forming at least two pixel rows and two pixel columns, each subpixel comprising a pixel driving circuit, the pixel driving circuit comprising a first transistor, a second transistor, a third transistor and a memory capacitor, the first electrode of the first transistor being connected to a data signal line, the second electrode of the first transistor being connected to the gate electrode of the second transistor and the first end of the memory capacitor, respectively, the first electrode of the second transistor being connected to a first power line, the second electrode of the second transistor being connected to the second electrode of the third transistor and the second end of the memory capacitor, respectively, the first electrode of the third transistor being connected to a compensation signal line, and in the pixel driving circuit of at least one subpixel, the gate electrode of the first transistor and the gate electrode of the third transistor are connected to the same scan signal line.

2. The display substrate according to claim 1, wherein in a plurality of pixel driving circuits of at least one pixel row, the gate electrodes of a plurality of first transistors and the gate electrodes of a plurality of third transistors are connected to the same scanning signal line.

3. The display board according to claim 1, wherein in a plurality of pixel driving circuits of at least one repeating unit, the gate electrodes of a plurality of first transistors and the gate electrodes of a plurality of third transistors are connected to the same scanning signal line.

4. The display board according to claim 1, wherein in at least one repeating unit, the scanning signal line extends from the display area to the light-transmitting area, and the scanning signal line comprises a single-line segment with a single-line structure and a double-line segment with a double-line structure, the single-line segment is installed in the light-transmitting area, the double-line segment is installed in the display area, and each of the double-line segments is connected to a pixel driving circuit for a plurality of subpixels in the repeating unit.

5. The display substrate according to claim 4, wherein the double-line segment comprises a first sub-line and a second sub-line extending along the pixel row direction, the first sub-line and the second sub-line are arranged along the pixel column direction, the first sub-line is connected to the pixel driving circuits of a plurality of sub-pixels in one pixel row, and the second sub-line is connected to the pixel driving circuits of a plurality of sub-pixels in another adjacent pixel row, respectively.

6. The display board according to claim 5, wherein the double-wire segment further comprises a first connecting line and a second connecting line, the first connecting line being connected to one end of the first sub-wire and the second sub-wire, respectively, and the second connecting line being connected to the other end of the first sub-wire and the second sub-wire, and the first connecting line, the first sub-wire, the second connecting line, and the second sub-wire form an annular structure.

7. The display substrate according to claim 6, wherein the single-line segment is located in the direction of extension of the first sub-line or the second sub-line.

8. The display board according to claim 6, wherein the first connection line is connected to a single-line segment located in the light-transmitting region on one side of the pixel row direction of the display area, and the second connection line is connected to a single-line segment located in the light-transmitting region on the other side of the pixel row direction of the display area.

9. The display board according to claim 8, wherein in at least one repeating unit, the single-line segment and the double-line segment are connected to each other in an integrated structure.

10. The display board according to claim 6, wherein the orthographic projection of the first power line, the data signal line, and the compensation signal line on the plane of the display board and the orthographic projection of the annular structure on the plane of the display board overlap at least partially.

11. The display substrate according to claim 6, wherein in at least one repeating unit, the active layers of the third transistor of two subpixels in adjacent pixel rows are a single connected structure, and the orthogonal projection of the active layer of the third transistor on the plane of the display substrate and the orthogonal projection of the annular structure on the plane of the display substrate overlap at least partially.

12. The display substrate according to claim 1, wherein in at least one repeating unit, a plurality of subpixels are mirror-symmetric with respect to the scan signal line.

13. The display board according to any one of claims 1 to 12, wherein the first end of the memory capacitor comprises a first electrode plate and a third electrode plate, the second end of the memory capacitor comprises a second electrode plate, the orthographic projection of the second electrode plate on the plane of the display board and the orthographic projection of the first electrode plate on the plane of the display board overlap at least partially, the first electrode plate and the second electrode plate form a first capacitor, the orthographic projection of the second electrode plate on the plane of the display board and the orthographic projection of the third electrode plate on the plane of the display board overlap at least partially, the third electrode plate and the second electrode plate form a second capacitor, the first electrode plate is connected to the third electrode plate, the second electrode of the first transistor and the gate electrode of the second transistor, respectively, the second electrode plate is connected to the second electrode of the second transistor and the second electrode of the third transistor, and the first capacitor and the second capacitor constitute a memory capacitor in a parallel connection structure.

14. In a direction perpendicular to the display substrate, the display area comprises a drive circuit layer installed on a base and a light-emitting structure layer installed on the side of the drive circuit layer away from the base, the drive circuit layer comprises at least a first conductive layer, a second conductive layer, and a third conductive layer installed sequentially along the direction away from the base, the first electrode plate is installed on the first conductive layer, the second electrode plate is installed on the second conductive layer, the third electrode plate is installed on the third conductive layer, the third electrode plate is connected to the first electrode plate via vias, and at least one repeating unit further comprises an electrode plate connecting electrode, the electrode plate connecting electrode is installed in the light-transmitting area, and the electrode plate connecting electrode is connected to the first electrode plate, as described in claim 13.

15. The display substrate according to claim 14, wherein in at least one repeating unit, the electrode plate connecting electrode and the first electrode plate are connected to each other in an integrated structure.

16. The display substrate according to claim 14, wherein the light-emitting structure layer comprises at least a fourth conductive layer installed on the side of the third conductive layer away from the base, the fourth conductive layer comprises at least a first anode and an anode connecting electrode, the first anode is installed on a plurality of subpixels in the display area, the anode connecting electrode is installed in the light-transmitting area, the anode connecting electrode is connected to the electrode plate connecting electrode via an anode via, the anode via is installed in the light-transmitting area, and in at least one subpixel, the first anode comprises a first sub-anode and a second sub-anode installed separately, the first end of the anode connecting electrode is connected to the first sub-anode, and the second end of the anode connecting electrode is connected to the second sub-anode.

17. The display substrate according to claim 14, wherein the third conductive layer further comprises a second power line and a first auxiliary electrode, the second power line being installed in the display area, the first auxiliary electrode being installed in the light-transmitting area, and the first auxiliary electrode being connected to the second power line.

18. The display board according to claim 17, wherein in at least one repeating unit, the first auxiliary electrode and the second power line are connected to each other in an integrated structure.

19. The display board according to claim 17, wherein the orthographic projection of the second power line on the display board and the orthographic projection of the annular structure of the scanning signal line on the display board overlap at least partially.

20. A display device comprising a display board according to any one of claims 1 to 19.

21. A method for manufacturing a display substrate, wherein the display substrate comprises a plurality of regularly arranged repeating units, each repeating unit comprises a display area and a light-transmitting area located on at least one side of the display area, the display area is configured to display an image, the light-transmitting area is configured to transmit light rays, the display area comprises a plurality of subpixels forming at least two pixel rows and two pixel columns, each subpixel comprises a pixel driving circuit, and the manufacturing method is: A method for manufacturing a display board, comprising forming a pixel driving circuit in the sub-pixel, the pixel driving circuit comprising a first transistor, a second transistor, a third transistor, and a memory capacitor, the first electrode of the first transistor being connected to a data signal line, the second electrode of the first transistor being connected to the gate electrode of the second transistor and the first terminal of the memory capacitor, respectively, the first electrode of the second transistor being connected to a first power line, the second electrode of the second transistor being connected to the second electrode of the third transistor and the second terminal of the memory capacitor, respectively, the first electrode of the third transistor being connected to a compensation signal line, and the gate electrode of the first transistor and the gate electrode of the third transistor being connected to the same scan signal line.

Images