Display boards and display devices

Abstract

A display board and a display device, wherein the display board comprises a base, the base includes a display area and a non-display area, the display area includes M sub-display areas, the non-display area includes a circuit area and a fan-out area arranged along a second direction, and the fan-out area includes M sub-fan-out areas. The display board further comprises a plurality of sub-pixels and a first signal line located in the display area, a gate drive circuit and M initial signal lines located in the circuit area, and fan-out wiring located in the fan-out area, the gate drive circuit includes M drive circuits. The first signal line is electrically connected to the gate electrode of at least some transistors. Each i-th drive circuit is electrically connected to the i-th initial signal line and the fan-out wiring located in the i-th sub-fan-out area, and the fan-out wiring located in the i-th sub-fan-out area is electrically connected to the first signal line located in the i-th sub-display area.

Claims

1. A display board comprising a base, the base including a display area and a non-display area located on at least one side of the display area, the display area including M sub-display areas, the first to Mth sub-display areas being arranged sequentially along a first direction, the non-display area including a circuit area and a fan-out area arranged along a second direction, the circuit area being located on the side of the fan-out area away from the display area, the fan-out area including M sub-fan-out areas, the first to Mth sub-fan-out areas being arranged sequentially along a first direction, the first direction and the second direction intersect, and M > 1. The display board further comprises a plurality of subpixels and a first signal line located in the display area, a gate drive circuit and M initial signal lines located in the circuit area, and fan-out wiring located in the fan-out area, wherein the gate drive circuit includes M drive circuits, the first to the Mth drive circuits are arranged sequentially along a first direction, the first signal line extends along a second direction, the initial signal line extends along a first direction, and at least a portion of the fan-out wiring extends along a second direction. The sub-pixel includes a pixel driving circuit, the pixel driving circuit includes a plurality of transistors, and the first signal line is electrically connected to the gate electrodes of at least some of the transistors. The i-th drive circuit is electrically connected to the i-th initial signal line and the fan-out wiring located in the i-th sub-fan-out area, the fan-out wiring located in the i-th sub-fan-out area is electrically connected to the first signal line located in the i-th sub-display area, and the display board satisfies 1 ≤ i ≤ M.

2. The aforementioned subpixel includes a first-color subpixel, a second-color subpixel, and a third-color subpixel. The display substrate according to claim 1, wherein the subpixel in row 3m-2 is a subpixel of the first color, the subpixel in row 3m-1 is a subpixel of the second color, the subpixel in row 3m is a subpixel of the third color, 1 ≤ m ≤ N / 3, and N is the total number of rows of subpixels in the display area.

3. At least one drive circuit includes a first virtual drive circuit, an output drive circuit, and a second virtual drive circuit arranged sequentially along the first direction. The display board according to claim 1 or 2, wherein the first virtual drive circuit of the j-th drive circuit is located on the side of the output drive circuit of the j-th drive circuit that is closer to the (j-1)th drive circuit, and 1 < j ≤ M.

4. The first virtual drive circuit includes a plurality of first virtual shift registers connected in cascade, the output drive circuit includes a plurality of output shift registers connected in cascade, the second virtual drive circuit includes a plurality of second virtual shift registers connected in cascade, and the first virtual shift register, the output shift register, and the second virtual shift register each include an input terminal and an output terminal. The display board according to claim 3, wherein in the i-th drive circuit, the input terminal of at least one first virtual shift register is electrically connected to the i-th initial signal line, the input terminal of at least one output shift register is electrically connected to the output terminal of at least one first virtual shift register, and the output terminal of at least one output shift register is electrically connected to the input terminal of at least one second virtual shift register.

5. In the i-th drive circuit, the number of the first virtual shift registers is Ri, the number of the output shift registers is Si, and the number of the second virtual shift registers is Ti. The display substrate according to claim 4, wherein Ri < Si, Ti < Si, Si = 2Mi, and Mi is the number of rows of subpixels in the i-th subdisplay area.

6. The circuit area further comprises 4K clock signal lines, where K ≥ 4, K is an even number, the clock signal lines extend along the first direction, and the 4K clock signal lines are arranged along the second direction. The display substrate according to claim 5, wherein Ri = 4K or 12K and Ti = 4K or 12K.

7. In the i-th drive circuit, the output clock signal terminal of the 6p+1+4K*L stage output shift register is electrically connected to the 2p+1 clock signal line, the output clock signal terminal of the 6p+3+4K*L stage output shift register is electrically connected to the 2K+2p+1 clock signal line or the 2p+1-2K clock signal line, the output clock signal terminal of the 6p+5+4K*L stage output shift register is electrically connected to the 2p+1 clock signal line, and the 6p+2+4K* The output clock signal terminal of the L-stage output shift register is electrically connected to the 2p+2th clock signal line, the output clock signal terminal of the 6p+4+4K*L-stage output shift register is electrically connected to the 2K+2p+2 clock signal lines or the 2p+2-2Kth clock signal line, the output clock signal terminal of the 6p+6+4K*L-stage output shift register is electrically connected to the 2p+2 clock signal lines, 0≦L≦(Si / 4K)-1 and 0≦p≦2K-1, If 2p+1 < 2K, the output clock signal terminal of the 6p+3+4K*L stage output shift register is electrically connected to 2K+2p+1 clock signal lines, and the output clock signal terminal of the 6p+4 stage output shift register is electrically connected to 2K+2p+2 clock signal lines. The display board according to claim 6, wherein if 2p+1 > 2K, the output clock signal terminal of the 6p+3 stage output shift register is electrically connected to the 2p+1 - 2Kth clock signal line, and the output clock signal terminal of the 6p+4 stage output shift register is electrically connected to the 2p+2 - 2Kth clock signal lines.

8. When Ri = 4K, the output clock signal terminal of the first virtual shift register in the r-th stage is electrically connected to the r-th clock signal line, and 1 ≤ r ≤ 4K. When Ri = 12K, the output clock signal terminal of the 6p+1 stage first virtual shift register is electrically connected to the 2p+1 clock signal line, the output clock signal terminal of the 6p+3 stage first virtual shift register is electrically connected to the 2K+2p+1 clock signal line or the 2p+1-2K clock signal line, the output clock signal terminal of the 6p+5 stage first virtual shift register is electrically connected to the 2p+1 clock signal line, the output clock signal terminal of the 6p+2 stage first virtual shift register is electrically connected to the 2p+2 clock signal line, the output clock signal terminal of the 6p+4 stage first virtual shift register is electrically connected to the 2K+2p+2 clock signal line or the 2p+2-2K clock signal line, and the output clock signal terminal of the 6p+6 stage first virtual shift register is electrically connected to the 2p+2 clock signal line. If 2p+1 < 2K, the output clock signal terminal of the 6p+3 stage first virtual shift register is electrically connected to 2K+2p+1 clock signal lines, and the output clock signal terminal of the 6p+4 stage first virtual shift register is electrically connected to 2K+2p+2 clock signal lines. The display board according to claim 7, wherein if 2p+2 > 2K, the output clock signal terminal of the 6p+3 stage first virtual shift register is electrically connected to the 2p+1 - 2Kth clock signal line, and the output clock signal terminal of the 6p+4 stage first virtual shift register is electrically connected to the 2p+2 - 2Kth clock signal lines.

9. When Ti = 4K, the output clock signal terminal of the t-th stage second virtual shift register is electrically connected to the t-th clock signal line, and 1 ≤ t ≤ 4K. When Ti = 12K, the output clock signal terminal of the 6p+1 stage second virtual shift register is electrically connected to the 2p+1 clock signal line, the output clock signal terminal of the 6p+3 stage second virtual shift register is electrically connected to the 2K+2p+1 clock signal line or the 2p+1-2K clock signal line, the output clock signal terminal of the 6p+5 stage second virtual shift register is electrically connected to the 2p+1 clock signal line, the output clock signal terminal of the 6p+2 stage second virtual shift register is electrically connected to the 2p+2 clock signal line, the output clock signal terminal of the 6p+4 stage second virtual shift register is electrically connected to the 2K+2p+2 clock signal line or the 2p+2-2K clock signal line, and the output clock signal terminal of the 6p+6 stage second virtual shift register is electrically connected to the 2p+2 clock signal line. If 2p+1 < 2K, the output clock signal terminal of the 6p+3 stage second virtual shift register is electrically connected to 2K+2p+1 clock signal lines, and the output clock signal terminal of the 6p+4 stage second virtual shift register is electrically connected to 2K+2p+2 clock signal lines. The display board according to claim 7 or 8, wherein if 2p+2 > 2K, the output clock signal terminal of the 6p+3 stage first virtual shift register is electrically connected to the 2p+1 - 2Kth clock signal line, and the output clock signal terminal of the 6p+4 stage first virtual shift register is electrically connected to the 2p+2 - 2Kth clock signal lines.

10. The first virtual shift register, the output shift register, and the second virtual shift register further include an output clock signal terminal, the output clock signal terminal is configured to provide an output signal to the output terminal, and in the i-th drive circuit, the output drive circuit includes a first output drive circuit and a second output drive circuit, The first output drive circuit includes an odd number of output shift registers arranged sequentially along the first direction, and the output shift registers located in the first output drive circuit are cascaded to one another. The display board according to claim 5 or 6, wherein the second output drive circuit includes an even number of output shift registers arranged sequentially along the first direction, and the output shift registers located in the second output drive circuit are cascaded to one another.

11. The i-th drive circuit is configured such that the output shift registers of the first stage to the output shift register of the Si stage are arranged sequentially along the first direction, the first virtual shift register of the first stage to the first virtual shift register of the Ri stage are arranged sequentially along the first direction, the second virtual shift register of the first stage to the second virtual shift register of the Ti stage are arranged sequentially along the first direction, the first clock signal line to the 4Kth shift register are arranged sequentially along the second direction, and the i-th drive circuit is located on the side away from the display area of ​​the drive circuit, as described in claim 10.

12. In the i-th drive circuit, odd-numbered clock signal lines are located on the side of the first output drive circuit away from the display area, and even-numbered clock signal lines are located on the side of the second output drive circuit away from the display area. If the first output drive circuit is located on the side of the second output drive circuit away from the display area, the even-numbered clock signal lines are located between the first output drive circuit and the second output drive circuit. The display board according to claim 10, wherein, when the second output drive circuit is located away from the display area of ​​the first output drive circuit, odd-numbered clock signal lines are located between the first output drive circuit and the second output drive circuit.

13. The display modes of the sub-display area include a first display mode, a second display mode, and a third display mode, wherein the resolution of the first display mode is higher than the resolution of the second display mode, and the resolution of the second display mode is higher than the resolution of the third display mode. The display board according to claim 11 or 12, wherein the clock signal of any one clock signal line includes multiple pulse signals, the duration of the pulse signals of any two clock signal lines is the same, the period of the clock signals of any two clock signal lines is the same, the generation time of the pulse signal of the k-th clock signal line and the generation time of the pulse signal of the (k+1)-th clock signal line overlap, and 1 ≤ k ≤ 4K.

14. When the sub-display area's display mode is set to the first display mode, the pulse signal generation times of any two clock signal lines among all odd-numbered clock signal lines located away from the display area of ​​the 2K+1 clock signal line do not overlap, the pulse signal generation times of any two clock signal lines among all odd-numbered clock signal lines located closer to the display area of ​​the 2K-1 clock signal line do not overlap, the pulse signal generation times of any two clock signal lines among all even-numbered clock signal lines located away from the display area of ​​the 2K+2 clock signal line do not overlap, and the pulse signal generation times of any two clock signal lines among all even-numbered clock signal lines located closer to the display area of ​​the 2K clock signal line do not overlap. When the sub-display area's display mode is set to the second display mode, the pulse signal generation times of the first K / 2 clock signal lines among all odd-numbered clock signal lines located away from the display area of ​​the 2K+1 clock signal line overlap, the pulse signal generation times of the second K / 2 clock signal lines among all odd-numbered clock signal lines located away from the display area of ​​the 2K+1 clock signal line overlap, the pulse signal generation times of the 1st clock signal line and the K+1 clock signal line do not overlap, the pulse signal generation times of the first K / 2 clock signal lines among all odd-numbered clock signal lines located closer to the display area of ​​the 2K-1 clock signal line overlap, the pulse signal generation times of the second K / 2 clock signal lines among all odd-numbered clock signal lines located closer to the display area of ​​the 2K-1 clock signal line overlap, and the pulse signal generation times of the 2K+1 clock signal line and the 3K+1 clock signal line overlap. The pulse signal generation times do not overlap, the pulse signal generation times of the first K / 2 clock signal lines among all even-numbered clock signal lines located away from the display area of ​​the 2K+2 clock signal line overlap, the pulse signal generation times of the second K / 2 clock signal lines among all even-numbered clock signal lines located away from the display area of ​​the 2K+2 clock signal line overlap, the pulse signal generation times of the 2 clock signal line and the K+2 clock signal line do not overlap, the pulse signal generation times of the first K / 2 clock signal lines among all even-numbered clock signal lines located closer to the display area of ​​the 2K clock signal line overlap, the pulse signal generation times of the second K / 2 clock signal lines among all even-numbered clock signal lines located closer to the display area of ​​the 2K clock signal line overlap, and the pulse signal generation times of the 2K+2 clock signal line and the 3K+2 clock signal line do not overlap. The display board according to claim 13, wherein when the display mode of the sub-display area is the third display mode, the pulse signal generation times of any two clock signal lines among all odd-numbered clock signal lines located away from the display area of ​​the 2K+1 clock signal line overlap, the pulse signal generation times of any two clock signal lines among all odd-numbered clock signal lines located closer to the display area of ​​the 2K-1 clock signal line overlap, the pulse signal generation times of any two clock signal lines among all even-numbered clock signal lines located away from the display area of ​​the 2K+2 clock signal line overlap, the pulse signal generation times of any two clock signal lines among all even-numbered clock signal lines located closer to the display area of ​​the 2K clock signal line overlap, the pulse signal generation time of the y-th clock signal line and the pulse signal generation time of the 2K+y-th clock signal line do not overlap, and 1 ≤ y ≤ 2K.

15. The number of rows of subpixels in any two sub-display areas is the same. When the display mode of both the i-th sub-display area and the i+1 sub-display area is the first display mode, the start time of the signal of the i-th initial signal line STU ｉ and the start time of the signal of the i+1 initial signal line STU ｉ＋１ STU ｉ＋１ = STU ｉ The relationship + (N / M) * T * ovl is satisfied, When the display mode of both the i-th sub-display area and the i+1 sub-display area is the second display mode, the start time of the signal of the i-th initial signal line STU ｉ and the start time of the signal of the i+1 initial signal line STU ｉ＋１ STU ｉ＋１ = STU ｉ The relationship + (N / (M * A / B)) * T * ovl is satisfied, When the display modes of the i-th sub-display area and the (i + 1)-th sub-display area are both the third display mode, the start time STU of the signal on the i-th initial signal line ｉ and the start time STU of the signal on the (i + 1)-th initial signal line ｉ＋１ are such that STU ｉ＋１ = STU ｉ satisfies the relational expression STU = STU + (N / (M * A / C)) * T * ovl, If the display mode of the i-th sub-display area is the first display mode, and the display mode of the i+1 sub-display area is the second display mode, then the start time of the signal of the i-th initial signal line STU ｉ and the start time of the signal of the i+1 initial signal line STU ｉ＋１ STU ｉ＋１ = STU ｉ The relationship + (N / M) * T * ovl + (T1 - T2) is satisfied, If the display mode of the i-th sub-display area is the first display mode, and the display mode of the i+1 sub-display area is the third display mode, then the start time of the signal of the i-th initial signal line is STU. ｉ and the start time of the signal of the i+1 initial signal line STU ｉ＋１ STU ｉ＋１ = STU ｉ The relationship + (N / M) * T * ovl + (T1 - T3) is satisfied, If the display mode of the i-th sub-display area is the second display mode, and the display mode of the i+1 sub-display area is the first display mode, then the start time of the signal of the i-th initial signal line STU ｉ and the start time of the signal of the i+1 initial signal line STU ｉ＋１ STU ｉ＋１ = STU ｉ The relationship + (N / (M*A / B))*T*ovl - (T1-T2) is satisfied, If the display mode of the i-th sub-display area is the second display mode, and the display mode of the i+1 sub-display area is the third display mode, then the start time of the signal of the i-th initial signal line STU ｉ and the start time of the signal of the i+1 initial signal line STU ｉ＋１ STU ｉ＋１ = STU ｉ The relationship + (N / (M*A / B))*T*ovl + (T2-T3) is satisfied, If the display mode of the i-th sub-display area is the third display mode, and the display mode of the i+1 sub-display area is the first display mode, then the start time of the signal of the i-th initial signal line STU ｉ and the start time of the signal of the i+1 initial signal line STU ｉ＋１ STU ｉ＋１ = STU ｉ The relationship + (N / (M*A / C))*T*ovl - (T1-T3) is satisfied, If the display mode of the i-th sub-display area is the third display mode, and the display mode of the i+1-th sub-display area is the second display mode, then the start time of the i-th initial signal line STUi and the start time of the i+1-th initial signal line STUi+1 are STU ｉ＋１ = STU ｉ The relationship + (N / (M*A / C))*T*ovl-(T2-T3) is satisfied, The display board according to claim 14, wherein T is the duration of the pulse signal of any one clock signal line, ovl is the overlap time of the pulse signals of two adjacent clock signal lines, A is the number of clock signal lines with different signals in the first display mode, B is the number of clock signal lines with different signals in the second display mode, B < A, C is the number of clock signal lines with different signals in the third display mode, C < A, T1 is the period of the pulse signal of any one clock signal line in the first display mode, T2 is the period of the pulse signal of any one clock signal line in the second display mode, and T3 is the period of the pulse signal of any one clock signal line in the third display mode.

16. The display board according to claim 15, wherein the generation time of the output signal of an output shift register connected to the last row of subpixels in the i-th sub-display area and the generation time of the output signal of an output shift register connected to the first row of subpixels in the (i+1)-th sub-display area overlap, and the overlapping time is half the duration of the output signal of the output shift register connected to the last row of subpixels in the i-th sub-display area.

17. The first signal line includes an illumination signal line, and in the same sub-display area, when u is a constant value, the occurrence times of the illumination signal line connected to the pixel driving circuit of K rows of sub-pixels satisfying 3(u+l)+1 overlap, u is an integer multiple of K, and 0≦l≦K-1. When u is a constant value, the occurrence times of the active level signal on the light emission signal line connected to the pixel drive circuit of the K rows of subpixels satisfying 3(u+l)+2 overlap. When u is a constant value, the occurrence times of the active level signal on the light emission signal line connected to the pixel drive circuit of the K rows of subpixels satisfying 3(u+l)+3 overlap. The time at which the light emission signal line connected to the pixel drive circuit of the subpixel in the 3u+1 row becomes an active level signal is earlier than the time at which the light emission signal line connected to the pixel drive circuit of the subpixel in the 3u+2 row becomes an active level signal, the time at which the light emission signal line connected to the pixel drive circuit of the subpixel in the 3u+2 row becomes an active level signal is earlier than the time at which the light emission signal line connected to the pixel drive circuit of the subpixel in the 3u+3 row becomes an active level signal, and the time at which the light emission signal line connected to the pixel drive circuit of the subpixel in the 3u+1 row becomes an active level signal is earlier than the time at which the light emission signal line connected to the pixel drive circuit of the subpixel in the 3u+3K+1 row becomes an active level signal. The display board according to claim 16, wherein the time at which the light-emitting signal line connected to the raw pixel driving circuit becomes an active level signal is earlier than the time at which the light-emitting signal line connected to the pixel driving circuit of the 3u+2 row sub-pixel becomes an active level signal is earlier than the time at which the light-emitting signal line connected to the pixel driving circuit of the 3u+3K+2 row sub-pixel becomes an active level signal is earlier than the time at which the light-emitting signal line connected to the pixel driving circuit of the 3u+3 row sub-pixel becomes an active level signal is earlier than the time at which the light-emitting signal line connected to the pixel driving circuit of the 3u+3K+3 row sub-pixel becomes an active level signal.

18. The first signal line further includes a first scan signal line, a second scan signal line, and a third scan signal line. Pixel drive circuits located in the same row of subpixels are connected to the same second scan signal line, the same third scan signal line, and the same light emission signal line, and pixel drive circuits located in the same row of subpixels are electrically connected to two first scan signal lines. The display board according to claim 1, wherein a pixel driving circuit located at the nth row, sth column subpixel is connected to the first first scan signal line, a pixel driving circuit located at the nth row, s+1 column subpixel is connected to the second first scan signal line, an odd-numbered output shift register is electrically connected to the first scan signal line, an even-numbered output shift register is electrically connected to the second first scan signal line, 1 ≤ n ≤ N, 1 ≤ s ≤ S, and S is the total number of columns of subpixels in the display area.

19. The system further comprises a reference signal line, an initial signal line, and a first power line located at least partially within the display area, the reference signal line, the initial signal line, and the first power line extending along a second direction and electrically connected to a first or second electrode of some transistors in the pixel driving circuit. The display substrate according to claim 18, wherein in the nth row subpixel, the reference signal line, second scan signal line, initial signal line, third scan signal line, light emission signal line, first power line, first scan signal line, and second first scan signal line are arranged sequentially along the first direction, and the reference signal line is located on the side of the second scan signal line closest to the (n-1)th row subpixel.

20. The system further comprises a second signal line, the second signal line being electrically connected to a pixel driving circuit, and the second signal line extending along a first direction. The display board according to claim 19, wherein the second signal line includes a data signal line, a power connection line, a reference connection line, and an initial connection line, the power connection line is electrically connected to the first power line, the reference connection line is electrically connected to the reference signal line, and the initial connection line is electrically connected to the initial signal line.

21. At least one fanout wiring includes a first fanout connector, a second fanout connector, and a third fanout connector, wherein the first fanout connector, the second fanout connector, and the third fanout connector are arranged sequentially along a second direction, and the first fanout connector and the third fanout connector extend along the second direction. In the i-th sub-fanout area, the first fanout connection is electrically connected to the output terminal of the output drive circuit of the i-th drive circuit and to the second fanout connection, and the third fanout connection is electrically connected to the first signal line of the i-th sub-display area and to the second fanout connection, and at least one sub-fanout area includes a first region and a second region arranged sequentially along a first direction, and the extending direction of the second fanout connection of the fanout wiring located in the first region intersects with the extending direction of the second fanout connection of the fanout wiring located in the second region, The fan-out wiring includes a first fan-out wiring, a second fan-out wiring, a third fan-out wiring, a fourth fan-out wiring, and a fifth fan-out wiring arranged along a first direction. The display board according to claim 20, wherein the first fan-out wiring is electrically connected to the first first scan signal line, the second fan-out wiring is electrically connected to the second first scan signal line, the third fan-out wiring is electrically connected to the second scan signal line, the fourth fan-out wiring is electrically connected to the third scan signal line, and the fifth fan-out wiring is electrically connected to the light-emitting signal line.

22. The fan-out area further comprises a reference signal power supply line and a first power supply line, wherein the first power supply line is located on the side of the reference signal power supply line closer to the display area, the reference signal power supply line and the first power supply line extend along a first direction, the reference signal power supply line is electrically connected to the reference signal line, and the first power supply line is electrically connected to the first power line. The display board according to claim 21, wherein the orthographic projection of the reference signal power supply line at its base and the orthographic projection of the third fan-out connection of at least one fan-out wiring at its base overlap at least partially, and the orthographic projection of the first power supply line at its base and the orthographic projection of the third fan-out connection of at least one fan-out wiring at its base overlap at least partially.

23. The reference signal feed line includes a first sub-reference signal feed line and a second sub-reference signal feed line, the first sub-reference signal feed line and the second sub-reference signal feed line are installed on different layers and are electrically connected to each other, and the orthographic projection of the base of the first sub-reference signal feed line and the orthographic projection of the base of the second sub-reference signal feed line overlap at least partially. Multiple first openings are provided in the first sub-reference signal power supply line, multiple second openings are provided in the second sub-reference signal power supply line, and multiple third openings are provided in the first power supply line. The display substrate according to claim 22, wherein the orthographic projection of at least one of the first and second apertures on its base and the orthographic projection of the third fan-out connection on its base at least partially overlap, and the orthographic projection of the third aperture on its base and the orthographic projection of the third fan-out connection on its base at least partially overlap.

24. The pixel driving circuit further comprises a circuit structure layer installed on the base, the circuit structure layer including a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, and the pixel driving circuit further includes a capacitor, the capacitor including a first electrode plate and a second electrode plate. The first conductive layer includes at least a plurality of gate electrodes of transistors and first electrodes of capacitors. The second conductive layer includes at least the second electrode plate of the capacitor and the first sub-reference feed line. The third conductive layer includes at least a first scanning signal line, a second scanning signal line, a third scanning signal line, a light emission signal line, an initial signal line, a reference signal line, a first power supply line, a second sub-reference power supply line, and a first power supply line. The display board according to claim 23, wherein the fourth conductive layer includes at least data signal lines, fan-out wiring, power connection lines, reference connection lines, and initial connection lines.

25. A display device comprising a display board according to any one of claims 1 to 24.

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