Display board and its manufacturing method, display panel, display device

Abstract

The display board has a display area and a peripheral area located on at least one side of the display area. The display board includes three first power lines and a light emission control circuit. The three first power lines are provided in the peripheral area. The first power lines extend along substantially a first direction and are configured to transmit a first signal or a second signal. The light emission control circuit is provided in the peripheral area. The light emission control circuit includes a plurality of cascaded light emission shift registers. At least one first power line is located on the side of the light emission control circuit away from the display area, and at least two other first power lines overlap the light emission control circuit, dividing the light emission shift registers into a first light emission subcircuit, a second light emission subcircuit, and a third light emission subcircuit. The first, second, and third light emission subcircuits are sequentially adjacent to the display area. Both the first and third light emission subcircuits include a first type of transistor connected to a first power line, and each of the first type of transistors is connected to the nearest first power line.

Description

Technical Field

[0001] (Cross - reference to related applications) This application claims the priority of a Chinese patent application with application number 202310574391.7, filed on May 19, 2023, the entire content of which is incorporated herein by reference.

[0002] This disclosure relates to the field of display technology, and particularly to a display substrate, a manufacturing method thereof, a display panel, and a display device.

Background Art

[0003] With the rapid development of display technology, display devices have gradually become popular in people's lives. Among these, Organic Light Emitting Diode (abbreviated as OLED) has advantages such as self - emission, low power consumption, wide viewing angle, high - speed response, high contrast, and flexible display, and is widely used in smart products such as mobile phones, televisions, and notebook computers.

Summary of the Invention

Means for Solving the Problems

[0004] According to one aspect, a display substrate is provided. The display substrate has a display area and a peripheral area located on at least one side of the display area. The display substrate includes a plurality of first power lines and a light - emitting control circuit. The first power lines are provided in the peripheral area. The first power lines extend along a substantially first direction and are configured to transmit a first signal or a second signal.

[0005] The light-emitting control circuit is provided in the peripheral region. The light-emitting control circuit includes a plurality of cascaded light-emitting shift registers. At least one first power line is located on the side of the light-emitting control circuit away from the display area, and at least two other first power lines overlap with the light-emitting control circuit, dividing the light-emitting shift registers into a first light-emitting subcircuit, a second light-emitting subcircuit, and a third light-emitting subcircuit. The first light-emitting subcircuit, the second light-emitting subcircuit, and the third light-emitting subcircuit are sequentially positioned closer to the display area.

[0006] Both the first light-emitting subcircuit and the third light-emitting subcircuit include a first type of transistor connected to the first power line, and each of the first type of transistors is connected to the nearest first power line.

[0007] In some embodiments, the display board further includes a plurality of second power lines, two of which extend substantially along the first direction and are configured to transmit a third or fourth signal. Of the plurality of second power lines, at least one second power line is provided on the side of the light emission control circuit away from the display area, and at least one other second power line is provided between the light emission control circuit and the display area. Both the first light emission subcircuit and the third light emission subcircuit include a second type of transistor, and the second type of transistor in the first light emission subcircuit and the third light emission subcircuit are each connected to the nearest second power line.

[0008] In some embodiments, the first and second power lines of the light emission control circuit, located on the side away from the display area, have orthogonal projections onto a reference plane that overlap at least partially. The reference plane is the plane on which the non-display side of the display substrate is located.

[0009] In some embodiments, of the first and second power lines located on the side of the light emission control circuit away from the display area, the first power line is located on the side of the second power line away from the display area or closer to the display area.

[0010] In some embodiments, the width of the second power line connected to the third light-emitting subcircuit is smaller than the width of the second power line connected to the first light-emitting subcircuit.

[0011] In some embodiments, the display board further includes a plurality of second connection lines extending substantially along a second direction, the second direction intersecting the first direction. One end of each second connection line is connected to the second type of transistor, and the other end is connected to the nearest second power line.

[0012] In some embodiments, the at least two second power lines include one second power line of a first type and one second power line of a second type. The second power line of the first type is configured to transmit a third signal. The second power line of the first type is provided on the side of the light emission control circuit away from the display area. The second power line of the second type is configured to transmit a fourth signal. The fourth power line of the second type is provided between the light emission control circuit and the display area.

[0013] In some embodiments, the first light-emitting subcircuit is connected to a first power signal terminal, a second power signal terminal, a first signal input terminal, a first reset signal terminal, a first clock signal terminal, a second clock signal terminal, a first cascade output terminal, a first control node, and a second control node. The first light-emitting subcircuit is configured to output one of the first signal, second signal, third signal, and fourth signal to the first control node, the second control node, and the first cascade output terminal, respectively, under the control of signals from the first signal input terminal, the first clock signal terminal, and the second clock signal terminal, and to output a first clock signal to the first control node and a first signal or a second signal to the second control node, under the control of a signal from the first reset signal terminal.

[0014] The second light-emitting subcircuit is coupled to the first control node and the enable signal output terminal. The second light-emitting subcircuit is configured to boost the voltage of the first control node when the first signal or the second signal is output from the enable signal output terminal.

[0015] The third light-emitting subcircuit is coupled to the first power signal terminal, the second power signal terminal, the first control node, the second control node, and the enable signal output terminal. The third light-emitting subcircuit is configured to output one of the first, second, third, and fourth signals to the enable signal output terminal under the voltage control of the first and second control nodes, and to boost the voltage of the second control node when the third or fourth signal is output from the enable signal output terminal.

[0016] In some embodiments, the width of the first power line connected to the third light-emitting subcircuit is greater than the width of the first power line connected to the first light-emitting subcircuit.

[0017] In some embodiments, the display board further includes a plurality of first connection lines extending substantially along a second direction, the second direction intersecting the first direction. One end of each first connection line is connected to a first type of transistor, and the other end is connected to the nearest first power supply line.

[0018] In some embodiments, the display board further includes a first start signal line, a first clock signal line, a second clock signal line, and a first reset signal line. The first start signal line is connected to the light-emitting control circuit. The first start signal line is located on the side of the light-emitting control circuit away from the display area. The first clock signal line is connected to the light-emitting control circuit. The first clock signal line is located on the side of the light-emitting control circuit away from the display area. The second clock signal line is connected to the light-emitting control circuit. The second clock signal line is located on the side of the light-emitting control circuit away from the display area. The first reset signal line is connected to the light-emitting control circuit. The first reset signal line is located between two first power lines that overlap with the light-emitting control circuit.

[0019] In some embodiments, the display board further includes a plurality of third power lines and a scanning drive circuit. The plurality of third power lines are provided in the peripheral region. The third power lines extend substantially along the first direction and are configured to transmit a fifth or sixth signal.

[0020] The scanning drive circuit is provided in the peripheral region. The scanning drive circuit includes a plurality of cascaded scanning shift registers. At least three third power lines overlap with the scanning drive circuit, dividing the scanning shift registers into a first scanning subcircuit, a second scanning subcircuit, a third scanning subcircuit, and a fourth scanning subcircuit, with the first, second, third, and fourth scanning subcircuits sequentially approaching the display region.

[0021] The first, second, and third scanning subcircuits each include a third type of transistor connected to the third power line, and the third type of transistor in the first, second, and third scanning subcircuits is connected to the nearest third power line.

[0022] In some embodiments, the display board further includes a plurality of fourth power lines extending substantially along the first direction, the plurality of fourth power lines configured to transmit a seventh or eighth signal. Of the plurality of fourth power lines, at least one fourth power line is provided between the second scanning subcircuit and the third scanning subcircuit, and at least one other fourth power line is provided between the fourth scanning subcircuit and the display area. The second and fourth scanning subcircuits include a fourth type of transistor, the fourth type of transistor in the second and fourth scanning subcircuits being connected to the nearest fourth power line, respectively.

[0023] In some embodiments, in the display board, the third and fourth power lines located between the second and third scanning subcircuits have orthogonal projections onto the reference plane that overlap at least partially. The reference plane is the plane on which the display surface of the display board is located.

[0024] In some embodiments, of the third and fourth power lines located between the second and third scanning subcircuits, the third power line is located on the side of the fourth power line that is away from the display area or closer to the display area.

[0025] In some embodiments, the width of the third power line connected to the third scanning subcircuit is smaller than the width of the third power line connected to the first scanning subcircuit and / or the second scanning subcircuit.

[0026] In some embodiments, the display substrate includes a plurality of fourth connection lines extending substantially along a second direction, and the second direction intersects the first direction. One end of each fourth connection line is connected to a transistor of the fourth type, and the other end is connected to the nearest fourth power line.

[0027] In some embodiments, the first scanning sub-circuit is connected to a third power signal terminal, a second signal input terminal, a third signal input terminal, a first voltage terminal, a second voltage terminal, a second reset signal terminal, a second cascade output terminal, a third control node, and a fourth control node.

[0028] The first scanning sub-circuit is configured to output a first voltage signal or a second voltage signal to the third control node under the control of the voltages of the second signal input terminal and the third signal input terminal, output a fifth signal or a sixth signal to the fourth control node, and output a fifth signal or a sixth signal to the third control node under the control of a signal from the second reset signal terminal.

[0029] The second scanning sub-circuit is coupled to the third power signal terminal, the fourth power signal terminal, the third control node, the fourth control node, and the second cascade output terminal. The second scanning sub-circuit is configured to output a fifth signal or a sixth signal to the second cascade output terminal under the control of the voltage of the fourth control node, and output a fifth signal or a sixth signal to the fourth control node under the control of a signal from the second cascade output terminal or the fourth power signal terminal.

[0030] The third scanning subcircuit is coupled to the third power signal terminal, the third clock signal terminal, the third control node, the fourth control node, the second cascade output terminal, and the scanning signal output terminal. The third scanning subcircuit is configured to output a third clock signal to the second cascade output terminal and one of the third clock signal, the fifth signal, or the sixth signal to the scanning signal output terminal, under the control of the voltages of the third and fourth control nodes.

[0031] The fourth scanning subcircuit is coupled to the fourth clock signal terminal, the fourth power signal terminal, the fourth control node, and the scanning signal output terminal, and is configured to output a seventh or eighth signal to the scanning signal output terminal under the control of a signal from the fourth power signal terminal, and to output a fourth clock signal to the fourth control node under the control of a signal from the fourth clock signal terminal.

[0032] In some embodiments, the display board includes a plurality of third connection lines extending substantially along a second direction, the second direction intersecting the first direction. One end of each third connection line is connected to a transistor of the third type, and the other end is connected to the nearest third power line.

[0033] In some embodiments, the plurality of third power lines include two first type third power lines and one second type third power line. The first type third power line is configured to transmit a fifth signal. One first type third power line is provided between the first scanning subcircuit and the second scanning subcircuit, and the other first type third power line is provided between the second scanning subcircuit and the third scanning subcircuit. The second type third power line is configured to transmit a sixth signal. The second type third power line is provided between the third scanning subcircuit and the fourth scanning subcircuit.

[0034] In some embodiments, the display board further includes a second start signal line, a third start signal line, a first voltage signal line, a second voltage signal line, a third clock signal line, a fourth clock signal line, and a second reset signal line.

[0035] The second start signal line is connected to the scanning drive circuit. The second start signal line is located on the side of the scanning drive circuit away from the display area. The third start signal line is connected to the scanning drive circuit, and along the first direction, the third start signal line is located on one side of the scanning drive circuit. The first voltage signal line is connected to the scanning drive circuit. The first voltage signal line is located on the side of the scanning drive circuit away from the display area. The second voltage signal line is connected to the scanning drive circuit. The second voltage signal line is located on the side of the scanning drive circuit away from the display area.

[0036] The third clock signal line is connected to the scanning drive circuit. The third clock signal line is located between the scanning drive circuit and the display area. The fourth clock signal line is connected to the scanning drive circuit. The fourth clock signal line is located between the scanning drive circuit and the display area. The second reset signal line is connected to the scanning drive circuit. The second reset signal line is located between the first scanning subcircuit and the second scanning subcircuit.

[0037] In another embodiment, a display panel is provided. The display panel includes a display substrate as described in any of the above embodiments.

[0038] In yet another embodiment, a display device is provided. The display device includes a display panel as described in any of the above embodiments.

[0039] In yet another embodiment, a method for manufacturing a display board is provided. The method for manufacturing the display board is a method for manufacturing a display board according to any of the above embodiments, including a first power line, a second power line, a third power line, a fourth power line, a first start signal line, a second start signal line, a third start signal line, a first voltage signal line, a second voltage signal line, a first clock signal line, a second clock signal line, a third clock signal line, a first reset signal line, and a second reset signal line.

[0040] The method for manufacturing the display substrate includes the step of sequentially forming a semiconductor layer, a gate insulating layer, a gate conductive layer, an interlayer insulating layer, a first source-drain conductive layer, and a first flat layer on the base. The first source-drain conductive layer includes at least one of the following: a first power line, a second power line, a third power line, a fourth power line, a first start signal line, a second start signal line, a third start signal line, a first voltage signal line, a second voltage signal line, a first clock signal line, a second clock signal line, a third clock signal line, a first reset signal line, and a second reset signal line.

[0041] In some embodiments, the first power line, the second power line, the third power line, the fourth power line, the first start signal line, the second start signal line, the third start signal line, the first voltage signal line, the second voltage signal line, the first clock signal line, the second clock signal line, the third clock signal line, the first reset signal line, and the second reset signal line are arranged such that their orthogonal projection onto the reference plane is shifted. The reference plane is the plane on which the non-display side of the display board is located.

[0042] The first source-drain conductive layer includes the first power line, the second power line, the third power line, the fourth power line, the first start signal line, the second start signal line, the third start signal line, the first voltage signal line, the second voltage signal line, the first clock signal line, the second clock signal line, the third clock signal line, the first reset signal line, and the second reset signal line.

[0043] In some embodiments, the first and second power lines located on the side away from the display area of ​​the light emission control circuit have orthogonal projections onto a reference plane that overlap at least partially. And / or, the third and fourth power lines located between the second and third scanning subcircuits have orthogonal projections onto the reference plane that overlap at least partially. The reference plane is the plane on which the non-display side of the display substrate is located.

[0044] The method for manufacturing the display substrate further includes the steps of forming a second source-drain conductive layer on the side of the first flat layer away from the base, and forming a second flat layer on the side of the second source-drain conductive layer away from the base.

[0045] If the orthogonal projections onto the reference plane of the first power line and the second power line, located on the side away from the display area of ​​the light emission control circuit, overlap at least partially, the first source-drain conductive layer includes the first power line, the third power line, the fourth power line, the first start signal line, the second start signal line, the third start signal line, the first voltage signal line, the second voltage signal line, the first clock signal line, the second clock signal line, the third clock signal line, the first reset signal line, and the second reset signal line. The second source-drain conductive layer includes the second power line.

[0046] If the orthogonal projections of the third and fourth power lines located between the second and third scanning subcircuits onto the reference plane overlap at least partially, the first source-drain conductive layer includes the first power line, the second power line, the third power line, the first start signal line, the second start signal line, the third start signal line, the first voltage signal line, the second voltage signal line, the first clock signal line, the second clock signal line, the third clock signal line, the first reset signal line, and the second reset signal line. The second source-drain conductive layer includes the fourth power line.

[0047] If the orthogonal projections of the first and second power lines located away from the display area of ​​the light emission control circuit onto the reference plane overlap at least partially, and the orthogonal projections of the third and fourth power lines located between the second and third scanning subcircuits onto the reference plane overlap at least partially, the first source-drain conductive layer includes the first power line, the third power line, the first start signal line, the second start signal line, the third start signal line, the first voltage signal line, the second voltage signal line, the first clock signal line, the second clock signal line, the third clock signal line, the first reset signal line, and the second reset signal line. The second source-drain conductive layer includes the second power line and the fourth power line.

[0048] To more clearly illustrate the technical solutions of this disclosure, some of the drawings used in some embodiments of this disclosure are briefly described below. The drawings in the following description are only those of some embodiments of this disclosure, and it will be obvious to those skilled in the art that other drawings can be obtained from these. Furthermore, the drawings in the following description are not intended to limit the actual size of the product relating to the embodiments of this disclosure, the actual flow of the method, the actual sequence of signals, etc., and can be considered as schematic diagrams. [Brief explanation of the drawing]

[0049] [Figure 1]This is a configuration diagram of a display device according to several embodiments. [Figure 2] This is a configuration diagram of another display device according to several embodiments. [Figure 3] This is a cross-sectional view along the cutting line A-A' in Figure 1. [Figure 4] This is a configuration diagram of a display panel according to several embodiments. [Figure 5] This is a cross-sectional view along the cutting line B-B' in Figure 4. [Figure 6] This is another cross-sectional view along the cutting line B-B' in Figure 4. [Figure 7] This is a configuration diagram of the gate drive circuit for a display panel according to several embodiments. [Figure 8] This diagram shows the configuration of a light emission control circuit and signal lines connected thereto for a display panel according to several embodiments. [Figure 9] This is a diagram showing the configuration of a light emission control circuit and the signal lines connected thereto for another display panel according to several embodiments. [Figure 10] Figure 8 shows the configuration diagram of the light emission control circuit of the display panel and the signal lines connected thereto. [Figure 11] This is a configuration diagram of the first light-emitting subcircuit of a display panel according to several embodiments. [Figure 12] This is a diagram showing the configuration of a second light-emitting subcircuit of a display panel according to several embodiments. [Figure 13] This is a configuration diagram of the third light-emitting subcircuit of a display panel according to several embodiments. [Figure 14] This is a circuit diagram of a light-emitting shift register for a display panel according to several embodiments. [Figure 15] This diagram shows the configuration of a scanning drive circuit for a display panel and the signal lines connected thereto, according to several embodiments. [Figure 16] This is a diagram showing the configuration of a scanning drive circuit and the signal lines connected thereto for another display panel according to several embodiments. [Figure 17] This is a configuration diagram of the first scanning subcircuit of a display panel according to several embodiments. [Figure 18] This is a diagram showing the configuration of the second scanning subcircuit of a display panel according to several embodiments. [Figure 19] This is a diagram showing the configuration of the third scanning subcircuit of a display panel according to several embodiments. [Figure 20] This is a diagram showing the configuration of the fourth scanning subcircuit of a display panel according to several embodiments. [Figure 21] This is a circuit diagram of a scanning shift register for a display panel according to several embodiments. [Modes for carrying out the invention]

[0050] The following describes, with reference to the attached drawings, some of the technical solutions of the embodiments of this disclosure clearly and completely, although it is clear that the embodiments described are only some of the embodiments of this disclosure, not all of them. All other embodiments that can be obtained by those skilled in the art based on the embodiments provided by this disclosure are within the scope of this disclosure.

[0051] Unless otherwise stated in the context, the term “comprise” and other forms, such as the third-person singular “comprises” and the present participle “comprising,” are interpreted in an open and comprehensive sense, meaning “including, but not limited to.” In the description, terms such as “one embodiment,” “some embodiments,” “exemplary embodiments,” “example,” “specific example,” or “some examples” are intended to indicate that certain features, structures, materials, or properties related to such embodiment or example are included in at least one embodiment or example of this disclosure. The general indications of the above terms do not necessarily refer to the same embodiment or example. Furthermore, any specific features, structures, materials, or properties described may be included in any one or more embodiments or examples in any appropriate manner.

[0052] Hereafter, the terms “first” and “second” are for illustrative purposes only and should not be understood as implicitly indicating or suggesting the relative importance of, or referring to, the number of technical features. Therefore, the features defining “first” and “second” may explicitly or implicitly include one or more features. In the description of the embodiments of this disclosure, “multiple” means two or more unless otherwise specified.

[0053] In describing some embodiments, the terms “coupling” and “connection” and their derived expressions may be used. The term “connection” should be understood in a broad sense; for example, “connection” may be a fixed connection, a detachable connection, a single unit, a direct connection, or an indirect connection via an intermediate medium. The term “coupling” means, for example, that two or more components are in direct physical or electrical contact. The terms “coupling” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other but are still cooperating or interacting with each other. The embodiments disclosed herein are not necessarily limited to those disclosed herein.

[0054] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," and both include A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0055] "A and / or B" includes three combinations: A only, B only, and a combination of A and B.

[0056] Where used herein, the term “when” may optionally be interpreted as “when…” or “on the occasion of…” or “in response to a decision” or “in response to detection.” Similarly, where contextually, the phrases “when…” or “when (the described condition or event) is detected” may optionally be interpreted as “when…” or “in response to a decision of…” or “when (the described condition or event) is detected” or “in response to (the described condition or event) being detected.”

[0057] The use of “applicable” or “configured to” in this specification means open and inclusive language and does not exclude devices that are applicable or configured to perform additional tasks or steps.

[0058] Furthermore, the use of "based on" implies an open and inclusive language, as a process, step, calculation, or other action "based on" one or more conditions or values ​​may actually be based on additional conditions or exceed the stated values.

[0059] Given the errors associated with the measurements under consideration and a certain number of measurements (i.e., limitations of the measurement system), as used herein, “about,” “approximate,” or “near” also means that the stated value is included and within the range of acceptable deviations to a particular value determined by those skilled in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0060] As used herein, “parallel,” “perpendicular,” and “equal” include the situation described and similar situations, the range of such similar situations being within the range of acceptable deviations that a person skilled in the art would determine, for example, taking into account the measurement under consideration and the error associated with the measurement of a particular quantity (i.e., the limits of the measuring system). For example, “parallel” includes absolutely parallel and nearly parallel, where the range of acceptable deviation for nearly parallel may be, for example, a deviation of 5° or less; “perpendicular” includes absolutely perpendicular and nearly perpendicular, where the range of acceptable deviation for nearly perpendicular may be, for example, a deviation of 5° or less; “equal” includes absolutely equal and nearly equal, where within the range of acceptable deviations for nearly equal, for example, the difference between the two equals may be 5% or less of either.

[0061] When a layer or element is described as being on another layer or substrate, please understand that the layer or element may exist directly on the other layer or substrate, or an intermediate layer may exist between the layer or element and the other layer or substrate.

[0062] Exemplary embodiments are described herein with reference to sectional and / or plan views, which serve as ideal illustrative drawings. In the drawings, for clarity, the thickness of the layers and the area of ​​the regions are enlarged. Thus, variations in shape from the drawings are possible, for example, due to manufacturing techniques and / or tolerances. Accordingly, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, and include, for example, shape deviations due to manufacturing. For example, an etching region shown as a rectangle typically has curved characteristics. Thus, the regions shown in the drawings are essentially schematic, and their shapes do not represent the actual shapes of the regions in the apparatus, nor do they limit the scope of the exemplary embodiments.

[0063] In this specification, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art to which this disclosure belongs, unless otherwise defined. It should be further understood that, unless explicitly defined herein, terms (e.g., terms defined in a general dictionary) should be interpreted as having meanings consistent with those in the context of the relevant art, and not as ideal or overly formalized meanings.

[0064] In this disclosure, terms such as “down,” “below,” “up,” and “top” are used to describe the relationships and associations of components shown in the drawings. The terms are relative concepts and may be described based on the orientation shown in the drawings, or based on the sequence of process steps, but are not limited to these.

[0065] The term "opposing" means that the first element can directly or indirectly oppose the second element. When a third element intervenes between the first and second elements, the first and second elements are still opposed to each other, but should be understood as opposing each other indirectly.

[0066] In the shift register according to the embodiments of this disclosure, the transistor used in the shift register may be a thin-film transistor (TFT), a field-effect transistor (metal oxide semiconductor, MOS), or any other switching element with the same characteristics. In the embodiments of this disclosure, thin-film transistors will be used as examples in the explanation.

[0067] In the shift register according to the embodiments of this disclosure, the control electrode of each thin-film transistor used in the shift register is the gate of the transistor, the first electrode is one of the source and drain of the thin-film transistor, and the second electrode is the other of the source and drain of the thin-film transistor. The source and drain of the thin-film transistor may be structurally symmetrical, so the source and drain do not need to be structurally distinguished, that is, the first electrode and the second electrode of the thin-film transistor in the embodiments of this disclosure do not need to be structurally distinguished. For example, if the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain, and for example, if the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0068] In embodiments of this disclosure, the capacitor may be a capacitor element fabricated separately by process. For example, it may be a capacitor element realized by fabricating dedicated capacitor electrodes, each electrode of the capacitor may be made of a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitor may be a parasitic capacitance between transistors, may be realized by the transistor itself and other devices or lines, or may be realized by utilizing the parasitic capacitance between lines of the circuit itself.

[0069] In the shift register according to the embodiment of this disclosure, the nodes such as the first node, the second node, the first control node, and the second control node do not represent actual existing components, but rather represent the confluence points of related electrical connections in the circuit diagram; that is, these nodes are equivalent to the confluence points of electrically related electrical connections in the circuit diagram.

[0070] In the embodiment of the present disclosure, "low level" of the shift register means a voltage that can turn on a P-type transistor that is the target of the operation, but cannot turn on a N-type transistor that is the target of the operation (i.e., it can turn off the N-type transistor), while "high level" means a voltage that can turn on a N-type transistor that is the target of the operation, but cannot turn on a P-type transistor that is the target of the operation (i.e., it can turn off the P-type transistor).

[0071] As shown in Figures 1 and 2, some embodiments of the present disclosure provide a display device 1000 which may be any device that displays either text or images, whether dynamic (e.g., video) or static (e.g., still images).

[0072] For example, the display device 1000 may be any product or component with display capabilities, such as a television, laptop, tablet, mobile phone, personal digital assistant (PDA), navigator, wearable device, or virtual reality (VR) device.

[0073] For example, as shown in Figure 1, the display device 1000 may be a portable display product, for example, the display device 1000 may be the mobile phone shown in Figure 1. As another example, referring to Figure 2, the display device 1000 may be a wearable device, for example, the display device 1000 may be the wristwatch shown in Figure 2.

[0074] Hereinafter, embodiments of the present disclosure will be schematically described using the case where the display device 1000 is a mobile phone as shown in Figure 1 as an example, but the embodiments of the present disclosure are not limited thereto.

[0075] In some embodiments, referring to Figure 3, the display device 1000 includes a display panel 100.

[0076] Here, the display panel 100 includes an Idemitsu side and a non-Idemitsu side, which are provided opposite each other. The Idemitsu side is the side of the display panel 100 used for display, i.e., the upper side in Figure 3.

[0077] For example, as shown in Figure 3, the display device 1000 may further include a housing 200, a cover 300, a circuit board 400, and other electronic components.

[0078] Referring to Figure 3, the cover 300 may be a single-layer glass cover or may include a stack of multilayer sub-covers. The embodiments of this disclosure are not specifically limited thereto.

[0079] As shown in Figure 3, the longitudinal cross-section of the housing 200 is, for example, U-shaped, and the display panel 100 and circuit board 400 are housed inside the housing 200, with the cover 300 located at the opening of the housing 200. Here, the circuit board 400 is located on the side of the display panel 100 away from the cover 300, and the circuit board 400 is connected to the display panel 100 to supply the display panel 100 with desired display signals.

[0080] The above-mentioned display panel 100 comes in various types and can be selected and installed according to actual needs.

[0081] The display panel 100 described above may, for example, be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, and the embodiments of this disclosure are not specifically limited thereto.

[0082] Hereinafter, several embodiments of this disclosure will be schematically described, using the case where the above-mentioned display panel 100 is an OLED display panel as an example.

[0083] In some embodiments, referring to Figures 4 and 5, the display panel 100 includes a display substrate 110 and an encapsulation layer 111 for enclosing the display substrate 110.

[0084] Here, the display board 110 includes a display side and a non-display side that are provided opposite each other, and a sealing layer 111 is provided on the display side of the display board 110 to prevent moisture and oxygen from the external environment from entering the display panel 100 and shortening the lifespan of the display panel 100.

[0085] Here, the sealing layer 111 may be a sealing film or a sealing substrate.

[0086] In some embodiments, referring to Figure 4, the display board 110 has a display area A and a peripheral area B provided on at least one side of the display area A. Figure 4 shows an example in which the peripheral area B is provided so as to surround the display area A.

[0087] Here, display area A is the area where the image is displayed, and it is provided with multiple subpixels P.

[0088] As an example, referring to Figure 4, the display board 110 includes a base 11 and a plurality of sub-pixels P provided on one side of the base 11 and located in the display area A.

[0089] The above-mentioned base 11 can be of various types and can be selected and installed according to actual needs.

[0090] For example, the base 11 may be a rigid base. For example, the rigid base may be a glass base or a polymethyl methacrylate (PMMA) base.

[0091] For example, base 11 may be a flexible base. For example, the flexible base may be a polyethylene terephthalate (PET) base, a polyethylene naphthalate (PEN) base, or a polyimide (PI) base.

[0092] Referring to Figures 4, 5, and 6, each sub-pixel P includes a light-emitting element 10 and a pixel circuit 20. The pixel circuit 20 includes a plurality of thin-film transistors 30.

[0093] As shown in Figures 5 and 6, the thin-film transistor 30 has a semiconductor channel 31, a source 32, a drain 33, and a gate 34, and both the source 32 and the drain 33 are in contact with the semiconductor channel 31.

[0094] As shown in Figures 5 and 6, the light-emitting element 10 includes a first electrode 11 electrically connected to the source 32 or drain 33 of a thin-film transistor 30, a light-emitting functional layer 12, and a second electrode 13. Figures 5 and 6 schematically show, as an example, that the first electrode 11 is electrically connected to the drain 33 of the thin-film transistor 30.

[0095] The above-mentioned light-emitting functional layer 12 may consist only of a light-emitting layer, or it may consist of a light-emitting layer plus at least one of the following: an Election Transporting Layer (ETL), an Election Injection Layer (EIL), a Hole Transporting Layer (HTL), and a Hole Injection Layer (HIL).

[0096] In some embodiments, as shown in Figures 5 and 6, the display substrate 110 further includes a pixel definition layer PDL having multiple apertures, with one light-emitting device 10 provided in one of the apertures.

[0097] In some embodiments, as shown in Figures 5 and 6, the display substrate 110 further includes a spacer PS provided between the pixel defining layer PDL and the first electrode 11 of the light-emitting element 10, which can support the mask during the process so that the gap between the mask and the pixel defining layer PDL is uniform.

[0098] In some embodiments, as shown in Figure 4, all subpixels P are arranged in multiple rows and multiple columns, each embodiment containing multiple subpixels P arranged along a first direction X, and each row containing multiple subpixels P arranged along a second direction Y, where the first direction X intersects the second direction Y. For example, the first direction X is approximately perpendicular to the second direction Y.

[0099] The first direction X may be, for example, the column direction in which multiple subpixels P are arranged, and the second direction Y may be, for example, the row direction in which multiple subpixels P are arranged.

[0100] In the following, several embodiments of the present disclosure will be illustrated by taking the case in which all subpixels P are arranged in multiple rows and multiple columns as an example, but the embodiments of the present disclosure are not limited thereto. Furthermore, multiple subpixels P arranged along a first direction X will be referred to as a column of subpixels P, and multiple subpixels P arranged along a second direction Y will be referred to as a row of subpixels P.

[0101] In addition, the display board 110 further includes a plurality of data lines DL, a plurality of scan signal lines GL, and a plurality of light emission control lines EL.

[0102] As shown in Figure 4, the data line DL is configured to extend along approximately a first direction X and transmit data signals. One data line DL may be connected to, for example, a row of subpixels P.

[0103] As shown in Figure 4, the scan signal line GL is configured to extend approximately along a second direction Y and transmit scan signals. One scan signal line GL may be connected to, for example, one row of subpixels P.

[0104] As shown in Figure 4, the light emission control line EL is configured to extend approximately along a second direction Y and transmit an enable signal. One light emission control line EL may be connected to, for example, one row of subpixels P.

[0105] Furthermore, peripheral region B is an area where no image is displayed, and is equipped with display drive circuits such as the gate drive circuit 120 and the source drive circuit 130.

[0106] As shown in Figure 4, along the second direction Y, the gate drive circuit 120 is provided on at least one side of the display area A and connected to the scan signal line GL and the light emission control signal line EL, supplying a scan signal and an enable signal to the scan signal line GL and the light emission control signal line EL, respectively.

[0107] In some examples, as shown in Figure 4, the gate drive circuits 120 are provided on both sides of the display area A along the second direction Y, and the two gate drive circuits 120 simultaneously drive each scan signal line GL and each light emission control signal line EL row by row from opposite sides of the display area A. In other words, it is a bilateral drive.

[0108] In some other examples, in the second direction Y, the gate drive circuits 120 are provided on opposite sides of the display area A and are connected to the scan signal line GL and the light emission control line EL corresponding to subpixels P of different rows, respectively. The two gate drive circuits 120 alternately drive each scan signal line GL and each light emission control line EL row by row from both sides. This is interlaced driving.

[0109] In several other examples, along the second direction Y, the gate drive circuit 120 is located on one side of the display area A and drives each scan signal line GL and each light emission control signal line EL sequentially row by row from one side of the display area A. In other words, it is a one-sided drive.

[0110] In the following, several embodiments of the present disclosure will be illustrated using bilateral drive as an example, but the embodiments of the present disclosure are not limited thereto, and unilateral drive or interlaced drive are also conceivable as long as the same technical idea applies.

[0111] In some embodiments, referring to Figure 7, the gate drive circuit 120 described above includes a scanning drive circuit 121 and a light emission control circuit 122.

[0112] In some examples, the light emission control circuit 122 is connected to the light emission control signal line EL, as shown in Figure 7, and supplies an enable signal to the light emission control signal line EL.

[0113] For example, as shown in Figure 7, the light emission control circuit 122 includes a plurality of cascaded light emission shift registers ERS, each light emission shift register ERS connected to at least one enable signal line EL.

[0114] In some examples, as shown in Figure 7, the scanning drive circuit 121 is connected to the scanning signal line GL and supplies the scanning signal to the scanning signal line GL.

[0115] For example, as shown in Figure 7, the scan drive circuit 121 includes a plurality of cascaded scan shift registers GRS, each scan shift register GRS connected to at least one scan signal line GL.

[0116] However, as the pixel resolution of the display device increases, the vertical wiring space (first direction X) for each stage of shift registers (scanning shift registers and light-emitting shift registers) decreases. Therefore, reducing the vertical wiring space (first direction X) for each stage of shift registers is an urgent issue.

[0117] Based on this, referring to Figures 7 and 8, the display board 110 according to some embodiments of the present disclosure further includes a plurality of first power lines 151 provided in the peripheral region B.

[0118] As shown in Figure 8, the first power line 151 extends in approximately the first direction X and is configured to transmit either the first or second signal. At least one of the first power lines 151 is located on the side away from the display area A of the light emission control circuit 122, while at least two other first power lines 151 overlap with the light emission control circuit 122, dividing the light emission shift register ERS into a first light emission subcircuit 221, a second light emission subcircuit 222, and a third light emission subcircuit 223. Here, the first light emission subcircuit 221, the second light emission subcircuit 222, and the third light emission subcircuit 223 are sequentially located near the display area A (see Figure 4).

[0119] Note that both the first signal and the second signal are either a constant low-level signal or a constant high-level signal. In the following, several embodiments of the present disclosure will be illustrated using the example of the first signal and the second signal being constant high-level signals, but the embodiments of the present disclosure are not limited thereto.

[0120] In addition, as shown in Figures 11 and 13, the first light-emitting subcircuit 221 and the third light-emitting subcircuit 223 each include a first type transistor M1 connected to the first power line 151, and each first type transistor M1 is connected to the nearest first power line 151.

[0121] The embodiments of this disclosure will be described below using the example of a case where the display board 110 includes three first power lines 151, but the embodiments of this disclosure are not limited thereto.

[0122] In some embodiments, as shown in Figure 7, each light-emitting shift register ERS includes a first signal input terminal STU1, a first power signal terminal VGH10, a second power signal terminal VGL20, a first clock signal terminal CLK1, a second clock signal terminal CLK2, a first reset signal terminal RST1, a first cascade output terminal CR1, and an enable signal output terminal OUT1.

[0123] In addition, as shown in Figure 8, the display board 110 includes a first power line 151, a second power line 152, a first start signal line 161, a first clock signal line 171, a second clock signal line 172, and a first reset signal line 181.

[0124] Furthermore, the first power line 151, the second power line 152, the first start signal line 161, the first clock signal line 171, the second clock signal line 172, and the first reset signal line 181 extend approximately in the first direction X and are connected to the light-emitting shift register ERS, respectively.

[0125] Here, a first hollow region may be provided around the first power line 151, the second power line 152, the first start signal line 161, the first clock signal line 171, the second clock signal line 172, and the first reset signal line 181. By having connecting lines (for example, the first connecting line 191 and the second connecting line 192 described later) that intersect with the first power line 151, the second power line 152, the first start signal line 161, the first clock signal line 171, the second clock signal line 172, and the first reset signal line 181 pass through this first hollow region, the overlapping area can be reduced, thereby reducing the risk of parasitic capacitance and unexpected short circuits.

[0126] As shown in Figure 7, the first signal input terminal STU1 of the first stage light-emitting shift register ERS is connected to the first start signal line 161. For every two adjacent stages of light-emitting shift registers ERS, the first signal input terminal STU1 of the next stage light-emitting shift register ERS is connected to the first cascade output terminal CR1 of the previous stage light-emitting shift register ERS. In addition, the enable signal output terminal OUT1 of the light-emitting shift register ERS is connected to the enable signal line EL.

[0127] Here, multiple first power signal terminals VGH10 can transmit the same high-level signal, for example, a first signal or a second signal. Depending on the actual situation, some of the multiple first power signal terminals VGH10 may transmit the first signal and other some may transmit the second signal.

[0128] In other words, the multiple first power signal terminals VGH10 may include a first type of power signal terminal VGH11 that transmits a first signal and a second type of power signal terminal VGH12 that transmits a second signal.

[0129] Referring to Figure 8, the plurality of first power lines 151 include first type first power lines 511 and second type first power lines 512. The first type first power line 511 is configured to transmit a first signal. The second type first power line 512 is configured to transmit a second signal.

[0130] In the following, several embodiments of the present disclosure will be described illustratively, using as examples a plurality of first power signal terminals VGH10, including a first type first power signal terminal VGH11 and a second type first power signal terminal VGH12, but the embodiments of the present disclosure are not limited thereto.

[0131] Furthermore, multiple second power signal terminals VGL20 can transmit the same low-level signal, for example, a third signal or a fourth signal. Depending on the actual situation, some of the second power signal terminals VGL20 may transmit the third signal, while others may transmit the fourth signal.

[0132] In other words, the multiple second power signal terminals VGL20 include a first type of second power signal terminal VGL21 and a second type of second power signal terminal VGL22, where the first type of second power signal terminal VGL21 transmits a third signal and the second type of second power signal terminal VGL22 transmits a fourth signal.

[0133] Furthermore, the third and fourth signals are either constant low-level signals or constant high-level signals, and the levels of the third and fourth signals are inversely related to the levels of the first and second signals. For example, if both the first and second signals are constant high-level signals, then the third and fourth signals will be constant low-level signals.

[0134] Referring to Figure 8, the second power line 152 includes a second power line 521 of the first type and a second power line 522 of the second type. The second power line 521 of the first type is configured to transmit a third signal. The second power line 522 of the second type is configured to transmit a fourth signal.

[0135] In the following, several embodiments of the present disclosure will be described illustratively, with examples including a plurality of second power signal terminals VGL20, which include a first type second power signal terminal VGL21 and a second type second power signal terminal VGL22, but the embodiments of the present disclosure are not limited thereto.

[0136] In some examples, referring to Figure 11, the first light-emitting subcircuit 221 has a first center line Z1 extending along a first direction X and includes a plurality of first type transistors M1. The plurality of first type transistors M1 in the first light-emitting subcircuit 221 are located on both sides of the first center line Z1 and are each connected to the nearest first power line 151.

[0137] In addition, referring to Figures 11 and 14, the first light-emitting sub-circuit 221 is connected to the first power signal terminal VGH10, the second power signal terminal VGL20, the first signal input terminal STU1, the first reset signal terminal RST1, the first clock signal terminal CLK1, the second clock signal terminal CLK2, the first cascade output terminal CR1, the first control node Q1, and the second control node Q2.

[0138] In this case, the first light-emitting sub-circuit 221 is configured to output one of the first signal, second signal, third signal, and fourth signal to the first control node Q1, the second control node Q2, and the first cascade output terminal CR1, respectively, under the control of signals from the first signal input terminal STI1, the first clock signal terminal CLK1, and the second clock signal terminal CLK2, and to output the first clock signal to the first control node Q1 and the first signal or the second signal to the second control node Q2, under the control of a signal from the first reset signal terminal RST1.

[0139] For example, as shown in Figure 14, the first light-emitting sub-circuit 221 is connected to the first power signal terminal VGH11 of the first type and the second power signal terminal VGL21 of the first type.

[0140] For example, as shown in Figure 14, the first light-emitting subcircuit 221 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a first capacitor C1.

[0141] As shown in Figure 14, the first electrode of the first transistor T1 is connected to the first power signal terminal VGH11 of the first type, the second electrode of the first transistor T1 is connected to the first node N1, and the control electrode of the first transistor T1 is connected to the first clock signal terminal CLK1.

[0142] As shown in Figure 14, the first electrode of the second transistor T2 is connected to the first node N1, the second electrode of the second transistor T2 is connected to the second node N2, and the control electrode of the second transistor T2 is connected to the first signal input terminal STU1.

[0143] As shown in Figure 14, the first electrode of the third transistor T3 is connected to the first power signal terminal VGH11 of the first type, the second electrode of the third transistor T3 is connected to the third node N3, and the control electrode of the third transistor T3 is connected to the second clock signal terminal CLK2.

[0144] As shown in Figure 14, the first electrode of the fourth transistor T4 is connected to the third node N3, the second electrode of the fourth transistor T4 is connected to the fourth node N4, and the control electrode of the fourth transistor T4 is connected to the first signal input terminal STU1.

[0145] As shown in Figure 14, the first electrode of the fifth transistor T5 is connected to the fourth node N4, the second electrode of the fifth transistor T5 is connected to the second clock signal terminal CLK2, and the control electrode of the fifth transistor T5 is connected to the first signal input terminal STU1.

[0146] As shown in Figure 14, the first electrode of the sixth transistor T6 is connected to the first power signal terminal VGH11 of the first type, the second electrode of the sixth transistor T6 is connected to the fourth node N4, and the control electrode of the sixth transistor T6 is connected to the third node N3.

[0147] As shown in Figure 14, the first electrode of the seventh transistor T7 is connected to the first clock signal terminal CLK1, the second electrode of the seventh transistor T7 is connected to the fifth node N5, and the control electrode of the seventh transistor T7 is connected to the third node N3.

[0148] As shown in Figure 14, the first electrode of the eighth transistor T8 is connected to the fifth node N5, the second electrode of the eighth transistor T8 is connected to the second control node Q2, and the control electrode of the eighth transistor T8 is connected to the first clock signal terminal CLK1.

[0149] As shown in Figure 14, the first electrode of the ninth transistor T9 is connected to the second power signal terminal VGL21 of the first type, the second electrode of the ninth transistor T9 is connected to the second control node Q2, and the control electrode of the ninth transistor T9 is connected to the second node N2.

[0150] As shown in Figure 14, the first electrode of the 10th transistor T10 is connected to the second node N2, the second electrode of the 10th transistor T10 is connected to the sixth node N6, and the control electrode of the 10th transistor T10 is connected to the third node N3.

[0151] As shown in Figure 14, the first electrode of the 11th transistor T11 is connected to the 6th node N6, the second electrode of the 11th transistor T11 is connected to the second power signal terminal VGL21 of the first type, and the control electrode of the 11th transistor T11 is connected to the first clock signal terminal CLK1.

[0152] As shown in Figure 14, the first electrode of the 12th transistor T12 is connected to the first clock signal terminal CLK1, the second electrode of the 12th transistor T12 is connected to the second node N2, and the control electrode of the 12th transistor T12 is connected to the first reset signal terminal RST1.

[0153] As shown in Figure 14, the first electrode of the 13th transistor T13 is connected to the first power signal terminal VGH11 of the first type, the second electrode of the 13th transistor T13 is connected to the second control node Q2, and the control electrode of the 13th transistor T13 is connected to the first reset signal terminal RST1.

[0154] As shown in Figure 14, the first electrode of the 14th transistor T14 is connected to the second node N2, the second electrode of the 14th transistor T14 is connected to the first control node Q1, and the control electrode of the 14th transistor T14 is connected to the first power signal terminal VGH11 of the first type.

[0155] As shown in Figure 14, the first electrode of the 15th transistor T15 is connected to the first power signal terminal VGH11 of the first type, the second electrode of the 15th transistor T15 is connected to the first cascade output terminal CR1, and the control electrode of the 15th transistor T15 is connected to the first control node Q1.

[0156] As shown in Figure 14, the first electrode of the 16th transistor T16 is connected to the second power signal terminal VGL21 of the first type, the second electrode of the 16th transistor T16 is connected to the first cascade output terminal CR1, and the control electrode of the 16th transistor T16 is connected to the second control node Q2.

[0157] As shown in Figure 14, the first plate of the first capacitor C1 is connected to the third node N3, and the second plate of the first capacitor C1 is connected to the fifth node N5.

[0158] In some examples, referring to Figures 12 and 14, the second light-emitting subcircuit 222 is coupled to the first control node Q1 and the enable signal output terminal OUT1.

[0159] Here, the second light-emitting sub-circuit 222 is configured to boost the voltage of the first control node Q1 when the first signal or the second signal is output from the enable signal output terminal OUT1.

[0160] For example, as shown in Figure 14, the second light-emitting sub-circuit 222 is connected to the first power signal terminal VGH11 of the first type.

[0161] For example, as shown in Figure 14, the second light-emitting subcircuit 222 includes a second capacitor C2, the first plate of the second capacitor C2 is connected to the first control node Q1, and the second plate of the second capacitor C2 is connected to the enable signal output terminal OUT1.

[0162] In some examples, referring to Figures 13 and 14, the third light-emitting subcircuit 223 is coupled to the first power signal terminal VGH11, the second power signal terminal VGL, the first control node Q1, the second control node Q2, and the enable signal output terminal OUT1 of the first type.

[0163] Here, the third light-emitting subcircuit 223 is configured to output one of the first, second, third, and fourth signals to the enable signal output terminal OUT1 under the voltage control of the first control node Q1 and the second control node Q2, and to boost the voltage of the second control node Q2 when outputting the third or fourth signal to the enable signal output terminal OUT1.

[0164] For example, as shown in Figure 14, the third light-emitting sub-circuit 223 is connected to the first power signal terminal VGH12 of the second type and the second power signal terminal VGL22 of the second type, and the first power line 512 of the second type and the second power line 522 of the second type are provided separately, thereby avoiding interference from other circuits and making the second or fourth signal output from the signal output terminal OUT1 more stable.

[0165] For example, as shown in Figure 14, the third light-emitting subcircuit 223 includes a 17th transistor T17, a 18th transistor T18, and a third capacitor C3.

[0166] As shown in Figure 14, the first electrode of the 17th transistor T17 is connected to the first power signal terminal VGH12 of the second type, the second electrode of the 17th transistor T17 is connected to the enable signal output terminal OUT1, and the control electrode of the 17th transistor T17 is connected to the first control node Q1.

[0167] As shown in Figure 14, the first electrode of the 18th transistor T18 is connected to the second power signal terminal VGL22 of the second type, the second electrode of the 18th transistor T18 is connected to the enable signal output terminal OUT1, and the control electrode of the 18th transistor T18 is connected to the second control node Q2.

[0168] Note that the number of the 17th transistor T17 and the 18th transistor T18 may be multiple, and specifically, it is set according to the number of enable signal lines EL to which this third light-emitting subcircuit 223 is connected. Figure 13 shows an example in which four 17th transistors T17 and four 18th transistors T18 are provided in parallel.

[0169] According to the first light-emitting subcircuit 221 described above, as shown in Figures 11 and 14, the plurality of first type transistors M1 in the first light-emitting subcircuit 221 include the first transistor T1, the third transistor T3, the sixth transistor T6, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15.

[0170] Referring to Figures 11 and 14, the third transistor T3 and the sixth transistor T6 are located on the side away from the indicated area A of the first center line Z1 (see Figure 4) (left side in Figure 11), while the first transistor T1, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are located on the side closer to the indicated area A of the first center line Z1 (see Figure 4) (right side in Figure 11).

[0171] Specifically, as shown in Figures 8, 10, and 11, the third transistor T3 and the sixth transistor T6 are connected to the first power line 151 on the side away from the display area A of the light emission control circuit 122 (the first power line 151 on the left side in Figure 11), while the first transistor T1, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are connected to the first power line 151 between the first light emission sub-circuit 221 and the second light emission sub-circuit 222 (the first power line 151 on the right side in Figure 11).

[0172] In this case, by directly connecting multiple first-type transistors M1 in the first light-emitting subcircuit 221 to the nearest first power line 151, bypass wiring in the second direction Y can be avoided, and the wiring space in the first direction X of each stage light-emitting shift register ERS can be reduced.

[0173] For example, as shown in Figure 11, the display board 110 further includes a plurality of first connection lines 191 extending substantially along a second direction Y. Here, one end of the first connection line 191 is connected to a first transistor M1, and the other end is connected to the nearest first power line 151.

[0174] That is, in the first light-emitting sub-circuit 221, the third transistor T3 and the sixth transistor T6 may each be directly connected via a first connection line 191 to the first power supply line 151 (the first power supply line 151 on the left side in Figure 11) located on the side away from the display area A of the light-emitting control circuit 122. The first transistor T1, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 may each be directly connected via a first connection line 191 to the first power supply line 151 located between the first light-emitting sub-circuit 221 and the second light-emitting sub-circuit 222.

[0175] In other words, each first type of transistor M1 in the first light-emitting subcircuit 221 is connected to the corresponding first power line 151, eliminating the need for bypass wiring in the second direction Y, and reducing the wiring space in the first direction X of each stage of light-emitting shift register ERS.

[0176] According to the third light-emitting subcircuit 223 described above, as shown in Figures 13 and 14, the first type of transistor M1 in the third light-emitting subcircuit 223 includes the 17th transistor T17.

[0177] As shown in Figures 12, 13, and 14, the 17th transistor T17 is connected to the first power line 151 located between the second light-emitting subcircuit 222 and the third light-emitting subcircuit 223.

[0178] In this case, the first type transistor M1 in the third light-emitting subcircuit 223 is directly connected to the nearest first power line 151, thereby avoiding detour wiring in the second direction Y and further reducing the wiring space in the first direction X for each stage of the light-emitting shift register ERS.

[0179] For example, as shown in Figure 13, in the third light-emitting sub-circuit 223, the 17th transistor T17 is directly connected via the first connection line 191 to the first power line 151 (the first power line 151 on the left side of Figure 13) located between the second light-emitting sub-circuit 222 and the third light-emitting sub-circuit 223. That is, the first type transistor M1 of the third light-emitting sub-circuit 223 is connected to the corresponding first power line 151, eliminating the need for bypass wiring in the second direction Y, and further reducing the wiring space in the first direction X of each stage of light-emitting shift register ERS.

[0180] In some embodiments, referring to Figures 11, 13, and 14, both the first light-emitting subcircuit 221 and the third light-emitting subcircuit 223 include a second type of transistor M2 connected to a second power line 152.

[0181] In addition, as shown in Figure 8, the display board 110 may include a plurality of second power lines 152, and the second power lines 152 may be configured to transmit a third signal or a fourth signal.

[0182] Here, as shown in Figures 4 and 8, of the multiple second power lines 152, at least one second power line 152 is provided on the side of the light emission control circuit 122 away from the display area A, and at least one other second power line 152 is provided between the light emission control circuit 122 and the display area A.

[0183] In the following, several embodiments of the present disclosure will be described illustratively, taking as an example the case in which the display board 110 includes two second power lines 152, and the two second power lines 152 are one first type second power line 521 and one second type second power line 522, respectively, but the embodiments of the present disclosure are not limited thereto.

[0184] If the two second power lines 152 include a first type second power line 521 and a second type second power line 522, the first type second power line 521 is provided on the side of the light emission control circuit 122 away from the display area A. The second type second power line 522 is provided between the light emission control circuit 122 and the display area A.

[0185] In this case, the second type transistor M2 in the first light-emitting sub-circuit 221 and the third light-emitting sub-circuit 223 may each be connected to the nearest second power supply line 152.

[0186] According to the first light-emitting subcircuit 221 and the third light-emitting subcircuit 223, as shown in Figures 11, 13, and 14, the second type of transistor M2 in the first light-emitting subcircuit 221 includes the ninth transistor T9, the eleventh transistor T11, and the sixteenth transistor T16. The second type of transistor M2 in the third light-emitting subcircuit 223 includes the eighteenth transistor T18.

[0187] Specifically, as shown in Figures 4 and 11, the ninth transistor T9, the eleventh transistor T11, and the sixteenth transistor T16 are connected to the second power line 152 (the second power line 521 of the first type in Figure 11) on the side of the light emission control circuit 122 that is away from the display area A. As shown in Figures 4 and 13, the eighteenth transistor T18 is connected to the second power line 152 (the second power line 522 of the second type in Figure 13) located between the light emission control circuit 122 and the display area A.

[0188] In this case, since the second type transistor M2 in both the first light-emitting subcircuit 221 and the third light-emitting subcircuit 223 are directly connected to the nearest second power line 152, bypass wiring in the second direction Y can be avoided, and the wiring space in the first direction X of each stage light-emitting shift register ERS can be further reduced.

[0189] For example, as shown in Figure 11, the display board 110 further includes a plurality of second connection lines 192 extending substantially along a second direction Y. Here, one end of the second connection line 192 is connected to a second type transistor M2, and the other end is connected to the nearest second power line 152.

[0190] As shown in Figure 11, in the first light-emitting subcircuit 221, the ninth transistor T9, the eleventh transistor T11, and the sixteenth transistor T16 may be directly connected to the first type of second power supply line 521 via the same second connection line 192. The eighteenth transistor T18 may be directly connected to the second type of second power supply line 522 via one second connection line 192.

[0191] In other words, the second type of transistor M2 in the first light-emitting subcircuit 221 and the third light-emitting subcircuit 223 is connected to the corresponding second power line 152, eliminating the need for bypass wiring in the second direction Y, and further reducing the wiring space in the first direction X of the light-emitting shift register ERS of each stage.

[0192] In some embodiments, referring to Figures 8, 11, and 13, the width of the second power line 152 connected to the third light-emitting subcircuit 223 is smaller than the width of the second power line 152 connected to the first light-emitting subcircuit 221. That is, the width of the second power line 522 of the second type is smaller than the width of the second power line 521 of the first type.

[0193] In this case, since the width of the second power line 522 of the second type is smaller than the width of the second power line 521 of the first type, the second power line 522 of the second type has a higher resistance and a larger voltage drop. In this case, when the first high level is output from the enable signal output terminal OUT1, the second control node Q2 becomes low level, the Vgs of the 18th transistor T18 becomes less than 0, ensuring that the 18th transistor T18 is turned off and reducing the risk of leakage current.

[0194] In some embodiments, referring to Figures 8, 11, and 13, the width of the first power supply line 151 connected to the third light-emitting sub-circuit 223 is greater than the width of the first power supply line 151 connected to the first light-emitting sub-circuit 221. In this case, the voltage drop across the first power supply line 151 connected to the third light-emitting sub-circuit 223 is smaller, and the first signal output from the enable signal output terminal OUT1 becomes more stable.

[0195] In some embodiments, referring to Figures 4 and 8, the first start signal line 161 is located on the side of the light emission control circuit 122 away from the display area A. The first clock signal line 171 is located on the side of the light emission control circuit 122 away from the display area A. The second clock signal line 172 is located on the side of the light emission control circuit 122 away from the display area A. The first reset signal line 181 is located between the two first power lines 151 that overlap with the light emission control circuit 122.

[0196] In this case, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the eleventh transistor T11, and the twelfth transistor T12, as well as the twelfth transistor T12 and the thirteenth transistor T13, are connected to the corresponding signal lines on both sides of the first light-emitting subcircuit 221, thereby reducing the detour wiring in the second direction Y and reducing the wiring space in the first direction X of each stage of the light-emitting shift register ERS.

[0197] Referring to Figures 8 and 11, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 may be connected to the first start signal line 161, the first transistor T1, the seventh transistor T7, the eighth transistor T8, the eleventh transistor T11, and the twelfth transistor T12 may be connected to the first clock signal line 171, and the third transistor T3 and the fifth transistor T5 may be connected to the second clock signal line 172.

[0198] Referring to Figure 8, the positional relationship between the first power line 151, the second power line 152, the first start signal line 161, the first clock signal line 171, the second clock signal line 172, and the first reset signal line 181 is not unique; they may be offset from each other or partially overlap.

[0199] As an example, referring to Figures 4 and 8, on the side of the light emission control circuit 122 away from the display area A, the first start signal line 161, the first clock signal line 171, and the second clock signal line 172 are sequentially arranged with a shift along the second direction Y, from the peripheral area B toward the display area A.

[0200] Furthermore, the first power line 151 and the second power line 152 are located closer to the display area A of the second clock signal line 172, reducing the distance between the first power line 151 and the second power line 152 and the connected transistor, thereby reducing voltage drop.

[0201] In addition, in some examples, as shown in Figures 4 and 8, the first power line 151 and the second power line 152 on the side away from the display area A of the light emission control circuit 122 may be provided, for example, offset from each other. Furthermore, the first power line 151 may be located on the side of the second power line 152 that is away from the display area A or on the side that is closer to the display area A. Figure 8 shows an example in which the first power line 151 is located on the side of the second power line 152 that is away from the display area A.

[0202] Furthermore, as shown in Figures 4 and 8, the first power supply line 151, located between the first light-emitting sub-circuit 221 and the second light-emitting sub-circuit 222, may be provided offset from the first reset signal line 181. For example, this first power supply line 151 is located on the side of the first reset signal line 181 that is away from the display area A.

[0203] In this case, the first start signal line 161, the first clock signal line 171, the second clock signal line 172, the first power supply line 151, the second power supply line 152, and the first reset signal line 181 may be provided on the same layer and made of the same material.

[0204] In some other examples, as shown in Figures 4 and 9, the orthogonal projections of the first power line 151 and the second power line 152, located on the side of the light emission control circuit 122 away from the display area A, onto the reference plane overlap at least partially, reducing the distance between the first power line 151 and the second power line 152 and the correspondingly connected transistors, reducing voltage drop, reducing the wiring space in the second direction Y of each signal line, and facilitating a narrow bezel design for the display panel 100. Here, the reference plane is the plane on which the non-display side of the display substrate 110 is located.

[0205] Furthermore, when the first power line 151 and the second power line 152 are located in different film layers, in embodiments where the orthogonal projections of the first power line 151 and the second power line 152 onto the reference plane overlap at least partially, the distance between the film layer where the first power line 151 is located and the film layer where the second power line 152 is located is larger than in embodiments where the orthogonal projections onto the reference plane do not overlap, thereby reducing parasitic capacitance.

[0206] For example, when the first power line 151 and the second power line 152 are located in different film layers, in embodiments where the orthogonal projections of the first power line 151 and the second power line 152 onto the reference plane overlap at least partially, it is possible to add an insulating film layer, such as a flat layer, compared to embodiments where the orthogonal projections onto the reference plane do not overlap.

[0207] Furthermore, as shown in Figures 4 and 9, by at least partially overlapping the first power line 151 provided between the first light-emitting subcircuit 221 and the second light-emitting subcircuit 222 with the orthographic projection of the first reset signal line 181 onto the reference plane, the distance between the transistor to which the first power line 151 and the first reset signal line 181 are connected can be shortened, reducing the voltage drop and decreasing the wiring space in the second direction Y of each signal line, thereby enabling a narrower bezel for the display panel 100.

[0208] Furthermore, when the first power line 151 and the first reset signal line 181 are located in different film layers, in embodiments where the orthogonal projections of the first power line 151 and the first reset signal line 181 onto the reference plane overlap at least partially, the distance between the film layer where the first power line 151 is located and the film layer where the first reset signal line 181 is located becomes larger than in embodiments where the orthogonal projections onto the reference plane do not overlap, thereby reducing parasitic capacitance.

[0209] For example, when the first power line 151 and the first reset signal line 181 are located in different film layers, in embodiments where the orthogonal projections of the first power line 151 and the first reset signal line 181 onto the reference plane overlap at least partially, it is possible to add an insulating film layer, such as a flat layer, compared to embodiments where the orthogonal projections onto the reference plane do not overlap.

[0210] In this case, the first start signal line 161, the first clock signal line 171, the second clock signal line 172, and the second power line 152 are provided on the same layer and of the same material, and the first power line 151 and the first reset signal line 181 are located on different layers, and either one of them may be provided on the same layer and of the same material as the first start signal line 161, the first clock signal line 171, the second clock signal line 172, and the second power line 152.

[0211] Referring to Figures 4 and 15, the display board 110 according to some embodiments of the present disclosure further includes a plurality of third power lines 153 provided in the peripheral region B.

[0212] As shown in Figure 15, the third power line 153 extends approximately along the first direction X and is configured to transmit a fifth or sixth signal. In addition, at least three third power lines 153 overlap with the scan drive circuit 121, dividing the scan shift register GRS into a first scan sub-circuit 211, a second scan sub-circuit 212, a third scan sub-circuit 213, and a fourth scan sub-circuit 214. Here, the first scan sub-circuit 211, the second scan sub-circuit 212, the third scan sub-circuit 213, and the fourth scan sub-circuit 214 are sequentially located near the display area A (see Figure 4).

[0213] The fifth and sixth signals are both constant low-level signals or constant high-level signals. Hereinafter, several embodiments of the present disclosure will be described illustratively, using the case where the fifth and sixth signals are constant low-level signals as an example; however, the embodiments of the present disclosure are not limited thereto.

[0214] In addition, referring to Figures 17 to 20, the first scanning subcircuit 211, the second scanning subcircuit 212, and the third scanning subcircuit 213 all include a third type of transistor M3 connected to a third power line 153, and the third type of transistor M3 in the first scanning subcircuit 211, the second scanning subcircuit 212, and the third scanning subcircuit 213 are each connected to the nearest third power line 153.

[0215] The following examples illustrate embodiments of the present disclosure, using the case where the display board 110 includes three third power lines 153 as an example, but the embodiments of the present disclosure are not limited thereto.

[0216] In some embodiments, as shown in Figure 7, each scan shift register GRS includes a second signal input terminal STU2, a third signal input terminal STD, a third power signal terminal VGL30, a fourth power signal terminal EN10, a first voltage terminal CN, a second voltage terminal CNB, a third clock signal terminal CLK3, a fourth clock signal terminal CLK4, a second reset signal terminal RST2, a second cascade output terminal CR2, and a scan signal output terminal OUT2.

[0217] In addition, as shown in Figures 7 and 15, the display board 110 includes a second start signal line 162, a third start signal line 163, a first voltage signal line 141, a second voltage signal line 142, a third power line 153, a fourth power line 154, a third clock signal line 173, a fourth clock signal line 174, and a second reset signal line 182.

[0218] The first voltage signal line 141 may be a constant high-level signal, and the second voltage signal line 142 may be a constant low-level signal. A high-level signal can be input to the fourth power line 154 when the display board 110 is powered off due to an abnormality, but the embodiments of this disclosure are not specifically limited to this.

[0219] Furthermore, the second start signal line 162, the third start signal line 163, the first voltage signal line 141, the second voltage signal line 142, the third power line 153, the fourth power line 154, the third clock signal line 173, the fourth clock signal line 174, and the second reset signal line 182 extend approximately along the first direction X and are connected to the scan shift register GRS, respectively.

[0220] Here, a second hollow region may be provided around the second start signal line 162, the third start signal line 163, the first voltage signal line 141, the second voltage signal line 142, the third power supply line 153, the fourth power supply line 154, the third clock signal line 173, the fourth clock signal line 174, and the second reset signal line 182. By having connecting lines (for example, the first connecting line 191 and the second connecting line 192 described later) that intersect with the second start signal line 162, the third start signal line 163, the first voltage signal line 141, the second voltage signal line 142, the third power supply line 153, the fourth power supply line 154, the third clock signal line 173, the fourth clock signal line 174, and the second reset signal line 182 pass through this second hollow region, the overlap area is reduced, and the risk of parasitic capacitance and unexpected short circuits is reduced.

[0221] As shown in Figure 7, the second signal input terminal STU2 of the first-stage scan shift register GRS is connected to the second start signal line 162. For each of the two adjacent scan shift registers GRS, the second signal input terminal STU2 of the next-stage scan shift register GRS is connected to the second cascade output terminal CR2 of the previous-stage scan shift register GRS.

[0222] As shown in Figure 7, the third signal input terminal STU3 of the final stage scan shift register GRS is connected to the third start signal line 163. For each of two adjacent scan shift registers GRS, the third signal input terminal STU3 of the preceding scan shift register GRS is connected to the second cascade output terminal CR2 of the following scan shift register GRS.

[0223] Here, multiple third power signal terminals VGL30 can transmit the same low-level signal, for example, a fifth signal or a sixth signal. Depending on the actual situation, some of the multiple third power signal terminals VGL30 may transmit the fifth signal and other some of the third power signal terminals VGL30 may transmit the sixth signal.

[0224] In other words, the multiple third power signal terminals VGL30 include a first type of third power signal terminal VGL31 and a second type of third power signal terminal VGL32, where the first type of third power signal terminal VGL31 transmits a fifth signal and the second type of third power signal terminal VGL32 transmits a sixth signal.

[0225] In this case, the multiple third power lines 153 may include two first type third power lines 531 and one second type third power line 532. The first type third power line 531 is configured to transmit a fifth signal. The second type third power line 532 is configured to transmit a sixth signal.

[0226] If all third power lines 153 include two first type third power lines 531 and a second type third power line 532, one first type third power line 153 is provided between the first scanning subcircuit 211 and the second scanning subcircuit 212, and the other first type third power line 153 is provided between the second scanning subcircuit 212 and the third scanning subcircuit 213. The second type third power line 153 is provided between the third scanning subcircuit 213 and the fourth scanning subcircuit 214.

[0227] In the following, several embodiments of the present disclosure will be described illustratively, with examples including a plurality of third power signal terminals VGL30, including a first type third power signal terminal VGL31 and a second type third power signal terminal VGL32, but the embodiments of the present disclosure are not limited thereto.

[0228] Furthermore, multiple fourth power signal terminals EN10 can transmit the same high-level signal, for example, the seventh or eighth signal. Depending on the actual situation, some of the fourth power signal terminals EN10 may transmit the seventh signal, while others may transmit the eighth signal.

[0229] In other words, the multiple fourth power signal terminals EN10 include a first type of fourth power signal terminal EN11 and a second type of fourth power signal terminal EN12, the first type of fourth power signal terminal EN11 transmits a seventh signal, and the second type of fourth power signal terminal EN12 transmits an eighth signal.

[0230] The seventh signal is either a constant low-level signal or a constant high-level signal, and the eighth signal is a constant high-level signal. Hereinafter, embodiments of the present disclosure will be illustrated using the case where the seventh signal is a constant high-level signal as an example, but the embodiments of the present disclosure are not limited thereto.

[0231] In this case, the plurality of fourth power lines 154 include two first type fourth power lines 541 and one second type fourth power line 542. The first type fourth power line 541 is configured to transmit a seventh signal. The second type fourth power line 542 is configured to transmit an eighth signal.

[0232] Hereinafter, several embodiments of the present disclosure will be described illustratively, with reference to a plurality of fourth power signal terminals EN10, including a first type fourth power signal terminal EN11 and a second type fourth power signal terminal EN12, but the embodiments of the present disclosure are not limited thereto.

[0233] In some examples, referring to Figures 17 and 21, the first scanning subcircuit 211 is coupled to the third power signal terminal VGL30, the second signal input terminal STU2, the third signal input terminal STD, the first voltage terminal CN, the second voltage terminal CNB, the second reset signal terminal RST2, the second cascade output terminal CR2, the third control node Q3, and the fourth control node Q4.

[0234] At this time, the first scanning subcircuit 211 is configured to output a first voltage signal or a second voltage signal to the third control node Q3 under the control of the voltages of the second signal input terminal STU2 and the third signal input terminal STU3, to output a fifth signal or a sixth signal to the fourth control node Q4, and to output a fifth signal or a sixth signal to the third control node Q3 under the control of the signal from the second reset signal terminal RST2.

[0235] For example, as shown in Figure 21, the first scanning subcircuit 211 is connected to the first type of third power signal terminal VGL31.

[0236] For example, as shown in Figure 21, the first scanning subcircuit 211 includes a 19th transistor T19, a 20th transistor T20, a 21st transistor T21, a 22nd transistor T22, and a 23rd transistor T23.

[0237] As shown in Figure 21, the first electrode of the 19th transistor T19 is connected to the first voltage terminal CN, the second electrode of the 19th transistor T19 is connected to the third control node Q3, and the control electrode of the 19th transistor T19 is connected to the second signal input terminal STU2.

[0238] As shown in Figure 21, the first electrode of the 20th transistor T20 is connected to the second voltage terminal CNB, the second electrode of the 20th transistor T20 is connected to the third control node Q3, and the control electrode of the 20th transistor T20 is connected to the third signal input terminal STD.

[0239] As shown in Figure 21, the first electrode of the 21st transistor T21 is connected to the third power signal terminal VGL31 of the first type, the second electrode of the 21st transistor T21 is connected to the third control node Q3, and the control electrode of the 21st transistor T21 is connected to the second reset signal terminal RST2.

[0240] As shown in Figure 21, the first electrode of the 22nd transistor T22 is connected to the third power signal terminal VGL31 of the first type, the second electrode of the 22nd transistor T22 is connected to the fourth control node Q4, and the control electrode of the 22nd transistor T22 is connected to the third control node Q3.

[0241] As shown in Figure 21, the first electrode of the 23rd transistor T23 is connected to the third power signal terminal VGL31 of the first type, the second electrode of the 23rd transistor T23 is connected to the fourth control node Q4, and the control electrode of the 23rd transistor T23 is connected to the second signal input terminal STU2.

[0242] In some examples, referring to Figures 18 and 21, the second scanning subcircuit 212 is coupled to the third power signal terminal VGL30, the fourth power signal terminal EN10, the third control node Q3, the fourth control node Q4, and the second cascade output terminal CR2.

[0243] At this time, the second scanning subcircuit 212 is configured to output a fifth signal or a sixth signal to the second cascade output terminal CR2 under the control of the voltage of the fourth control node Q4, and to output a fifth signal or a sixth signal to the fourth control node Q4 under the control of the signal from the second cascade output terminal CR2 or the fourth power supply signal terminal EN10.

[0244] For example, as shown in Figure 21, the second scanning subcircuit 212 is connected to the third power signal terminal VGL31 of the first type and the fourth power signal terminal EN11 of the first type.

[0245] For example, as shown in Figure 21, the second scanning subcircuit 212 includes a 24th transistor T24, a 25th transistor T25, a 26th transistor T26, and a 27th transistor T27.

[0246] As shown in Figure 21, the first electrode of the 24th transistor T24 is connected to the third power signal terminal VGL31 of the first type, the second electrode of the 24th transistor T24 is connected to the third control node Q3, and the control electrode of the 24th transistor T24 is connected to the fourth control node Q4.

[0247] As shown in Figure 21, the first electrode of the 25th transistor T25 is connected to the third power signal terminal VGL31 of the first type, the second electrode of the 25th transistor T25 is connected to the fourth control node Q4, and the control electrode of the 25th transistor T25 is connected to the second cascade output terminal CR2.

[0248] As shown in Figure 21, the first electrode of the 26th transistor T26 is connected to the third power signal terminal VGL31 of the first type, the second electrode of the 26th transistor T26 is connected to the second cascade output terminal CR2, and the control electrode of the 26th transistor T26 is connected to the fourth control node Q4.

[0249] As shown in Figure 21, the first electrode of the 27th transistor T27 is connected to the third power signal terminal VGL31 of the first type, the second electrode of the 27th transistor T27 is connected to the fourth control node Q4, and the control electrode of the 27th transistor T27 is connected to the fourth power signal terminal EN11 of the first type.

[0250] In some examples, referring to Figures 19 and 21, the third scanning subcircuit 213 is connected to the third power signal terminal VGL30, the third clock signal terminal CLK3, the third control node Q3, the fourth control node Q4, the second cascade output terminal CR2, and the scanning signal output terminal OUT2.

[0251] At this time, the third scanning sub-circuit 213 is configured to output the third clock signal to the second cascade output terminal CR2 and to output one of the third clock signal, the fifth signal, or the sixth signal to the scanning signal output terminal OUT2, under the control of the voltages of the third control node Q3 and the fourth control node Q4.

[0252] For example, as shown in Figure 21, the third scanning subcircuit 213 is connected to the third power signal terminal VGL32 of the second type. In this way, by providing a separate third power line 532 of the second type, interference from other circuits can be avoided and the sixth signal output from the scanning signal output terminal OUT2 can be made more stable.

[0253] For example, as shown in Figure 21, the third scanning subcircuit 213 includes a 28th transistor T28, a 29th transistor T29, a 30th transistor T30, a 4th capacitor C4, and a 5th capacitor C5.

[0254] As shown in Figure 21, the first electrode of the 28th transistor T28 is connected to the third clock signal terminal CLK3, the second electrode of the 28th transistor T28 is connected to the second cascade output terminal CR2, and the control electrode of the 28th transistor T28 is connected to the third control node Q3.

[0255] As shown in Figure 21, the first electrode of the 29th transistor T29 is connected to the third clock signal terminal CLK3, the second electrode of the 29th transistor T29 is connected to the scan signal output terminal OUT2, and the control electrode of the 29th transistor T29 is connected to the third control node Q3.

[0256] As shown in Figure 21, the first electrode of the 30th transistor T30 is connected to the third power signal terminal VGL32 of the second type, the second electrode of the 30th transistor T30 is connected to the scan signal output terminal OUT2, and the control electrode of the 30th transistor T30 is connected to the fourth control node Q4.

[0257] As shown in Figure 21, the first plate of the fourth capacitor C4 is connected to the third control node Q3, and the second plate of the fourth capacitor C4 is connected to the scan signal output terminal OUT2.

[0258] As shown in Figure 21, the first plate of the fifth capacitor C5 is connected to the third power signal terminal VGL32 of the second type, and the second plate of the fifth capacitor C5 is connected to the fourth control node Q4.

[0259] In some examples, referring to Figures 20 and 21, the fourth scanning subcircuit 214 is coupled to the fourth clock signal terminal CLK4, the fourth power signal terminal EN10, the fourth control node Q4, and the scanning signal output terminal OUT2.

[0260] At this time, the fourth scanning subcircuit 214 is configured to output the seventh signal or the eighth signal to the scanning signal output terminal OUT2 under the control of the signal from the fourth power signal terminal EN10, and to output the fourth clock signal to the third control node Q3 under the control of the signal from the fourth clock signal terminal CLK4.

[0261] For example, as shown in Figure 21, the fourth scanning subcircuit 214 is connected to the fourth power signal terminal EN12 of the second type. In this way, the fourth power line 542 of the second type is provided separately, thereby avoiding interference from other circuits and making the eighth signal output from the scanning signal output terminal OUT2 more stable.

[0262] For example, as shown in Figure 21, the fourth scanning subcircuit 214 includes a 31st transistor T31 and a 32nd transistor T32.

[0263] As shown in Figure 21, the first electrode of the 31st transistor T31 is connected to the second type fourth power signal terminal EN12, the second electrode of the 31st transistor T31 is connected to the scan signal output terminal OUT2, and the control electrode of the 31st transistor T31 is connected to the second type fourth power signal terminal EN12.

[0264] As shown in Figure 21, the first electrode of the 32nd transistor T32 is connected to the fourth clock signal terminal CLK4, the second electrode of the 32nd transistor T32 is connected to the fourth control node Q4, and the control electrode of the 32nd transistor T32 is connected to the fourth clock signal terminal CLK4.

[0265] According to the first scanning subcircuit 211 described above, as shown in Figures 17 and 21, the third type of transistor M3 in the first scanning subcircuit 211 includes the 21st transistor T21, the 22nd transistor T22, and the 23rd transistor T23.

[0266] As shown in Figures 15 and 17, the 21st transistor T21, the 22nd transistor T22, and the 23rd transistor T23 are directly connected to the third power line 153 located between the first scanning subcircuit 211 and the second scanning subcircuit 212, avoiding detour wiring in the second direction Y and reducing the wiring space for each stage of the scanning shift register GRS in the first direction X.

[0267] For example, as shown in Figure 17, the display board 110 further includes a plurality of third connection lines 193 extending substantially along a second direction Y. Here, one end of the third connection line 193 is connected to a third type transistor M3, and the other end is connected to the nearest third power line 153.

[0268] For example, as shown in Figure 17, the 21st transistor T21, the 22nd transistor T22, and the 23rd transistor T23 may be connected via the same third connection line 193 to the third power line 153 (the third power line 153 on the right side of Figure 17) between the first scanning subcircuit 211 and the second scanning subcircuit 212. That is, the third type of transistor M3 in the first scanning subcircuit 211 is connected to the corresponding third power line 153, eliminating the need for detour wiring in the second direction Y and reducing the wiring space in the first direction X of each stage's scanning shift register GRS.

[0269] According to the second scanning subcircuit 212 described above, as shown in Figures 18 and 21, the third type of transistor M3 in the second scanning subcircuit 212 includes the 24th transistor T24, the 25th transistor T25, the 26th transistor T26, and the 27th transistor T27.

[0270] As shown in Figures 15 and 18, the 24th transistor T24, the 25th transistor T25, the 26th transistor T26, and the 27th transistor T27 are connected to at least one of two adjacent third power lines 153 located on either side of the second scanning subcircuit 212, thereby avoiding detours in the second direction Y and further reducing the wiring space in the first direction X for each stage of the scanning shift register GRS.

[0271] For example, as shown in Figure 18, the 24th transistor T24, the 25th transistor T25, the 26th transistor T26, and the 27th transistor T27 may be connected to both of two adjacent third power lines 153 located on either side of the second scanning subcircuit 212 via the same third connection line 193. That is, the third type of transistor M3 in the second scanning subcircuit 212 is connected to the corresponding third power line 153, eliminating the need for detour wiring in the second direction Y and further reducing the wiring space in the first direction X of each stage of the scanning shift register GRS.

[0272] According to the third scanning subcircuit 213 described above, as shown in Figures 19 and 21, the third type of transistor M3 in the third scanning subcircuit 213 includes a 30th transistor T30.

[0273] As shown in Figures 15 and 19, the 30th transistor T30 is connected to the third power line 153 located between the second scanning subcircuit 212 and the third scanning subcircuit 213, avoiding detour wiring in the second direction Y and further reducing the wiring space in the first direction X for each stage of the scanning shift register GRS.

[0274] For example, as shown in Figure 19, the 30th transistor T30 can be connected via a third connection line 193 to a third power line 153 located between the second scanning subcircuit 212 and the third scanning subcircuit 213, eliminating the need for bypass wiring in the second direction Y and further reducing the wiring space of each stage's scanning shift register GRS in the first direction X.

[0275] In some embodiments, referring to Figures 15, 18, and 20, both the second scanning subcircuit 212 and the fourth scanning subcircuit 214 include a fourth type transistor M4 connected to the nearest fourth power line 154.

[0276] In addition, as shown in FIG. 15, the display substrate 110 may include a plurality of fourth power lines 154, and the fourth power lines 154 may be configured to transmit a seventh signal or an eighth signal.

[0277] Here, as shown in FIG. 15, among the plurality of fourth power lines 154, at least one fourth power line 154 is provided between the second scanning sub-circuit 212 and the third scanning sub-circuit 213, and at least one other fourth power line 154 is provided between the fourth scanning sub-circuit 214 and the display area A (see FIG. 4).

[0278] Hereinafter, some embodiments of the present disclosure will be illustratively described by taking as an example the case where the display substrate 110 includes two fourth power lines 154, and the two fourth power lines 154 are respectively one first type of fourth power line 541 and one second type of fourth power line 542. However, the embodiments of the present disclosure are not limited thereto.

[0279] In addition, when the two fourth power lines 154 include one first type of fourth power line 541 and one second type of fourth power line 542, the first type of fourth power line 541 is located between the second scanning sub-circuit 212 and the third scanning sub-circuit 213, and the second type of fourth power line 542 is located between the fourth scanning sub-circuit 214 and the display area A (see FIG. 4).

[0280] At this time, the fourth-type transistors M4 in the second scanning sub-circuit 212 and the fourth scanning sub-circuit 214 may be respectively connected to the nearest fourth power line 154.

[0281] According to the configurations of the second scanning sub-circuit 212 and the fourth scanning sub-circuit 214 described above, as shown in FIGS. 18, 20, and 21, the fourth-type transistor M4 in the second scanning sub-circuit 212 includes the 27th transistor T27. The fourth-type transistor M4 in the fourth scanning sub-circuit 214 includes the 31st transistor T31.

[0282] That is, as shown in FIGS. 15 and 18, the 27th transistor T27 is connected to a fourth power line 154 located between the second scanning sub-circuit 212 and the third scanning sub-circuit 213. As shown in FIGS. 15 and 20, the 31st transistor T31 is connected to the fourth power line 154 located between the fourth scanning sub-circuit 214 and the display area A (see FIG. 4).

[0283] In this case, the fourth type of transistor M4 in the second scanning sub-circuit 212 and the fourth scanning sub-circuit 214 is directly connected to the nearest fourth power line 154, thereby avoiding the bypass wiring in the second direction Y and further reducing the wiring space in the first direction X of each stage of the scanning shift register GRS.

[0284] As an example, as shown in FIGS. 15 and 18, the display substrate 110 (see FIG. 4) further includes a plurality of fourth connection lines 194 extending substantially along the second direction Y. Here, one end of the fourth connection line 194 is connected to the fourth type of transistor M2, and the other end is connected to the nearest fourth power line 154.

[0285] As shown in FIGS. 15 and 18, the 27th transistor T27 and the 31st transistor T31 can be respectively connected to the corresponding fourth power line 154 via one fourth connection line 194. That is, the fourth type of transistor M4 in the second scanning sub-circuit 212 and the fourth scanning sub-circuit 214 is connected to the corresponding fourth power line 154, eliminating the need for bypass wiring in the second direction Y, and further reducing the wiring space in the first direction X of each stage of the scanning shift register GRS.

[0286] In some embodiments, referring to FIGS. 15, 17, 18, and 19, the width of the third power line 153 connected to the third scanning sub-circuit 213 is smaller than the width of the third power line 153 connected to the first scanning sub-circuit 211 and / or the second scanning sub-circuit 212. That is, the width of the third power line 532 of the second type is smaller than the width of the third power line 531 of the first type.

[0287] In this case, the width of the third power line 532 of the second type is smaller than the width of the third power line 531 of the first type, so the third power line 532 of the second type has a higher resistance and a larger voltage drop. In this case, when the second high level is output from the scan signal output terminal OUT2, the fourth control node Q4 becomes low level, the Vgs of the 30th transistor T30 becomes less than 0, and the 30th transistor T30 is turned off, reducing the risk of leakage current.

[0288] In some embodiments, referring to Figures 4 and 15, the second start signal line 162 is located on the side of the scanning drive circuit 121 away from the display area A. In the first direction X, the third start signal line 163 can be located on the side of the scanning drive circuit 121 (e.g., bonded to the side of the circuit board 400) to facilitate connection with the drive chip. The first voltage signal line 141 is located on the side of the scanning drive circuit 121 away from the display area A. The second voltage signal line 142 is located on the side of the scanning drive circuit 121 away from the display area A. The third clock signal line CLK3 is located between the scanning drive circuit 121 and the display area A. The fourth clock signal line CLK4 is located between the scanning drive circuit 121 and the display area A. The second reset signal line 182 is located between the first scanning subcircuit 211 and the second scanning subcircuit 212.

[0289] In this case, each transistor in the scanning shift register GRS may be connected to the corresponding first voltage signal line 141, second voltage signal line 142, third clock signal line CLK3, and fourth clock signal line CLK4 on both sides of the scanning shift register GRS, respectively. The transistors in the first scanning subcircuit 211 may be connected to the first voltage signal line 141, second voltage signal line 142, and second reset signal line 182 on both sides of the first scanning subcircuit 211, respectively. The third start signal line 163 may be directly connected to the driver chip. By providing the circuit in this manner, bypass wiring in the second direction Y can be reduced, and the wiring space in the first direction X of each stage of the scanning shift register GRS can be reduced.

[0290] Referring to Figures 17 to 20, the 19th transistor T19 may be connected to the second start signal line 162 and the first voltage signal line 141, the 20th transistor T20 may be connected to the second voltage signal line 142, and the 21st transistor T21 may be connected to the second reset signal line 182. The 28th transistor T28 and the 29th transistor T29 may be connected to the third clock signal line CLK3. The 32nd transistor T32 may be connected to the fourth clock signal line CLK4.

[0291] Referring to Figures 15 and 16, the positional relationship between the third power line 153, the fourth power line 154, the second start signal line 162, the first voltage signal line 141, the second voltage signal line 142, the third clock signal line CLK3, and the fourth clock signal line CLK4, and the second reset signal line 182 is not unique; they may be offset from each other or partially overlap.

[0292] As an example, referring to Figures 4 and 15, on the side of the scanning drive circuit 121 away from the display area A, the second start signal line 162, the first voltage signal line 141, and the second voltage signal line 142 are sequentially arranged with a staggered pattern along the second direction Y, from the peripheral area B toward the display area A.

[0293] Between the scanning drive circuit 121 and the display area A, the fourth power line 154, the third clock signal line CLK3, and the fourth clock signal line CLK4 are arranged sequentially with a staggered arrangement along the second direction Y, from the peripheral area B toward the display area A.

[0294] Between the first scanning subcircuit 211 and the second scanning subcircuit 212, a third power supply line 153 is located between the second reset signal line 182 and the second scanning subcircuit 212.

[0295] In addition, in some examples, as shown in Figure 15, of the third power line 153 and fourth power line 154 located between the second scanning subcircuit 212 and the third scanning subcircuit 213, the third power line 153 is located on the side of the fourth power line 154 that is away from display area A or closer to display area A. Figure 15 shows an example where the third power line 153 is located on the side of the fourth power line 154 that is away from display area A.

[0296] In this case, the second start signal line 162, the third start signal line 163, the third clock signal 173, the fourth clock signal 174, the first voltage signal line 141, the second voltage signal line 142, the third power supply line 153, the fourth power supply line 154, and the second reset signal line 182 may be provided on the same layer and made of the same material.

[0297] In some other examples, as shown in Figures 4 and 16, the third power line 153 and the fourth power line 154, located between the second scanning subcircuit 212 and the third scanning subcircuit 213, overlap at least partially in their orthographic projection onto the reference plane, thereby reducing the distance between the third power line 153 and the fourth power line 154 and the corresponding transistors, reducing voltage drop, and decreasing the wiring space in the second direction Y of each signal line, thereby facilitating a narrow bezel design for the display panel 100.

[0298] Furthermore, when the third power line 153 and the fourth power line 154 are located in different film layers, in embodiments where the orthogonal projections of the third power line 153 and the fourth power line 154 onto the reference plane overlap at least partially, the distance between the film layer where the third power line 153 is located and the film layer where the fourth power line 154 is located is larger, and parasitic capacitance is reduced, compared to embodiments where the orthogonal projections onto the reference plane do not overlap.

[0299] For example, when the third power line 153 and the fourth power line 154 are located in different film layers, in embodiments where the orthogonal projections of the third power line 153 and the fourth power line 154 onto the reference plane overlap at least partially, it is possible to add an insulating film layer, such as a flat layer, compared to embodiments where the orthogonal projections onto the reference plane do not overlap.

[0300] In this case, the second start signal line 162, the third start signal line 163, the third clock signal 173, the fourth clock signal 174, the first voltage signal line 141, the second voltage signal line 142, and the second reset signal line 182 may be provided on the same layer and of the same material, while the third power line 153 and the fourth power line 154 may be provided on different layers, and either one of them may be provided on the same layer and of the same material as the second start signal line 162, the third start signal line 163, the third clock signal 173, the fourth clock signal 174, the first voltage signal line 141, the second voltage signal line 142, and the second reset signal line 182.

[0301] Figure 5 is a cross-sectional view along the cutting line B-B' in Figure 4. Figure 6 is another cross-sectional view along the cutting line B-B' in Figure 4. The film layers on which each signal line is located in the embodiments of this disclosure will be described illustratively below with reference to Figures 5 and 6.

[0302] In some embodiments, as shown in Figure 5, the display substrate 110 includes a base 11, a semiconductor layer ACT, a gate insulating layer GI, a gate conductive layer GT, an interlayer insulating layer ILD, a first source-drain conductive layer SD1, and a first flat layer PLN1, which are sequentially stacked.

[0303] Here, as shown in FIG. 5, the semiconductor layer ACT includes the semiconductor channel 31 of the thin film transistor 30. The gate conductive layer GT includes the gate 34 of the thin film transistor 30 and the first plate of each capacitor C. The first source-drain conductive layer SD1 includes the source 32 and drain 33 of the thin film transistor 30 and the second plate of each capacitor C. Further, the above signal lines are provided with a shift, and all of them are located in the first source-drain conductive layer SD1.

[0304] In some other embodiments, as shown in FIG. 6, the display substrate 110 includes a base 11, a semiconductor layer ACT, a gate insulating layer GI, a gate conductive layer GT, an interlayer insulating layer ILD, a first source-drain conductive layer SD1, a first planarization layer PLN1, a second source-drain conductive layer SD2, and a second planarization layer PLN2, which are sequentially stacked.

[0305] Here, as shown in FIG. 6, the semiconductor layer ACT includes the semiconductor channel 31 of the thin film transistor 30. The gate conductive layer GT includes the gate 34 of the thin film transistor 30 and the first plate of each capacitor C. The first source-drain conductive layer SD1 includes the source 32 and drain 33 of the thin film transistor 30 and the second plate of each capacitor C. Among the above signal lines, some of the signal lines may be provided overlapping, and among the two overlapping signal lines, one may be located in the first source-drain conductive layer SD1 and the other may be located in the second source-drain conductive layer SD2. FIG. 6 shows an example where the first power supply line 151 and the second power supply line 152 overlap.

[0306] Some embodiments of the present disclosure further provide a method for manufacturing a display substrate for manufacturing the display substrate 110 according to any of the above embodiments. Referring to FIG. 5, the method for manufacturing the display substrate 110 includes the following steps.

[0307] The semiconductor layer ACT, the gate insulating layer GI, the gate conductive layer GT, the interlayer insulating layer ILD, the first source-drain conductive layer SD1, and the first planarization layer PLN1 are sequentially formed on the base 11.

[0308] Referring here to Figures 5, 8 and 15, the first source-drain conductive layer SD1 includes at least one of the following: a first power line 151, a second power line 152, a third power line 153, a fourth power line 154, a first start signal line 161, a second start signal line 162, a third start signal line 163, a first voltage signal line 141, a second voltage signal line 142, a first clock signal 171, a second clock signal 172, a third clock signal line 173, a first reset signal line 181, and a second reset signal line 182.

[0309] In some embodiments, as shown in Figures 8 and 15, the first power line 151, the second power line 152, the third power line 153, the fourth power line 154, the first start signal line 161, the second start signal line 162, the third start signal line 163, the first voltage signal line 141, the second voltage signal line 142, the first clock signal line 171, the second clock signal line 172, the third clock signal line 173, the first reset signal line 181, and the second reset signal line 182 are provided such that their orthogonal projection onto the reference plane is shifted.

[0310] In addition, as shown in Figures 5, 8, and 15, the first source-drain conductive layer SD1 may include, for example, a first power line 151, a second power line 152, a third power line 153, a fourth power line 154, a first start signal line 161, a second start signal line 162, a third start signal line 163, a first voltage signal line 141, a second voltage signal line 142, a first clock signal line 171, a second clock signal line 172, a third clock signal line 173, a first reset signal line 181, and a second reset signal line 182.

[0311] In some other embodiments, as shown in Figures 9 and 16, the first power lines 151 and the second power lines 152, located on the side away from the display area A (see Figure 4) of the light emission control circuit 122, have at least partially overlapping orthogonal projections onto the reference plane. And / or the third power lines 153 and the fourth power lines 154, located between the second scanning subcircuit 212 and the third scanning subcircuit 213, have at least partially overlapping orthogonal projections onto the reference plane.

[0312] In addition, referring to Figure 6, the manufacturing method of the display substrate 110 further includes the steps of forming a second source-drain conductive layer SD2 on the side of the first flat layer PLN1 away from the base 11, and forming a second flat layer PLN2 on the side of the second source-drain conductive layer SD2 away from the base 11.

[0313] As shown in Figures 6, 9, and 15, if the first power line 151 and the second power line 152, located on the side away from the display area A (see Figure 4) of the light emission control circuit 122, have orthogonal projections onto the reference plane that overlap at least partially, then the first source-drain conductive layer SD1 includes the first power line 151, the third power line 153, the fourth power line 154, the first start signal line 161, the second start signal line 162, the third start signal line 163, the first voltage signal line 141, the second voltage signal line 142, the first clock signal line 171, the second clock signal line 172, the third clock signal line 173, the first reset signal line 181, and the second reset signal line 182. The second source-drain conductive layer SD2 includes the second power line 152.

[0314] As shown in Figures 6, 8, and 16, the first source-drain conductive layer SD1 includes the first power line 151, the second power line 152, the third power line 153, the fourth power line 154, located between the second scanning subcircuit 212 and the third scanning subcircuit 213, if their orthogonal projections onto the reference plane overlap at least partially, then the first source-drain conductive layer SD1 includes the first power line 151, the second power line 152, the third power line 153, the first start signal line 161, the second start signal line 162, the third start signal line 163, the first voltage signal line 141, the second voltage signal line 142, the first clock signal line 171, the second clock signal line 172, the third clock signal line 173, the first reset signal line 181, and the second reset signal line 182. The second source-drain conductive layer SD2 includes the fourth power line 154.

[0315] As shown in Figures 6, 9, and 16, if the first power line 151 and the second power line 152, located on the side away from the display area A (see Figure 4) of the light emission control circuit 122, have at least partially overlapping orthogonal projections onto the reference plane, and the third power line 153 and the fourth power line 154, located between the second scanning subcircuit 212 and the third scanning subcircuit 213, have at least partially overlapping orthogonal projections onto the reference plane, then the first source-drain conductive layer SD1 includes the first power line 151, the third power line 153, the first start signal line 161, the second start signal line 162, the third start signal line 163, the first voltage signal line 141, the second voltage signal line 142, the first clock signal line 171, the second clock signal line 172, the third clock signal line 173, the first reset signal line 181, and the second reset signal line. The second source-drain conductive layer SD2 includes a second power line 152 and a fourth power line 154.

[0316] The above are merely specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto. Any modifications or substitutions that a person skilled in the art could conceive of within the scope of the technology disclosed herein are included within the scope of the present disclosure. Accordingly, the scope of the present disclosure is subject to the claims.

Claims

1. A display substrate having a display area and a peripheral area located on at least one side of the display area, A plurality of first power lines provided in the aforementioned peripheral region, extending along a substantially first direction and configured to transmit a first signal or a second signal, The peripheral region includes a light emission control circuit that includes a plurality of cascaded light emission shift registers, At least one first power line is located on the side away from the display area of ​​the light emission control circuit, at least two other first power lines overlap with the light emission control circuit, the light emission shift register is divided into a first light emission subcircuit, a second light emission subcircuit and a third light emission subcircuit, and the first light emission subcircuit, the second light emission subcircuit and the third light emission subcircuit are sequentially close to the display area. A display board wherein the first light-emitting subcircuit and the third light-emitting subcircuit each include a first type of transistor connected to the first power line, and each first type of transistor is connected to the nearest first power line.

2. The present invention further includes a plurality of second power lines extending substantially along the first direction and configured to transmit a third or fourth signal, Of the plurality of second power lines, at least one second power line is provided on the side of the light emission control circuit away from the display area, and at least one other second power line is provided between the light emission control circuit and the display area. The display board according to claim 1, wherein both the first light-emitting subcircuit and the third light-emitting subcircuit include a second type of transistor, and the second type of transistor in the first light-emitting subcircuit and the third light-emitting subcircuit are each connected to the nearest second power line.

3. The display substrate according to claim 2, wherein the first power line and the second power line located on the side of the light emission control circuit away from the display area have orthogonal projections onto a reference plane that overlap at least partially, and the reference plane is the plane on which the non-display side of the display substrate is located.

4. The display board according to claim 2, wherein, of the first power line and the second power line located on the side of the light emission control circuit away from the display area, the first power line is located on the side of the second power line away from the display area or closer to the display area.

5. The display board according to any one of claims 2 to 4, wherein the width of the second power line connected to the third light-emitting sub-circuit is smaller than the width of the second power line connected to the first light-emitting sub-circuit.

6. It further includes a plurality of second connecting lines extending along approximately the second direction, The display board according to any one of claims 2 to 5, wherein the second direction intersects the first direction, and the second connection line has one end connected to the second type of transistor and the other end connected to the nearest second power line.

7. The aforementioned at least two second power lines are A first type of second power line configured to transmit a third signal is provided on the side of the light emission control circuit away from the display area, The display board according to any one of claims 2 to 6, further comprising a second power line of a second type configured to transmit a fourth signal, provided between the light emission control circuit and the display area.

8. The first light-emitting subcircuit is connected to a first power signal terminal, a second power signal terminal, a first signal input terminal, a first reset signal terminal, a first clock signal terminal, a second clock signal terminal, a first cascade output terminal, a first control node, and a second control node. The first light-emitting subcircuit is configured to output one of the first signal, second signal, third signal, and fourth signal to the first control node, the second control node, and the first cascade output terminal, respectively, under the control of signals from the first signal input terminal, the first clock signal terminal, and the second clock signal terminal, and to output a first clock signal to the first control node and a first signal or a second signal to the second control node, under the control of a signal from the first reset signal terminal. The second light-emitting subcircuit is coupled to the first control node and the enable signal output terminal, and the second light-emitting subcircuit is configured to boost the voltage of the first control node when the first signal or the second signal is output from the enable signal output terminal. The display board according to any one of claims 2 to 7, wherein the third light-emitting subcircuit is coupled to the first power signal terminal, the second power signal terminal, the first control node, the second control node, and the enable signal output terminal, and the third light-emitting subcircuit outputs one of the first signal, the second signal, the third signal, and the fourth signal to the enable signal output terminal under voltage control of the first control node and the second control node, and is configured to boost the voltage of the second control node when the third signal or the fourth signal is output from the enable signal output terminal.

9. The display board according to any one of claims 1 to 8, wherein the width of the first power line connected to the third light-emitting subcircuit is greater than the width of the first power line connected to the first light-emitting subcircuit.

10. It further includes a plurality of first connecting lines extending along approximately the second direction, The display board according to any one of claims 1 to 9, wherein the second direction intersects the first direction, and the first connection line has one end connected to a transistor of the first type and the other end connected to the nearest first power line.

11. A first start signal line connected to the light emission control circuit, located on the side of the light emission control circuit away from the display area, A first clock signal line connected to the light emission control circuit, located on the side of the light emission control circuit away from the display area, A second clock signal line connected to the light-emitting control circuit, located on the side of the light-emitting control circuit away from the display area, The display board according to any one of claims 1 to 10, further comprising a first reset signal line connected to the light-emitting control circuit, located between two first power lines that overlap with the light-emitting control circuit.

12. A plurality of third power lines provided in the peripheral region, extending substantially along the first direction and configured to transmit a fifth signal or a sixth signal, The system further includes a scan drive circuit comprising a plurality of cascaded scan shift registers provided in the aforementioned peripheral region, At least three third power lines overlap with the scanning drive circuit, dividing the scanning shift register into a first scanning subcircuit, a second scanning subcircuit, a third scanning subcircuit, and a fourth scanning subcircuit, with the first scanning subcircuit, the second scanning subcircuit, the third scanning subcircuit, and the fourth scanning subcircuit sequentially approaching the display area. The display board according to any one of claims 1 to 11, wherein the first scanning subcircuit, the second scanning subcircuit, and the third scanning subcircuit each include a third type of transistor connected to the third power line, and the third type of transistor in the first scanning subcircuit, the second scanning subcircuit, and the third scanning subcircuit are each connected to the nearest third power line.

13. The system further includes a plurality of fourth power lines extending along approximately the first direction and configured to transmit a seventh or eighth signal, Of the plurality of fourth power lines, at least one fourth power line is provided between the second scanning subcircuit and the third scanning subcircuit, and at least one other fourth power line is provided between the fourth scanning subcircuit and the display area. The display board according to claim 12, wherein the second scanning subcircuit and the fourth scanning subcircuit each include a fourth type of transistor, and the fourth type of transistor in the second scanning subcircuit and the fourth scanning subcircuit is each connected to the nearest fourth power line.

14. The display board according to claim 13, wherein the third power line and the fourth power line located between the second scanning subcircuit and the third scanning subcircuit have orthogonal projections onto the reference plane that at least partially overlap, and the reference plane is the plane on which the display surface of the display board is located.

15. The display board according to claim 13, wherein, of the third power line and the fourth power line located between the second scanning subcircuit and the third scanning subcircuit, the third power line is located on the side of the fourth power line that is away from the display area or closer to the display area.

16. The display board according to any one of claims 13 to 15, wherein the width of the third power line connected to the third scanning subcircuit is smaller than the width of the third power line connected to the first scanning subcircuit and / or the second scanning subcircuit.

17. It includes a plurality of fourth connecting lines extending along approximately the second direction, The display board according to any one of claims 13 to 16, wherein the second direction intersects the first direction, and the fourth connection line has one end connected to the fourth type of transistor and the other end connected to the nearest fourth power line.

18. The first scanning subcircuit is connected to a third power signal terminal, a second signal input terminal, a third signal input terminal, a first voltage terminal, a second voltage terminal, a second reset signal terminal, a second cascade output terminal, a third control node, and a fourth control node. The first scanning subcircuit is configured to output a first voltage signal or a second voltage signal to the third control node, output a fifth signal or a sixth signal to the fourth control node, and output a fifth signal or a sixth signal to the third control node, under the control of the signal from the second reset signal terminal. The second scanning subcircuit is coupled to the third power signal terminal, the fourth power signal terminal, the third control node, the fourth control node, and the second cascade output terminal, and is configured to output a fifth or sixth signal to the second cascade output terminal under the control of the voltage of the fourth control node, and to output a fifth or sixth signal to the fourth control node under the control of the signal from the second cascade output terminal or the fourth power signal terminal. The third scanning subcircuit is coupled to the third power signal terminal, the third clock signal terminal, the third control node, the fourth control node, the second cascade output terminal, and the scanning signal output terminal, and the third scanning subcircuit is configured to output a third clock signal to the second cascade output terminal and to output any of the third clock signal, the fifth signal, and the sixth signal to the scanning signal output terminal, under the control of the voltages of the third and fourth control nodes. The display board according to any one of claims 13 to 17, wherein the fourth scanning subcircuit is coupled to a fourth clock signal terminal, a fourth power signal terminal, a fourth control node, and a scanning signal output terminal, and the fourth scanning subcircuit is configured to output a seventh signal or an eighth signal to the scanning signal output terminal under the control of a signal from the fourth power signal terminal, and to output a fourth clock signal to the fourth control node under the control of a signal from the fourth clock signal terminal.

19. It includes a plurality of third connecting lines extending along approximately the second direction, The display board according to any one of claims 12 to 18, wherein the second direction intersects the first direction, and the third connection line has one end connected to the third type of transistor and the other end connected to the nearest third power line.

20. The aforementioned plurality of third power lines are Two first type third power lines configured to transmit a fifth signal, one of which is provided between the first scanning subcircuit and the second scanning subcircuit, and the other of which is provided between the second scanning subcircuit and the third scanning subcircuit, The display board according to any one of claims 12 to 19, further comprising a second type of third power line configured to transmit a sixth signal, provided between the third scanning subcircuit and the fourth scanning subcircuit.

21. A second start signal line connected to the scanning drive circuit, located on the side of the scanning drive circuit away from the display area, A third start signal line connected to the scanning drive circuit, located on one side of the scanning drive circuit along the first direction, A first voltage signal line connected to the scanning drive circuit, located on the side of the scanning drive circuit away from the display area, A second voltage signal line connected to the scanning drive circuit, located on the side of the scanning drive circuit away from the display area, A third clock signal line connected to the scanning drive circuit is located between the scanning drive circuit and the display area, A fourth clock signal line connected to the scanning drive circuit is located between the scanning drive circuit and the display area, The display board according to any one of claims 12 to 20, further comprising a second reset signal line connected to the scanning drive circuit, located between the first scanning subcircuit and the second scanning subcircuit.

22. A display panel including a display board according to any one of claims 1 to 21.

23. A display device comprising the display panel described in claim 22.

24. A method for manufacturing a display board according to any one of claims 1 to 21, comprising a first power line, a second power line, a third power line, a fourth power line, a first start signal line, a second start signal line, a third start signal line, a first voltage signal line, a second voltage signal line, a first clock signal line, a second clock signal line, a third clock signal line, a first reset signal line, and a second reset signal line, The process includes sequentially forming a semiconductor layer, a gate insulating layer, a gate conductive layer, an interlayer insulating layer, a first source-drain conductive layer, and a first flat layer on the base, A method for manufacturing a display board, wherein the first source-drain conductive layer includes at least one of the following: the first power line, the second power line, the third power line, the fourth power line, the first start signal line, the second start signal line, the third start signal line, the first voltage signal line, the second voltage signal line, the first clock signal line, the second clock signal line, the third clock signal line, the first reset signal line, and the second reset signal line.

25. The first power line, the second power line, the third power line, the fourth power line, the first start signal line, the second start signal line, the third start signal line, the first voltage signal line, the second voltage signal line, the first clock signal line, the second clock signal line, the third clock signal line, the first reset signal line, and the second reset signal line are provided such that their orthogonal projection onto the reference plane is offset, and the reference plane is the plane on which the non-display side of the display board is located. A method for manufacturing a display board according to claim 24, wherein the first source-drain conductive layer includes a first power line, a second power line, a third power line, a fourth power line, a first start signal line, a second start signal line, a third start signal line, a first voltage signal line, a second voltage signal line, a first clock signal line, a second clock signal line, a third clock signal line, a first reset signal line, and a second reset signal line.

26. The first and second power lines located on the side away from the display area of ​​the light emission control circuit have orthogonal projections onto the reference plane that at least partially overlap, and / or the third and fourth power lines located between the second and third scanning subcircuits have orthogonal projections onto the reference plane that at least partially overlap, and the reference plane is the plane on which the non-display side of the display substrate is located. The method for manufacturing the display board is as follows: A step of forming a second source-drain conductive layer on the side of the first flat layer away from the base, The process further includes the step of forming a second flat layer on the side of the second source-drain conductive layer away from the base, If the orthogonal projections onto the reference plane of the first power line and the second power line located on the side away from the display area of ​​the light emission control circuit overlap at least partially, the first source-drain conductive layer includes the first power line, the third power line, the fourth power line, the first start signal line, the second start signal line, the third start signal line, the first voltage signal line, the second voltage signal line, the first clock signal line, the second clock signal line, the third clock signal line, the first reset signal line and the second reset signal line, and the second source-drain conductive layer includes the second power line, If the orthogonal projections of the third and fourth power lines located between the second and third scanning subcircuits onto the reference plane overlap at least partially, the first source-drain conductive layer includes the first power line, the second power line, the third power line, the first start signal line, the second start signal line, the third start signal line, the first voltage signal line, the second voltage signal line, the first clock signal line, the second clock signal line, the third clock signal line, the first reset signal line, and the second reset signal line, and the second source-drain conductive layer includes the fourth power line, The method for manufacturing a display substrate according to claim 24, wherein if the orthogonal projections onto the reference plane of a first power line and a second power line located away from the display area of ​​the light emission control circuit overlap at least partially, and the orthogonal projections onto the reference plane of a third power line and a fourth power line located between a second scanning subcircuit and a third scanning subcircuit overlap at least partially, the first source-drain conductive layer includes the first power line, the third power line, the first start signal line, the second start signal line, the third start signal line, the first voltage signal line, the second voltage signal line, the first clock signal line, the second clock signal line, the third clock signal line, the first reset signal line, and the second reset signal line, and the second source-drain conductive layer includes the second power line and the fourth power line.

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